drivers/infiniband/hw/mthca/mthca_cmd.h

   1 /*
   2  * Copyright (c) 2004, 2005 Topspin Communications.  All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  *
  32  * $Id: mthca_cmd.h 1349 2004-12-16 21:09:43Z roland $
  33  */
  34
  35 #ifndef MTHCA_CMD_H
  36 #define MTHCA_CMD_H
  37
  38 #include <ib_verbs.h>
  39
  40 #define MTHCA_CMD_MAILBOX_ALIGN 16UL
  41 #define MTHCA_CMD_MAILBOX_EXTRA (MTHCA_CMD_MAILBOX_ALIGN - 1)
  42
  43 enum {
  44         /* command completed successfully: */
  45         MTHCA_CMD_STAT_OK             = 0x00,
  46         /* Internal error (such as a bus error) occurred while processing command: */
  47         MTHCA_CMD_STAT_INTERNAL_ERR   = 0x01,
  48         /* Operation/command not supported or opcode modifier not supported: */
  49         MTHCA_CMD_STAT_BAD_OP         = 0x02,
  50         /* Parameter not supported or parameter out of range: */
  51         MTHCA_CMD_STAT_BAD_PARAM      = 0x03,
  52         /* System not enabled or bad system state: */
  53         MTHCA_CMD_STAT_BAD_SYS_STATE  = 0x04,
  54         /* Attempt to access reserved or unallocaterd resource: */
  55         MTHCA_CMD_STAT_BAD_RESOURCE   = 0x05,
  56         /* Requested resource is currently executing a command, or is otherwise busy: */
  57         MTHCA_CMD_STAT_RESOURCE_BUSY  = 0x06,
  58         /* memory error: */
  59         MTHCA_CMD_STAT_DDR_MEM_ERR    = 0x07,
  60         /* Required capability exceeds device limits: */
  61         MTHCA_CMD_STAT_EXCEED_LIM     = 0x08,
  62         /* Resource is not in the appropriate state or ownership: */
  63         MTHCA_CMD_STAT_BAD_RES_STATE  = 0x09,
  64         /* Index out of range: */
  65         MTHCA_CMD_STAT_BAD_INDEX      = 0x0a,
  66         /* FW image corrupted: */
  67         MTHCA_CMD_STAT_BAD_NVMEM      = 0x0b,
  68         /* Attempt to modify a QP/EE which is not in the presumed state: */
  69         MTHCA_CMD_STAT_BAD_QPEE_STATE = 0x10,
  70         /* Bad segment parameters (Address/Size): */
  71         MTHCA_CMD_STAT_BAD_SEG_PARAM  = 0x20,
  72         /* Memory Region has Memory Windows bound to: */
  73         MTHCA_CMD_STAT_REG_BOUND      = 0x21,
  74         /* HCA local attached memory not present: */
  75         MTHCA_CMD_STAT_LAM_NOT_PRE    = 0x22,
  76         /* Bad management packet (silently discarded): */
  77         MTHCA_CMD_STAT_BAD_PKT        = 0x30,
  78         /* More outstanding CQEs in CQ than new CQ size: */
  79         MTHCA_CMD_STAT_BAD_SIZE       = 0x40
  80 };
  81
  82 enum {
  83         MTHCA_TRANS_INVALID = 0,
  84         MTHCA_TRANS_RST2INIT,
  85         MTHCA_TRANS_INIT2INIT,
  86         MTHCA_TRANS_INIT2RTR,
  87         MTHCA_TRANS_RTR2RTS,
  88         MTHCA_TRANS_RTS2RTS,
  89         MTHCA_TRANS_SQERR2RTS,
  90         MTHCA_TRANS_ANY2ERR,
  91         MTHCA_TRANS_RTS2SQD,
  92         MTHCA_TRANS_SQD2SQD,
  93         MTHCA_TRANS_SQD2RTS,
  94         MTHCA_TRANS_ANY2RST,
  95 };
  96
  97 enum {
  98         DEV_LIM_FLAG_RC                 = 1 << 0,
  99         DEV_LIM_FLAG_UC                 = 1 << 1,
 100         DEV_LIM_FLAG_UD                 = 1 << 2,
 101         DEV_LIM_FLAG_RD                 = 1 << 3,
 102         DEV_LIM_FLAG_RAW_IPV6           = 1 << 4,
 103         DEV_LIM_FLAG_RAW_ETHER          = 1 << 5,
 104         DEV_LIM_FLAG_SRQ                = 1 << 6,
 105         DEV_LIM_FLAG_BAD_PKEY_CNTR      = 1 << 8,
 106         DEV_LIM_FLAG_BAD_QKEY_CNTR      = 1 << 9,
 107         DEV_LIM_FLAG_MW                 = 1 << 16,
 108         DEV_LIM_FLAG_AUTO_PATH_MIG      = 1 << 17,
 109         DEV_LIM_FLAG_ATOMIC             = 1 << 18,
 110         DEV_LIM_FLAG_RAW_MULTI          = 1 << 19,
 111         DEV_LIM_FLAG_UD_AV_PORT_ENFORCE = 1 << 20,
 112         DEV_LIM_FLAG_UD_MULTI           = 1 << 21,
 113 };
 114
 115 struct mthca_dev_lim {
 116         int max_srq_sz;
 117         int max_qp_sz;
 118         int reserved_qps;
 119         int max_qps;
 120         int reserved_srqs;
 121         int max_srqs;
 122         int reserved_eecs;
 123         int max_eecs;
 124         int max_cq_sz;
 125         int reserved_cqs;
 126         int max_cqs;
 127         int max_mpts;
 128         int reserved_eqs;
 129         int max_eqs;
 130         int reserved_mtts;
 131         int max_mrw_sz;
 132         int reserved_mrws;
 133         int max_mtt_seg;
 134         int max_requester_per_qp;
 135         int max_responder_per_qp;
 136         int max_rdma_global;
 137         int local_ca_ack_delay;
 138         int max_mtu;
 139         int max_port_width;
 140         int max_vl;
 141         int num_ports;
 142         int max_gids;
 143         int max_pkeys;
 144         u32 flags;
 145         int reserved_uars;
 146         int uar_size;
 147         int min_page_sz;
 148         int max_sg;
 149         int max_desc_sz;
 150         int max_qp_per_mcg;
 151         int reserved_mgms;
 152         int max_mcgs;
 153         int reserved_pds;
 154         int max_pds;
 155         int reserved_rdds;
 156         int max_rdds;
 157         int eec_entry_sz;
 158         int qpc_entry_sz;
 159         int eeec_entry_sz;
 160         int eqpc_entry_sz;
 161         int eqc_entry_sz;
 162         int cqc_entry_sz;
 163         int srq_entry_sz;
 164         int uar_scratch_entry_sz;
 165         int mpt_entry_sz;
 166         union {
 167                 struct {
 168                         int max_avs;
 169                 } tavor;
 170                 struct {
 171                         int resize_srq;
 172                         int max_pbl_sz;
 173                         u8  bmme_flags;
 174                         u32 reserved_lkey;
 175                         int lam_required;
 176                         u64 max_icm_sz;
 177                 } arbel;
 178         } hca;
 179 };
 180
 181 struct mthca_adapter {
 182         u32 vendor_id;
 183         u32 device_id;
 184         u32 revision_id;
 185         u8  inta_pin;
 186 };
 187
 188 struct mthca_init_hca_param {
 189         u64 qpc_base;
 190         u64 eec_base;
 191         u64 srqc_base;
 192         u64 cqc_base;
 193         u64 eqpc_base;
 194         u64 eeec_base;
 195         u64 eqc_base;
 196         u64 rdb_base;
 197         u64 mc_base;
 198         u64 mpt_base;
 199         u64 mtt_base;
 200         u64 uar_scratch_base;
 201         u64 uarc_base;
 202         u16 log_mc_entry_sz;
 203         u16 mc_hash_sz;
 204         u8  log_num_qps;
 205         u8  log_num_eecs;
 206         u8  log_num_srqs;
 207         u8  log_num_cqs;
 208         u8  log_num_eqs;
 209         u8  log_mc_table_sz;
 210         u8  mtt_seg_sz;
 211         u8  log_mpt_sz;
 212         u8  log_uar_sz;
 213         u8  log_uarc_sz;
 214 };
 215
 216 struct mthca_init_ib_param {
 217         int enable_1x;
 218         int enable_4x;
 219         int vl_cap;
 220         int mtu_cap;
 221         u16 gid_cap;
 222         u16 pkey_cap;
 223         int set_guid0;
 224         u64 guid0;
 225         int set_node_guid;
 226         u64 node_guid;
 227         int set_si_guid;
 228         u64 si_guid;
 229 };
 230
 231 struct mthca_set_ib_param {
 232         int set_si_guid;
 233         int reset_qkey_viol;
 234         u64 si_guid;
 235         u32 cap_mask;
 236 };
 237
 238 int mthca_cmd_use_events(struct mthca_dev *dev);
 239 void mthca_cmd_use_polling(struct mthca_dev *dev);
 240 void mthca_cmd_event(struct mthca_dev *dev, u16 token,
 241                      u8  status, u64 out_param);
 242
 243 int mthca_SYS_EN(struct mthca_dev *dev, u8 *status);
 244 int mthca_SYS_DIS(struct mthca_dev *dev, u8 *status);
 245 int mthca_MAP_FA(struct mthca_dev *dev, struct mthca_icm *icm, u8 *status);
 246 int mthca_UNMAP_FA(struct mthca_dev *dev, u8 *status);
 247 int mthca_RUN_FW(struct mthca_dev *dev, u8 *status);
 248 int mthca_QUERY_FW(struct mthca_dev *dev, u8 *status);
 249 int mthca_ENABLE_LAM(struct mthca_dev *dev, u8 *status);
 250 int mthca_DISABLE_LAM(struct mthca_dev *dev, u8 *status);
 251 int mthca_QUERY_DDR(struct mthca_dev *dev, u8 *status);
 252 int mthca_QUERY_DEV_LIM(struct mthca_dev *dev,
 253                         struct mthca_dev_lim *dev_lim, u8 *status);
 254 int mthca_QUERY_ADAPTER(struct mthca_dev *dev,
 255                         struct mthca_adapter *adapter, u8 *status);
 256 int mthca_INIT_HCA(struct mthca_dev *dev,
 257                    struct mthca_init_hca_param *param,
 258                    u8 *status);
 259 int mthca_INIT_IB(struct mthca_dev *dev,
 260                   struct mthca_init_ib_param *param,
 261                   int port, u8 *status);
 262 int mthca_CLOSE_IB(struct mthca_dev *dev, int port, u8 *status);
 263 int mthca_CLOSE_HCA(struct mthca_dev *dev, int panic, u8 *status);
 264 int mthca_SET_IB(struct mthca_dev *dev, struct mthca_set_ib_param *param,
 265                  int port, u8 *status);
 266 int mthca_MAP_ICM(struct mthca_dev *dev, struct mthca_icm *icm, u64 virt, u8 *status);
 267 int mthca_MAP_ICM_page(struct mthca_dev *dev, u64 dma_addr, u64 virt, u8 *status);
 268 int mthca_UNMAP_ICM(struct mthca_dev *dev, u64 virt, u32 page_count, u8 *status);
 269 int mthca_MAP_ICM_AUX(struct mthca_dev *dev, struct mthca_icm *icm, u8 *status);
 270 int mthca_UNMAP_ICM_AUX(struct mthca_dev *dev, u8 *status);
 271 int mthca_SET_ICM_SIZE(struct mthca_dev *dev, u64 icm_size, u64 *aux_pages,
 272                        u8 *status);
 273 int mthca_SW2HW_MPT(struct mthca_dev *dev, void *mpt_entry,
 274                     int mpt_index, u8 *status);
 275 int mthca_HW2SW_MPT(struct mthca_dev *dev, void *mpt_entry,
 276                     int mpt_index, u8 *status);
 277 int mthca_WRITE_MTT(struct mthca_dev *dev, u64 *mtt_entry,
 278                     int num_mtt, u8 *status);
 279 int mthca_SYNC_TPT(struct mthca_dev *dev, u8 *status);
 280 int mthca_MAP_EQ(struct mthca_dev *dev, u64 event_mask, int unmap,
 281                  int eq_num, u8 *status);
 282 int mthca_SW2HW_EQ(struct mthca_dev *dev, void *eq_context,
 283                    int eq_num, u8 *status);
 284 int mthca_HW2SW_EQ(struct mthca_dev *dev, void *eq_context,
 285                    int eq_num, u8 *status);
 286 int mthca_SW2HW_CQ(struct mthca_dev *dev, void *cq_context,
 287                    int cq_num, u8 *status);
 288 int mthca_HW2SW_CQ(struct mthca_dev *dev, void *cq_context,
 289                    int cq_num, u8 *status);
 290 int mthca_MODIFY_QP(struct mthca_dev *dev, int trans, u32 num,
 291                     int is_ee, void *qp_context, u32 optmask,
 292                     u8 *status);
 293 int mthca_QUERY_QP(struct mthca_dev *dev, u32 num, int is_ee,
 294                    void *qp_context, u8 *status);
 295 int mthca_CONF_SPECIAL_QP(struct mthca_dev *dev, int type, u32 qpn,
 296                           u8 *status);
 297 int mthca_MAD_IFC(struct mthca_dev *dev, int ignore_mkey, int ignore_bkey,
 298                   int port, struct ib_wc* in_wc, struct ib_grh* in_grh,
 299                   void *in_mad, void *response_mad, u8 *status);
 300 int mthca_READ_MGM(struct mthca_dev *dev, int index, void *mgm,
 301                    u8 *status);
 302 int mthca_WRITE_MGM(struct mthca_dev *dev, int index, void *mgm,
 303                     u8 *status);
 304 int mthca_MGID_HASH(struct mthca_dev *dev, void *gid, u16 *hash,
 305                     u8 *status);
 306 int mthca_NOP(struct mthca_dev *dev, u8 *status);
 307
 308 #define MAILBOX_ALIGN(x) ((void *) ALIGN((unsigned long) (x), MTHCA_CMD_MAILBOX_ALIGN))
 309
 310 #endif /* MTHCA_CMD_H */