?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
[TG3]: Set minimal hw interrupt mitigation.
[linux-2.6/verdex.git] / drivers / isdn / hisax / hfc_2bs0.c
blobbb376f39ac89d9b06e3c0d76828a8c5aa6f1565a
1 /* $Id: hfc_2bs0.c,v 1.20.2.6 2004/02/11 13:21:33 keil Exp $
2 *
3 * specific routines for CCD's HFC 2BS0
4 *
5 * Author Karsten Keil
6 * Copyright by Karsten Keil <keil@isdn4linux.de>
7 *
8 * This software may be used and distributed according to the terms
9 * of the GNU General Public License, incorporated herein by reference.
10 *
11 */
12
13 #include <linux/init.h>
14 #include "hisax.h"
15 #include "hfc_2bs0.h"
16 #include "isac.h"
17 #include "isdnl1.h"
18 #include <linux/interrupt.h>
19
20 static inline int
21 WaitForBusy(struct IsdnCardState *cs)
22 {
23 int to = 130;
24 u_char val;
25
26 while (!(cs->BC_Read_Reg(cs, HFC_STATUS, 0) & HFC_BUSY) && to) {
27 val = cs->BC_Read_Reg(cs, HFC_DATA, HFC_CIP | HFC_F2 |
28 (cs->hw.hfc.cip & 3));
29 udelay(1);
30 to--;
31 }
32 if (!to) {
33 printk(KERN_WARNING "HiSax: waitforBusy timeout\n");
34 return (0);
35 } else
36 return (to);
37 }
38
39 static inline int
40 WaitNoBusy(struct IsdnCardState *cs)
41 {
42 int to = 125;
43
44 while ((cs->BC_Read_Reg(cs, HFC_STATUS, 0) & HFC_BUSY) && to) {
45 udelay(1);
46 to--;
47 }
48 if (!to) {
49 printk(KERN_WARNING "HiSax: waitforBusy timeout\n");
50 return (0);
51 } else
52 return (to);
53 }
54
55 int
56 GetFreeFifoBytes(struct BCState *bcs)
57 {
58 int s;
59
60 if (bcs->hw.hfc.f1 == bcs->hw.hfc.f2)
61 return (bcs->cs->hw.hfc.fifosize);
62 s = bcs->hw.hfc.send[bcs->hw.hfc.f1] - bcs->hw.hfc.send[bcs->hw.hfc.f2];
63 if (s <= 0)
64 s += bcs->cs->hw.hfc.fifosize;
65 s = bcs->cs->hw.hfc.fifosize - s;
66 return (s);
67 }
68
69 int
70 ReadZReg(struct BCState *bcs, u_char reg)
71 {
72 int val;
73
74 WaitNoBusy(bcs->cs);
75 val = 256 * bcs->cs->BC_Read_Reg(bcs->cs, HFC_DATA, reg | HFC_CIP | HFC_Z_HIGH);
76 WaitNoBusy(bcs->cs);
77 val += bcs->cs->BC_Read_Reg(bcs->cs, HFC_DATA, reg | HFC_CIP | HFC_Z_LOW);
78 return (val);
79 }
80
81 static void
82 hfc_clear_fifo(struct BCState *bcs)
83 {
84 struct IsdnCardState *cs = bcs->cs;
85 int idx, cnt;
86 int rcnt, z1, z2;
87 u_char cip, f1, f2;
88
89 if ((cs->debug & L1_DEB_HSCX) && !(cs->debug & L1_DEB_HSCX_FIFO))
90 debugl1(cs, "hfc_clear_fifo");
91 cip = HFC_CIP | HFC_F1 | HFC_REC | HFC_CHANNEL(bcs->channel);
92 if ((cip & 0xc3) != (cs->hw.hfc.cip & 0xc3)) {
93 cs->BC_Write_Reg(cs, HFC_STATUS, cip, cip);
94 WaitForBusy(cs);
95 }
96 WaitNoBusy(cs);
97 f1 = cs->BC_Read_Reg(cs, HFC_DATA, cip);
98 cip = HFC_CIP | HFC_F2 | HFC_REC | HFC_CHANNEL(bcs->channel);
99 WaitNoBusy(cs);
100 f2 = cs->BC_Read_Reg(cs, HFC_DATA, cip);
101 z1 = ReadZReg(bcs, HFC_Z1 | HFC_REC | HFC_CHANNEL(bcs->channel));
102 z2 = ReadZReg(bcs, HFC_Z2 | HFC_REC | HFC_CHANNEL(bcs->channel));
103 cnt = 32;
104 while (((f1 != f2) || (z1 != z2)) && cnt--) {
105 if (cs->debug & L1_DEB_HSCX)
106 debugl1(cs, "hfc clear %d f1(%d) f2(%d)",
107 bcs->channel, f1, f2);
108 rcnt = z1 - z2;
109 if (rcnt < 0)
110 rcnt += cs->hw.hfc.fifosize;
111 if (rcnt)
112 rcnt++;
113 if (cs->debug & L1_DEB_HSCX)
114 debugl1(cs, "hfc clear %d z1(%x) z2(%x) cnt(%d)",
115 bcs->channel, z1, z2, rcnt);
116 cip = HFC_CIP | HFC_FIFO_OUT | HFC_REC | HFC_CHANNEL(bcs->channel);
117 idx = 0;
118 while ((idx < rcnt) && WaitNoBusy(cs)) {
119 cs->BC_Read_Reg(cs, HFC_DATA_NODEB, cip);
120 idx++;
121 }
122 if (f1 != f2) {
123 WaitNoBusy(cs);
124 cs->BC_Read_Reg(cs, HFC_DATA, HFC_CIP | HFC_F2_INC | HFC_REC |
125 HFC_CHANNEL(bcs->channel));
126 WaitForBusy(cs);
127 }
128 cip = HFC_CIP | HFC_F1 | HFC_REC | HFC_CHANNEL(bcs->channel);
129 WaitNoBusy(cs);
130 f1 = cs->BC_Read_Reg(cs, HFC_DATA, cip);
131 cip = HFC_CIP | HFC_F2 | HFC_REC | HFC_CHANNEL(bcs->channel);
132 WaitNoBusy(cs);
133 f2 = cs->BC_Read_Reg(cs, HFC_DATA, cip);
134 z1 = ReadZReg(bcs, HFC_Z1 | HFC_REC | HFC_CHANNEL(bcs->channel));
135 z2 = ReadZReg(bcs, HFC_Z2 | HFC_REC | HFC_CHANNEL(bcs->channel));
136 }
137 return;
138 }
139
140
141 static struct sk_buff
142 *
143 hfc_empty_fifo(struct BCState *bcs, int count)
144 {
145 u_char *ptr;
146 struct sk_buff *skb;
147 struct IsdnCardState *cs = bcs->cs;
148 int idx;
149 int chksum;
150 u_char stat, cip;
151
152 if ((cs->debug & L1_DEB_HSCX) && !(cs->debug & L1_DEB_HSCX_FIFO))
153 debugl1(cs, "hfc_empty_fifo");
154 idx = 0;
155 if (count > HSCX_BUFMAX + 3) {
156 if (cs->debug & L1_DEB_WARN)
157 debugl1(cs, "hfc_empty_fifo: incoming packet too large");
158 cip = HFC_CIP | HFC_FIFO_OUT | HFC_REC | HFC_CHANNEL(bcs->channel);
159 while ((idx++ < count) && WaitNoBusy(cs))
160 cs->BC_Read_Reg(cs, HFC_DATA_NODEB, cip);
161 WaitNoBusy(cs);
162 stat = cs->BC_Read_Reg(cs, HFC_DATA, HFC_CIP | HFC_F2_INC | HFC_REC |
163 HFC_CHANNEL(bcs->channel));
164 WaitForBusy(cs);
165 return (NULL);
166 }
167 if ((count < 4) && (bcs->mode != L1_MODE_TRANS)) {
168 if (cs->debug & L1_DEB_WARN)
169 debugl1(cs, "hfc_empty_fifo: incoming packet too small");
170 cip = HFC_CIP | HFC_FIFO_OUT | HFC_REC | HFC_CHANNEL(bcs->channel);
171 while ((idx++ < count) && WaitNoBusy(cs))
172 cs->BC_Read_Reg(cs, HFC_DATA_NODEB, cip);
173 WaitNoBusy(cs);
174 stat = cs->BC_Read_Reg(cs, HFC_DATA, HFC_CIP | HFC_F2_INC | HFC_REC |
175 HFC_CHANNEL(bcs->channel));
176 WaitForBusy(cs);
177 #ifdef ERROR_STATISTIC
178 bcs->err_inv++;
179 #endif
180 return (NULL);
181 }
182 if (bcs->mode == L1_MODE_TRANS)
183 count -= 1;
184 else
185 count -= 3;
186 if (!(skb = dev_alloc_skb(count)))
187 printk(KERN_WARNING "HFC: receive out of memory\n");
188 else {
189 ptr = skb_put(skb, count);
190 idx = 0;
191 cip = HFC_CIP | HFC_FIFO_OUT | HFC_REC | HFC_CHANNEL(bcs->channel);
192 while ((idx < count) && WaitNoBusy(cs)) {
193 *ptr++ = cs->BC_Read_Reg(cs, HFC_DATA_NODEB, cip);
194 idx++;
195 }
196 if (idx != count) {
197 debugl1(cs, "RFIFO BUSY error");
198 printk(KERN_WARNING "HFC FIFO channel %d BUSY Error\n", bcs->channel);
199 dev_kfree_skb_any(skb);
200 if (bcs->mode != L1_MODE_TRANS) {
201 WaitNoBusy(cs);
202 stat = cs->BC_Read_Reg(cs, HFC_DATA, HFC_CIP | HFC_F2_INC | HFC_REC |
203 HFC_CHANNEL(bcs->channel));
204 WaitForBusy(cs);
205 }
206 return (NULL);
207 }
208 if (bcs->mode != L1_MODE_TRANS) {
209 WaitNoBusy(cs);
210 chksum = (cs->BC_Read_Reg(cs, HFC_DATA, cip) << 8);
211 WaitNoBusy(cs);
212 chksum += cs->BC_Read_Reg(cs, HFC_DATA, cip);
213 WaitNoBusy(cs);
214 stat = cs->BC_Read_Reg(cs, HFC_DATA, cip);
215 if (cs->debug & L1_DEB_HSCX)
216 debugl1(cs, "hfc_empty_fifo %d chksum %x stat %x",
217 bcs->channel, chksum, stat);
218 if (stat) {
219 debugl1(cs, "FIFO CRC error");
220 dev_kfree_skb_any(skb);
221 skb = NULL;
222 #ifdef ERROR_STATISTIC
223 bcs->err_crc++;
224 #endif
225 }
226 WaitNoBusy(cs);
227 stat = cs->BC_Read_Reg(cs, HFC_DATA, HFC_CIP | HFC_F2_INC | HFC_REC |
228 HFC_CHANNEL(bcs->channel));
229 WaitForBusy(cs);
230 }
231 }
232 return (skb);
233 }
234
235 static void
236 hfc_fill_fifo(struct BCState *bcs)
237 {
238 struct IsdnCardState *cs = bcs->cs;
239 int idx, fcnt;
240 int count;
241 int z1, z2;
242 u_char cip;
243
244 if (!bcs->tx_skb)
245 return;
246 if (bcs->tx_skb->len <= 0)
247 return;
248
249 cip = HFC_CIP | HFC_F1 | HFC_SEND | HFC_CHANNEL(bcs->channel);
250 if ((cip & 0xc3) != (cs->hw.hfc.cip & 0xc3)) {
251 cs->BC_Write_Reg(cs, HFC_STATUS, cip, cip);
252 WaitForBusy(cs);
253 }
254 WaitNoBusy(cs);
255 if (bcs->mode != L1_MODE_TRANS) {
256 bcs->hw.hfc.f1 = cs->BC_Read_Reg(cs, HFC_DATA, cip);
257 cip = HFC_CIP | HFC_F2 | HFC_SEND | HFC_CHANNEL(bcs->channel);
258 WaitNoBusy(cs);
259 bcs->hw.hfc.f2 = cs->BC_Read_Reg(cs, HFC_DATA, cip);
260 bcs->hw.hfc.send[bcs->hw.hfc.f1] = ReadZReg(bcs, HFC_Z1 | HFC_SEND | HFC_CHANNEL(bcs->channel));
261 if (cs->debug & L1_DEB_HSCX)
262 debugl1(cs, "hfc_fill_fifo %d f1(%d) f2(%d) z1(%x)",
263 bcs->channel, bcs->hw.hfc.f1, bcs->hw.hfc.f2,
264 bcs->hw.hfc.send[bcs->hw.hfc.f1]);
265 fcnt = bcs->hw.hfc.f1 - bcs->hw.hfc.f2;
266 if (fcnt < 0)
267 fcnt += 32;
268 if (fcnt > 30) {
269 if (cs->debug & L1_DEB_HSCX)
270 debugl1(cs, "hfc_fill_fifo more as 30 frames");
271 return;
272 }
273 count = GetFreeFifoBytes(bcs);
274 }
275 else {
276 WaitForBusy(cs);
277 z1 = ReadZReg(bcs, HFC_Z1 | HFC_REC | HFC_CHANNEL(bcs->channel));
278 z2 = ReadZReg(bcs, HFC_Z2 | HFC_REC | HFC_CHANNEL(bcs->channel));
279 count = z1 - z2;
280 if (count < 0)
281 count += cs->hw.hfc.fifosize;
282 } /* L1_MODE_TRANS */
283 if (cs->debug & L1_DEB_HSCX)
284 debugl1(cs, "hfc_fill_fifo %d count(%ld/%d)",
285 bcs->channel, bcs->tx_skb->len,
286 count);
287 if (count < bcs->tx_skb->len) {
288 if (cs->debug & L1_DEB_HSCX)
289 debugl1(cs, "hfc_fill_fifo no fifo mem");
290 return;
291 }
292 cip = HFC_CIP | HFC_FIFO_IN | HFC_SEND | HFC_CHANNEL(bcs->channel);
293 idx = 0;
294 while ((idx < bcs->tx_skb->len) && WaitNoBusy(cs))
295 cs->BC_Write_Reg(cs, HFC_DATA_NODEB, cip, bcs->tx_skb->data[idx++]);
296 if (idx != bcs->tx_skb->len) {
297 debugl1(cs, "FIFO Send BUSY error");
298 printk(KERN_WARNING "HFC S FIFO channel %d BUSY Error\n", bcs->channel);
299 } else {
300 count = bcs->tx_skb->len;
301 bcs->tx_cnt -= count;
302 if (PACKET_NOACK == bcs->tx_skb->pkt_type)
303 count = -1;
304 dev_kfree_skb_any(bcs->tx_skb);
305 bcs->tx_skb = NULL;
306 if (bcs->mode != L1_MODE_TRANS) {
307 WaitForBusy(cs);
308 WaitNoBusy(cs);
309 cs->BC_Read_Reg(cs, HFC_DATA, HFC_CIP | HFC_F1_INC | HFC_SEND | HFC_CHANNEL(bcs->channel));
310 }
311 if (test_bit(FLG_LLI_L1WAKEUP,&bcs->st->lli.flag) &&
312 (count >= 0)) {
313 u_long flags;
314 spin_lock_irqsave(&bcs->aclock, flags);
315 bcs->ackcnt += count;
316 spin_unlock_irqrestore(&bcs->aclock, flags);
317 schedule_event(bcs, B_ACKPENDING);
318 }
319 test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
320 }
321 return;
322 }
323
324 void
325 main_irq_hfc(struct BCState *bcs)
326 {
327 struct IsdnCardState *cs = bcs->cs;
328 int z1, z2, rcnt;
329 u_char f1, f2, cip;
330 int receive, transmit, count = 5;
331 struct sk_buff *skb;
332
333 Begin:
334 count--;
335 cip = HFC_CIP | HFC_F1 | HFC_REC | HFC_CHANNEL(bcs->channel);
336 if ((cip & 0xc3) != (cs->hw.hfc.cip & 0xc3)) {
337 cs->BC_Write_Reg(cs, HFC_STATUS, cip, cip);
338 WaitForBusy(cs);
339 }
340 WaitNoBusy(cs);
341 receive = 0;
342 if (bcs->mode == L1_MODE_HDLC) {
343 f1 = cs->BC_Read_Reg(cs, HFC_DATA, cip);
344 cip = HFC_CIP | HFC_F2 | HFC_REC | HFC_CHANNEL(bcs->channel);
345 WaitNoBusy(cs);
346 f2 = cs->BC_Read_Reg(cs, HFC_DATA, cip);
347 if (f1 != f2) {
348 if (cs->debug & L1_DEB_HSCX)
349 debugl1(cs, "hfc rec %d f1(%d) f2(%d)",
350 bcs->channel, f1, f2);
351 receive = 1;
352 }
353 }
354 if (receive || (bcs->mode == L1_MODE_TRANS)) {
355 WaitForBusy(cs);
356 z1 = ReadZReg(bcs, HFC_Z1 | HFC_REC | HFC_CHANNEL(bcs->channel));
357 z2 = ReadZReg(bcs, HFC_Z2 | HFC_REC | HFC_CHANNEL(bcs->channel));
358 rcnt = z1 - z2;
359 if (rcnt < 0)
360 rcnt += cs->hw.hfc.fifosize;
361 if ((bcs->mode == L1_MODE_HDLC) || (rcnt)) {
362 rcnt++;
363 if (cs->debug & L1_DEB_HSCX)
364 debugl1(cs, "hfc rec %d z1(%x) z2(%x) cnt(%d)",
365 bcs->channel, z1, z2, rcnt);
366 /* sti(); */
367 if ((skb = hfc_empty_fifo(bcs, rcnt))) {
368 skb_queue_tail(&bcs->rqueue, skb);
369 schedule_event(bcs, B_RCVBUFREADY);
370 }
371 }
372 receive = 1;
373 }
374 if (bcs->tx_skb) {
375 transmit = 1;
376 test_and_set_bit(BC_FLG_BUSY, &bcs->Flag);
377 hfc_fill_fifo(bcs);
378 if (test_bit(BC_FLG_BUSY, &bcs->Flag))
379 transmit = 0;
380 } else {
381 if ((bcs->tx_skb = skb_dequeue(&bcs->squeue))) {
382 transmit = 1;
383 test_and_set_bit(BC_FLG_BUSY, &bcs->Flag);
384 hfc_fill_fifo(bcs);
385 if (test_bit(BC_FLG_BUSY, &bcs->Flag))
386 transmit = 0;
387 } else {
388 transmit = 0;
389 schedule_event(bcs, B_XMTBUFREADY);
390 }
391 }
392 if ((receive || transmit) && count)
393 goto Begin;
394 return;
395 }
396
397 void
398 mode_hfc(struct BCState *bcs, int mode, int bc)
399 {
400 struct IsdnCardState *cs = bcs->cs;
401
402 if (cs->debug & L1_DEB_HSCX)
403 debugl1(cs, "HFC 2BS0 mode %d bchan %d/%d",
404 mode, bc, bcs->channel);
405 bcs->mode = mode;
406 bcs->channel = bc;
407
408 switch (mode) {
409 case (L1_MODE_NULL):
410 if (bc) {
411 cs->hw.hfc.ctmt &= ~1;
412 cs->hw.hfc.isac_spcr &= ~0x03;
413 }
414 else {
415 cs->hw.hfc.ctmt &= ~2;
416 cs->hw.hfc.isac_spcr &= ~0x0c;
417 }
418 break;
419 case (L1_MODE_TRANS):
420 cs->hw.hfc.ctmt &= ~(1 << bc); /* set HDLC mode */
421 cs->BC_Write_Reg(cs, HFC_STATUS, cs->hw.hfc.ctmt, cs->hw.hfc.ctmt);
422 hfc_clear_fifo(bcs); /* complete fifo clear */
423 if (bc) {
424 cs->hw.hfc.ctmt |= 1;
425 cs->hw.hfc.isac_spcr &= ~0x03;
426 cs->hw.hfc.isac_spcr |= 0x02;
427 } else {
428 cs->hw.hfc.ctmt |= 2;
429 cs->hw.hfc.isac_spcr &= ~0x0c;
430 cs->hw.hfc.isac_spcr |= 0x08;
431 }
432 break;
433 case (L1_MODE_HDLC):
434 if (bc) {
435 cs->hw.hfc.ctmt &= ~1;
436 cs->hw.hfc.isac_spcr &= ~0x03;
437 cs->hw.hfc.isac_spcr |= 0x02;
438 } else {
439 cs->hw.hfc.ctmt &= ~2;
440 cs->hw.hfc.isac_spcr &= ~0x0c;
441 cs->hw.hfc.isac_spcr |= 0x08;
442 }
443 break;
444 }
445 cs->BC_Write_Reg(cs, HFC_STATUS, cs->hw.hfc.ctmt, cs->hw.hfc.ctmt);
446 cs->writeisac(cs, ISAC_SPCR, cs->hw.hfc.isac_spcr);
447 if (mode == L1_MODE_HDLC)
448 hfc_clear_fifo(bcs);
449 }
450
451 static void
452 hfc_l2l1(struct PStack *st, int pr, void *arg)
453 {
454 struct BCState *bcs = st->l1.bcs;
455 struct sk_buff *skb = arg;
456 u_long flags;
457
458 switch (pr) {
459 case (PH_DATA | REQUEST):
460 spin_lock_irqsave(&bcs->cs->lock, flags);
461 if (bcs->tx_skb) {
462 skb_queue_tail(&bcs->squeue, skb);
463 } else {
464 bcs->tx_skb = skb;
465 test_and_set_bit(BC_FLG_BUSY, &bcs->Flag);
466 bcs->cs->BC_Send_Data(bcs);
467 }
468 spin_unlock_irqrestore(&bcs->cs->lock, flags);
469 break;
470 case (PH_PULL | INDICATION):
471 spin_lock_irqsave(&bcs->cs->lock, flags);
472 if (bcs->tx_skb) {
473 printk(KERN_WARNING "hfc_l2l1: this shouldn't happen\n");
474 } else {
475 test_and_set_bit(BC_FLG_BUSY, &bcs->Flag);
476 bcs->tx_skb = skb;
477 bcs->cs->BC_Send_Data(bcs);
478 }
479 spin_unlock_irqrestore(&bcs->cs->lock, flags);
480 break;
481 case (PH_PULL | REQUEST):
482 if (!bcs->tx_skb) {
483 test_and_clear_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
484 st->l1.l1l2(st, PH_PULL | CONFIRM, NULL);
485 } else
486 test_and_set_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
487 break;
488 case (PH_ACTIVATE | REQUEST):
489 spin_lock_irqsave(&bcs->cs->lock, flags);
490 test_and_set_bit(BC_FLG_ACTIV, &bcs->Flag);
491 mode_hfc(bcs, st->l1.mode, st->l1.bc);
492 spin_unlock_irqrestore(&bcs->cs->lock, flags);
493 l1_msg_b(st, pr, arg);
494 break;
495 case (PH_DEACTIVATE | REQUEST):
496 l1_msg_b(st, pr, arg);
497 break;
498 case (PH_DEACTIVATE | CONFIRM):
499 spin_lock_irqsave(&bcs->cs->lock, flags);
500 test_and_clear_bit(BC_FLG_ACTIV, &bcs->Flag);
501 test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
502 mode_hfc(bcs, 0, st->l1.bc);
503 spin_unlock_irqrestore(&bcs->cs->lock, flags);
504 st->l1.l1l2(st, PH_DEACTIVATE | CONFIRM, NULL);
505 break;
506 }
507 }
508
509
510 void
511 close_hfcstate(struct BCState *bcs)
512 {
513 mode_hfc(bcs, 0, bcs->channel);
514 if (test_bit(BC_FLG_INIT, &bcs->Flag)) {
515 skb_queue_purge(&bcs->rqueue);
516 skb_queue_purge(&bcs->squeue);
517 if (bcs->tx_skb) {
518 dev_kfree_skb_any(bcs->tx_skb);
519 bcs->tx_skb = NULL;
520 test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
521 }
522 }
523 test_and_clear_bit(BC_FLG_INIT, &bcs->Flag);
524 }
525
526 static int
527 open_hfcstate(struct IsdnCardState *cs, struct BCState *bcs)
528 {
529 if (!test_and_set_bit(BC_FLG_INIT, &bcs->Flag)) {
530 skb_queue_head_init(&bcs->rqueue);
531 skb_queue_head_init(&bcs->squeue);
532 }
533 bcs->tx_skb = NULL;
534 test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
535 bcs->event = 0;
536 bcs->tx_cnt = 0;
537 return (0);
538 }
539
540 int
541 setstack_hfc(struct PStack *st, struct BCState *bcs)
542 {
543 bcs->channel = st->l1.bc;
544 if (open_hfcstate(st->l1.hardware, bcs))
545 return (-1);
546 st->l1.bcs = bcs;
547 st->l2.l2l1 = hfc_l2l1;
548 setstack_manager(st);
549 bcs->st = st;
550 setstack_l1_B(st);
551 return (0);
552 }
553
554 void __init
555 init_send(struct BCState *bcs)
556 {
557 int i;
558
559 if (!(bcs->hw.hfc.send = kmalloc(32 * sizeof(unsigned int), GFP_ATOMIC))) {
560 printk(KERN_WARNING
561 "HiSax: No memory for hfc.send\n");
562 return;
563 }
564 for (i = 0; i < 32; i++)
565 bcs->hw.hfc.send[i] = 0x1fff;
566 }
567
568 void __init
569 inithfc(struct IsdnCardState *cs)
570 {
571 init_send(&cs->bcs[0]);
572 init_send(&cs->bcs[1]);
573 cs->BC_Send_Data = &hfc_fill_fifo;
574 cs->bcs[0].BC_SetStack = setstack_hfc;
575 cs->bcs[1].BC_SetStack = setstack_hfc;
576 cs->bcs[0].BC_Close = close_hfcstate;
577 cs->bcs[1].BC_Close = close_hfcstate;
578 mode_hfc(cs->bcs, 0, 0);
579 mode_hfc(cs->bcs + 1, 0, 0);
580 }
581
582 void
583 releasehfc(struct IsdnCardState *cs)
584 {
585 if (cs->bcs[0].hw.hfc.send) {
586 kfree(cs->bcs[0].hw.hfc.send);
587 cs->bcs[0].hw.hfc.send = NULL;
588 }
589 if (cs->bcs[1].hw.hfc.send) {
590 kfree(cs->bcs[1].hw.hfc.send);
591 cs->bcs[1].hw.hfc.send = NULL;
592 }
593 }
Verdex Pro support