?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
[TG3]: Set minimal hw interrupt mitigation.
[linux-2.6/verdex.git] / drivers / isdn / hisax / hfc_pci.c
blobc2db52696a86bb2350261556116877aa1fe8e06c
1 /* $Id: hfc_pci.c,v 1.48.2.4 2004/02/11 13:21:33 keil Exp $
2 *
3 * low level driver for CCD´s hfc-pci based cards
4 *
5 * Author Werner Cornelius
6 * based on existing driver for CCD hfc ISA cards
7 * Copyright by Werner Cornelius <werner@isdn4linux.de>
8 * by Karsten Keil <keil@isdn4linux.de>
9 *
10 * This software may be used and distributed according to the terms
11 * of the GNU General Public License, incorporated herein by reference.
12 *
13 * For changes and modifications please read
14 * Documentation/isdn/HiSax.cert
15 *
16 */
17
18 #include <linux/init.h>
19 #include <linux/config.h>
20 #include "hisax.h"
21 #include "hfc_pci.h"
22 #include "isdnl1.h"
23 #include <linux/pci.h>
24 #include <linux/interrupt.h>
25
26 extern const char *CardType[];
27
28 static const char *hfcpci_revision = "$Revision: 1.48.2.4 $";
29
30 /* table entry in the PCI devices list */
31 typedef struct {
32 int vendor_id;
33 int device_id;
34 char *vendor_name;
35 char *card_name;
36 } PCI_ENTRY;
37
38 #define NT_T1_COUNT 20 /* number of 3.125ms interrupts for G2 timeout */
39 #define CLKDEL_TE 0x0e /* CLKDEL in TE mode */
40 #define CLKDEL_NT 0x6c /* CLKDEL in NT mode */
41
42 static const PCI_ENTRY id_list[] =
43 {
44 {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_2BD0, "CCD/Billion/Asuscom", "2BD0"},
45 {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_B000, "Billion", "B000"},
46 {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_B006, "Billion", "B006"},
47 {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_B007, "Billion", "B007"},
48 {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_B008, "Billion", "B008"},
49 {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_B009, "Billion", "B009"},
50 {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_B00A, "Billion", "B00A"},
51 {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_B00B, "Billion", "B00B"},
52 {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_B00C, "Billion", "B00C"},
53 {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_B100, "Seyeon", "B100"},
54 {PCI_VENDOR_ID_ABOCOM, PCI_DEVICE_ID_ABOCOM_2BD1, "Abocom/Magitek", "2BD1"},
55 {PCI_VENDOR_ID_ASUSTEK, PCI_DEVICE_ID_ASUSTEK_0675, "Asuscom/Askey", "675"},
56 {PCI_VENDOR_ID_BERKOM, PCI_DEVICE_ID_BERKOM_T_CONCEPT, "German telekom", "T-Concept"},
57 {PCI_VENDOR_ID_BERKOM, PCI_DEVICE_ID_BERKOM_A1T, "German telekom", "A1T"},
58 {PCI_VENDOR_ID_ANIGMA, PCI_DEVICE_ID_ANIGMA_MC145575, "Motorola MC145575", "MC145575"},
59 {PCI_VENDOR_ID_ZOLTRIX, PCI_DEVICE_ID_ZOLTRIX_2BD0, "Zoltrix", "2BD0"},
60 {PCI_VENDOR_ID_DIGI, PCI_DEVICE_ID_DIGI_DF_M_IOM2_E,"Digi International", "Digi DataFire Micro V IOM2 (Europe)"},
61 {PCI_VENDOR_ID_DIGI, PCI_DEVICE_ID_DIGI_DF_M_E,"Digi International", "Digi DataFire Micro V (Europe)"},
62 {PCI_VENDOR_ID_DIGI, PCI_DEVICE_ID_DIGI_DF_M_IOM2_A,"Digi International", "Digi DataFire Micro V IOM2 (North America)"},
63 {PCI_VENDOR_ID_DIGI, PCI_DEVICE_ID_DIGI_DF_M_A,"Digi International", "Digi DataFire Micro V (North America)"},
64 {0, 0, NULL, NULL},
65 };
66
67
68 #ifdef CONFIG_PCI
69
70 /******************************************/
71 /* free hardware resources used by driver */
72 /******************************************/
73 void
74 release_io_hfcpci(struct IsdnCardState *cs)
75 {
76 printk(KERN_INFO "HiSax: release hfcpci at %p\n",
77 cs->hw.hfcpci.pci_io);
78 cs->hw.hfcpci.int_m2 = 0; /* interrupt output off ! */
79 Write_hfc(cs, HFCPCI_INT_M2, cs->hw.hfcpci.int_m2);
80 Write_hfc(cs, HFCPCI_CIRM, HFCPCI_RESET); /* Reset On */
81 mdelay(10);
82 Write_hfc(cs, HFCPCI_CIRM, 0); /* Reset Off */
83 mdelay(10);
84 Write_hfc(cs, HFCPCI_INT_M2, cs->hw.hfcpci.int_m2);
85 pci_write_config_word(cs->hw.hfcpci.dev, PCI_COMMAND, 0); /* disable memory mapped ports + busmaster */
86 del_timer(&cs->hw.hfcpci.timer);
87 kfree(cs->hw.hfcpci.share_start);
88 cs->hw.hfcpci.share_start = NULL;
89 iounmap((void *)cs->hw.hfcpci.pci_io);
90 }
91
92 /********************************************************************************/
93 /* function called to reset the HFC PCI chip. A complete software reset of chip */
94 /* and fifos is done. */
95 /********************************************************************************/
96 static void
97 reset_hfcpci(struct IsdnCardState *cs)
98 {
99 pci_write_config_word(cs->hw.hfcpci.dev, PCI_COMMAND, PCI_ENA_MEMIO); /* enable memory mapped ports, disable busmaster */
100 cs->hw.hfcpci.int_m2 = 0; /* interrupt output off ! */
101 Write_hfc(cs, HFCPCI_INT_M2, cs->hw.hfcpci.int_m2);
102
103 printk(KERN_INFO "HFC_PCI: resetting card\n");
104 pci_write_config_word(cs->hw.hfcpci.dev, PCI_COMMAND, PCI_ENA_MEMIO + PCI_ENA_MASTER); /* enable memory ports + busmaster */
105 Write_hfc(cs, HFCPCI_CIRM, HFCPCI_RESET); /* Reset On */
106 mdelay(10);
107 Write_hfc(cs, HFCPCI_CIRM, 0); /* Reset Off */
108 mdelay(10);
109 if (Read_hfc(cs, HFCPCI_STATUS) & 2)
110 printk(KERN_WARNING "HFC-PCI init bit busy\n");
111
112 cs->hw.hfcpci.fifo_en = 0x30; /* only D fifos enabled */
113 Write_hfc(cs, HFCPCI_FIFO_EN, cs->hw.hfcpci.fifo_en);
114
115 cs->hw.hfcpci.trm = 0 + HFCPCI_BTRANS_THRESMASK; /* no echo connect , threshold */
116 Write_hfc(cs, HFCPCI_TRM, cs->hw.hfcpci.trm);
117
118 Write_hfc(cs, HFCPCI_CLKDEL, CLKDEL_TE); /* ST-Bit delay for TE-Mode */
119 cs->hw.hfcpci.sctrl_e = HFCPCI_AUTO_AWAKE;
120 Write_hfc(cs, HFCPCI_SCTRL_E, cs->hw.hfcpci.sctrl_e); /* S/T Auto awake */
121 cs->hw.hfcpci.bswapped = 0; /* no exchange */
122 cs->hw.hfcpci.nt_mode = 0; /* we are in TE mode */
123 cs->hw.hfcpci.ctmt = HFCPCI_TIM3_125 | HFCPCI_AUTO_TIMER;
124 Write_hfc(cs, HFCPCI_CTMT, cs->hw.hfcpci.ctmt);
125
126 cs->hw.hfcpci.int_m1 = HFCPCI_INTS_DTRANS | HFCPCI_INTS_DREC |
127 HFCPCI_INTS_L1STATE | HFCPCI_INTS_TIMER;
128 Write_hfc(cs, HFCPCI_INT_M1, cs->hw.hfcpci.int_m1);
129
130 /* Clear already pending ints */
131 if (Read_hfc(cs, HFCPCI_INT_S1));
132
133 Write_hfc(cs, HFCPCI_STATES, HFCPCI_LOAD_STATE | 2); /* HFC ST 2 */
134 udelay(10);
135 Write_hfc(cs, HFCPCI_STATES, 2); /* HFC ST 2 */
136 cs->hw.hfcpci.mst_m = HFCPCI_MASTER; /* HFC Master Mode */
137
138 Write_hfc(cs, HFCPCI_MST_MODE, cs->hw.hfcpci.mst_m);
139 cs->hw.hfcpci.sctrl = 0x40; /* set tx_lo mode, error in datasheet ! */
140 Write_hfc(cs, HFCPCI_SCTRL, cs->hw.hfcpci.sctrl);
141 cs->hw.hfcpci.sctrl_r = 0;
142 Write_hfc(cs, HFCPCI_SCTRL_R, cs->hw.hfcpci.sctrl_r);
143
144 /* Init GCI/IOM2 in master mode */
145 /* Slots 0 and 1 are set for B-chan 1 and 2 */
146 /* D- and monitor/CI channel are not enabled */
147 /* STIO1 is used as output for data, B1+B2 from ST->IOM+HFC */
148 /* STIO2 is used as data input, B1+B2 from IOM->ST */
149 /* ST B-channel send disabled -> continous 1s */
150 /* The IOM slots are always enabled */
151 cs->hw.hfcpci.conn = 0x36; /* set data flow directions */
152 Write_hfc(cs, HFCPCI_CONNECT, cs->hw.hfcpci.conn);
153 Write_hfc(cs, HFCPCI_B1_SSL, 0x80); /* B1-Slot 0 STIO1 out enabled */
154 Write_hfc(cs, HFCPCI_B2_SSL, 0x81); /* B2-Slot 1 STIO1 out enabled */
155 Write_hfc(cs, HFCPCI_B1_RSL, 0x80); /* B1-Slot 0 STIO2 in enabled */
156 Write_hfc(cs, HFCPCI_B2_RSL, 0x81); /* B2-Slot 1 STIO2 in enabled */
157
158 /* Finally enable IRQ output */
159 cs->hw.hfcpci.int_m2 = HFCPCI_IRQ_ENABLE;
160 Write_hfc(cs, HFCPCI_INT_M2, cs->hw.hfcpci.int_m2);
161 if (Read_hfc(cs, HFCPCI_INT_S1));
162 }
163
164 /***************************************************/
165 /* Timer function called when kernel timer expires */
166 /***************************************************/
167 static void
168 hfcpci_Timer(struct IsdnCardState *cs)
169 {
170 cs->hw.hfcpci.timer.expires = jiffies + 75;
171 /* WD RESET */
172 /* WriteReg(cs, HFCD_DATA, HFCD_CTMT, cs->hw.hfcpci.ctmt | 0x80);
173 add_timer(&cs->hw.hfcpci.timer);
174 */
175 }
176
177
178 /*********************************/
179 /* schedule a new D-channel task */
180 /*********************************/
181 static void
182 sched_event_D_pci(struct IsdnCardState *cs, int event)
183 {
184 test_and_set_bit(event, &cs->event);
185 schedule_work(&cs->tqueue);
186 }
187
188 /*********************************/
189 /* schedule a new b_channel task */
190 /*********************************/
191 static void
192 hfcpci_sched_event(struct BCState *bcs, int event)
193 {
194 test_and_set_bit(event, &bcs->event);
195 schedule_work(&bcs->tqueue);
196 }
197
198 /************************************************/
199 /* select a b-channel entry matching and active */
200 /************************************************/
201 static
202 struct BCState *
203 Sel_BCS(struct IsdnCardState *cs, int channel)
204 {
205 if (cs->bcs[0].mode && (cs->bcs[0].channel == channel))
206 return (&cs->bcs[0]);
207 else if (cs->bcs[1].mode && (cs->bcs[1].channel == channel))
208 return (&cs->bcs[1]);
209 else
210 return (NULL);
211 }
212
213 /***************************************/
214 /* clear the desired B-channel rx fifo */
215 /***************************************/
216 static void hfcpci_clear_fifo_rx(struct IsdnCardState *cs, int fifo)
217 { u_char fifo_state;
218 bzfifo_type *bzr;
219
220 if (fifo) {
221 bzr = &((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.rxbz_b2;
222 fifo_state = cs->hw.hfcpci.fifo_en & HFCPCI_FIFOEN_B2RX;
223 } else {
224 bzr = &((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.rxbz_b1;
225 fifo_state = cs->hw.hfcpci.fifo_en & HFCPCI_FIFOEN_B1RX;
226 }
227 if (fifo_state)
228 cs->hw.hfcpci.fifo_en ^= fifo_state;
229 Write_hfc(cs, HFCPCI_FIFO_EN, cs->hw.hfcpci.fifo_en);
230 cs->hw.hfcpci.last_bfifo_cnt[fifo] = 0;
231 bzr->za[MAX_B_FRAMES].z1 = B_FIFO_SIZE + B_SUB_VAL - 1;
232 bzr->za[MAX_B_FRAMES].z2 = bzr->za[MAX_B_FRAMES].z1;
233 bzr->f1 = MAX_B_FRAMES;
234 bzr->f2 = bzr->f1; /* init F pointers to remain constant */
235 if (fifo_state)
236 cs->hw.hfcpci.fifo_en |= fifo_state;
237 Write_hfc(cs, HFCPCI_FIFO_EN, cs->hw.hfcpci.fifo_en);
238 }
239
240 /***************************************/
241 /* clear the desired B-channel tx fifo */
242 /***************************************/
243 static void hfcpci_clear_fifo_tx(struct IsdnCardState *cs, int fifo)
244 { u_char fifo_state;
245 bzfifo_type *bzt;
246
247 if (fifo) {
248 bzt = &((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.txbz_b2;
249 fifo_state = cs->hw.hfcpci.fifo_en & HFCPCI_FIFOEN_B2TX;
250 } else {
251 bzt = &((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.txbz_b1;
252 fifo_state = cs->hw.hfcpci.fifo_en & HFCPCI_FIFOEN_B1TX;
253 }
254 if (fifo_state)
255 cs->hw.hfcpci.fifo_en ^= fifo_state;
256 Write_hfc(cs, HFCPCI_FIFO_EN, cs->hw.hfcpci.fifo_en);
257 bzt->za[MAX_B_FRAMES].z1 = B_FIFO_SIZE + B_SUB_VAL - 1;
258 bzt->za[MAX_B_FRAMES].z2 = bzt->za[MAX_B_FRAMES].z1;
259 bzt->f1 = MAX_B_FRAMES;
260 bzt->f2 = bzt->f1; /* init F pointers to remain constant */
261 if (fifo_state)
262 cs->hw.hfcpci.fifo_en |= fifo_state;
263 Write_hfc(cs, HFCPCI_FIFO_EN, cs->hw.hfcpci.fifo_en);
264 }
265
266 /*********************************************/
267 /* read a complete B-frame out of the buffer */
268 /*********************************************/
269 static struct sk_buff
270 *
271 hfcpci_empty_fifo(struct BCState *bcs, bzfifo_type * bz, u_char * bdata, int count)
272 {
273 u_char *ptr, *ptr1, new_f2;
274 struct sk_buff *skb;
275 struct IsdnCardState *cs = bcs->cs;
276 int total, maxlen, new_z2;
277 z_type *zp;
278
279 if ((cs->debug & L1_DEB_HSCX) && !(cs->debug & L1_DEB_HSCX_FIFO))
280 debugl1(cs, "hfcpci_empty_fifo");
281 zp = &bz->za[bz->f2]; /* point to Z-Regs */
282 new_z2 = zp->z2 + count; /* new position in fifo */
283 if (new_z2 >= (B_FIFO_SIZE + B_SUB_VAL))
284 new_z2 -= B_FIFO_SIZE; /* buffer wrap */
285 new_f2 = (bz->f2 + 1) & MAX_B_FRAMES;
286 if ((count > HSCX_BUFMAX + 3) || (count < 4) ||
287 (*(bdata + (zp->z1 - B_SUB_VAL)))) {
288 if (cs->debug & L1_DEB_WARN)
289 debugl1(cs, "hfcpci_empty_fifo: incoming packet invalid length %d or crc", count);
290 #ifdef ERROR_STATISTIC
291 bcs->err_inv++;
292 #endif
293 bz->za[new_f2].z2 = new_z2;
294 bz->f2 = new_f2; /* next buffer */
295 skb = NULL;
296 } else if (!(skb = dev_alloc_skb(count - 3)))
297 printk(KERN_WARNING "HFCPCI: receive out of memory\n");
298 else {
299 total = count;
300 count -= 3;
301 ptr = skb_put(skb, count);
302
303 if (zp->z2 + count <= B_FIFO_SIZE + B_SUB_VAL)
304 maxlen = count; /* complete transfer */
305 else
306 maxlen = B_FIFO_SIZE + B_SUB_VAL - zp->z2; /* maximum */
307
308 ptr1 = bdata + (zp->z2 - B_SUB_VAL); /* start of data */
309 memcpy(ptr, ptr1, maxlen); /* copy data */
310 count -= maxlen;
311
312 if (count) { /* rest remaining */
313 ptr += maxlen;
314 ptr1 = bdata; /* start of buffer */
315 memcpy(ptr, ptr1, count); /* rest */
316 }
317 bz->za[new_f2].z2 = new_z2;
318 bz->f2 = new_f2; /* next buffer */
319
320 }
321 return (skb);
322 }
323
324 /*******************************/
325 /* D-channel receive procedure */
326 /*******************************/
327 static
328 int
329 receive_dmsg(struct IsdnCardState *cs)
330 {
331 struct sk_buff *skb;
332 int maxlen;
333 int rcnt, total;
334 int count = 5;
335 u_char *ptr, *ptr1;
336 dfifo_type *df;
337 z_type *zp;
338
339 df = &((fifo_area *) (cs->hw.hfcpci.fifos))->d_chan.d_rx;
340 if (test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
341 debugl1(cs, "rec_dmsg blocked");
342 return (1);
343 }
344 while (((df->f1 & D_FREG_MASK) != (df->f2 & D_FREG_MASK)) && count--) {
345 zp = &df->za[df->f2 & D_FREG_MASK];
346 rcnt = zp->z1 - zp->z2;
347 if (rcnt < 0)
348 rcnt += D_FIFO_SIZE;
349 rcnt++;
350 if (cs->debug & L1_DEB_ISAC)
351 debugl1(cs, "hfcpci recd f1(%d) f2(%d) z1(%x) z2(%x) cnt(%d)",
352 df->f1, df->f2, zp->z1, zp->z2, rcnt);
353
354 if ((rcnt > MAX_DFRAME_LEN + 3) || (rcnt < 4) ||
355 (df->data[zp->z1])) {
356 if (cs->debug & L1_DEB_WARN)
357 debugl1(cs, "empty_fifo hfcpci paket inv. len %d or crc %d", rcnt, df->data[zp->z1]);
358 #ifdef ERROR_STATISTIC
359 cs->err_rx++;
360 #endif
361 df->f2 = ((df->f2 + 1) & MAX_D_FRAMES) | (MAX_D_FRAMES + 1); /* next buffer */
362 df->za[df->f2 & D_FREG_MASK].z2 = (zp->z2 + rcnt) & (D_FIFO_SIZE - 1);
363 } else if ((skb = dev_alloc_skb(rcnt - 3))) {
364 total = rcnt;
365 rcnt -= 3;
366 ptr = skb_put(skb, rcnt);
367
368 if (zp->z2 + rcnt <= D_FIFO_SIZE)
369 maxlen = rcnt; /* complete transfer */
370 else
371 maxlen = D_FIFO_SIZE - zp->z2; /* maximum */
372
373 ptr1 = df->data + zp->z2; /* start of data */
374 memcpy(ptr, ptr1, maxlen); /* copy data */
375 rcnt -= maxlen;
376
377 if (rcnt) { /* rest remaining */
378 ptr += maxlen;
379 ptr1 = df->data; /* start of buffer */
380 memcpy(ptr, ptr1, rcnt); /* rest */
381 }
382 df->f2 = ((df->f2 + 1) & MAX_D_FRAMES) | (MAX_D_FRAMES + 1); /* next buffer */
383 df->za[df->f2 & D_FREG_MASK].z2 = (zp->z2 + total) & (D_FIFO_SIZE - 1);
384
385 skb_queue_tail(&cs->rq, skb);
386 sched_event_D_pci(cs, D_RCVBUFREADY);
387 } else
388 printk(KERN_WARNING "HFC-PCI: D receive out of memory\n");
389 }
390 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
391 return (1);
392 }
393
394 /*******************************************************************************/
395 /* check for transparent receive data and read max one threshold size if avail */
396 /*******************************************************************************/
397 int
398 hfcpci_empty_fifo_trans(struct BCState *bcs, bzfifo_type * bz, u_char * bdata)
399 {
400 unsigned short *z1r, *z2r;
401 int new_z2, fcnt, maxlen;
402 struct sk_buff *skb;
403 u_char *ptr, *ptr1;
404
405 z1r = &bz->za[MAX_B_FRAMES].z1; /* pointer to z reg */
406 z2r = z1r + 1;
407
408 if (!(fcnt = *z1r - *z2r))
409 return (0); /* no data avail */
410
411 if (fcnt <= 0)
412 fcnt += B_FIFO_SIZE; /* bytes actually buffered */
413 if (fcnt > HFCPCI_BTRANS_THRESHOLD)
414 fcnt = HFCPCI_BTRANS_THRESHOLD; /* limit size */
415
416 new_z2 = *z2r + fcnt; /* new position in fifo */
417 if (new_z2 >= (B_FIFO_SIZE + B_SUB_VAL))
418 new_z2 -= B_FIFO_SIZE; /* buffer wrap */
419
420 if (!(skb = dev_alloc_skb(fcnt)))
421 printk(KERN_WARNING "HFCPCI: receive out of memory\n");
422 else {
423 ptr = skb_put(skb, fcnt);
424 if (*z2r + fcnt <= B_FIFO_SIZE + B_SUB_VAL)
425 maxlen = fcnt; /* complete transfer */
426 else
427 maxlen = B_FIFO_SIZE + B_SUB_VAL - *z2r; /* maximum */
428
429 ptr1 = bdata + (*z2r - B_SUB_VAL); /* start of data */
430 memcpy(ptr, ptr1, maxlen); /* copy data */
431 fcnt -= maxlen;
432
433 if (fcnt) { /* rest remaining */
434 ptr += maxlen;
435 ptr1 = bdata; /* start of buffer */
436 memcpy(ptr, ptr1, fcnt); /* rest */
437 }
438 skb_queue_tail(&bcs->rqueue, skb);
439 hfcpci_sched_event(bcs, B_RCVBUFREADY);
440 }
441
442 *z2r = new_z2; /* new position */
443 return (1);
444 } /* hfcpci_empty_fifo_trans */
445
446 /**********************************/
447 /* B-channel main receive routine */
448 /**********************************/
449 void
450 main_rec_hfcpci(struct BCState *bcs)
451 {
452 struct IsdnCardState *cs = bcs->cs;
453 int rcnt, real_fifo;
454 int receive, count = 5;
455 struct sk_buff *skb;
456 bzfifo_type *bz;
457 u_char *bdata;
458 z_type *zp;
459
460
461 if ((bcs->channel) && (!cs->hw.hfcpci.bswapped)) {
462 bz = &((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.rxbz_b2;
463 bdata = ((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.rxdat_b2;
464 real_fifo = 1;
465 } else {
466 bz = &((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.rxbz_b1;
467 bdata = ((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.rxdat_b1;
468 real_fifo = 0;
469 }
470 Begin:
471 count--;
472 if (test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
473 debugl1(cs, "rec_data %d blocked", bcs->channel);
474 return;
475 }
476 if (bz->f1 != bz->f2) {
477 if (cs->debug & L1_DEB_HSCX)
478 debugl1(cs, "hfcpci rec %d f1(%d) f2(%d)",
479 bcs->channel, bz->f1, bz->f2);
480 zp = &bz->za[bz->f2];
481
482 rcnt = zp->z1 - zp->z2;
483 if (rcnt < 0)
484 rcnt += B_FIFO_SIZE;
485 rcnt++;
486 if (cs->debug & L1_DEB_HSCX)
487 debugl1(cs, "hfcpci rec %d z1(%x) z2(%x) cnt(%d)",
488 bcs->channel, zp->z1, zp->z2, rcnt);
489 if ((skb = hfcpci_empty_fifo(bcs, bz, bdata, rcnt))) {
490 skb_queue_tail(&bcs->rqueue, skb);
491 hfcpci_sched_event(bcs, B_RCVBUFREADY);
492 }
493 rcnt = bz->f1 - bz->f2;
494 if (rcnt < 0)
495 rcnt += MAX_B_FRAMES + 1;
496 if (cs->hw.hfcpci.last_bfifo_cnt[real_fifo] > rcnt + 1) {
497 rcnt = 0;
498 hfcpci_clear_fifo_rx(cs, real_fifo);
499 }
500 cs->hw.hfcpci.last_bfifo_cnt[real_fifo] = rcnt;
501 if (rcnt > 1)
502 receive = 1;
503 else
504 receive = 0;
505 } else if (bcs->mode == L1_MODE_TRANS)
506 receive = hfcpci_empty_fifo_trans(bcs, bz, bdata);
507 else
508 receive = 0;
509 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
510 if (count && receive)
511 goto Begin;
512 return;
513 }
514
515 /**************************/
516 /* D-channel send routine */
517 /**************************/
518 static void
519 hfcpci_fill_dfifo(struct IsdnCardState *cs)
520 {
521 int fcnt;
522 int count, new_z1, maxlen;
523 dfifo_type *df;
524 u_char *src, *dst, new_f1;
525
526 if (!cs->tx_skb)
527 return;
528 if (cs->tx_skb->len <= 0)
529 return;
530
531 df = &((fifo_area *) (cs->hw.hfcpci.fifos))->d_chan.d_tx;
532
533 if (cs->debug & L1_DEB_ISAC)
534 debugl1(cs, "hfcpci_fill_Dfifo f1(%d) f2(%d) z1(f1)(%x)",
535 df->f1, df->f2,
536 df->za[df->f1 & D_FREG_MASK].z1);
537 fcnt = df->f1 - df->f2; /* frame count actually buffered */
538 if (fcnt < 0)
539 fcnt += (MAX_D_FRAMES + 1); /* if wrap around */
540 if (fcnt > (MAX_D_FRAMES - 1)) {
541 if (cs->debug & L1_DEB_ISAC)
542 debugl1(cs, "hfcpci_fill_Dfifo more as 14 frames");
543 #ifdef ERROR_STATISTIC
544 cs->err_tx++;
545 #endif
546 return;
547 }
548 /* now determine free bytes in FIFO buffer */
549 count = df->za[df->f2 & D_FREG_MASK].z2 - df->za[df->f1 & D_FREG_MASK].z1 - 1;
550 if (count <= 0)
551 count += D_FIFO_SIZE; /* count now contains available bytes */
552
553 if (cs->debug & L1_DEB_ISAC)
554 debugl1(cs, "hfcpci_fill_Dfifo count(%ld/%d)",
555 cs->tx_skb->len, count);
556 if (count < cs->tx_skb->len) {
557 if (cs->debug & L1_DEB_ISAC)
558 debugl1(cs, "hfcpci_fill_Dfifo no fifo mem");
559 return;
560 }
561 count = cs->tx_skb->len; /* get frame len */
562 new_z1 = (df->za[df->f1 & D_FREG_MASK].z1 + count) & (D_FIFO_SIZE - 1);
563 new_f1 = ((df->f1 + 1) & D_FREG_MASK) | (D_FREG_MASK + 1);
564 src = cs->tx_skb->data; /* source pointer */
565 dst = df->data + df->za[df->f1 & D_FREG_MASK].z1;
566 maxlen = D_FIFO_SIZE - df->za[df->f1 & D_FREG_MASK].z1; /* end fifo */
567 if (maxlen > count)
568 maxlen = count; /* limit size */
569 memcpy(dst, src, maxlen); /* first copy */
570
571 count -= maxlen; /* remaining bytes */
572 if (count) {
573 dst = df->data; /* start of buffer */
574 src += maxlen; /* new position */
575 memcpy(dst, src, count);
576 }
577 df->za[new_f1 & D_FREG_MASK].z1 = new_z1; /* for next buffer */
578 df->za[df->f1 & D_FREG_MASK].z1 = new_z1; /* new pos actual buffer */
579 df->f1 = new_f1; /* next frame */
580
581 dev_kfree_skb_any(cs->tx_skb);
582 cs->tx_skb = NULL;
583 return;
584 }
585
586 /**************************/
587 /* B-channel send routine */
588 /**************************/
589 static void
590 hfcpci_fill_fifo(struct BCState *bcs)
591 {
592 struct IsdnCardState *cs = bcs->cs;
593 int maxlen, fcnt;
594 int count, new_z1;
595 bzfifo_type *bz;
596 u_char *bdata;
597 u_char new_f1, *src, *dst;
598 unsigned short *z1t, *z2t;
599
600 if (!bcs->tx_skb)
601 return;
602 if (bcs->tx_skb->len <= 0)
603 return;
604
605 if ((bcs->channel) && (!cs->hw.hfcpci.bswapped)) {
606 bz = &((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.txbz_b2;
607 bdata = ((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.txdat_b2;
608 } else {
609 bz = &((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.txbz_b1;
610 bdata = ((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.txdat_b1;
611 }
612
613 if (bcs->mode == L1_MODE_TRANS) {
614 z1t = &bz->za[MAX_B_FRAMES].z1;
615 z2t = z1t + 1;
616 if (cs->debug & L1_DEB_HSCX)
617 debugl1(cs, "hfcpci_fill_fifo_trans %d z1(%x) z2(%x)",
618 bcs->channel, *z1t, *z2t);
619 fcnt = *z2t - *z1t;
620 if (fcnt <= 0)
621 fcnt += B_FIFO_SIZE; /* fcnt contains available bytes in fifo */
622 fcnt = B_FIFO_SIZE - fcnt; /* remaining bytes to send */
623
624 while ((fcnt < 2 * HFCPCI_BTRANS_THRESHOLD) && (bcs->tx_skb)) {
625 if (bcs->tx_skb->len < B_FIFO_SIZE - fcnt) {
626 /* data is suitable for fifo */
627 count = bcs->tx_skb->len;
628
629 new_z1 = *z1t + count; /* new buffer Position */
630 if (new_z1 >= (B_FIFO_SIZE + B_SUB_VAL))
631 new_z1 -= B_FIFO_SIZE; /* buffer wrap */
632 src = bcs->tx_skb->data; /* source pointer */
633 dst = bdata + (*z1t - B_SUB_VAL);
634 maxlen = (B_FIFO_SIZE + B_SUB_VAL) - *z1t; /* end of fifo */
635 if (maxlen > count)
636 maxlen = count; /* limit size */
637 memcpy(dst, src, maxlen); /* first copy */
638
639 count -= maxlen; /* remaining bytes */
640 if (count) {
641 dst = bdata; /* start of buffer */
642 src += maxlen; /* new position */
643 memcpy(dst, src, count);
644 }
645 bcs->tx_cnt -= bcs->tx_skb->len;
646 fcnt += bcs->tx_skb->len;
647 *z1t = new_z1; /* now send data */
648 } else if (cs->debug & L1_DEB_HSCX)
649 debugl1(cs, "hfcpci_fill_fifo_trans %d frame length %d discarded",
650 bcs->channel, bcs->tx_skb->len);
651
652 if (test_bit(FLG_LLI_L1WAKEUP,&bcs->st->lli.flag) &&
653 (PACKET_NOACK != bcs->tx_skb->pkt_type)) {
654 u_long flags;
655 spin_lock_irqsave(&bcs->aclock, flags);
656 bcs->ackcnt += bcs->tx_skb->len;
657 spin_unlock_irqrestore(&bcs->aclock, flags);
658 schedule_event(bcs, B_ACKPENDING);
659 }
660
661 dev_kfree_skb_any(bcs->tx_skb);
662 bcs->tx_skb = skb_dequeue(&bcs->squeue); /* fetch next data */
663 }
664 test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
665 return;
666 }
667 if (cs->debug & L1_DEB_HSCX)
668 debugl1(cs, "hfcpci_fill_fifo_hdlc %d f1(%d) f2(%d) z1(f1)(%x)",
669 bcs->channel, bz->f1, bz->f2,
670 bz->za[bz->f1].z1);
671
672 fcnt = bz->f1 - bz->f2; /* frame count actually buffered */
673 if (fcnt < 0)
674 fcnt += (MAX_B_FRAMES + 1); /* if wrap around */
675 if (fcnt > (MAX_B_FRAMES - 1)) {
676 if (cs->debug & L1_DEB_HSCX)
677 debugl1(cs, "hfcpci_fill_Bfifo more as 14 frames");
678 return;
679 }
680 /* now determine free bytes in FIFO buffer */
681 count = bz->za[bz->f2].z2 - bz->za[bz->f1].z1 - 1;
682 if (count <= 0)
683 count += B_FIFO_SIZE; /* count now contains available bytes */
684
685 if (cs->debug & L1_DEB_HSCX)
686 debugl1(cs, "hfcpci_fill_fifo %d count(%ld/%d),%lx",
687 bcs->channel, bcs->tx_skb->len,
688 count, current->state);
689
690 if (count < bcs->tx_skb->len) {
691 if (cs->debug & L1_DEB_HSCX)
692 debugl1(cs, "hfcpci_fill_fifo no fifo mem");
693 return;
694 }
695 count = bcs->tx_skb->len; /* get frame len */
696 new_z1 = bz->za[bz->f1].z1 + count; /* new buffer Position */
697 if (new_z1 >= (B_FIFO_SIZE + B_SUB_VAL))
698 new_z1 -= B_FIFO_SIZE; /* buffer wrap */
699
700 new_f1 = ((bz->f1 + 1) & MAX_B_FRAMES);
701 src = bcs->tx_skb->data; /* source pointer */
702 dst = bdata + (bz->za[bz->f1].z1 - B_SUB_VAL);
703 maxlen = (B_FIFO_SIZE + B_SUB_VAL) - bz->za[bz->f1].z1; /* end fifo */
704 if (maxlen > count)
705 maxlen = count; /* limit size */
706 memcpy(dst, src, maxlen); /* first copy */
707
708 count -= maxlen; /* remaining bytes */
709 if (count) {
710 dst = bdata; /* start of buffer */
711 src += maxlen; /* new position */
712 memcpy(dst, src, count);
713 }
714 bcs->tx_cnt -= bcs->tx_skb->len;
715 if (test_bit(FLG_LLI_L1WAKEUP,&bcs->st->lli.flag) &&
716 (PACKET_NOACK != bcs->tx_skb->pkt_type)) {
717 u_long flags;
718 spin_lock_irqsave(&bcs->aclock, flags);
719 bcs->ackcnt += bcs->tx_skb->len;
720 spin_unlock_irqrestore(&bcs->aclock, flags);
721 schedule_event(bcs, B_ACKPENDING);
722 }
723
724 bz->za[new_f1].z1 = new_z1; /* for next buffer */
725 bz->f1 = new_f1; /* next frame */
726
727 dev_kfree_skb_any(bcs->tx_skb);
728 bcs->tx_skb = NULL;
729 test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
730 return;
731 }
732
733 /**********************************************/
734 /* D-channel l1 state call for leased NT-mode */
735 /**********************************************/
736 static void
737 dch_nt_l2l1(struct PStack *st, int pr, void *arg)
738 {
739 struct IsdnCardState *cs = (struct IsdnCardState *) st->l1.hardware;
740
741 switch (pr) {
742 case (PH_DATA | REQUEST):
743 case (PH_PULL | REQUEST):
744 case (PH_PULL | INDICATION):
745 st->l1.l1hw(st, pr, arg);
746 break;
747 case (PH_ACTIVATE | REQUEST):
748 st->l1.l1l2(st, PH_ACTIVATE | CONFIRM, NULL);
749 break;
750 case (PH_TESTLOOP | REQUEST):
751 if (1 & (long) arg)
752 debugl1(cs, "PH_TEST_LOOP B1");
753 if (2 & (long) arg)
754 debugl1(cs, "PH_TEST_LOOP B2");
755 if (!(3 & (long) arg))
756 debugl1(cs, "PH_TEST_LOOP DISABLED");
757 st->l1.l1hw(st, HW_TESTLOOP | REQUEST, arg);
758 break;
759 default:
760 if (cs->debug)
761 debugl1(cs, "dch_nt_l2l1 msg %04X unhandled", pr);
762 break;
763 }
764 }
765
766
767
768 /***********************/
769 /* set/reset echo mode */
770 /***********************/
771 static int
772 hfcpci_auxcmd(struct IsdnCardState *cs, isdn_ctrl * ic)
773 {
774 u_long flags;
775 int i = *(unsigned int *) ic->parm.num;
776
777 if ((ic->arg == 98) &&
778 (!(cs->hw.hfcpci.int_m1 & (HFCPCI_INTS_B2TRANS + HFCPCI_INTS_B2REC + HFCPCI_INTS_B1TRANS + HFCPCI_INTS_B1REC)))) {
779 spin_lock_irqsave(&cs->lock, flags);
780 Write_hfc(cs, HFCPCI_CLKDEL, CLKDEL_NT); /* ST-Bit delay for NT-Mode */
781 Write_hfc(cs, HFCPCI_STATES, HFCPCI_LOAD_STATE | 0); /* HFC ST G0 */
782 udelay(10);
783 cs->hw.hfcpci.sctrl |= SCTRL_MODE_NT;
784 Write_hfc(cs, HFCPCI_SCTRL, cs->hw.hfcpci.sctrl); /* set NT-mode */
785 udelay(10);
786 Write_hfc(cs, HFCPCI_STATES, HFCPCI_LOAD_STATE | 1); /* HFC ST G1 */
787 udelay(10);
788 Write_hfc(cs, HFCPCI_STATES, 1 | HFCPCI_ACTIVATE | HFCPCI_DO_ACTION);
789 cs->dc.hfcpci.ph_state = 1;
790 cs->hw.hfcpci.nt_mode = 1;
791 cs->hw.hfcpci.nt_timer = 0;
792 cs->stlist->l2.l2l1 = dch_nt_l2l1;
793 spin_unlock_irqrestore(&cs->lock, flags);
794 debugl1(cs, "NT mode activated");
795 return (0);
796 }
797 if ((cs->chanlimit > 1) || (cs->hw.hfcpci.bswapped) ||
798 (cs->hw.hfcpci.nt_mode) || (ic->arg != 12))
799 return (-EINVAL);
800
801 spin_lock_irqsave(&cs->lock, flags);
802 if (i) {
803 cs->logecho = 1;
804 cs->hw.hfcpci.trm |= 0x20; /* enable echo chan */
805 cs->hw.hfcpci.int_m1 |= HFCPCI_INTS_B2REC;
806 cs->hw.hfcpci.fifo_en |= HFCPCI_FIFOEN_B2RX;
807 } else {
808 cs->logecho = 0;
809 cs->hw.hfcpci.trm &= ~0x20; /* disable echo chan */
810 cs->hw.hfcpci.int_m1 &= ~HFCPCI_INTS_B2REC;
811 cs->hw.hfcpci.fifo_en &= ~HFCPCI_FIFOEN_B2RX;
812 }
813 cs->hw.hfcpci.sctrl_r &= ~SCTRL_B2_ENA;
814 cs->hw.hfcpci.sctrl &= ~SCTRL_B2_ENA;
815 cs->hw.hfcpci.conn |= 0x10; /* B2-IOM -> B2-ST */
816 cs->hw.hfcpci.ctmt &= ~2;
817 Write_hfc(cs, HFCPCI_CTMT, cs->hw.hfcpci.ctmt);
818 Write_hfc(cs, HFCPCI_SCTRL_R, cs->hw.hfcpci.sctrl_r);
819 Write_hfc(cs, HFCPCI_SCTRL, cs->hw.hfcpci.sctrl);
820 Write_hfc(cs, HFCPCI_CONNECT, cs->hw.hfcpci.conn);
821 Write_hfc(cs, HFCPCI_TRM, cs->hw.hfcpci.trm);
822 Write_hfc(cs, HFCPCI_FIFO_EN, cs->hw.hfcpci.fifo_en);
823 Write_hfc(cs, HFCPCI_INT_M1, cs->hw.hfcpci.int_m1);
824 spin_unlock_irqrestore(&cs->lock, flags);
825 return (0);
826 } /* hfcpci_auxcmd */
827
828 /*****************************/
829 /* E-channel receive routine */
830 /*****************************/
831 static void
832 receive_emsg(struct IsdnCardState *cs)
833 {
834 int rcnt;
835 int receive, count = 5;
836 bzfifo_type *bz;
837 u_char *bdata;
838 z_type *zp;
839 u_char *ptr, *ptr1, new_f2;
840 int total, maxlen, new_z2;
841 u_char e_buffer[256];
842
843 bz = &((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.rxbz_b2;
844 bdata = ((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.rxdat_b2;
845 Begin:
846 count--;
847 if (test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
848 debugl1(cs, "echo_rec_data blocked");
849 return;
850 }
851 if (bz->f1 != bz->f2) {
852 if (cs->debug & L1_DEB_ISAC)
853 debugl1(cs, "hfcpci e_rec f1(%d) f2(%d)",
854 bz->f1, bz->f2);
855 zp = &bz->za[bz->f2];
856
857 rcnt = zp->z1 - zp->z2;
858 if (rcnt < 0)
859 rcnt += B_FIFO_SIZE;
860 rcnt++;
861 if (cs->debug & L1_DEB_ISAC)
862 debugl1(cs, "hfcpci e_rec z1(%x) z2(%x) cnt(%d)",
863 zp->z1, zp->z2, rcnt);
864 new_z2 = zp->z2 + rcnt; /* new position in fifo */
865 if (new_z2 >= (B_FIFO_SIZE + B_SUB_VAL))
866 new_z2 -= B_FIFO_SIZE; /* buffer wrap */
867 new_f2 = (bz->f2 + 1) & MAX_B_FRAMES;
868 if ((rcnt > 256 + 3) || (count < 4) ||
869 (*(bdata + (zp->z1 - B_SUB_VAL)))) {
870 if (cs->debug & L1_DEB_WARN)
871 debugl1(cs, "hfcpci_empty_echan: incoming packet invalid length %d or crc", rcnt);
872 bz->za[new_f2].z2 = new_z2;
873 bz->f2 = new_f2; /* next buffer */
874 } else {
875 total = rcnt;
876 rcnt -= 3;
877 ptr = e_buffer;
878
879 if (zp->z2 <= B_FIFO_SIZE + B_SUB_VAL)
880 maxlen = rcnt; /* complete transfer */
881 else
882 maxlen = B_FIFO_SIZE + B_SUB_VAL - zp->z2; /* maximum */
883
884 ptr1 = bdata + (zp->z2 - B_SUB_VAL); /* start of data */
885 memcpy(ptr, ptr1, maxlen); /* copy data */
886 rcnt -= maxlen;
887
888 if (rcnt) { /* rest remaining */
889 ptr += maxlen;
890 ptr1 = bdata; /* start of buffer */
891 memcpy(ptr, ptr1, rcnt); /* rest */
892 }
893 bz->za[new_f2].z2 = new_z2;
894 bz->f2 = new_f2; /* next buffer */
895 if (cs->debug & DEB_DLOG_HEX) {
896 ptr = cs->dlog;
897 if ((total - 3) < MAX_DLOG_SPACE / 3 - 10) {
898 *ptr++ = 'E';
899 *ptr++ = 'C';
900 *ptr++ = 'H';
901 *ptr++ = 'O';
902 *ptr++ = ':';
903 ptr += QuickHex(ptr, e_buffer, total - 3);
904 ptr--;
905 *ptr++ = '\n';
906 *ptr = 0;
907 HiSax_putstatus(cs, NULL, cs->dlog);
908 } else
909 HiSax_putstatus(cs, "LogEcho: ", "warning Frame too big (%d)", total - 3);
910 }
911 }
912
913 rcnt = bz->f1 - bz->f2;
914 if (rcnt < 0)
915 rcnt += MAX_B_FRAMES + 1;
916 if (rcnt > 1)
917 receive = 1;
918 else
919 receive = 0;
920 } else
921 receive = 0;
922 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
923 if (count && receive)
924 goto Begin;
925 return;
926 } /* receive_emsg */
927
928 /*********************/
929 /* Interrupt handler */
930 /*********************/
931 static irqreturn_t
932 hfcpci_interrupt(int intno, void *dev_id, struct pt_regs *regs)
933 {
934 u_long flags;
935 struct IsdnCardState *cs = dev_id;
936 u_char exval;
937 struct BCState *bcs;
938 int count = 15;
939 u_char val, stat;
940
941 if (!(cs->hw.hfcpci.int_m2 & 0x08)) {
942 debugl1(cs, "HFC-PCI: int_m2 %x not initialised", cs->hw.hfcpci.int_m2);
943 return IRQ_NONE; /* not initialised */
944 }
945 spin_lock_irqsave(&cs->lock, flags);
946 if (HFCPCI_ANYINT & (stat = Read_hfc(cs, HFCPCI_STATUS))) {
947 val = Read_hfc(cs, HFCPCI_INT_S1);
948 if (cs->debug & L1_DEB_ISAC)
949 debugl1(cs, "HFC-PCI: stat(%02x) s1(%02x)", stat, val);
950 } else {
951 spin_unlock_irqrestore(&cs->lock, flags);
952 return IRQ_NONE;
953 }
954 if (cs->debug & L1_DEB_ISAC)
955 debugl1(cs, "HFC-PCI irq %x %s", val,
956 test_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags) ?
957 "locked" : "unlocked");
958 val &= cs->hw.hfcpci.int_m1;
959 if (val & 0x40) { /* state machine irq */
960 exval = Read_hfc(cs, HFCPCI_STATES) & 0xf;
961 if (cs->debug & L1_DEB_ISAC)
962 debugl1(cs, "ph_state chg %d->%d", cs->dc.hfcpci.ph_state,
963 exval);
964 cs->dc.hfcpci.ph_state = exval;
965 sched_event_D_pci(cs, D_L1STATECHANGE);
966 val &= ~0x40;
967 }
968 if (val & 0x80) { /* timer irq */
969 if (cs->hw.hfcpci.nt_mode) {
970 if ((--cs->hw.hfcpci.nt_timer) < 0)
971 sched_event_D_pci(cs, D_L1STATECHANGE);
972 }
973 val &= ~0x80;
974 Write_hfc(cs, HFCPCI_CTMT, cs->hw.hfcpci.ctmt | HFCPCI_CLTIMER);
975 }
976 while (val) {
977 if (test_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
978 cs->hw.hfcpci.int_s1 |= val;
979 spin_unlock_irqrestore(&cs->lock, flags);
980 return IRQ_HANDLED;
981 }
982 if (cs->hw.hfcpci.int_s1 & 0x18) {
983 exval = val;
984 val = cs->hw.hfcpci.int_s1;
985 cs->hw.hfcpci.int_s1 = exval;
986 }
987 if (val & 0x08) {
988 if (!(bcs = Sel_BCS(cs, cs->hw.hfcpci.bswapped ? 1 : 0))) {
989 if (cs->debug)
990 debugl1(cs, "hfcpci spurious 0x08 IRQ");
991 } else
992 main_rec_hfcpci(bcs);
993 }
994 if (val & 0x10) {
995 if (cs->logecho)
996 receive_emsg(cs);
997 else if (!(bcs = Sel_BCS(cs, 1))) {
998 if (cs->debug)
999 debugl1(cs, "hfcpci spurious 0x10 IRQ");
1000 } else
1001 main_rec_hfcpci(bcs);
1002 }
1003 if (val & 0x01) {
1004 if (!(bcs = Sel_BCS(cs, cs->hw.hfcpci.bswapped ? 1 : 0))) {
1005 if (cs->debug)
1006 debugl1(cs, "hfcpci spurious 0x01 IRQ");
1007 } else {
1008 if (bcs->tx_skb) {
1009 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
1010 hfcpci_fill_fifo(bcs);
1011 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
1012 } else
1013 debugl1(cs, "fill_data %d blocked", bcs->channel);
1014 } else {
1015 if ((bcs->tx_skb = skb_dequeue(&bcs->squeue))) {
1016 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
1017 hfcpci_fill_fifo(bcs);
1018 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
1019 } else
1020 debugl1(cs, "fill_data %d blocked", bcs->channel);
1021 } else {
1022 hfcpci_sched_event(bcs, B_XMTBUFREADY);
1023 }
1024 }
1025 }
1026 }
1027 if (val & 0x02) {
1028 if (!(bcs = Sel_BCS(cs, 1))) {
1029 if (cs->debug)
1030 debugl1(cs, "hfcpci spurious 0x02 IRQ");
1031 } else {
1032 if (bcs->tx_skb) {
1033 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
1034 hfcpci_fill_fifo(bcs);
1035 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
1036 } else
1037 debugl1(cs, "fill_data %d blocked", bcs->channel);
1038 } else {
1039 if ((bcs->tx_skb = skb_dequeue(&bcs->squeue))) {
1040 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
1041 hfcpci_fill_fifo(bcs);
1042 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
1043 } else
1044 debugl1(cs, "fill_data %d blocked", bcs->channel);
1045 } else {
1046 hfcpci_sched_event(bcs, B_XMTBUFREADY);
1047 }
1048 }
1049 }
1050 }
1051 if (val & 0x20) { /* receive dframe */
1052 receive_dmsg(cs);
1053 }
1054 if (val & 0x04) { /* dframe transmitted */
1055 if (test_and_clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags))
1056 del_timer(&cs->dbusytimer);
1057 if (test_and_clear_bit(FLG_L1_DBUSY, &cs->HW_Flags))
1058 sched_event_D_pci(cs, D_CLEARBUSY);
1059 if (cs->tx_skb) {
1060 if (cs->tx_skb->len) {
1061 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
1062 hfcpci_fill_dfifo(cs);
1063 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
1064 } else {
1065 debugl1(cs, "hfcpci_fill_dfifo irq blocked");
1066 }
1067 goto afterXPR;
1068 } else {
1069 dev_kfree_skb_irq(cs->tx_skb);
1070 cs->tx_cnt = 0;
1071 cs->tx_skb = NULL;
1072 }
1073 }
1074 if ((cs->tx_skb = skb_dequeue(&cs->sq))) {
1075 cs->tx_cnt = 0;
1076 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
1077 hfcpci_fill_dfifo(cs);
1078 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
1079 } else {
1080 debugl1(cs, "hfcpci_fill_dfifo irq blocked");
1081 }
1082 } else
1083 sched_event_D_pci(cs, D_XMTBUFREADY);
1084 }
1085 afterXPR:
1086 if (cs->hw.hfcpci.int_s1 && count--) {
1087 val = cs->hw.hfcpci.int_s1;
1088 cs->hw.hfcpci.int_s1 = 0;
1089 if (cs->debug & L1_DEB_ISAC)
1090 debugl1(cs, "HFC-PCI irq %x loop %d", val, 15 - count);
1091 } else
1092 val = 0;
1093 }
1094 spin_unlock_irqrestore(&cs->lock, flags);
1095 return IRQ_HANDLED;
1096 }
1097
1098 /********************************************************************/
1099 /* timer callback for D-chan busy resolution. Currently no function */
1100 /********************************************************************/
1101 static void
1102 hfcpci_dbusy_timer(struct IsdnCardState *cs)
1103 {
1104 }
1105
1106 /*************************************/
1107 /* Layer 1 D-channel hardware access */
1108 /*************************************/
1109 static void
1110 HFCPCI_l1hw(struct PStack *st, int pr, void *arg)
1111 {
1112 u_long flags;
1113 struct IsdnCardState *cs = (struct IsdnCardState *) st->l1.hardware;
1114 struct sk_buff *skb = arg;
1115
1116 switch (pr) {
1117 case (PH_DATA | REQUEST):
1118 if (cs->debug & DEB_DLOG_HEX)
1119 LogFrame(cs, skb->data, skb->len);
1120 if (cs->debug & DEB_DLOG_VERBOSE)
1121 dlogframe(cs, skb, 0);
1122 spin_lock_irqsave(&cs->lock, flags);
1123 if (cs->tx_skb) {
1124 skb_queue_tail(&cs->sq, skb);
1125 #ifdef L2FRAME_DEBUG /* psa */
1126 if (cs->debug & L1_DEB_LAPD)
1127 Logl2Frame(cs, skb, "PH_DATA Queued", 0);
1128 #endif
1129 } else {
1130 cs->tx_skb = skb;
1131 cs->tx_cnt = 0;
1132 #ifdef L2FRAME_DEBUG /* psa */
1133 if (cs->debug & L1_DEB_LAPD)
1134 Logl2Frame(cs, skb, "PH_DATA", 0);
1135 #endif
1136 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
1137 hfcpci_fill_dfifo(cs);
1138 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
1139 } else
1140 debugl1(cs, "hfcpci_fill_dfifo blocked");
1141
1142 }
1143 spin_unlock_irqrestore(&cs->lock, flags);
1144 break;
1145 case (PH_PULL | INDICATION):
1146 spin_lock_irqsave(&cs->lock, flags);
1147 if (cs->tx_skb) {
1148 if (cs->debug & L1_DEB_WARN)
1149 debugl1(cs, " l2l1 tx_skb exist this shouldn't happen");
1150 skb_queue_tail(&cs->sq, skb);
1151 spin_unlock_irqrestore(&cs->lock, flags);
1152 break;
1153 }
1154 if (cs->debug & DEB_DLOG_HEX)
1155 LogFrame(cs, skb->data, skb->len);
1156 if (cs->debug & DEB_DLOG_VERBOSE)
1157 dlogframe(cs, skb, 0);
1158 cs->tx_skb = skb;
1159 cs->tx_cnt = 0;
1160 #ifdef L2FRAME_DEBUG /* psa */
1161 if (cs->debug & L1_DEB_LAPD)
1162 Logl2Frame(cs, skb, "PH_DATA_PULLED", 0);
1163 #endif
1164 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
1165 hfcpci_fill_dfifo(cs);
1166 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
1167 } else
1168 debugl1(cs, "hfcpci_fill_dfifo blocked");
1169 spin_unlock_irqrestore(&cs->lock, flags);
1170 break;
1171 case (PH_PULL | REQUEST):
1172 #ifdef L2FRAME_DEBUG /* psa */
1173 if (cs->debug & L1_DEB_LAPD)
1174 debugl1(cs, "-> PH_REQUEST_PULL");
1175 #endif
1176 if (!cs->tx_skb) {
1177 test_and_clear_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
1178 st->l1.l1l2(st, PH_PULL | CONFIRM, NULL);
1179 } else
1180 test_and_set_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
1181 break;
1182 case (HW_RESET | REQUEST):
1183 spin_lock_irqsave(&cs->lock, flags);
1184 Write_hfc(cs, HFCPCI_STATES, HFCPCI_LOAD_STATE | 3); /* HFC ST 3 */
1185 udelay(6);
1186 Write_hfc(cs, HFCPCI_STATES, 3); /* HFC ST 2 */
1187 cs->hw.hfcpci.mst_m |= HFCPCI_MASTER;
1188 Write_hfc(cs, HFCPCI_MST_MODE, cs->hw.hfcpci.mst_m);
1189 Write_hfc(cs, HFCPCI_STATES, HFCPCI_ACTIVATE | HFCPCI_DO_ACTION);
1190 spin_unlock_irqrestore(&cs->lock, flags);
1191 l1_msg(cs, HW_POWERUP | CONFIRM, NULL);
1192 break;
1193 case (HW_ENABLE | REQUEST):
1194 spin_lock_irqsave(&cs->lock, flags);
1195 Write_hfc(cs, HFCPCI_STATES, HFCPCI_DO_ACTION);
1196 spin_unlock_irqrestore(&cs->lock, flags);
1197 break;
1198 case (HW_DEACTIVATE | REQUEST):
1199 spin_lock_irqsave(&cs->lock, flags);
1200 cs->hw.hfcpci.mst_m &= ~HFCPCI_MASTER;
1201 Write_hfc(cs, HFCPCI_MST_MODE, cs->hw.hfcpci.mst_m);
1202 spin_unlock_irqrestore(&cs->lock, flags);
1203 break;
1204 case (HW_INFO3 | REQUEST):
1205 spin_lock_irqsave(&cs->lock, flags);
1206 cs->hw.hfcpci.mst_m |= HFCPCI_MASTER;
1207 Write_hfc(cs, HFCPCI_MST_MODE, cs->hw.hfcpci.mst_m);
1208 spin_unlock_irqrestore(&cs->lock, flags);
1209 break;
1210 case (HW_TESTLOOP | REQUEST):
1211 spin_lock_irqsave(&cs->lock, flags);
1212 switch ((int) arg) {
1213 case (1):
1214 Write_hfc(cs, HFCPCI_B1_SSL, 0x80); /* tx slot */
1215 Write_hfc(cs, HFCPCI_B1_RSL, 0x80); /* rx slot */
1216 cs->hw.hfcpci.conn = (cs->hw.hfcpci.conn & ~7) | 1;
1217 Write_hfc(cs, HFCPCI_CONNECT, cs->hw.hfcpci.conn);
1218 break;
1219
1220 case (2):
1221 Write_hfc(cs, HFCPCI_B2_SSL, 0x81); /* tx slot */
1222 Write_hfc(cs, HFCPCI_B2_RSL, 0x81); /* rx slot */
1223 cs->hw.hfcpci.conn = (cs->hw.hfcpci.conn & ~0x38) | 0x08;
1224 Write_hfc(cs, HFCPCI_CONNECT, cs->hw.hfcpci.conn);
1225 break;
1226
1227 default:
1228 spin_unlock_irqrestore(&cs->lock, flags);
1229 if (cs->debug & L1_DEB_WARN)
1230 debugl1(cs, "hfcpci_l1hw loop invalid %4x", (int) arg);
1231 return;
1232 }
1233 cs->hw.hfcpci.trm |= 0x80; /* enable IOM-loop */
1234 Write_hfc(cs, HFCPCI_TRM, cs->hw.hfcpci.trm);
1235 spin_unlock_irqrestore(&cs->lock, flags);
1236 break;
1237 default:
1238 if (cs->debug & L1_DEB_WARN)
1239 debugl1(cs, "hfcpci_l1hw unknown pr %4x", pr);
1240 break;
1241 }
1242 }
1243
1244 /***********************************************/
1245 /* called during init setting l1 stack pointer */
1246 /***********************************************/
1247 void
1248 setstack_hfcpci(struct PStack *st, struct IsdnCardState *cs)
1249 {
1250 st->l1.l1hw = HFCPCI_l1hw;
1251 }
1252
1253 /**************************************/
1254 /* send B-channel data if not blocked */
1255 /**************************************/
1256 static void
1257 hfcpci_send_data(struct BCState *bcs)
1258 {
1259 struct IsdnCardState *cs = bcs->cs;
1260
1261 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
1262 hfcpci_fill_fifo(bcs);
1263 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
1264 } else
1265 debugl1(cs, "send_data %d blocked", bcs->channel);
1266 }
1267
1268 /***************************************************************/
1269 /* activate/deactivate hardware for selected channels and mode */
1270 /***************************************************************/
1271 void
1272 mode_hfcpci(struct BCState *bcs, int mode, int bc)
1273 {
1274 struct IsdnCardState *cs = bcs->cs;
1275 int fifo2;
1276
1277 if (cs->debug & L1_DEB_HSCX)
1278 debugl1(cs, "HFCPCI bchannel mode %d bchan %d/%d",
1279 mode, bc, bcs->channel);
1280 bcs->mode = mode;
1281 bcs->channel = bc;
1282 fifo2 = bc;
1283 if (cs->chanlimit > 1) {
1284 cs->hw.hfcpci.bswapped = 0; /* B1 and B2 normal mode */
1285 cs->hw.hfcpci.sctrl_e &= ~0x80;
1286 } else {
1287 if (bc) {
1288 if (mode != L1_MODE_NULL) {
1289 cs->hw.hfcpci.bswapped = 1; /* B1 and B2 exchanged */
1290 cs->hw.hfcpci.sctrl_e |= 0x80;
1291 } else {
1292 cs->hw.hfcpci.bswapped = 0; /* B1 and B2 normal mode */
1293 cs->hw.hfcpci.sctrl_e &= ~0x80;
1294 }
1295 fifo2 = 0;
1296 } else {
1297 cs->hw.hfcpci.bswapped = 0; /* B1 and B2 normal mode */
1298 cs->hw.hfcpci.sctrl_e &= ~0x80;
1299 }
1300 }
1301 switch (mode) {
1302 case (L1_MODE_NULL):
1303 if (bc) {
1304 cs->hw.hfcpci.sctrl &= ~SCTRL_B2_ENA;
1305 cs->hw.hfcpci.sctrl_r &= ~SCTRL_B2_ENA;
1306 } else {
1307 cs->hw.hfcpci.sctrl &= ~SCTRL_B1_ENA;
1308 cs->hw.hfcpci.sctrl_r &= ~SCTRL_B1_ENA;
1309 }
1310 if (fifo2) {
1311 cs->hw.hfcpci.fifo_en &= ~HFCPCI_FIFOEN_B2;
1312 cs->hw.hfcpci.int_m1 &= ~(HFCPCI_INTS_B2TRANS + HFCPCI_INTS_B2REC);
1313 } else {
1314 cs->hw.hfcpci.fifo_en &= ~HFCPCI_FIFOEN_B1;
1315 cs->hw.hfcpci.int_m1 &= ~(HFCPCI_INTS_B1TRANS + HFCPCI_INTS_B1REC);
1316 }
1317 break;
1318 case (L1_MODE_TRANS):
1319 hfcpci_clear_fifo_rx(cs, fifo2);
1320 hfcpci_clear_fifo_tx(cs, fifo2);
1321 if (bc) {
1322 cs->hw.hfcpci.sctrl |= SCTRL_B2_ENA;
1323 cs->hw.hfcpci.sctrl_r |= SCTRL_B2_ENA;
1324 } else {
1325 cs->hw.hfcpci.sctrl |= SCTRL_B1_ENA;
1326 cs->hw.hfcpci.sctrl_r |= SCTRL_B1_ENA;
1327 }
1328 if (fifo2) {
1329 cs->hw.hfcpci.fifo_en |= HFCPCI_FIFOEN_B2;
1330 cs->hw.hfcpci.int_m1 |= (HFCPCI_INTS_B2TRANS + HFCPCI_INTS_B2REC);
1331 cs->hw.hfcpci.ctmt |= 2;
1332 cs->hw.hfcpci.conn &= ~0x18;
1333 } else {
1334 cs->hw.hfcpci.fifo_en |= HFCPCI_FIFOEN_B1;
1335 cs->hw.hfcpci.int_m1 |= (HFCPCI_INTS_B1TRANS + HFCPCI_INTS_B1REC);
1336 cs->hw.hfcpci.ctmt |= 1;
1337 cs->hw.hfcpci.conn &= ~0x03;
1338 }
1339 break;
1340 case (L1_MODE_HDLC):
1341 hfcpci_clear_fifo_rx(cs, fifo2);
1342 hfcpci_clear_fifo_tx(cs, fifo2);
1343 if (bc) {
1344 cs->hw.hfcpci.sctrl |= SCTRL_B2_ENA;
1345 cs->hw.hfcpci.sctrl_r |= SCTRL_B2_ENA;
1346 } else {
1347 cs->hw.hfcpci.sctrl |= SCTRL_B1_ENA;
1348 cs->hw.hfcpci.sctrl_r |= SCTRL_B1_ENA;
1349 }
1350 if (fifo2) {
1351 cs->hw.hfcpci.last_bfifo_cnt[1] = 0;
1352 cs->hw.hfcpci.fifo_en |= HFCPCI_FIFOEN_B2;
1353 cs->hw.hfcpci.int_m1 |= (HFCPCI_INTS_B2TRANS + HFCPCI_INTS_B2REC);
1354 cs->hw.hfcpci.ctmt &= ~2;
1355 cs->hw.hfcpci.conn &= ~0x18;
1356 } else {
1357 cs->hw.hfcpci.last_bfifo_cnt[0] = 0;
1358 cs->hw.hfcpci.fifo_en |= HFCPCI_FIFOEN_B1;
1359 cs->hw.hfcpci.int_m1 |= (HFCPCI_INTS_B1TRANS + HFCPCI_INTS_B1REC);
1360 cs->hw.hfcpci.ctmt &= ~1;
1361 cs->hw.hfcpci.conn &= ~0x03;
1362 }
1363 break;
1364 case (L1_MODE_EXTRN):
1365 if (bc) {
1366 cs->hw.hfcpci.conn |= 0x10;
1367 cs->hw.hfcpci.sctrl |= SCTRL_B2_ENA;
1368 cs->hw.hfcpci.sctrl_r |= SCTRL_B2_ENA;
1369 cs->hw.hfcpci.fifo_en &= ~HFCPCI_FIFOEN_B2;
1370 cs->hw.hfcpci.int_m1 &= ~(HFCPCI_INTS_B2TRANS + HFCPCI_INTS_B2REC);
1371 } else {
1372 cs->hw.hfcpci.conn |= 0x02;
1373 cs->hw.hfcpci.sctrl |= SCTRL_B1_ENA;
1374 cs->hw.hfcpci.sctrl_r |= SCTRL_B1_ENA;
1375 cs->hw.hfcpci.fifo_en &= ~HFCPCI_FIFOEN_B1;
1376 cs->hw.hfcpci.int_m1 &= ~(HFCPCI_INTS_B1TRANS + HFCPCI_INTS_B1REC);
1377 }
1378 break;
1379 }
1380 Write_hfc(cs, HFCPCI_SCTRL_E, cs->hw.hfcpci.sctrl_e);
1381 Write_hfc(cs, HFCPCI_INT_M1, cs->hw.hfcpci.int_m1);
1382 Write_hfc(cs, HFCPCI_FIFO_EN, cs->hw.hfcpci.fifo_en);
1383 Write_hfc(cs, HFCPCI_SCTRL, cs->hw.hfcpci.sctrl);
1384 Write_hfc(cs, HFCPCI_SCTRL_R, cs->hw.hfcpci.sctrl_r);
1385 Write_hfc(cs, HFCPCI_CTMT, cs->hw.hfcpci.ctmt);
1386 Write_hfc(cs, HFCPCI_CONNECT, cs->hw.hfcpci.conn);
1387 }
1388
1389 /******************************/
1390 /* Layer2 -> Layer 1 Transfer */
1391 /******************************/
1392 static void
1393 hfcpci_l2l1(struct PStack *st, int pr, void *arg)
1394 {
1395 struct BCState *bcs = st->l1.bcs;
1396 u_long flags;
1397 struct sk_buff *skb = arg;
1398
1399 switch (pr) {
1400 case (PH_DATA | REQUEST):
1401 spin_lock_irqsave(&bcs->cs->lock, flags);
1402 if (bcs->tx_skb) {
1403 skb_queue_tail(&bcs->squeue, skb);
1404 } else {
1405 bcs->tx_skb = skb;
1406 // test_and_set_bit(BC_FLG_BUSY, &bcs->Flag);
1407 bcs->cs->BC_Send_Data(bcs);
1408 }
1409 spin_unlock_irqrestore(&bcs->cs->lock, flags);
1410 break;
1411 case (PH_PULL | INDICATION):
1412 spin_lock_irqsave(&bcs->cs->lock, flags);
1413 if (bcs->tx_skb) {
1414 spin_unlock_irqrestore(&bcs->cs->lock, flags);
1415 printk(KERN_WARNING "hfc_l2l1: this shouldn't happen\n");
1416 break;
1417 }
1418 // test_and_set_bit(BC_FLG_BUSY, &bcs->Flag);
1419 bcs->tx_skb = skb;
1420 bcs->cs->BC_Send_Data(bcs);
1421 spin_unlock_irqrestore(&bcs->cs->lock, flags);
1422 break;
1423 case (PH_PULL | REQUEST):
1424 if (!bcs->tx_skb) {
1425 test_and_clear_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
1426 st->l1.l1l2(st, PH_PULL | CONFIRM, NULL);
1427 } else
1428 test_and_set_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
1429 break;
1430 case (PH_ACTIVATE | REQUEST):
1431 spin_lock_irqsave(&bcs->cs->lock, flags);
1432 test_and_set_bit(BC_FLG_ACTIV, &bcs->Flag);
1433 mode_hfcpci(bcs, st->l1.mode, st->l1.bc);
1434 spin_unlock_irqrestore(&bcs->cs->lock, flags);
1435 l1_msg_b(st, pr, arg);
1436 break;
1437 case (PH_DEACTIVATE | REQUEST):
1438 l1_msg_b(st, pr, arg);
1439 break;
1440 case (PH_DEACTIVATE | CONFIRM):
1441 spin_lock_irqsave(&bcs->cs->lock, flags);
1442 test_and_clear_bit(BC_FLG_ACTIV, &bcs->Flag);
1443 test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
1444 mode_hfcpci(bcs, 0, st->l1.bc);
1445 spin_unlock_irqrestore(&bcs->cs->lock, flags);
1446 st->l1.l1l2(st, PH_DEACTIVATE | CONFIRM, NULL);
1447 break;
1448 }
1449 }
1450
1451 /******************************************/
1452 /* deactivate B-channel access and queues */
1453 /******************************************/
1454 static void
1455 close_hfcpci(struct BCState *bcs)
1456 {
1457 mode_hfcpci(bcs, 0, bcs->channel);
1458 if (test_and_clear_bit(BC_FLG_INIT, &bcs->Flag)) {
1459 skb_queue_purge(&bcs->rqueue);
1460 skb_queue_purge(&bcs->squeue);
1461 if (bcs->tx_skb) {
1462 dev_kfree_skb_any(bcs->tx_skb);
1463 bcs->tx_skb = NULL;
1464 test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
1465 }
1466 }
1467 }
1468
1469 /*************************************/
1470 /* init B-channel queues and control */
1471 /*************************************/
1472 static int
1473 open_hfcpcistate(struct IsdnCardState *cs, struct BCState *bcs)
1474 {
1475 if (!test_and_set_bit(BC_FLG_INIT, &bcs->Flag)) {
1476 skb_queue_head_init(&bcs->rqueue);
1477 skb_queue_head_init(&bcs->squeue);
1478 }
1479 bcs->tx_skb = NULL;
1480 test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
1481 bcs->event = 0;
1482 bcs->tx_cnt = 0;
1483 return (0);
1484 }
1485
1486 /*********************************/
1487 /* inits the stack for B-channel */
1488 /*********************************/
1489 static int
1490 setstack_2b(struct PStack *st, struct BCState *bcs)
1491 {
1492 bcs->channel = st->l1.bc;
1493 if (open_hfcpcistate(st->l1.hardware, bcs))
1494 return (-1);
1495 st->l1.bcs = bcs;
1496 st->l2.l2l1 = hfcpci_l2l1;
1497 setstack_manager(st);
1498 bcs->st = st;
1499 setstack_l1_B(st);
1500 return (0);
1501 }
1502
1503 /***************************/
1504 /* handle L1 state changes */
1505 /***************************/
1506 static void
1507 hfcpci_bh(struct IsdnCardState *cs)
1508 {
1509 u_long flags;
1510 // struct PStack *stptr;
1511
1512 if (!cs)
1513 return;
1514 if (test_and_clear_bit(D_L1STATECHANGE, &cs->event)) {
1515 if (!cs->hw.hfcpci.nt_mode)
1516 switch (cs->dc.hfcpci.ph_state) {
1517 case (0):
1518 l1_msg(cs, HW_RESET | INDICATION, NULL);
1519 break;
1520 case (3):
1521 l1_msg(cs, HW_DEACTIVATE | INDICATION, NULL);
1522 break;
1523 case (8):
1524 l1_msg(cs, HW_RSYNC | INDICATION, NULL);
1525 break;
1526 case (6):
1527 l1_msg(cs, HW_INFO2 | INDICATION, NULL);
1528 break;
1529 case (7):
1530 l1_msg(cs, HW_INFO4_P8 | INDICATION, NULL);
1531 break;
1532 default:
1533 break;
1534 } else {
1535 spin_lock_irqsave(&cs->lock, flags);
1536 switch (cs->dc.hfcpci.ph_state) {
1537 case (2):
1538 if (cs->hw.hfcpci.nt_timer < 0) {
1539 cs->hw.hfcpci.nt_timer = 0;
1540 cs->hw.hfcpci.int_m1 &= ~HFCPCI_INTS_TIMER;
1541 Write_hfc(cs, HFCPCI_INT_M1, cs->hw.hfcpci.int_m1);
1542 /* Clear already pending ints */
1543 if (Read_hfc(cs, HFCPCI_INT_S1));
1544 Write_hfc(cs, HFCPCI_STATES, 4 | HFCPCI_LOAD_STATE);
1545 udelay(10);
1546 Write_hfc(cs, HFCPCI_STATES, 4);
1547 cs->dc.hfcpci.ph_state = 4;
1548 } else {
1549 cs->hw.hfcpci.int_m1 |= HFCPCI_INTS_TIMER;
1550 Write_hfc(cs, HFCPCI_INT_M1, cs->hw.hfcpci.int_m1);
1551 cs->hw.hfcpci.ctmt &= ~HFCPCI_AUTO_TIMER;
1552 cs->hw.hfcpci.ctmt |= HFCPCI_TIM3_125;
1553 Write_hfc(cs, HFCPCI_CTMT, cs->hw.hfcpci.ctmt | HFCPCI_CLTIMER);
1554 Write_hfc(cs, HFCPCI_CTMT, cs->hw.hfcpci.ctmt | HFCPCI_CLTIMER);
1555 cs->hw.hfcpci.nt_timer = NT_T1_COUNT;
1556 Write_hfc(cs, HFCPCI_STATES, 2 | HFCPCI_NT_G2_G3); /* allow G2 -> G3 transition */
1557 }
1558 break;
1559 case (1):
1560 case (3):
1561 case (4):
1562 cs->hw.hfcpci.nt_timer = 0;
1563 cs->hw.hfcpci.int_m1 &= ~HFCPCI_INTS_TIMER;
1564 Write_hfc(cs, HFCPCI_INT_M1, cs->hw.hfcpci.int_m1);
1565 break;
1566 default:
1567 break;
1568 }
1569 spin_unlock_irqrestore(&cs->lock, flags);
1570 }
1571 }
1572 if (test_and_clear_bit(D_RCVBUFREADY, &cs->event))
1573 DChannel_proc_rcv(cs);
1574 if (test_and_clear_bit(D_XMTBUFREADY, &cs->event))
1575 DChannel_proc_xmt(cs);
1576 }
1577
1578
1579 /********************************/
1580 /* called for card init message */
1581 /********************************/
1582 void __init
1583 inithfcpci(struct IsdnCardState *cs)
1584 {
1585 cs->bcs[0].BC_SetStack = setstack_2b;
1586 cs->bcs[1].BC_SetStack = setstack_2b;
1587 cs->bcs[0].BC_Close = close_hfcpci;
1588 cs->bcs[1].BC_Close = close_hfcpci;
1589 cs->dbusytimer.function = (void *) hfcpci_dbusy_timer;
1590 cs->dbusytimer.data = (long) cs;
1591 init_timer(&cs->dbusytimer);
1592 mode_hfcpci(cs->bcs, 0, 0);
1593 mode_hfcpci(cs->bcs + 1, 0, 1);
1594 }
1595
1596
1597
1598 /*******************************************/
1599 /* handle card messages from control layer */
1600 /*******************************************/
1601 static int
1602 hfcpci_card_msg(struct IsdnCardState *cs, int mt, void *arg)
1603 {
1604 u_long flags;
1605
1606 if (cs->debug & L1_DEB_ISAC)
1607 debugl1(cs, "HFCPCI: card_msg %x", mt);
1608 switch (mt) {
1609 case CARD_RESET:
1610 spin_lock_irqsave(&cs->lock, flags);
1611 reset_hfcpci(cs);
1612 spin_unlock_irqrestore(&cs->lock, flags);
1613 return (0);
1614 case CARD_RELEASE:
1615 release_io_hfcpci(cs);
1616 return (0);
1617 case CARD_INIT:
1618 spin_lock_irqsave(&cs->lock, flags);
1619 inithfcpci(cs);
1620 reset_hfcpci(cs);
1621 spin_unlock_irqrestore(&cs->lock, flags);
1622 msleep(80); /* Timeout 80ms */
1623 /* now switch timer interrupt off */
1624 spin_lock_irqsave(&cs->lock, flags);
1625 cs->hw.hfcpci.int_m1 &= ~HFCPCI_INTS_TIMER;
1626 Write_hfc(cs, HFCPCI_INT_M1, cs->hw.hfcpci.int_m1);
1627 /* reinit mode reg */
1628 Write_hfc(cs, HFCPCI_MST_MODE, cs->hw.hfcpci.mst_m);
1629 spin_unlock_irqrestore(&cs->lock, flags);
1630 return (0);
1631 case CARD_TEST:
1632 return (0);
1633 }
1634 return (0);
1635 }
1636
1637
1638 /* this variable is used as card index when more than one cards are present */
1639 static struct pci_dev *dev_hfcpci __initdata = NULL;
1640
1641 #endif /* CONFIG_PCI */
1642
1643 int __init
1644 setup_hfcpci(struct IsdnCard *card)
1645 {
1646 u_long flags;
1647 struct IsdnCardState *cs = card->cs;
1648 char tmp[64];
1649 int i;
1650 struct pci_dev *tmp_hfcpci = NULL;
1651
1652 #ifdef __BIG_ENDIAN
1653 #error "not running on big endian machines now"
1654 #endif
1655 strcpy(tmp, hfcpci_revision);
1656 printk(KERN_INFO "HiSax: HFC-PCI driver Rev. %s\n", HiSax_getrev(tmp));
1657 #ifdef CONFIG_PCI
1658 cs->hw.hfcpci.int_s1 = 0;
1659 cs->dc.hfcpci.ph_state = 0;
1660 cs->hw.hfcpci.fifo = 255;
1661 if (cs->typ == ISDN_CTYPE_HFC_PCI) {
1662 i = 0;
1663 while (id_list[i].vendor_id) {
1664 tmp_hfcpci = pci_find_device(id_list[i].vendor_id,
1665 id_list[i].device_id,
1666 dev_hfcpci);
1667 i++;
1668 if (tmp_hfcpci) {
1669 if (pci_enable_device(tmp_hfcpci))
1670 continue;
1671 pci_set_master(tmp_hfcpci);
1672 if ((card->para[0]) && (card->para[0] != (tmp_hfcpci->resource[ 0].start & PCI_BASE_ADDRESS_IO_MASK)))
1673 continue;
1674 else
1675 break;
1676 }
1677 }
1678
1679 if (tmp_hfcpci) {
1680 i--;
1681 dev_hfcpci = tmp_hfcpci; /* old device */
1682 cs->hw.hfcpci.dev = dev_hfcpci;
1683 cs->irq = dev_hfcpci->irq;
1684 if (!cs->irq) {
1685 printk(KERN_WARNING "HFC-PCI: No IRQ for PCI card found\n");
1686 return (0);
1687 }
1688 cs->hw.hfcpci.pci_io = (char *) dev_hfcpci->resource[ 1].start;
1689 printk(KERN_INFO "HiSax: HFC-PCI card manufacturer: %s card name: %s\n", id_list[i].vendor_name, id_list[i].card_name);
1690 } else {
1691 printk(KERN_WARNING "HFC-PCI: No PCI card found\n");
1692 return (0);
1693 }
1694 if (!cs->hw.hfcpci.pci_io) {
1695 printk(KERN_WARNING "HFC-PCI: No IO-Mem for PCI card found\n");
1696 return (0);
1697 }
1698 /* Allocate memory for FIFOS */
1699 /* Because the HFC-PCI needs a 32K physical alignment, we */
1700 /* need to allocate the double mem and align the address */
1701 if (!(cs->hw.hfcpci.share_start = kmalloc(65536, GFP_KERNEL))) {
1702 printk(KERN_WARNING "HFC-PCI: Error allocating memory for FIFO!\n");
1703 return 0;
1704 }
1705 cs->hw.hfcpci.fifos = (void *)
1706 (((ulong) cs->hw.hfcpci.share_start) & ~0x7FFF) + 0x8000;
1707 pci_write_config_dword(cs->hw.hfcpci.dev, 0x80, (u_int) virt_to_bus(cs->hw.hfcpci.fifos));
1708 cs->hw.hfcpci.pci_io = ioremap((ulong) cs->hw.hfcpci.pci_io, 256);
1709 printk(KERN_INFO
1710 "HFC-PCI: defined at mem %#x fifo %#x(%#x) IRQ %d HZ %d\n",
1711 (u_int) cs->hw.hfcpci.pci_io,
1712 (u_int) cs->hw.hfcpci.fifos,
1713 (u_int) virt_to_bus(cs->hw.hfcpci.fifos),
1714 cs->irq, HZ);
1715 spin_lock_irqsave(&cs->lock, flags);
1716 pci_write_config_word(cs->hw.hfcpci.dev, PCI_COMMAND, PCI_ENA_MEMIO); /* enable memory mapped ports, disable busmaster */
1717 cs->hw.hfcpci.int_m2 = 0; /* disable alle interrupts */
1718 cs->hw.hfcpci.int_m1 = 0;
1719 Write_hfc(cs, HFCPCI_INT_M1, cs->hw.hfcpci.int_m1);
1720 Write_hfc(cs, HFCPCI_INT_M2, cs->hw.hfcpci.int_m2);
1721 /* At this point the needed PCI config is done */
1722 /* fifos are still not enabled */
1723 INIT_WORK(&cs->tqueue, (void *)(void *) hfcpci_bh, cs);
1724 cs->setstack_d = setstack_hfcpci;
1725 cs->BC_Send_Data = &hfcpci_send_data;
1726 cs->readisac = NULL;
1727 cs->writeisac = NULL;
1728 cs->readisacfifo = NULL;
1729 cs->writeisacfifo = NULL;
1730 cs->BC_Read_Reg = NULL;
1731 cs->BC_Write_Reg = NULL;
1732 cs->irq_func = &hfcpci_interrupt;
1733 cs->irq_flags |= SA_SHIRQ;
1734 cs->hw.hfcpci.timer.function = (void *) hfcpci_Timer;
1735 cs->hw.hfcpci.timer.data = (long) cs;
1736 init_timer(&cs->hw.hfcpci.timer);
1737 cs->cardmsg = &hfcpci_card_msg;
1738 cs->auxcmd = &hfcpci_auxcmd;
1739 spin_unlock_irqrestore(&cs->lock, flags);
1740 return (1);
1741 } else
1742 return (0); /* no valid card type */
1743 #else
1744 printk(KERN_WARNING "HFC-PCI: NO_PCI_BIOS\n");
1745 return (0);
1746 #endif /* CONFIG_PCI */
1747 }
Verdex Pro support