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[TG3]: Set minimal hw interrupt mitigation.
[linux-2.6/verdex.git] / drivers / media / common / saa7146_vbi.c
blobcb86a97fda1faad89cfd12a3f40527803913c7a7
1 #include <media/saa7146_vv.h>
2
3 static int vbi_pixel_to_capture = 720 * 2;
4
5 static int vbi_workaround(struct saa7146_dev *dev)
6 {
7 struct saa7146_vv *vv = dev->vv_data;
8
9 u32 *cpu;
10 dma_addr_t dma_addr;
11
12 int count = 0;
13 int i;
14
15 DECLARE_WAITQUEUE(wait, current);
16
17 DEB_VBI(("dev:%p\n",dev));
18
19 /* once again, a bug in the saa7146: the brs acquisition
20 is buggy and especially the BXO-counter does not work
21 as specified. there is this workaround, but please
22 don't let me explain it. ;-) */
23
24 cpu = pci_alloc_consistent(dev->pci, 4096, &dma_addr);
25 if (NULL == cpu)
26 return -ENOMEM;
27
28 /* setup some basic programming, just for the workaround */
29 saa7146_write(dev, BASE_EVEN3, dma_addr);
30 saa7146_write(dev, BASE_ODD3, dma_addr+vbi_pixel_to_capture);
31 saa7146_write(dev, PROT_ADDR3, dma_addr+4096);
32 saa7146_write(dev, PITCH3, vbi_pixel_to_capture);
33 saa7146_write(dev, BASE_PAGE3, 0x0);
34 saa7146_write(dev, NUM_LINE_BYTE3, (2<<16)|((vbi_pixel_to_capture)<<0));
35 saa7146_write(dev, MC2, MASK_04|MASK_20);
36
37 /* load brs-control register */
38 WRITE_RPS1(CMD_WR_REG | (1 << 8) | (BRS_CTRL/4));
39 /* BXO = 1h, BRS to outbound */
40 WRITE_RPS1(0xc000008c);
41 /* wait for vbi_a or vbi_b*/
42 if ( 0 != (SAA7146_USE_PORT_B_FOR_VBI & dev->ext_vv_data->flags)) {
43 DEB_D(("...using port b\n"));
44 WRITE_RPS1(CMD_PAUSE | CMD_OAN | CMD_SIG1 | CMD_E_FID_B);
45 WRITE_RPS1(CMD_PAUSE | CMD_OAN | CMD_SIG1 | CMD_O_FID_B);
46 /*
47 WRITE_RPS1(CMD_PAUSE | MASK_09);
48 */
49 } else {
50 DEB_D(("...using port a\n"));
51 WRITE_RPS1(CMD_PAUSE | MASK_10);
52 }
53 /* upload brs */
54 WRITE_RPS1(CMD_UPLOAD | MASK_08);
55 /* load brs-control register */
56 WRITE_RPS1(CMD_WR_REG | (1 << 8) | (BRS_CTRL/4));
57 /* BYO = 1, BXO = NQBIL (=1728 for PAL, for NTSC this is 858*2) - NumByte3 (=1440) = 288 */
58 WRITE_RPS1(((1728-(vbi_pixel_to_capture)) << 7) | MASK_19);
59 /* wait for brs_done */
60 WRITE_RPS1(CMD_PAUSE | MASK_08);
61 /* upload brs */
62 WRITE_RPS1(CMD_UPLOAD | MASK_08);
63 /* load video-dma3 NumLines3 and NumBytes3 */
64 WRITE_RPS1(CMD_WR_REG | (1 << 8) | (NUM_LINE_BYTE3/4));
65 /* dev->vbi_count*2 lines, 720 pixel (= 1440 Bytes) */
66 WRITE_RPS1((2 << 16) | (vbi_pixel_to_capture));
67 /* load brs-control register */
68 WRITE_RPS1(CMD_WR_REG | (1 << 8) | (BRS_CTRL/4));
69 /* Set BRS right: note: this is an experimental value for BXO (=> PAL!) */
70 WRITE_RPS1((540 << 7) | (5 << 19)); // 5 == vbi_start
71 /* wait for brs_done */
72 WRITE_RPS1(CMD_PAUSE | MASK_08);
73 /* upload brs and video-dma3*/
74 WRITE_RPS1(CMD_UPLOAD | MASK_08 | MASK_04);
75 /* load mc2 register: enable dma3 */
76 WRITE_RPS1(CMD_WR_REG | (1 << 8) | (MC1/4));
77 WRITE_RPS1(MASK_20 | MASK_04);
78 /* generate interrupt */
79 WRITE_RPS1(CMD_INTERRUPT);
80 /* stop rps1 */
81 WRITE_RPS1(CMD_STOP);
82
83 /* we have to do the workaround twice to be sure that
84 everything is ok */
85 for(i = 0; i < 2; i++) {
86
87 /* indicate to the irq handler that we do the workaround */
88 saa7146_write(dev, MC2, MASK_31|MASK_15);
89
90 saa7146_write(dev, NUM_LINE_BYTE3, (1<<16)|(2<<0));
91 saa7146_write(dev, MC2, MASK_04|MASK_20);
92
93 /* enable rps1 irqs */
94 SAA7146_IER_ENABLE(dev,MASK_28);
95
96 /* prepare to wait to be woken up by the irq-handler */
97 add_wait_queue(&vv->vbi_wq, &wait);
98 current->state = TASK_INTERRUPTIBLE;
99
100 /* start rps1 to enable workaround */
101 saa7146_write(dev, RPS_ADDR1, dev->d_rps1.dma_handle);
102 saa7146_write(dev, MC1, (MASK_13 | MASK_29));
103
104 schedule();
105
106 DEB_VBI(("brs bug workaround %d/1.\n",i));
107
108 remove_wait_queue(&vv->vbi_wq, &wait);
109 current->state = TASK_RUNNING;
110
111 /* disable rps1 irqs */
112 SAA7146_IER_DISABLE(dev,MASK_28);
113
114 /* stop video-dma3 */
115 saa7146_write(dev, MC1, MASK_20);
116
117 if(signal_pending(current)) {
118
119 DEB_VBI(("aborted (rps:0x%08x).\n",saa7146_read(dev,RPS_ADDR1)));
120
121 /* stop rps1 for sure */
122 saa7146_write(dev, MC1, MASK_29);
123
124 pci_free_consistent(dev->pci, 4096, cpu, dma_addr);
125 return -EINTR;
126 }
127 }
128
129 pci_free_consistent(dev->pci, 4096, cpu, dma_addr);
130 return 0;
131 }
132
133 static void saa7146_set_vbi_capture(struct saa7146_dev *dev, struct saa7146_buf *buf, struct saa7146_buf *next)
134 {
135 struct saa7146_vv *vv = dev->vv_data;
136
137 struct saa7146_video_dma vdma3;
138
139 int count = 0;
140 unsigned long e_wait = vv->current_hps_sync == SAA7146_HPS_SYNC_PORT_A ? CMD_E_FID_A : CMD_E_FID_B;
141 unsigned long o_wait = vv->current_hps_sync == SAA7146_HPS_SYNC_PORT_A ? CMD_O_FID_A : CMD_O_FID_B;
142
143 /*
144 vdma3.base_even = 0xc8000000+2560*70;
145 vdma3.base_odd = 0xc8000000;
146 vdma3.prot_addr = 0xc8000000+2560*164;
147 vdma3.pitch = 2560;
148 vdma3.base_page = 0;
149 vdma3.num_line_byte = (64<<16)|((vbi_pixel_to_capture)<<0); // set above!
150 */
151 vdma3.base_even = buf->pt[2].offset;
152 vdma3.base_odd = buf->pt[2].offset + 16 * vbi_pixel_to_capture;
153 vdma3.prot_addr = buf->pt[2].offset + 16 * 2 * vbi_pixel_to_capture;
154 vdma3.pitch = vbi_pixel_to_capture;
155 vdma3.base_page = buf->pt[2].dma | ME1;
156 vdma3.num_line_byte = (16 << 16) | vbi_pixel_to_capture;
157
158 saa7146_write_out_dma(dev, 3, &vdma3);
159
160 /* write beginning of rps-program */
161 count = 0;
162
163 /* wait for o_fid_a/b / e_fid_a/b toggle only if bit 1 is not set */
164
165 /* we don't wait here for the first field anymore. this is different from the video
166 capture and might cause that the first buffer is only half filled (with only
167 one field). but since this is some sort of streaming data, this is not that negative.
168 but by doing this, we can use the whole engine from video-buf.c... */
169
170 /*
171 WRITE_RPS1(CMD_PAUSE | CMD_OAN | CMD_SIG1 | e_wait);
172 WRITE_RPS1(CMD_PAUSE | CMD_OAN | CMD_SIG1 | o_wait);
173 */
174 /* set bit 1 */
175 WRITE_RPS1(CMD_WR_REG | (1 << 8) | (MC2/4));
176 WRITE_RPS1(MASK_28 | MASK_12);
177
178 /* turn on video-dma3 */
179 WRITE_RPS1(CMD_WR_REG_MASK | (MC1/4));
180 WRITE_RPS1(MASK_04 | MASK_20); /* => mask */
181 WRITE_RPS1(MASK_04 | MASK_20); /* => values */
182
183 /* wait for o_fid_a/b / e_fid_a/b toggle */
184 WRITE_RPS1(CMD_PAUSE | o_wait);
185 WRITE_RPS1(CMD_PAUSE | e_wait);
186
187 /* generate interrupt */
188 WRITE_RPS1(CMD_INTERRUPT);
189
190 /* stop */
191 WRITE_RPS1(CMD_STOP);
192
193 /* enable rps1 irqs */
194 SAA7146_IER_ENABLE(dev, MASK_28);
195
196 /* write the address of the rps-program */
197 saa7146_write(dev, RPS_ADDR1, dev->d_rps1.dma_handle);
198
199 /* turn on rps */
200 saa7146_write(dev, MC1, (MASK_13 | MASK_29));
201 }
202
203 static int buffer_activate(struct saa7146_dev *dev,
204 struct saa7146_buf *buf,
205 struct saa7146_buf *next)
206 {
207 struct saa7146_vv *vv = dev->vv_data;
208 buf->vb.state = STATE_ACTIVE;
209
210 DEB_VBI(("dev:%p, buf:%p, next:%p\n",dev,buf,next));
211 saa7146_set_vbi_capture(dev,buf,next);
212
213 mod_timer(&vv->vbi_q.timeout, jiffies+BUFFER_TIMEOUT);
214 return 0;
215 }
216
217 static int buffer_prepare(struct videobuf_queue *q, struct videobuf_buffer *vb,enum v4l2_field field)
218 {
219 struct file *file = q->priv_data;
220 struct saa7146_fh *fh = file->private_data;
221 struct saa7146_dev *dev = fh->dev;
222 struct saa7146_buf *buf = (struct saa7146_buf *)vb;
223
224 int err = 0;
225 int lines, llength, size;
226
227 lines = 16 * 2 ; /* 2 fields */
228 llength = vbi_pixel_to_capture;
229 size = lines * llength;
230
231 DEB_VBI(("vb:%p\n",vb));
232
233 if (0 != buf->vb.baddr && buf->vb.bsize < size) {
234 DEB_VBI(("size mismatch.\n"));
235 return -EINVAL;
236 }
237
238 if (buf->vb.size != size)
239 saa7146_dma_free(dev,buf);
240
241 if (STATE_NEEDS_INIT == buf->vb.state) {
242 buf->vb.width = llength;
243 buf->vb.height = lines;
244 buf->vb.size = size;
245 buf->vb.field = field; // FIXME: check this
246
247 saa7146_pgtable_free(dev->pci, &buf->pt[2]);
248 saa7146_pgtable_alloc(dev->pci, &buf->pt[2]);
249
250 err = videobuf_iolock(dev->pci,&buf->vb, NULL);
251 if (err)
252 goto oops;
253 err = saa7146_pgtable_build_single(dev->pci, &buf->pt[2], buf->vb.dma.sglist, buf->vb.dma.sglen);
254 if (0 != err)
255 return err;
256 }
257 buf->vb.state = STATE_PREPARED;
258 buf->activate = buffer_activate;
259
260 return 0;
261
262 oops:
263 DEB_VBI(("error out.\n"));
264 saa7146_dma_free(dev,buf);
265
266 return err;
267 }
268
269 static int buffer_setup(struct videobuf_queue *q, unsigned int *count, unsigned int *size)
270 {
271 int llength,lines;
272
273 lines = 16 * 2 ; /* 2 fields */
274 llength = vbi_pixel_to_capture;
275
276 *size = lines * llength;
277 *count = 2;
278
279 DEB_VBI(("count:%d, size:%d\n",*count,*size));
280
281 return 0;
282 }
283
284 static void buffer_queue(struct videobuf_queue *q, struct videobuf_buffer *vb)
285 {
286 struct file *file = q->priv_data;
287 struct saa7146_fh *fh = file->private_data;
288 struct saa7146_dev *dev = fh->dev;
289 struct saa7146_vv *vv = dev->vv_data;
290 struct saa7146_buf *buf = (struct saa7146_buf *)vb;
291
292 DEB_VBI(("vb:%p\n",vb));
293 saa7146_buffer_queue(dev,&vv->vbi_q,buf);
294 }
295
296 static void buffer_release(struct videobuf_queue *q, struct videobuf_buffer *vb)
297 {
298 struct file *file = q->priv_data;
299 struct saa7146_fh *fh = file->private_data;
300 struct saa7146_dev *dev = fh->dev;
301 struct saa7146_buf *buf = (struct saa7146_buf *)vb;
302
303 DEB_VBI(("vb:%p\n",vb));
304 saa7146_dma_free(dev,buf);
305 }
306
307 static struct videobuf_queue_ops vbi_qops = {
308 .buf_setup = buffer_setup,
309 .buf_prepare = buffer_prepare,
310 .buf_queue = buffer_queue,
311 .buf_release = buffer_release,
312 };
313
314 /* ------------------------------------------------------------------ */
315
316 static void vbi_stop(struct saa7146_fh *fh, struct file *file)
317 {
318 struct saa7146_dev *dev = fh->dev;
319 struct saa7146_vv *vv = dev->vv_data;
320 unsigned long flags;
321 DEB_VBI(("dev:%p, fh:%p\n",dev, fh));
322
323 spin_lock_irqsave(&dev->slock,flags);
324
325 /* disable rps1 */
326 saa7146_write(dev, MC1, MASK_29);
327
328 /* disable rps1 irqs */
329 SAA7146_IER_DISABLE(dev, MASK_28);
330
331 /* shut down dma 3 transfers */
332 saa7146_write(dev, MC1, MASK_20);
333
334 if (vv->vbi_q.curr) {
335 saa7146_buffer_finish(dev,&vv->vbi_q,STATE_DONE);
336 }
337
338 videobuf_queue_cancel(&fh->vbi_q);
339
340 vv->vbi_streaming = NULL;
341
342 del_timer(&vv->vbi_q.timeout);
343 del_timer(&fh->vbi_read_timeout);
344
345 spin_unlock_irqrestore(&dev->slock, flags);
346 }
347
348 static void vbi_read_timeout(unsigned long data)
349 {
350 struct file *file = (struct file*)data;
351 struct saa7146_fh *fh = file->private_data;
352 struct saa7146_dev *dev = fh->dev;
353
354 DEB_VBI(("dev:%p, fh:%p\n",dev, fh));
355
356 vbi_stop(fh, file);
357 }
358
359 static void vbi_init(struct saa7146_dev *dev, struct saa7146_vv *vv)
360 {
361 DEB_VBI(("dev:%p\n",dev));
362
363 INIT_LIST_HEAD(&vv->vbi_q.queue);
364
365 init_timer(&vv->vbi_q.timeout);
366 vv->vbi_q.timeout.function = saa7146_buffer_timeout;
367 vv->vbi_q.timeout.data = (unsigned long)(&vv->vbi_q);
368 vv->vbi_q.dev = dev;
369
370 init_waitqueue_head(&vv->vbi_wq);
371 }
372
373 static int vbi_open(struct saa7146_dev *dev, struct file *file)
374 {
375 struct saa7146_fh *fh = (struct saa7146_fh *)file->private_data;
376
377 u32 arbtr_ctrl = saa7146_read(dev, PCI_BT_V1);
378 int ret = 0;
379
380 DEB_VBI(("dev:%p, fh:%p\n",dev,fh));
381
382 ret = saa7146_res_get(fh, RESOURCE_DMA3_BRS);
383 if (0 == ret) {
384 DEB_S(("cannot get vbi RESOURCE_DMA3_BRS resource\n"));
385 return -EBUSY;
386 }
387
388 /* adjust arbitrition control for video dma 3 */
389 arbtr_ctrl &= ~0x1f0000;
390 arbtr_ctrl |= 0x1d0000;
391 saa7146_write(dev, PCI_BT_V1, arbtr_ctrl);
392 saa7146_write(dev, MC2, (MASK_04|MASK_20));
393
394 memset(&fh->vbi_fmt,0,sizeof(fh->vbi_fmt));
395
396 fh->vbi_fmt.sampling_rate = 27000000;
397 fh->vbi_fmt.offset = 248; /* todo */
398 fh->vbi_fmt.samples_per_line = vbi_pixel_to_capture;
399 fh->vbi_fmt.sample_format = V4L2_PIX_FMT_GREY;
400
401 /* fixme: this only works for PAL */
402 fh->vbi_fmt.start[0] = 5;
403 fh->vbi_fmt.count[0] = 16;
404 fh->vbi_fmt.start[1] = 312;
405 fh->vbi_fmt.count[1] = 16;
406
407 videobuf_queue_init(&fh->vbi_q, &vbi_qops,
408 dev->pci, &dev->slock,
409 V4L2_BUF_TYPE_VBI_CAPTURE,
410 V4L2_FIELD_SEQ_TB, // FIXME: does this really work?
411 sizeof(struct saa7146_buf),
412 file);
413 init_MUTEX(&fh->vbi_q.lock);
414
415 init_timer(&fh->vbi_read_timeout);
416 fh->vbi_read_timeout.function = vbi_read_timeout;
417 fh->vbi_read_timeout.data = (unsigned long)file;
418
419 /* initialize the brs */
420 if ( 0 != (SAA7146_USE_PORT_B_FOR_VBI & dev->ext_vv_data->flags)) {
421 saa7146_write(dev, BRS_CTRL, MASK_30|MASK_29 | (7 << 19));
422 } else {
423 saa7146_write(dev, BRS_CTRL, 0x00000001);
424
425 if (0 != (ret = vbi_workaround(dev))) {
426 DEB_VBI(("vbi workaround failed!\n"));
427 /* return ret;*/
428 }
429 }
430
431 /* upload brs register */
432 saa7146_write(dev, MC2, (MASK_08|MASK_24));
433 return 0;
434 }
435
436 static void vbi_close(struct saa7146_dev *dev, struct file *file)
437 {
438 struct saa7146_fh *fh = (struct saa7146_fh *)file->private_data;
439 struct saa7146_vv *vv = dev->vv_data;
440 DEB_VBI(("dev:%p, fh:%p\n",dev,fh));
441
442 if( fh == vv->vbi_streaming ) {
443 vbi_stop(fh, file);
444 }
445 saa7146_res_free(fh, RESOURCE_DMA3_BRS);
446 }
447
448 static void vbi_irq_done(struct saa7146_dev *dev, unsigned long status)
449 {
450 struct saa7146_vv *vv = dev->vv_data;
451 spin_lock(&dev->slock);
452
453 if (vv->vbi_q.curr) {
454 DEB_VBI(("dev:%p, curr:%p\n",dev,vv->vbi_q.curr));
455 /* this must be += 2, one count for each field */
456 vv->vbi_fieldcount+=2;
457 vv->vbi_q.curr->vb.field_count = vv->vbi_fieldcount;
458 saa7146_buffer_finish(dev,&vv->vbi_q,STATE_DONE);
459 } else {
460 DEB_VBI(("dev:%p\n",dev));
461 }
462 saa7146_buffer_next(dev,&vv->vbi_q,1);
463
464 spin_unlock(&dev->slock);
465 }
466
467 static ssize_t vbi_read(struct file *file, char __user *data, size_t count, loff_t *ppos)
468 {
469 struct saa7146_fh *fh = file->private_data;
470 struct saa7146_dev *dev = fh->dev;
471 struct saa7146_vv *vv = dev->vv_data;
472 ssize_t ret = 0;
473
474 DEB_VBI(("dev:%p, fh:%p\n",dev,fh));
475
476 if( NULL == vv->vbi_streaming ) {
477 // fixme: check if dma3 is available
478 // fixme: activate vbi engine here if necessary. (really?)
479 vv->vbi_streaming = fh;
480 }
481
482 if( fh != vv->vbi_streaming ) {
483 DEB_VBI(("open %p is already using vbi capture.",vv->vbi_streaming));
484 return -EBUSY;
485 }
486
487 mod_timer(&fh->vbi_read_timeout, jiffies+BUFFER_TIMEOUT);
488 ret = videobuf_read_stream(&fh->vbi_q, data, count, ppos, 1,
489 file->f_flags & O_NONBLOCK);
490 /*
491 printk("BASE_ODD3: 0x%08x\n", saa7146_read(dev, BASE_ODD3));
492 printk("BASE_EVEN3: 0x%08x\n", saa7146_read(dev, BASE_EVEN3));
493 printk("PROT_ADDR3: 0x%08x\n", saa7146_read(dev, PROT_ADDR3));
494 printk("PITCH3: 0x%08x\n", saa7146_read(dev, PITCH3));
495 printk("BASE_PAGE3: 0x%08x\n", saa7146_read(dev, BASE_PAGE3));
496 printk("NUM_LINE_BYTE3: 0x%08x\n", saa7146_read(dev, NUM_LINE_BYTE3));
497 printk("BRS_CTRL: 0x%08x\n", saa7146_read(dev, BRS_CTRL));
498 */
499 return ret;
500 }
501
502 struct saa7146_use_ops saa7146_vbi_uops = {
503 .init = vbi_init,
504 .open = vbi_open,
505 .release = vbi_close,
506 .irq_done = vbi_irq_done,
507 .read = vbi_read,
508 };
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