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[TG3]: Set minimal hw interrupt mitigation.
[linux-2.6/verdex.git] / drivers / media / dvb / b2c2 / flexcop-reg.h
blob5e131be55cb3f342d3dfdb982fd909c159d791f9
1 /*
2 * This file is part of linux driver the digital TV devices equipped with B2C2 FlexcopII(b)/III
3 *
4 * flexcop-reg.h - register abstraction for FlexCopII, FlexCopIIb and FlexCopIII
5 *
6 * see flexcop.c for copyright information.
7 */
8 #ifndef __FLEXCOP_REG_H__
9 #define __FLEXCOP_REG_H__
10
11
12 typedef enum {
13 FLEXCOP_UNK = 0,
14 FLEXCOP_II,
15 FLEXCOP_IIB,
16 FLEXCOP_III,
17 } flexcop_revision_t;
18
19 extern const char *flexcop_revision_names[];
20
21 typedef enum {
22 FC_UNK = 0,
23 FC_AIR_DVB,
24 FC_AIR_ATSC,
25 FC_SKY,
26 FC_SKY_OLD,
27 FC_CABLE,
28 } flexcop_device_type_t;
29
30 typedef enum {
31 FC_USB = 0,
32 FC_PCI,
33 } flexcop_bus_t;
34
35 extern const char *flexcop_device_names[];
36
37 /* FlexCop IBI Registers */
38
39 /* flexcop_ibi_reg - a huge union representing the register structure */
40 typedef union {
41 u32 raw;
42
43 /* DMA 0x000 to 0x01c
44 * DMA1 0x000 to 0x00c
45 * DMA2 0x010 to 0x01c
46 */
47 struct {
48 u32 dma_0start : 1; /* set: data will be delivered to dma1_address0 */
49 u32 dma_0No_update : 1; /* set: dma1_cur_address will be updated, unset: no update */
50 u32 dma_address0 :30; /* physical/virtual host memory address0 DMA */
51 } dma_0x0;
52
53 struct {
54 u32 DMA_maxpackets : 8; /* (remapped) PCI DMA1 Packet Count Interrupt. This variable
55 is able to be read and written while bit(1) of register
56 0x00c (remap_enable) is set. This variable represents
57 the number of packets that will be transmitted to the PCI
58 host using PCI DMA1 before an interrupt to the PCI is
59 asserted. This functionality may be enabled using bit(20)
60 of register 0x208. N=0 disables the IRQ. */
61 u32 dma_addr_size :24; /* size of memory buffer in DWORDs (bytesize / 4) for DMA */
62 } dma_0x4_remap;
63
64 struct {
65 u32 dma1timer : 7; /* reading PCI DMA1 timer ... when remap_enable is 0 */
66 u32 unused : 1;
67 u32 dma_addr_size :24;
68 } dma_0x4_read;
69
70 struct {
71 u32 unused : 1;
72 u32 dmatimer : 7; /* writing PCI DMA1 timer ... when remap_enable is 0 */
73 u32 dma_addr_size :24;
74 } dma_0x4_write;
75
76 struct {
77 u32 unused : 2;
78 u32 dma_cur_addr :30; /* current physical host memory address pointer for DMA */
79 } dma_0x8;
80
81 struct {
82 u32 dma_1start : 1; /* set: data will be delivered to dma_address1, when dma_address0 is full */
83 u32 remap_enable : 1; /* remap enable for 0x0x4(7:0) */
84 u32 dma_address1 :30; /* Physical/virtual address 1 on DMA */
85 } dma_0xc;
86
87 /* Two-wire Serial Master and Clock 0x100-0x110 */
88 struct {
89 // u32 slave_transmitter : 1; /* ???*/
90 u32 chipaddr : 7; /* two-line serial address of the target slave */
91 u32 reserved1 : 1;
92 u32 baseaddr : 8; /* address of the location of the read/write operation */
93 u32 data1_reg : 8; /* first byte in two-line serial read/write operation */
94 u32 working_start : 1; /* when doing a write operation this indicator is 0 when ready
95 * set to 1 when doing a write operation */
96 u32 twoWS_rw : 1; /* read/write indicator (1 = read, 0 write) */
97 u32 total_bytes : 2; /* number of data bytes in each two-line serial transaction (0 = 1 byte, 11 = 4byte)*/
98 u32 twoWS_port_reg : 2; /* port selection: 01 - Front End/Demod, 10 - EEPROM, 11 - Tuner */
99 u32 no_base_addr_ack_error : 1; /* writing: write-req: frame is produced w/o baseaddr, read-req: read-cycles w/o
100 * preceding address assignment write frame
101 * ACK_ERROR = 1 when no ACK from slave in the last transaction */
102 u32 st_done : 1; /* indicator for transaction is done */
103 } tw_sm_c_100;
104
105 struct {
106 u32 data2_reg : 8; /* 2nd data byte */
107 u32 data3_reg : 8; /* 3rd data byte */
108 u32 data4_reg : 8; /* 4th data byte */
109 u32 exlicit_stops : 1; /* when set, transactions are produced w/o trailing STOP flag, then send isolated STOP flags */
110 u32 force_stop : 1; /* isolated stop flag */
111 u32 unused : 6;
112 } tw_sm_c_104;
113
114 /* Clock. The register allows the FCIII to convert an incoming Master clock
115 * (MCLK) signal into a lower frequency clock through the use of a LowCounter
116 * (TLO) and a High- Counter (THI). The time counts for THI and TLO are
117 * measured in MCLK; each count represents 4 MCLK input clock cycles.
118 *
119 * The default output for port #1 is set for Front End Demod communication. (0x108)
120 * The default output for port #2 is set for EEPROM communication. (0x10c)
121 * The default output for port #3 is set for Tuner communication. (0x110)
122 */
123 struct {
124 u32 thi1 : 6; /* Thi for port #1 (def: 100110b; 38) */
125 u32 reserved1 : 2;
126 u32 tlo1 : 5; /* Tlo for port #1 (def: 11100b; 28) */
127 u32 reserved2 :19;
128 } tw_sm_c_108;
129
130 struct {
131 u32 thi1 : 6; /* Thi for port #2 (def: 111001b; 57) */
132 u32 reserved1 : 2;
133 u32 tlo1 : 5; /* Tlo for port #2 (def: 11100b; 28) */
134 u32 reserved2 :19;
135 } tw_sm_c_10c;
136
137 struct {
138 u32 thi1 : 6; /* Thi for port #3 (def: 111001b; 57) */
139 u32 reserved1 : 2;
140 u32 tlo1 : 5; /* Tlo for port #3 (def: 11100b; 28) */
141 u32 reserved2 :19;
142 } tw_sm_c_110;
143
144 /* LNB Switch Frequency 0x200
145 * Clock that creates the LNB switch tone. The default is set to have a fixed
146 * low output (not oscillating) to the LNB_CTL line.
147 */
148 struct {
149 u32 LNB_CTLHighCount_sig :15; /* It is the number of pre-scaled clock cycles that will be low. */
150 u32 LNB_CTLLowCount_sig :15; /* For example, to obtain a 22KHz output given a 45 Mhz Master
151 Clock signal (MCLK), set PreScalar=01 and LowCounter value to 0x1ff. */
152 u32 LNB_CTLPrescaler_sig : 2; /* pre-scaler divides MCLK: 00 (no division), 01 by 2, 10 by 4, 11 by 12 */
153 } lnb_switch_freq_200;
154
155 /* ACPI, Peripheral Reset, LNB Polarity
156 * ACPI power conservation mode, LNB polarity selection (low or high voltage),
157 * and peripheral reset.
158 */
159 struct {
160 u32 ACPI1_sig : 1; /* turn of the power of tuner and LNB, not implemented in FCIII */
161 u32 ACPI3_sig : 1; /* turn of power of the complete satelite receiver board (except FCIII) */
162 u32 LNB_L_H_sig : 1; /* low or high voltage for LNB. (0 = low, 1 = high) */
163 u32 Per_reset_sig : 1; /* misc. init reset (default: 1), to reset set to low and back to high */
164 u32 reserved :20;
165 u32 Rev_N_sig_revision_hi : 4;/* 0xc in case of FCIII */
166 u32 Rev_N_sig_reserved1 : 2;
167 u32 Rev_N_sig_caps : 1; /* if 1, FCIII has 32 PID- and MAC-filters and is capable of IP multicast */
168 u32 Rev_N_sig_reserved2 : 1;
169 } misc_204;
170
171 /* Control and Status 0x208 to 0x21c */
172 /* Gross enable and disable control */
173 struct {
174 u32 Stream1_filter_sig : 1; /* Stream1 PID filtering */
175 u32 Stream2_filter_sig : 1; /* Stream2 PID filtering */
176 u32 PCR_filter_sig : 1; /* PCR PID filter */
177 u32 PMT_filter_sig : 1; /* PMT PID filter */
178
179 u32 EMM_filter_sig : 1; /* EMM PID filter */
180 u32 ECM_filter_sig : 1; /* ECM PID filter */
181 u32 Null_filter_sig : 1; /* Filters null packets, PID=0x1fff. */
182 u32 Mask_filter_sig : 1; /* mask PID filter */
183
184 u32 WAN_Enable_sig : 1; /* WAN output line through V8 memory space is activated. */
185 u32 WAN_CA_Enable_sig : 1; /* not in FCIII */
186 u32 CA_Enable_sig : 1; /* not in FCIII */
187 u32 SMC_Enable_sig : 1; /* CI stream data (CAI) goes directly to the smart card intf (opposed IBI 0x600 or SC-cmd buf). */
188
189 u32 Per_CA_Enable_sig : 1; /* not in FCIII */
190 u32 Multi2_Enable_sig : 1; /* ? */
191 u32 MAC_filter_Mode_sig : 1; /* (MAC_filter_enable) Globally enables MAC filters for Net PID filteres. */
192 u32 Rcv_Data_sig : 1; /* PID filtering module enable. When this bit is a one, the PID filter will
193 examine and process packets according to all other (individual) PID
194 filtering controls. If it a zero, no packet processing of any kind will
195 take place. All data from the tuner will be thrown away. */
196
197 u32 DMA1_IRQ_Enable_sig : 1; /* When set, a DWORD counter is enabled on PCI DMA1 that asserts the PCI
198 * interrupt after the specified count for filling the buffer. */
199 u32 DMA1_Timer_Enable_sig : 1; /* When set, a timer is enabled on PCI DMA1 that asserts the PCI interrupt
200 after a specified amount of time. */
201 u32 DMA2_IRQ_Enable_sig : 1; /* same as DMA1_IRQ_Enable_sig but for DMA2 */
202 u32 DMA2_Timer_Enable_sig : 1; /* same as DMA1_Timer_Enable_sig but for DMA2 */
203
204 u32 DMA1_Size_IRQ_Enable_sig : 1; /* When set, a packet count detector is enabled on PCI DMA1 that asserts the PCI interrupt. */
205 u32 DMA2_Size_IRQ_Enable_sig : 1; /* When set, a packet count detector is enabled on PCI DMA2 that asserts the PCI interrupt. */
206 u32 Mailbox_from_V8_Enable_sig: 1; /* When set, writes to the mailbox register produce an interrupt to the
207 PCI host to indicate that mailbox data is available. */
208
209 u32 unused : 9;
210 } ctrl_208;
211
212 /* General status. When a PCI interrupt occurs, this register is read to
213 * discover the reason for the interrupt.
214 */
215 struct {
216 u32 DMA1_IRQ_Status : 1; /* When set(1) the DMA1 counter had generated an IRQ. Read Only. */
217 u32 DMA1_Timer_Status : 1; /* When set(1) the DMA1 timer had generated an IRQ. Read Only. */
218 u32 DMA2_IRQ_Status : 1; /* When set(1) the DMA2 counter had generated an IRQ. Read Only. */
219 u32 DMA2_Timer_Status : 1; /* When set(1) the DMA2 timer had generated an IRQ. Read Only. */
220 u32 DMA1_Size_IRQ_Status : 1; /* (Read only). This register is read after an interrupt to */
221 u32 DMA2_Size_IRQ_Status : 1; /* find out why we had an IRQ. Reading this register will clear this bit. Packet count*/
222 u32 Mailbox_from_V8_Status_sig: 1; /* Same as above. Reading this register will clear this bit. */
223 u32 Data_receiver_error : 1; /* 1 indicate an error in the receiver Front End (Tuner module) */
224 u32 Continuity_error_flag : 1; /* 1 indicates a continuity error in the TS stream. */
225 u32 LLC_SNAP_FLAG_set : 1; /* 1 indicates that the LCC_SNAP_FLAG was set. */
226 u32 Transport_Error : 1; /* When set indicates that an unexpected packet was received. */
227 u32 reserved :21;
228 } irq_20c;
229
230
231 /* Software reset register */
232 struct {
233 u32 reset_blocks : 8; /* Enabled when Block_reset_enable = 0xB2 and 0x208 bits 15:8 = 0x00.
234 Each bit location represents a 0x100 block of registers. Writing
235 a one in a bit location resets that block of registers and the logic
236 that it controls. */
237 u32 Block_reset_enable : 8; /* This variable is set to 0xB2 when the register is written. */
238 u32 Special_controls :16; /* Asserts Reset_V8 => 0xC258; Turns on pci encryption => 0xC25A;
239 Turns off pci encryption => 0xC259 Note: pci_encryption default
240 at power-up is ON. */
241 } sw_reset_210;
242
243 struct {
244 u32 vuart_oe_sig : 1; /* When clear, the V8 processor has sole control of the serial UART
245 (RS-232 Smart Card interface). When set, the IBI interface
246 defined by register 0x600 controls the serial UART. */
247 u32 v2WS_oe_sig : 1; /* When clear, the V8 processor has direct control of the Two-line
248 Serial Master EEPROM target. When set, the Two-line Serial Master
249 EEPROM target interface is controlled by IBI register 0x100. */
250 u32 halt_V8_sig : 1; /* When set, contiguous wait states are applied to the V8-space
251 bus masters. Once this signal is cleared, normal V8-space
252 operations resume. */
253 u32 section_pkg_enable_sig: 1; /* When set, this signal enables the front end translation circuitry
254 to process section packed transport streams. */
255 u32 s2p_sel_sig : 1; /* Serial to parallel conversion. When set, polarized transport data
256 within the FlexCop3 front end circuitry is converted from a serial
257 stream into parallel data before downstream processing otherwise
258 interprets the data. */
259 u32 unused1 : 3;
260 u32 polarity_PS_CLK_sig: 1; /* This signal is used to invert the input polarity of the tranport
261 stream CLOCK signal before any processing occurs on the transport
262 stream within FlexCop3. */
263 u32 polarity_PS_VALID_sig: 1; /* This signal is used to invert the input polarity of the tranport
264 stream VALID signal before any processing occurs on the transport
265 stream within FlexCop3. */
266 u32 polarity_PS_SYNC_sig: 1; /* This signal is used to invert the input polarity of the tranport
267 stream SYNC signal before any processing occurs on the transport
268 stream within FlexCop3. */
269 u32 polarity_PS_ERR_sig: 1; /* This signal is used to invert the input polarity of the tranport
270 stream ERROR signal before any processing occurs on the transport
271 stream within FlexCop3. */
272 u32 unused2 :20;
273 } misc_214;
274
275 /* Mailbox from V8 to host */
276 struct {
277 u32 Mailbox_from_V8 :32; /* When this register is written by either the V8 processor or by an
278 end host, an interrupt is generated to the PCI host to indicate
279 that mailbox data is available. Reading register 20c will clear
280 the IRQ. */
281 } mbox_v8_to_host_218;
282
283 /* Mailbox from host to v8 Mailbox_to_V8
284 * Mailbox_to_V8 mailbox storage register
285 * used to send messages from PCI to V8. Writing to this register will send an
286 * IRQ to the V8. Then it can read the data from here. Reading this register
287 * will clear the IRQ. If the V8 is halted and bit 31 of this register is set,
288 * then this register is used instead as a direct interface to access the
289 * V8space memory.
290 */
291 struct {
292 u32 sysramaccess_data : 8; /* Data byte written or read from the specified address in V8 SysRAM. */
293 u32 sysramaccess_addr :15; /* 15 bit address used to access V8 Sys-RAM. */
294 u32 unused : 7;
295 u32 sysramaccess_write: 1; /* Write flag used to latch data into the V8 SysRAM. */
296 u32 sysramaccess_busmuster: 1; /* Setting this bit when the V8 is halted at 0x214 Bit(2) allows
297 this IBI register interface to directly drive the V8-space memory. */
298 } mbox_host_to_v8_21c;
299
300
301 /* PIDs, Translation Bit, SMC Filter Select 0x300 to 0x31c */
302 struct {
303 u32 Stream1_PID :13; /* Primary use is receiving Net data, so these 13 bits normally
304 hold the PID value for the desired network stream. */
305 u32 Stream1_trans : 1; /* When set, Net translation will take place for Net data ferried in TS packets. */
306 u32 MAC_Multicast_filter : 1; /* When clear, multicast MAC filtering is not allowed for Stream1 and PID_n filters. */
307 u32 debug_flag_pid_saved : 1;
308 u32 Stream2_PID :13; /* 13 bits for Stream 2 PID filter value. General use. */
309 u32 Stream2_trans : 1; /* When set Tables/CAI translation will take place for the data ferried in
310 Stream2_PID TS packets. */
311 u32 debug_flag_write_status00 : 1;
312 u32 debug_fifo_problem : 1;
313 } pid_filter_300;
314
315 struct {
316 u32 PCR_PID :13; /* PCR stream PID filter value. Primary use is Program Clock Reference stream filtering. */
317 u32 PCR_trans : 1; /* When set, Tables/CAI translation will take place for these packets. */
318 u32 debug_overrun3 : 1;
319 u32 debug_overrun2 : 1;
320 u32 PMT_PID :13; /* stream PID filter value. Primary use is Program Management Table segment filtering. */
321 u32 PMT_trans : 1; /* When set, Tables/CAI translation will take place for these packets. */
322 u32 reserved : 2;
323 } pid_filter_304;
324
325 struct {
326 u32 EMM_PID :13; /* EMM PID filter value. Primary use is Entitlement Management Messaging for
327 conditional access-related data. */
328 u32 EMM_trans : 1; /* When set, Tables/CAI translation will take place for these packets. */
329 u32 EMM_filter_4 : 1; /* When set will pass only EMM data possessing the same ID code as the
330 first four bytes (32 bits) of the end-user s 6-byte Smart Card ID number Select */
331 u32 EMM_filter_6 : 1; /* When set will pass only EMM data possessing the same 6-byte code as the end-users
332 complete 6-byte Smart Card ID number. */
333 u32 ECM_PID :13; /* ECM PID filter value. Primary use is Entitlement Control Messaging for conditional
334 access-related data. */
335 u32 ECM_trans : 1; /* When set, Tables/CAI translation will take place for these packets. */
336 u32 reserved : 2;
337 } pid_filter_308;
338
339 struct {
340 u32 Group_PID :13; /* PID value for group filtering. */
341 u32 Group_trans : 1; /* When set, Tables/CAI translation will take place for these packets. */
342 u32 unused1 : 2;
343 u32 Group_mask :13; /* Mask value used in logical "and" equation that defines group filtering */
344 u32 unused2 : 3;
345 } pid_filter_30c_ext_ind_0_7;
346
347 struct {
348 u32 net_master_read :17;
349 u32 unused :15;
350 } pid_filter_30c_ext_ind_1;
351
352 struct {
353 u32 net_master_write :17;
354 u32 unused :15;
355 } pid_filter_30c_ext_ind_2;
356
357 struct {
358 u32 next_net_master_write :17;
359 u32 unused :15;
360 } pid_filter_30c_ext_ind_3;
361
362 struct {
363 u32 unused1 : 1;
364 u32 state_write :10;
365 u32 reserved1 : 6; /* default: 000100 */
366 u32 stack_read :10;
367 u32 reserved2 : 5; /* default: 00100 */
368 } pid_filter_30c_ext_ind_4;
369
370 struct {
371 u32 stack_cnt :10;
372 u32 unused :22;
373 } pid_filter_30c_ext_ind_5;
374
375 struct {
376 u32 pid_fsm_save_reg0 : 2;
377 u32 pid_fsm_save_reg1 : 2;
378 u32 pid_fsm_save_reg2 : 2;
379 u32 pid_fsm_save_reg3 : 2;
380 u32 pid_fsm_save_reg4 : 2;
381 u32 pid_fsm_save_reg300 : 2;
382 u32 write_status1 : 2;
383 u32 write_status4 : 2;
384 u32 data_size_reg :12;
385 u32 unused : 4;
386 } pid_filter_30c_ext_ind_6;
387
388 struct {
389 u32 index_reg : 5; /* (Index pointer) Points at an internal PIDn register. A binary code
390 representing one of 32 internal PIDn registers as well as its
391 corresponding internal MAC_lown register. */
392 u32 extra_index_reg : 3; /* This vector is used to select between sets of debug signals routed to register 0x30c. */
393 u32 AB_select : 1; /* Used in conjunction with 0x31c. read/write to the MAC_highA or MAC_highB register
394 0=MAC_highB register, 1=MAC_highA */
395 u32 pass_alltables : 1; /* 1=Net packets are not filtered against the Network Table ID found in register 0x400.
396 All types of networks (DVB, ATSC, ISDB) are passed. */
397 u32 unused :22;
398 } index_reg_310;
399
400 struct {
401 u32 PID :13; /* PID value */
402 u32 PID_trans : 1; /* translation will take place for packets filtered */
403 u32 PID_enable_bit : 1; /* When set this PID filter is enabled */
404 u32 reserved :17;
405 } pid_n_reg_314;
406
407 struct {
408 u32 A4_byte : 8;
409 u32 A5_byte : 8;
410 u32 A6_byte : 8;
411 u32 Enable_bit : 1; /* enabled (1) or disabled (1) */
412 u32 HighAB_bit : 1; /* use MAC_highA (1) or MAC_highB (0) as MSB */
413 u32 reserved : 6;
414 } mac_low_reg_318;
415
416 struct {
417 u32 A1_byte : 8;
418 u32 A2_byte : 8;
419 u32 A3_byte : 8;
420 u32 reserved : 8;
421 } mac_high_reg_31c;
422
423 /* Table, SMCID,MACDestination Filters 0x400 to 0x41c */
424 struct {
425 u32 reserved :16;
426 #define fc_data_Tag_ID_DVB 0x3e
427 #define fc_data_Tag_ID_ATSC 0x3f
428 #define fc_data_Tag_ID_IDSB 0x8b
429 u32 data_Tag_ID :16;
430 } data_tag_400;
431
432 struct {
433 u32 Card_IDbyte6 : 8;
434 u32 Card_IDbyte5 : 8;
435 u32 Card_IDbyte4 : 8;
436 u32 Card_IDbyte3 : 8;
437 } card_id_408;
438
439 struct {
440 u32 Card_IDbyte2 : 8;
441 u32 Card_IDbyte1 : 8;
442 } card_id_40c;
443
444 /* holding the unique mac address of the receiver which houses the FlexCopIII */
445 struct {
446 u32 MAC1 : 8;
447 u32 MAC2 : 8;
448 u32 MAC3 : 8;
449 u32 MAC6 : 8;
450 } mac_address_418;
451
452 struct {
453 u32 MAC7 : 8;
454 u32 MAC8 : 8;
455 u32 reserved : 16;
456 } mac_address_41c;
457
458 struct {
459 u32 transmitter_data_byte : 8;
460 u32 ReceiveDataReady : 1;
461 u32 ReceiveByteFrameError: 1;
462 u32 txbuffempty : 1;
463 u32 reserved :21;
464 } ci_600;
465
466 struct {
467 u32 pi_d : 8;
468 u32 pi_ha :20;
469 u32 pi_rw : 1;
470 u32 pi_component_reg : 3;
471 } pi_604;
472
473 struct {
474 u32 serialReset : 1;
475 u32 oncecycle_read : 1;
476 u32 Timer_Read_req : 1;
477 u32 Timer_Load_req : 1;
478 u32 timer_data : 7;
479 u32 unused : 1; /* ??? not mentioned in data book */
480 u32 Timer_addr : 5;
481 u32 reserved : 3;
482 u32 pcmcia_a_mod_pwr_n : 1;
483 u32 pcmcia_b_mod_pwr_n : 1;
484 u32 config_Done_stat : 1;
485 u32 config_Init_stat : 1;
486 u32 config_Prog_n : 1;
487 u32 config_wr_n : 1;
488 u32 config_cs_n : 1;
489 u32 config_cclk : 1;
490 u32 pi_CiMax_IRQ_n : 1;
491 u32 pi_timeout_status : 1;
492 u32 pi_wait_n : 1;
493 u32 pi_busy_n : 1;
494 } pi_608;
495
496 struct {
497 u32 PID :13;
498 u32 key_enable : 1;
499 #define fc_key_code_default 0x1
500 #define fc_key_code_even 0x2
501 #define fc_key_code_odd 0x3
502 u32 key_code : 2;
503 u32 key_array_col : 3;
504 u32 key_array_row : 5;
505 u32 dvb_en : 1; /* 0=TS bypasses the Descrambler */
506 u32 rw_flag : 1;
507 u32 reserved : 6;
508 } dvb_reg_60c;
509
510 /* SRAM and Output Destination 0x700 to 0x714 */
511 struct {
512 u32 sram_addr :15;
513 u32 sram_rw : 1; /* 0=write, 1=read */
514 u32 sram_data : 8;
515 u32 sc_xfer_bit : 1;
516 u32 reserved1 : 3;
517 u32 oe_pin_reg : 1;
518 u32 ce_pin_reg : 1;
519 u32 reserved2 : 1;
520 u32 start_sram_ibi : 1;
521 } sram_ctrl_reg_700;
522
523 struct {
524 u32 net_addr_read :16;
525 u32 net_addr_write :16;
526 } net_buf_reg_704;
527
528 struct {
529 u32 cai_read :11;
530 u32 reserved1 : 5;
531 u32 cai_write :11;
532 u32 reserved2 : 6;
533 u32 cai_cnt : 4;
534 } cai_buf_reg_708;
535
536 struct {
537 u32 cao_read :11;
538 u32 reserved1 : 5;
539 u32 cap_write :11;
540 u32 reserved2 : 6;
541 u32 cao_cnt : 4;
542 } cao_buf_reg_70c;
543
544 struct {
545 u32 media_read :11;
546 u32 reserved1 : 5;
547 u32 media_write :11;
548 u32 reserved2 : 6;
549 u32 media_cnt : 4;
550 } media_buf_reg_710;
551
552 struct {
553 u32 NET_Dest : 2;
554 u32 CAI_Dest : 2;
555 u32 CAO_Dest : 2;
556 u32 MEDIA_Dest : 2;
557 u32 net_ovflow_error : 1;
558 u32 media_ovflow_error : 1;
559 u32 cai_ovflow_error : 1;
560 u32 cao_ovflow_error : 1;
561 u32 ctrl_usb_wan : 1;
562 u32 ctrl_sramdma : 1;
563 u32 ctrl_maximumfill : 1;
564 u32 reserved :17;
565 } sram_dest_reg_714;
566
567 struct {
568 u32 net_cnt :12;
569 u32 reserved1 : 4;
570 u32 net_addr_read : 1;
571 u32 reserved2 : 3;
572 u32 net_addr_write : 1;
573 u32 reserved3 :11;
574 } net_buf_reg_718;
575
576 struct {
577 u32 wan_speed_sig : 2;
578 u32 reserved1 : 6;
579 u32 wan_wait_state : 8;
580 u32 sram_chip : 2;
581 u32 sram_memmap : 2;
582 u32 reserved2 : 4;
583 u32 wan_pkt_frame : 4;
584 u32 reserved3 : 4;
585 } wan_ctrl_reg_71c;
586 } flexcop_ibi_value;
587
588 extern flexcop_ibi_value ibi_zero;
589
590 typedef enum {
591 FC_I2C_PORT_DEMOD = 1,
592 FC_I2C_PORT_EEPROM = 2,
593 FC_I2C_PORT_TUNER = 3,
594 } flexcop_i2c_port_t;
595
596 typedef enum {
597 FC_WRITE = 0,
598 FC_READ = 1,
599 } flexcop_access_op_t;
600
601 typedef enum {
602 FC_SRAM_DEST_NET = 1,
603 FC_SRAM_DEST_CAI = 2,
604 FC_SRAM_DEST_CAO = 4,
605 FC_SRAM_DEST_MEDIA = 8
606 } flexcop_sram_dest_t;
607
608 typedef enum {
609 FC_SRAM_DEST_TARGET_WAN_USB = 0,
610 FC_SRAM_DEST_TARGET_DMA1 = 1,
611 FC_SRAM_DEST_TARGET_DMA2 = 2,
612 FC_SRAM_DEST_TARGET_FC3_CA = 3
613 } flexcop_sram_dest_target_t;
614
615 typedef enum {
616 FC_SRAM_2_32KB = 0, /* 64KB */
617 FC_SRAM_1_32KB = 1, /* 32KB - default fow FCII */
618 FC_SRAM_1_128KB = 2, /* 128KB */
619 FC_SRAM_1_48KB = 3, /* 48KB - default for FCIII */
620 } flexcop_sram_type_t;
621
622 typedef enum {
623 FC_WAN_SPEED_4MBITS = 0,
624 FC_WAN_SPEED_8MBITS = 1,
625 FC_WAN_SPEED_12MBITS = 2,
626 FC_WAN_SPEED_16MBITS = 3,
627 } flexcop_wan_speed_t;
628
629 typedef enum {
630 FC_DMA_1 = 1,
631 FC_DMA_2 = 2,
632 } flexcop_dma_index_t;
633
634 typedef enum {
635 FC_DMA_SUBADDR_0 = 1,
636 FC_DMA_SUBADDR_1 = 2,
637 } flexcop_dma_addr_index_t;
638
639 /* names of the particular registers */
640 typedef enum {
641 dma1_000 = 0x000,
642 dma1_004 = 0x004,
643 dma1_008 = 0x008,
644 dma1_00c = 0x00c,
645 dma2_010 = 0x010,
646 dma2_014 = 0x014,
647 dma2_018 = 0x018,
648 dma2_01c = 0x01c,
649
650 tw_sm_c_100 = 0x100,
651 tw_sm_c_104 = 0x104,
652 tw_sm_c_108 = 0x108,
653 tw_sm_c_10c = 0x10c,
654 tw_sm_c_110 = 0x110,
655
656 lnb_switch_freq_200 = 0x200,
657 misc_204 = 0x204,
658 ctrl_208 = 0x208,
659 irq_20c = 0x20c,
660 sw_reset_210 = 0x210,
661 misc_214 = 0x214,
662 mbox_v8_to_host_218 = 0x218,
663 mbox_host_to_v8_21c = 0x21c,
664
665 pid_filter_300 = 0x300,
666 pid_filter_304 = 0x304,
667 pid_filter_308 = 0x308,
668 pid_filter_30c = 0x30c,
669 index_reg_310 = 0x310,
670 pid_n_reg_314 = 0x314,
671 mac_low_reg_318 = 0x318,
672 mac_high_reg_31c = 0x31c,
673
674 data_tag_400 = 0x400,
675 card_id_408 = 0x408,
676 card_id_40c = 0x40c,
677 mac_address_418 = 0x418,
678 mac_address_41c = 0x41c,
679
680 ci_600 = 0x600,
681 pi_604 = 0x604,
682 pi_608 = 0x608,
683 dvb_reg_60c = 0x60c,
684
685 sram_ctrl_reg_700 = 0x700,
686 net_buf_reg_704 = 0x704,
687 cai_buf_reg_708 = 0x708,
688 cao_buf_reg_70c = 0x70c,
689 media_buf_reg_710 = 0x710,
690 sram_dest_reg_714 = 0x714,
691 net_buf_reg_718 = 0x718,
692 wan_ctrl_reg_71c = 0x71c,
693 } flexcop_ibi_register;
694
695 #define flexcop_set_ibi_value(reg,attr,val) { \
696 flexcop_ibi_value v = fc->read_ibi_reg(fc,reg); \
697 v.reg.attr = val; \
698 fc->write_ibi_reg(fc,reg,v); \
699 }
700
701 #endif
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