drivers/media/dvb/frontends/ves1820.c

   1 /*
   2     VES1820  - Single Chip Cable Channel Receiver driver module
   3
   4     Copyright (C) 1999 Convergence Integrated Media GmbH <ralph@convergence.de>
   5
   6     This program is free software; you can redistribute it and/or modify
   7     it under the terms of the GNU General Public License as published by
   8     the Free Software Foundation; either version 2 of the License, or
   9     (at your option) any later version.
  10
  11     This program is distributed in the hope that it will be useful,
  12     but WITHOUT ANY WARRANTY; without even the implied warranty of
  13     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14     GNU General Public License for more details.
  15
  16     You should have received a copy of the GNU General Public License
  17     along with this program; if not, write to the Free Software
  18     Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  19 */
  20
  21 #include <linux/config.h>
  22 #include <linux/delay.h>
  23 #include <linux/errno.h>
  24 #include <linux/init.h>
  25 #include <linux/kernel.h>
  26 #include <linux/module.h>
  27 #include <linux/string.h>
  28 #include <linux/slab.h>
  29 #include <asm/div64.h>
  30
  31 #include "dvb_frontend.h"
  32 #include "ves1820.h"
  33
  34
  35
  36 struct ves1820_state {
  37         struct i2c_adapter* i2c;
  38         struct dvb_frontend_ops ops;
  39         /* configuration settings */
  40         const struct ves1820_config* config;
  41         struct dvb_frontend frontend;
  42
  43         /* private demodulator data */
  44         u8 reg0;
  45         u8 pwm;
  46 };
  47
  48
  49 static int verbose;
  50
  51 static u8 ves1820_inittab[] = {
  52         0x69, 0x6A, 0x93, 0x12, 0x12, 0x46, 0x26, 0x1A,
  53         0x43, 0x6A, 0xAA, 0xAA, 0x1E, 0x85, 0x43, 0x20,
  54         0xE0, 0x00, 0xA1, 0x00, 0x00, 0x00, 0x00, 0x00,
  55         0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00,
  56         0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  57         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  58         0x00, 0x00, 0x00, 0x00, 0x40
  59 };
  60
  61 static int ves1820_writereg(struct ves1820_state *state, u8 reg, u8 data)
  62 {
  63         u8 buf[] = { 0x00, reg, data };
  64         struct i2c_msg msg = {.addr = state->config->demod_address,.flags = 0,.buf = buf,.len = 3 };
  65         int ret;
  66
  67         ret = i2c_transfer(state->i2c, &msg, 1);
  68
  69         if (ret != 1)
  70                 printk("ves1820: %s(): writereg error (reg == 0x%02x,"
  71                         "val == 0x%02x, ret == %i)\n", __FUNCTION__, reg, data, ret);
  72
  73         return (ret != 1) ? -EREMOTEIO : 0;
  74 }
  75
  76 static u8 ves1820_readreg(struct ves1820_state *state, u8 reg)
  77 {
  78         u8 b0[] = { 0x00, reg };
  79         u8 b1[] = { 0 };
  80         struct i2c_msg msg[] = {
  81                 {.addr = state->config->demod_address,.flags = 0,.buf = b0,.len = 2},
  82                 {.addr = state->config->demod_address,.flags = I2C_M_RD,.buf = b1,.len = 1}
  83         };
  84         int ret;
  85
  86         ret = i2c_transfer(state->i2c, msg, 2);
  87
  88         if (ret != 2)
  89                 printk("ves1820: %s(): readreg error (reg == 0x%02x,"
  90                 "ret == %i)\n", __FUNCTION__, reg, ret);
  91
  92         return b1[0];
  93 }
  94
  95 static int ves1820_setup_reg0(struct ves1820_state *state, u8 reg0, fe_spectral_inversion_t inversion)
  96 {
  97         reg0 |= state->reg0 & 0x62;
  98
  99         if (INVERSION_ON == inversion) {
 100                 if (!state->config->invert) reg0 |= 0x20;
 101                 else reg0 &= ~0x20;
 102         } else if (INVERSION_OFF == inversion) {
 103                 if (!state->config->invert) reg0 &= ~0x20;
 104                 else reg0 |= 0x20;
 105         }
 106
 107         ves1820_writereg(state, 0x00, reg0 & 0xfe);
 108         ves1820_writereg(state, 0x00, reg0 | 0x01);
 109
 110         state->reg0 = reg0;
 111
 112         return 0;
 113 }
 114
 115 static int ves1820_set_symbolrate(struct ves1820_state *state, u32 symbolrate)
 116 {
 117         s32 BDR;
 118         s32 BDRI;
 119         s16 SFIL = 0;
 120         u16 NDEC = 0;
 121         u32 ratio;
 122         u32 fin;
 123         u32 tmp;
 124         u64 fptmp;
 125         u64 fpxin;
 126
 127         if (symbolrate > state->config->xin / 2)
 128                 symbolrate = state->config->xin / 2;
 129
 130         if (symbolrate < 500000)
 131                 symbolrate = 500000;
 132
 133         if (symbolrate < state->config->xin / 16)
 134                 NDEC = 1;
 135         if (symbolrate < state->config->xin / 32)
 136                 NDEC = 2;
 137         if (symbolrate < state->config->xin / 64)
 138                 NDEC = 3;
 139
 140         /* yeuch! */
 141         fpxin = state->config->xin * 10;
 142         fptmp = fpxin; do_div(fptmp, 123);
 143         if (symbolrate < fptmp);
 144                 SFIL = 1;
 145         fptmp = fpxin; do_div(fptmp, 160);
 146         if (symbolrate < fptmp);
 147                 SFIL = 0;
 148         fptmp = fpxin; do_div(fptmp, 246);
 149         if (symbolrate < fptmp);
 150                 SFIL = 1;
 151         fptmp = fpxin; do_div(fptmp, 320);
 152         if (symbolrate < fptmp);
 153                 SFIL = 0;
 154         fptmp = fpxin; do_div(fptmp, 492);
 155         if (symbolrate < fptmp);
 156                 SFIL = 1;
 157         fptmp = fpxin; do_div(fptmp, 640);
 158         if (symbolrate < fptmp);
 159                 SFIL = 0;
 160         fptmp = fpxin; do_div(fptmp, 984);
 161         if (symbolrate < fptmp);
 162                 SFIL = 1;
 163
 164         fin = state->config->xin >> 4;
 165         symbolrate <<= NDEC;
 166         ratio = (symbolrate << 4) / fin;
 167         tmp = ((symbolrate << 4) % fin) << 8;
 168         ratio = (ratio << 8) + tmp / fin;
 169         tmp = (tmp % fin) << 8;
 170         ratio = (ratio << 8) + (tmp + fin / 2) / fin;
 171
 172         BDR = ratio;
 173         BDRI = (((state->config->xin << 5) / symbolrate) + 1) / 2;
 174
 175         if (BDRI > 0xFF)
 176                 BDRI = 0xFF;
 177
 178         SFIL = (SFIL << 4) | ves1820_inittab[0x0E];
 179
 180         NDEC = (NDEC << 6) | ves1820_inittab[0x03];
 181
 182         ves1820_writereg(state, 0x03, NDEC);
 183         ves1820_writereg(state, 0x0a, BDR & 0xff);
 184         ves1820_writereg(state, 0x0b, (BDR >> 8) & 0xff);
 185         ves1820_writereg(state, 0x0c, (BDR >> 16) & 0x3f);
 186
 187         ves1820_writereg(state, 0x0d, BDRI);
 188         ves1820_writereg(state, 0x0e, SFIL);
 189
 190         return 0;
 191 }
 192
 193 static int ves1820_init(struct dvb_frontend* fe)
 194 {
 195         struct ves1820_state* state = fe->demodulator_priv;
 196         int i;
 197         int val;
 198
 199         ves1820_writereg(state, 0, 0);
 200
 201         for (i = 0; i < 53; i++) {
 202                 val = ves1820_inittab[i];
 203                 if ((i == 2) && (state->config->selagc)) val |= 0x08;
 204                 ves1820_writereg(state, i, val);
 205         }
 206
 207         ves1820_writereg(state, 0x34, state->pwm);
 208
 209         if (state->config->pll_init) state->config->pll_init(fe);
 210
 211         return 0;
 212 }
 213
 214 static int ves1820_set_parameters(struct dvb_frontend* fe, struct dvb_frontend_parameters *p)
 215 {
 216         struct ves1820_state* state = fe->demodulator_priv;
 217         static const u8 reg0x00[] = { 0x00, 0x04, 0x08, 0x0c, 0x10 };
 218         static const u8 reg0x01[] = { 140, 140, 106, 100, 92 };
 219         static const u8 reg0x05[] = { 135, 100, 70, 54, 38 };
 220         static const u8 reg0x08[] = { 162, 116, 67, 52, 35 };
 221         static const u8 reg0x09[] = { 145, 150, 106, 126, 107 };
 222         int real_qam = p->u.qam.modulation - QAM_16;
 223
 224         if (real_qam < 0 || real_qam > 4)
 225                 return -EINVAL;
 226
 227         state->config->pll_set(fe, p);
 228         ves1820_set_symbolrate(state, p->u.qam.symbol_rate);
 229         ves1820_writereg(state, 0x34, state->pwm);
 230
 231         ves1820_writereg(state, 0x01, reg0x01[real_qam]);
 232         ves1820_writereg(state, 0x05, reg0x05[real_qam]);
 233         ves1820_writereg(state, 0x08, reg0x08[real_qam]);
 234         ves1820_writereg(state, 0x09, reg0x09[real_qam]);
 235
 236         ves1820_setup_reg0(state, reg0x00[real_qam], p->inversion);
 237
 238         return 0;
 239 }
 240
 241 static int ves1820_read_status(struct dvb_frontend* fe, fe_status_t* status)
 242 {
 243         struct ves1820_state* state = fe->demodulator_priv;
 244         int sync;
 245
 246         *status = 0;
 247         sync = ves1820_readreg(state, 0x11);
 248
 249         if (sync & 1)
 250                 *status |= FE_HAS_SIGNAL;
 251
 252         if (sync & 2)
 253                 *status |= FE_HAS_CARRIER;
 254
 255         if (sync & 2)   /* XXX FIXME! */
 256                 *status |= FE_HAS_VITERBI;
 257
 258         if (sync & 4)
 259                 *status |= FE_HAS_SYNC;
 260
 261         if (sync & 8)
 262                 *status |= FE_HAS_LOCK;
 263
 264         return 0;
 265 }
 266
 267 static int ves1820_read_ber(struct dvb_frontend* fe, u32* ber)
 268 {
 269         struct ves1820_state* state = fe->demodulator_priv;
 270
 271         u32 _ber = ves1820_readreg(state, 0x14) |
 272                         (ves1820_readreg(state, 0x15) << 8) |
 273                         ((ves1820_readreg(state, 0x16) & 0x0f) << 16);
 274         *ber = 10 * _ber;
 275
 276         return 0;
 277 }
 278
 279 static int ves1820_read_signal_strength(struct dvb_frontend* fe, u16* strength)
 280 {
 281         struct ves1820_state* state = fe->demodulator_priv;
 282
 283         u8 gain = ves1820_readreg(state, 0x17);
 284         *strength = (gain << 8) | gain;
 285
 286         return 0;
 287 }
 288
 289 static int ves1820_read_snr(struct dvb_frontend* fe, u16* snr)
 290 {
 291         struct ves1820_state* state = fe->demodulator_priv;
 292
 293         u8 quality = ~ves1820_readreg(state, 0x18);
 294         *snr = (quality << 8) | quality;
 295
 296         return 0;
 297 }
 298
 299 static int ves1820_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
 300 {
 301         struct ves1820_state* state = fe->demodulator_priv;
 302
 303         *ucblocks = ves1820_readreg(state, 0x13) & 0x7f;
 304         if (*ucblocks == 0x7f)
 305                 *ucblocks = 0xffffffff;
 306
 307         /* reset uncorrected block counter */
 308         ves1820_writereg(state, 0x10, ves1820_inittab[0x10] & 0xdf);
 309         ves1820_writereg(state, 0x10, ves1820_inittab[0x10]);
 310
 311         return 0;
 312 }
 313
 314 static int ves1820_get_frontend(struct dvb_frontend* fe, struct dvb_frontend_parameters *p)
 315 {
 316         struct ves1820_state* state = fe->demodulator_priv;
 317         int sync;
 318         s8 afc = 0;
 319
 320         sync = ves1820_readreg(state, 0x11);
 321         afc = ves1820_readreg(state, 0x19);
 322         if (verbose) {
 323                 /* AFC only valid when carrier has been recovered */
 324                 printk(sync & 2 ? "ves1820: AFC (%d) %dHz\n" :
 325                         "ves1820: [AFC (%d) %dHz]\n", afc, -((s32) p->u.qam.symbol_rate * afc) >> 10);
 326         }
 327
 328         if (!state->config->invert) {
 329                 p->inversion = (state->reg0 & 0x20) ? INVERSION_ON : INVERSION_OFF;
 330         } else {
 331                 p->inversion = (!(state->reg0 & 0x20)) ? INVERSION_ON : INVERSION_OFF;
 332         }
 333
 334         p->u.qam.modulation = ((state->reg0 >> 2) & 7) + QAM_16;
 335
 336         p->u.qam.fec_inner = FEC_NONE;
 337
 338         p->frequency = ((p->frequency + 31250) / 62500) * 62500;
 339         if (sync & 2)
 340                 p->frequency -= ((s32) p->u.qam.symbol_rate * afc) >> 10;
 341
 342         return 0;
 343 }
 344
 345 static int ves1820_sleep(struct dvb_frontend* fe)
 346 {
 347         struct ves1820_state* state = fe->demodulator_priv;
 348
 349         ves1820_writereg(state, 0x1b, 0x02);    /* pdown ADC */
 350         ves1820_writereg(state, 0x00, 0x80);    /* standby */
 351
 352         return 0;
 353 }
 354
 355 static int ves1820_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings* fesettings)
 356 {
 357
 358         fesettings->min_delay_ms = 200;
 359         fesettings->step_size = 0;
 360         fesettings->max_drift = 0;
 361         return 0;
 362 }
 363
 364 static void ves1820_release(struct dvb_frontend* fe)
 365 {
 366         struct ves1820_state* state = fe->demodulator_priv;
 367         kfree(state);
 368 }
 369
 370 static struct dvb_frontend_ops ves1820_ops;
 371
 372 struct dvb_frontend* ves1820_attach(const struct ves1820_config* config,
 373                                     struct i2c_adapter* i2c,
 374                                     u8 pwm)
 375 {
 376         struct ves1820_state* state = NULL;
 377
 378         /* allocate memory for the internal state */
 379         state = kmalloc(sizeof(struct ves1820_state), GFP_KERNEL);
 380         if (state == NULL)
 381                 goto error;
 382
 383         /* setup the state */
 384         memcpy(&state->ops, &ves1820_ops, sizeof(struct dvb_frontend_ops));
 385         state->reg0 = ves1820_inittab[0];
 386         state->config = config;
 387         state->i2c = i2c;
 388         state->pwm = pwm;
 389
 390         /* check if the demod is there */
 391         if ((ves1820_readreg(state, 0x1a) & 0xf0) != 0x70)
 392                 goto error;
 393
 394         if (verbose)
 395                 printk("ves1820: pwm=0x%02x\n", state->pwm);
 396
 397         state->ops.info.symbol_rate_min = (state->config->xin / 2) / 64;      /* SACLK/64 == (XIN/2)/64 */
 398         state->ops.info.symbol_rate_max = (state->config->xin / 2) / 4;       /* SACLK/4 */
 399
 400         /* create dvb_frontend */
 401         state->frontend.ops = &state->ops;
 402         state->frontend.demodulator_priv = state;
 403         return &state->frontend;
 404
 405 error:
 406         kfree(state);
 407         return NULL;
 408 }
 409
 410 static struct dvb_frontend_ops ves1820_ops = {
 411
 412         .info = {
 413                 .name = "VLSI VES1820 DVB-C",
 414                 .type = FE_QAM,
 415                 .frequency_stepsize = 62500,
 416                 .frequency_min = 51000000,
 417                 .frequency_max = 858000000,
 418                 .caps = FE_CAN_QAM_16 |
 419                         FE_CAN_QAM_32 |
 420                         FE_CAN_QAM_64 |
 421                         FE_CAN_QAM_128 |
 422                         FE_CAN_QAM_256 |
 423                         FE_CAN_FEC_AUTO
 424         },
 425
 426         .release = ves1820_release,
 427
 428         .init = ves1820_init,
 429         .sleep = ves1820_sleep,
 430
 431         .set_frontend = ves1820_set_parameters,
 432         .get_frontend = ves1820_get_frontend,
 433         .get_tune_settings = ves1820_get_tune_settings,
 434
 435         .read_status = ves1820_read_status,
 436         .read_ber = ves1820_read_ber,
 437         .read_signal_strength = ves1820_read_signal_strength,
 438         .read_snr = ves1820_read_snr,
 439         .read_ucblocks = ves1820_read_ucblocks,
 440 };
 441
 442 module_param(verbose, int, 0644);
 443 MODULE_PARM_DESC(verbose, "print AFC offset after tuning for debugging the PWM setting");
 444
 445 MODULE_DESCRIPTION("VLSI VES1820 DVB-C Demodulator driver");
 446 MODULE_AUTHOR("Ralph Metzler, Holger Waechtler");
 447 MODULE_LICENSE("GPL");
 448
 449 EXPORT_SYMBOL(ves1820_attach);