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[TG3]: Set minimal hw interrupt mitigation.
[linux-2.6/verdex.git] / drivers / mmc / pxamci.c
blobb78beb1b0159cc66748c15c19e05407c8c12d076
1 /*
2 * linux/drivers/mmc/pxa.c - PXA MMCI driver
3 *
4 * Copyright (C) 2003 Russell King, All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This hardware is really sick:
11 * - No way to clear interrupts.
12 * - Have to turn off the clock whenever we touch the device.
13 * - Doesn't tell you how many data blocks were transferred.
14 * Yuck!
15 *
16 * 1 and 3 byte data transfers not supported
17 * max block length up to 1023
18 */
19 #include <linux/config.h>
20 #include <linux/module.h>
21 #include <linux/init.h>
22 #include <linux/ioport.h>
23 #include <linux/device.h>
24 #include <linux/delay.h>
25 #include <linux/interrupt.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/mmc/host.h>
28 #include <linux/mmc/protocol.h>
29
30 #include <asm/dma.h>
31 #include <asm/io.h>
32 #include <asm/irq.h>
33 #include <asm/scatterlist.h>
34 #include <asm/sizes.h>
35
36 #include <asm/arch/pxa-regs.h>
37 #include <asm/arch/mmc.h>
38
39 #include "pxamci.h"
40
41 #ifdef CONFIG_MMC_DEBUG
42 #define DBG(x...) printk(KERN_DEBUG x)
43 #else
44 #define DBG(x...) do { } while (0)
45 #endif
46
47 #define DRIVER_NAME "pxa2xx-mci"
48
49 #define NR_SG 1
50
51 struct pxamci_host {
52 struct mmc_host *mmc;
53 spinlock_t lock;
54 struct resource *res;
55 void __iomem *base;
56 int irq;
57 int dma;
58 unsigned int clkrt;
59 unsigned int cmdat;
60 unsigned int imask;
61 unsigned int power_mode;
62 struct pxamci_platform_data *pdata;
63
64 struct mmc_request *mrq;
65 struct mmc_command *cmd;
66 struct mmc_data *data;
67
68 dma_addr_t sg_dma;
69 struct pxa_dma_desc *sg_cpu;
70 unsigned int dma_len;
71
72 unsigned int dma_dir;
73 };
74
75 static inline unsigned int ns_to_clocks(unsigned int ns)
76 {
77 return (ns * (CLOCKRATE / 1000000) + 999) / 1000;
78 }
79
80 static void pxamci_stop_clock(struct pxamci_host *host)
81 {
82 if (readl(host->base + MMC_STAT) & STAT_CLK_EN) {
83 unsigned long timeout = 10000;
84 unsigned int v;
85
86 writel(STOP_CLOCK, host->base + MMC_STRPCL);
87
88 do {
89 v = readl(host->base + MMC_STAT);
90 if (!(v & STAT_CLK_EN))
91 break;
92 udelay(1);
93 } while (timeout--);
94
95 if (v & STAT_CLK_EN)
96 dev_err(mmc_dev(host->mmc), "unable to stop clock\n");
97 }
98 }
99
100 static void pxamci_enable_irq(struct pxamci_host *host, unsigned int mask)
101 {
102 unsigned long flags;
103
104 spin_lock_irqsave(&host->lock, flags);
105 host->imask &= ~mask;
106 writel(host->imask, host->base + MMC_I_MASK);
107 spin_unlock_irqrestore(&host->lock, flags);
108 }
109
110 static void pxamci_disable_irq(struct pxamci_host *host, unsigned int mask)
111 {
112 unsigned long flags;
113
114 spin_lock_irqsave(&host->lock, flags);
115 host->imask |= mask;
116 writel(host->imask, host->base + MMC_I_MASK);
117 spin_unlock_irqrestore(&host->lock, flags);
118 }
119
120 static void pxamci_setup_data(struct pxamci_host *host, struct mmc_data *data)
121 {
122 unsigned int nob = data->blocks;
123 unsigned int timeout;
124 u32 dcmd;
125 int i;
126
127 host->data = data;
128
129 if (data->flags & MMC_DATA_STREAM)
130 nob = 0xffff;
131
132 writel(nob, host->base + MMC_NOB);
133 writel(1 << data->blksz_bits, host->base + MMC_BLKLEN);
134
135 timeout = ns_to_clocks(data->timeout_ns) + data->timeout_clks;
136 writel((timeout + 255) / 256, host->base + MMC_RDTO);
137
138 if (data->flags & MMC_DATA_READ) {
139 host->dma_dir = DMA_FROM_DEVICE;
140 dcmd = DCMD_INCTRGADDR | DCMD_FLOWTRG;
141 DRCMRTXMMC = 0;
142 DRCMRRXMMC = host->dma | DRCMR_MAPVLD;
143 } else {
144 host->dma_dir = DMA_TO_DEVICE;
145 dcmd = DCMD_INCSRCADDR | DCMD_FLOWSRC;
146 DRCMRRXMMC = 0;
147 DRCMRTXMMC = host->dma | DRCMR_MAPVLD;
148 }
149
150 dcmd |= DCMD_BURST32 | DCMD_WIDTH1;
151
152 host->dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
153 host->dma_dir);
154
155 for (i = 0; i < host->dma_len; i++) {
156 if (data->flags & MMC_DATA_READ) {
157 host->sg_cpu[i].dsadr = host->res->start + MMC_RXFIFO;
158 host->sg_cpu[i].dtadr = sg_dma_address(&data->sg[i]);
159 } else {
160 host->sg_cpu[i].dsadr = sg_dma_address(&data->sg[i]);
161 host->sg_cpu[i].dtadr = host->res->start + MMC_TXFIFO;
162 }
163 host->sg_cpu[i].dcmd = dcmd | sg_dma_len(&data->sg[i]);
164 host->sg_cpu[i].ddadr = host->sg_dma + (i + 1) *
165 sizeof(struct pxa_dma_desc);
166 }
167 host->sg_cpu[host->dma_len - 1].ddadr = DDADR_STOP;
168 wmb();
169
170 DDADR(host->dma) = host->sg_dma;
171 DCSR(host->dma) = DCSR_RUN;
172 }
173
174 static void pxamci_start_cmd(struct pxamci_host *host, struct mmc_command *cmd, unsigned int cmdat)
175 {
176 WARN_ON(host->cmd != NULL);
177 host->cmd = cmd;
178
179 if (cmd->flags & MMC_RSP_BUSY)
180 cmdat |= CMDAT_BUSY;
181
182 switch (cmd->flags & (MMC_RSP_MASK | MMC_RSP_CRC)) {
183 case MMC_RSP_SHORT | MMC_RSP_CRC:
184 cmdat |= CMDAT_RESP_SHORT;
185 break;
186 case MMC_RSP_SHORT:
187 cmdat |= CMDAT_RESP_R3;
188 break;
189 case MMC_RSP_LONG | MMC_RSP_CRC:
190 cmdat |= CMDAT_RESP_R2;
191 break;
192 default:
193 break;
194 }
195
196 writel(cmd->opcode, host->base + MMC_CMD);
197 writel(cmd->arg >> 16, host->base + MMC_ARGH);
198 writel(cmd->arg & 0xffff, host->base + MMC_ARGL);
199 writel(cmdat, host->base + MMC_CMDAT);
200 writel(host->clkrt, host->base + MMC_CLKRT);
201
202 writel(START_CLOCK, host->base + MMC_STRPCL);
203
204 pxamci_enable_irq(host, END_CMD_RES);
205 }
206
207 static void pxamci_finish_request(struct pxamci_host *host, struct mmc_request *mrq)
208 {
209 DBG("PXAMCI: request done\n");
210 host->mrq = NULL;
211 host->cmd = NULL;
212 host->data = NULL;
213 mmc_request_done(host->mmc, mrq);
214 }
215
216 static int pxamci_cmd_done(struct pxamci_host *host, unsigned int stat)
217 {
218 struct mmc_command *cmd = host->cmd;
219 int i;
220 u32 v;
221
222 if (!cmd)
223 return 0;
224
225 host->cmd = NULL;
226
227 /*
228 * Did I mention this is Sick. We always need to
229 * discard the upper 8 bits of the first 16-bit word.
230 */
231 v = readl(host->base + MMC_RES) & 0xffff;
232 for (i = 0; i < 4; i++) {
233 u32 w1 = readl(host->base + MMC_RES) & 0xffff;
234 u32 w2 = readl(host->base + MMC_RES) & 0xffff;
235 cmd->resp[i] = v << 24 | w1 << 8 | w2 >> 8;
236 v = w2;
237 }
238
239 if (stat & STAT_TIME_OUT_RESPONSE) {
240 cmd->error = MMC_ERR_TIMEOUT;
241 } else if (stat & STAT_RES_CRC_ERR && cmd->flags & MMC_RSP_CRC) {
242 #ifdef CONFIG_PXA27x
243 /*
244 * workaround for erratum #42:
245 * Intel PXA27x Family Processor Specification Update Rev 001
246 */
247 if (cmd->opcode == MMC_ALL_SEND_CID ||
248 cmd->opcode == MMC_SEND_CSD ||
249 cmd->opcode == MMC_SEND_CID) {
250 /* a bogus CRC error can appear if the msb of
251 the 15 byte response is a one */
252 if ((cmd->resp[0] & 0x80000000) == 0)
253 cmd->error = MMC_ERR_BADCRC;
254 } else {
255 DBG("ignoring CRC from command %d - *risky*\n",cmd->opcode);
256 }
257 #else
258 cmd->error = MMC_ERR_BADCRC;
259 #endif
260 }
261
262 pxamci_disable_irq(host, END_CMD_RES);
263 if (host->data && cmd->error == MMC_ERR_NONE) {
264 pxamci_enable_irq(host, DATA_TRAN_DONE);
265 } else {
266 pxamci_finish_request(host, host->mrq);
267 }
268
269 return 1;
270 }
271
272 static int pxamci_data_done(struct pxamci_host *host, unsigned int stat)
273 {
274 struct mmc_data *data = host->data;
275
276 if (!data)
277 return 0;
278
279 DCSR(host->dma) = 0;
280 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_len,
281 host->dma_dir);
282
283 if (stat & STAT_READ_TIME_OUT)
284 data->error = MMC_ERR_TIMEOUT;
285 else if (stat & (STAT_CRC_READ_ERROR|STAT_CRC_WRITE_ERROR))
286 data->error = MMC_ERR_BADCRC;
287
288 /*
289 * There appears to be a hardware design bug here. There seems to
290 * be no way to find out how much data was transferred to the card.
291 * This means that if there was an error on any block, we mark all
292 * data blocks as being in error.
293 */
294 if (data->error == MMC_ERR_NONE)
295 data->bytes_xfered = data->blocks << data->blksz_bits;
296 else
297 data->bytes_xfered = 0;
298
299 pxamci_disable_irq(host, DATA_TRAN_DONE);
300
301 host->data = NULL;
302 if (host->mrq->stop && data->error == MMC_ERR_NONE) {
303 pxamci_stop_clock(host);
304 pxamci_start_cmd(host, host->mrq->stop, 0);
305 } else {
306 pxamci_finish_request(host, host->mrq);
307 }
308
309 return 1;
310 }
311
312 static irqreturn_t pxamci_irq(int irq, void *devid, struct pt_regs *regs)
313 {
314 struct pxamci_host *host = devid;
315 unsigned int ireg;
316 int handled = 0;
317
318 ireg = readl(host->base + MMC_I_REG);
319
320 DBG("PXAMCI: irq %08x\n", ireg);
321
322 if (ireg) {
323 unsigned stat = readl(host->base + MMC_STAT);
324
325 DBG("PXAMCI: stat %08x\n", stat);
326
327 if (ireg & END_CMD_RES)
328 handled |= pxamci_cmd_done(host, stat);
329 if (ireg & DATA_TRAN_DONE)
330 handled |= pxamci_data_done(host, stat);
331 }
332
333 return IRQ_RETVAL(handled);
334 }
335
336 static void pxamci_request(struct mmc_host *mmc, struct mmc_request *mrq)
337 {
338 struct pxamci_host *host = mmc_priv(mmc);
339 unsigned int cmdat;
340
341 WARN_ON(host->mrq != NULL);
342
343 host->mrq = mrq;
344
345 pxamci_stop_clock(host);
346
347 cmdat = host->cmdat;
348 host->cmdat &= ~CMDAT_INIT;
349
350 if (mrq->data) {
351 pxamci_setup_data(host, mrq->data);
352
353 cmdat &= ~CMDAT_BUSY;
354 cmdat |= CMDAT_DATAEN | CMDAT_DMAEN;
355 if (mrq->data->flags & MMC_DATA_WRITE)
356 cmdat |= CMDAT_WRITE;
357
358 if (mrq->data->flags & MMC_DATA_STREAM)
359 cmdat |= CMDAT_STREAM;
360 }
361
362 pxamci_start_cmd(host, mrq->cmd, cmdat);
363 }
364
365 static void pxamci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
366 {
367 struct pxamci_host *host = mmc_priv(mmc);
368
369 DBG("pxamci_set_ios: clock %u power %u vdd %u.%02u\n",
370 ios->clock, ios->power_mode, ios->vdd / 100,
371 ios->vdd % 100);
372
373 if (ios->clock) {
374 unsigned int clk = CLOCKRATE / ios->clock;
375 if (CLOCKRATE / clk > ios->clock)
376 clk <<= 1;
377 host->clkrt = fls(clk) - 1;
378 pxa_set_cken(CKEN12_MMC, 1);
379
380 /*
381 * we write clkrt on the next command
382 */
383 } else {
384 pxamci_stop_clock(host);
385 pxa_set_cken(CKEN12_MMC, 0);
386 }
387
388 if (host->power_mode != ios->power_mode) {
389 host->power_mode = ios->power_mode;
390
391 if (host->pdata && host->pdata->setpower)
392 host->pdata->setpower(mmc->dev, ios->vdd);
393
394 if (ios->power_mode == MMC_POWER_ON)
395 host->cmdat |= CMDAT_INIT;
396 }
397
398 DBG("pxamci_set_ios: clkrt = %x cmdat = %x\n",
399 host->clkrt, host->cmdat);
400 }
401
402 static struct mmc_host_ops pxamci_ops = {
403 .request = pxamci_request,
404 .set_ios = pxamci_set_ios,
405 };
406
407 static void pxamci_dma_irq(int dma, void *devid, struct pt_regs *regs)
408 {
409 printk(KERN_ERR "DMA%d: IRQ???\n", dma);
410 DCSR(dma) = DCSR_STARTINTR|DCSR_ENDINTR|DCSR_BUSERR;
411 }
412
413 static irqreturn_t pxamci_detect_irq(int irq, void *devid, struct pt_regs *regs)
414 {
415 mmc_detect_change(devid);
416 return IRQ_HANDLED;
417 }
418
419 static int pxamci_probe(struct device *dev)
420 {
421 struct platform_device *pdev = to_platform_device(dev);
422 struct mmc_host *mmc;
423 struct pxamci_host *host = NULL;
424 struct resource *r;
425 int ret, irq;
426
427 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
428 irq = platform_get_irq(pdev, 0);
429 if (!r || irq == NO_IRQ)
430 return -ENXIO;
431
432 r = request_mem_region(r->start, SZ_4K, DRIVER_NAME);
433 if (!r)
434 return -EBUSY;
435
436 mmc = mmc_alloc_host(sizeof(struct pxamci_host), dev);
437 if (!mmc) {
438 ret = -ENOMEM;
439 goto out;
440 }
441
442 mmc->ops = &pxamci_ops;
443 mmc->f_min = CLOCKRATE_MIN;
444 mmc->f_max = CLOCKRATE_MAX;
445
446 /*
447 * We can do SG-DMA, but we don't because we never know how much
448 * data we successfully wrote to the card.
449 */
450 mmc->max_phys_segs = NR_SG;
451
452 /*
453 * Our hardware DMA can handle a maximum of one page per SG entry.
454 */
455 mmc->max_seg_size = PAGE_SIZE;
456
457 host = mmc_priv(mmc);
458 host->mmc = mmc;
459 host->dma = -1;
460 host->pdata = pdev->dev.platform_data;
461 mmc->ocr_avail = host->pdata ?
462 host->pdata->ocr_mask :
463 MMC_VDD_32_33|MMC_VDD_33_34;
464
465 host->sg_cpu = dma_alloc_coherent(dev, PAGE_SIZE, &host->sg_dma, GFP_KERNEL);
466 if (!host->sg_cpu) {
467 ret = -ENOMEM;
468 goto out;
469 }
470
471 spin_lock_init(&host->lock);
472 host->res = r;
473 host->irq = irq;
474 host->imask = MMC_I_MASK_ALL;
475
476 host->base = ioremap(r->start, SZ_4K);
477 if (!host->base) {
478 ret = -ENOMEM;
479 goto out;
480 }
481
482 /*
483 * Ensure that the host controller is shut down, and setup
484 * with our defaults.
485 */
486 pxamci_stop_clock(host);
487 writel(0, host->base + MMC_SPI);
488 writel(64, host->base + MMC_RESTO);
489 writel(host->imask, host->base + MMC_I_MASK);
490
491 host->dma = pxa_request_dma(DRIVER_NAME, DMA_PRIO_LOW,
492 pxamci_dma_irq, host);
493 if (host->dma < 0) {
494 ret = -EBUSY;
495 goto out;
496 }
497
498 ret = request_irq(host->irq, pxamci_irq, 0, DRIVER_NAME, host);
499 if (ret)
500 goto out;
501
502 dev_set_drvdata(dev, mmc);
503
504 if (host->pdata && host->pdata->init)
505 host->pdata->init(dev, pxamci_detect_irq, mmc);
506
507 mmc_add_host(mmc);
508
509 return 0;
510
511 out:
512 if (host) {
513 if (host->dma >= 0)
514 pxa_free_dma(host->dma);
515 if (host->base)
516 iounmap(host->base);
517 if (host->sg_cpu)
518 dma_free_coherent(dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
519 }
520 if (mmc)
521 mmc_free_host(mmc);
522 release_resource(r);
523 return ret;
524 }
525
526 static int pxamci_remove(struct device *dev)
527 {
528 struct mmc_host *mmc = dev_get_drvdata(dev);
529
530 dev_set_drvdata(dev, NULL);
531
532 if (mmc) {
533 struct pxamci_host *host = mmc_priv(mmc);
534
535 if (host->pdata && host->pdata->exit)
536 host->pdata->exit(dev, mmc);
537
538 mmc_remove_host(mmc);
539
540 pxamci_stop_clock(host);
541 writel(TXFIFO_WR_REQ|RXFIFO_RD_REQ|CLK_IS_OFF|STOP_CMD|
542 END_CMD_RES|PRG_DONE|DATA_TRAN_DONE,
543 host->base + MMC_I_MASK);
544
545 DRCMRRXMMC = 0;
546 DRCMRTXMMC = 0;
547
548 free_irq(host->irq, host);
549 pxa_free_dma(host->dma);
550 iounmap(host->base);
551 dma_free_coherent(dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
552
553 release_resource(host->res);
554
555 mmc_free_host(mmc);
556 }
557 return 0;
558 }
559
560 #ifdef CONFIG_PM
561 static int pxamci_suspend(struct device *dev, pm_message_t state, u32 level)
562 {
563 struct mmc_host *mmc = dev_get_drvdata(dev);
564 int ret = 0;
565
566 if (mmc && level == SUSPEND_DISABLE)
567 ret = mmc_suspend_host(mmc, state);
568
569 return ret;
570 }
571
572 static int pxamci_resume(struct device *dev, u32 level)
573 {
574 struct mmc_host *mmc = dev_get_drvdata(dev);
575 int ret = 0;
576
577 if (mmc && level == RESUME_ENABLE)
578 ret = mmc_resume_host(mmc);
579
580 return ret;
581 }
582 #else
583 #define pxamci_suspend NULL
584 #define pxamci_resume NULL
585 #endif
586
587 static struct device_driver pxamci_driver = {
588 .name = DRIVER_NAME,
589 .bus = &platform_bus_type,
590 .probe = pxamci_probe,
591 .remove = pxamci_remove,
592 .suspend = pxamci_suspend,
593 .resume = pxamci_resume,
594 };
595
596 static int __init pxamci_init(void)
597 {
598 return driver_register(&pxamci_driver);
599 }
600
601 static void __exit pxamci_exit(void)
602 {
603 driver_unregister(&pxamci_driver);
604 }
605
606 module_init(pxamci_init);
607 module_exit(pxamci_exit);
608
609 MODULE_DESCRIPTION("PXA Multimedia Card Interface Driver");
610 MODULE_LICENSE("GPL");
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