drivers/mtd/nand/rtc_from4.c

   1 /*
   2  *  drivers/mtd/nand/rtc_from4.c
   3  *
   4  *  Copyright (C) 2004  Red Hat, Inc.
   5  *
   6  *  Derived from drivers/mtd/nand/spia.c
   7  *       Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
   8  *
   9  * $Id: rtc_from4.c,v 1.7 2004/11/04 12:53:10 gleixner Exp $
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14  *
  15  * Overview:
  16  *   This is a device driver for the AG-AND flash device found on the
  17  *   Renesas Technology Corp. Flash ROM 4-slot interface board (FROM_BOARD4),
  18  *   which utilizes the Renesas HN29V1G91T-30 part.
  19  *   This chip is a 1 GBibit (128MiB x 8 bits) AG-AND flash device.
  20  */
  21
  22 #include <linux/delay.h>
  23 #include <linux/kernel.h>
  24 #include <linux/init.h>
  25 #include <linux/slab.h>
  26 #include <linux/rslib.h>
  27 #include <linux/module.h>
  28 #include <linux/mtd/compatmac.h>
  29 #include <linux/mtd/mtd.h>
  30 #include <linux/mtd/nand.h>
  31 #include <linux/mtd/partitions.h>
  32 #include <asm/io.h>
  33
  34 /*
  35  * MTD structure for Renesas board
  36  */
  37 static struct mtd_info *rtc_from4_mtd = NULL;
  38
  39 #define RTC_FROM4_MAX_CHIPS     2
  40
  41 /* HS77x9 processor register defines */
  42 #define SH77X9_BCR1     ((volatile unsigned short *)(0xFFFFFF60))
  43 #define SH77X9_BCR2     ((volatile unsigned short *)(0xFFFFFF62))
  44 #define SH77X9_WCR1     ((volatile unsigned short *)(0xFFFFFF64))
  45 #define SH77X9_WCR2     ((volatile unsigned short *)(0xFFFFFF66))
  46 #define SH77X9_MCR      ((volatile unsigned short *)(0xFFFFFF68))
  47 #define SH77X9_PCR      ((volatile unsigned short *)(0xFFFFFF6C))
  48 #define SH77X9_FRQCR    ((volatile unsigned short *)(0xFFFFFF80))
  49
  50 /*
  51  * Values specific to the Renesas Technology Corp. FROM_BOARD4 (used with HS77x9 processor)
  52  */
  53 /* Address where flash is mapped */
  54 #define RTC_FROM4_FIO_BASE      0x14000000
  55
  56 /* CLE and ALE are tied to address lines 5 & 4, respectively */
  57 #define RTC_FROM4_CLE           (1 << 5)
  58 #define RTC_FROM4_ALE           (1 << 4)
  59
  60 /* address lines A24-A22 used for chip selection */
  61 #define RTC_FROM4_NAND_ADDR_SLOT3       (0x00800000)
  62 #define RTC_FROM4_NAND_ADDR_SLOT4       (0x00C00000)
  63 #define RTC_FROM4_NAND_ADDR_FPGA        (0x01000000)
  64 /* mask address lines A24-A22 used for chip selection */
  65 #define RTC_FROM4_NAND_ADDR_MASK        (RTC_FROM4_NAND_ADDR_SLOT3 | RTC_FROM4_NAND_ADDR_SLOT4 | RTC_FROM4_NAND_ADDR_FPGA)
  66
  67 /* FPGA status register for checking device ready (bit zero) */
  68 #define RTC_FROM4_FPGA_SR               (RTC_FROM4_NAND_ADDR_FPGA | 0x00000002)
  69 #define RTC_FROM4_DEVICE_READY          0x0001
  70
  71 /* FPGA Reed-Solomon ECC Control register */
  72
  73 #define RTC_FROM4_RS_ECC_CTL            (RTC_FROM4_NAND_ADDR_FPGA | 0x00000050)
  74 #define RTC_FROM4_RS_ECC_CTL_CLR        (1 << 7)
  75 #define RTC_FROM4_RS_ECC_CTL_GEN        (1 << 6)
  76 #define RTC_FROM4_RS_ECC_CTL_FD_E       (1 << 5)
  77
  78 /* FPGA Reed-Solomon ECC code base */
  79 #define RTC_FROM4_RS_ECC                (RTC_FROM4_NAND_ADDR_FPGA | 0x00000060)
  80 #define RTC_FROM4_RS_ECCN               (RTC_FROM4_NAND_ADDR_FPGA | 0x00000080)
  81
  82 /* FPGA Reed-Solomon ECC check register */
  83 #define RTC_FROM4_RS_ECC_CHK            (RTC_FROM4_NAND_ADDR_FPGA | 0x00000070)
  84 #define RTC_FROM4_RS_ECC_CHK_ERROR      (1 << 7)
  85
  86 /* Undefine for software ECC */
  87 #define RTC_FROM4_HWECC 1
  88
  89 /*
  90  * Module stuff
  91  */
  92 static void __iomem *rtc_from4_fio_base = P2SEGADDR(RTC_FROM4_FIO_BASE);
  93
  94 const static struct mtd_partition partition_info[] = {
  95         {
  96                 .name   = "Renesas flash partition 1",
  97                 .offset = 0,
  98                 .size   = MTDPART_SIZ_FULL
  99         },
 100 };
 101 #define NUM_PARTITIONS 1
 102
 103 /*
 104  *      hardware specific flash bbt decriptors
 105  *      Note: this is to allow debugging by disabling
 106  *              NAND_BBT_CREATE and/or NAND_BBT_WRITE
 107  *
 108  */
 109 static uint8_t bbt_pattern[] = {'B', 'b', 't', '0' };
 110 static uint8_t mirror_pattern[] = {'1', 't', 'b', 'B' };
 111
 112 static struct nand_bbt_descr rtc_from4_bbt_main_descr = {
 113         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
 114                 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
 115         .offs = 40,
 116         .len = 4,
 117         .veroffs = 44,
 118         .maxblocks = 4,
 119         .pattern = bbt_pattern
 120 };
 121
 122 static struct nand_bbt_descr rtc_from4_bbt_mirror_descr = {
 123         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
 124                 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
 125         .offs = 40,
 126         .len = 4,
 127         .veroffs = 44,
 128         .maxblocks = 4,
 129         .pattern = mirror_pattern
 130 };
 131
 132
 133
 134 #ifdef RTC_FROM4_HWECC
 135
 136 /* the Reed Solomon control structure */
 137 static struct rs_control *rs_decoder;
 138
 139 /*
 140  *      hardware specific Out Of Band information
 141  */
 142 static struct nand_oobinfo rtc_from4_nand_oobinfo = {
 143         .useecc = MTD_NANDECC_AUTOPLACE,
 144         .eccbytes = 32,
 145         .eccpos = {
 146                  0,  1,  2,  3,  4,  5,  6,  7,
 147                  8,  9, 10, 11, 12, 13, 14, 15,
 148                 16, 17, 18, 19, 20, 21, 22, 23,
 149                 24, 25, 26, 27, 28, 29, 30, 31},
 150         .oobfree = { {32, 32} }
 151 };
 152
 153 /* Aargh. I missed the reversed bit order, when I
 154  * was talking to Renesas about the FPGA.
 155  *
 156  * The table is used for bit reordering and inversion
 157  * of the ecc byte which we get from the FPGA
 158  */
 159 static uint8_t revbits[256] = {
 160         0x00, 0x80, 0x40, 0xc0, 0x20, 0xa0, 0x60, 0xe0,
 161         0x10, 0x90, 0x50, 0xd0, 0x30, 0xb0, 0x70, 0xf0,
 162         0x08, 0x88, 0x48, 0xc8, 0x28, 0xa8, 0x68, 0xe8,
 163         0x18, 0x98, 0x58, 0xd8, 0x38, 0xb8, 0x78, 0xf8,
 164         0x04, 0x84, 0x44, 0xc4, 0x24, 0xa4, 0x64, 0xe4,
 165         0x14, 0x94, 0x54, 0xd4, 0x34, 0xb4, 0x74, 0xf4,
 166         0x0c, 0x8c, 0x4c, 0xcc, 0x2c, 0xac, 0x6c, 0xec,
 167         0x1c, 0x9c, 0x5c, 0xdc, 0x3c, 0xbc, 0x7c, 0xfc,
 168         0x02, 0x82, 0x42, 0xc2, 0x22, 0xa2, 0x62, 0xe2,
 169         0x12, 0x92, 0x52, 0xd2, 0x32, 0xb2, 0x72, 0xf2,
 170         0x0a, 0x8a, 0x4a, 0xca, 0x2a, 0xaa, 0x6a, 0xea,
 171         0x1a, 0x9a, 0x5a, 0xda, 0x3a, 0xba, 0x7a, 0xfa,
 172         0x06, 0x86, 0x46, 0xc6, 0x26, 0xa6, 0x66, 0xe6,
 173         0x16, 0x96, 0x56, 0xd6, 0x36, 0xb6, 0x76, 0xf6,
 174         0x0e, 0x8e, 0x4e, 0xce, 0x2e, 0xae, 0x6e, 0xee,
 175         0x1e, 0x9e, 0x5e, 0xde, 0x3e, 0xbe, 0x7e, 0xfe,
 176         0x01, 0x81, 0x41, 0xc1, 0x21, 0xa1, 0x61, 0xe1,
 177         0x11, 0x91, 0x51, 0xd1, 0x31, 0xb1, 0x71, 0xf1,
 178         0x09, 0x89, 0x49, 0xc9, 0x29, 0xa9, 0x69, 0xe9,
 179         0x19, 0x99, 0x59, 0xd9, 0x39, 0xb9, 0x79, 0xf9,
 180         0x05, 0x85, 0x45, 0xc5, 0x25, 0xa5, 0x65, 0xe5,
 181         0x15, 0x95, 0x55, 0xd5, 0x35, 0xb5, 0x75, 0xf5,
 182         0x0d, 0x8d, 0x4d, 0xcd, 0x2d, 0xad, 0x6d, 0xed,
 183         0x1d, 0x9d, 0x5d, 0xdd, 0x3d, 0xbd, 0x7d, 0xfd,
 184         0x03, 0x83, 0x43, 0xc3, 0x23, 0xa3, 0x63, 0xe3,
 185         0x13, 0x93, 0x53, 0xd3, 0x33, 0xb3, 0x73, 0xf3,
 186         0x0b, 0x8b, 0x4b, 0xcb, 0x2b, 0xab, 0x6b, 0xeb,
 187         0x1b, 0x9b, 0x5b, 0xdb, 0x3b, 0xbb, 0x7b, 0xfb,
 188         0x07, 0x87, 0x47, 0xc7, 0x27, 0xa7, 0x67, 0xe7,
 189         0x17, 0x97, 0x57, 0xd7, 0x37, 0xb7, 0x77, 0xf7,
 190         0x0f, 0x8f, 0x4f, 0xcf, 0x2f, 0xaf, 0x6f, 0xef,
 191         0x1f, 0x9f, 0x5f, 0xdf, 0x3f, 0xbf, 0x7f, 0xff,
 192 };
 193
 194 #endif
 195
 196
 197
 198 /*
 199  * rtc_from4_hwcontrol - hardware specific access to control-lines
 200  * @mtd:        MTD device structure
 201  * @cmd:        hardware control command
 202  *
 203  * Address lines (A5 and A4) are used to control Command and Address Latch
 204  * Enable on this board, so set the read/write address appropriately.
 205  *
 206  * Chip Enable is also controlled by the Chip Select (CS5) and
 207  * Address lines (A24-A22), so no action is required here.
 208  *
 209  */
 210 static void rtc_from4_hwcontrol(struct mtd_info *mtd, int cmd)
 211 {
 212         struct nand_chip* this = (struct nand_chip *) (mtd->priv);
 213
 214         switch(cmd) {
 215
 216         case NAND_CTL_SETCLE:
 217                 this->IO_ADDR_W = (void __iomem *)((unsigned long)this->IO_ADDR_W | RTC_FROM4_CLE);
 218                 break;
 219         case NAND_CTL_CLRCLE:
 220                 this->IO_ADDR_W = (void __iomem *)((unsigned long)this->IO_ADDR_W & ~RTC_FROM4_CLE);
 221                 break;
 222
 223         case NAND_CTL_SETALE:
 224                 this->IO_ADDR_W = (void __iomem *)((unsigned long)this->IO_ADDR_W | RTC_FROM4_ALE);
 225                 break;
 226         case NAND_CTL_CLRALE:
 227                 this->IO_ADDR_W = (void __iomem *)((unsigned long)this->IO_ADDR_W & ~RTC_FROM4_ALE);
 228                 break;
 229
 230         case NAND_CTL_SETNCE:
 231                 break;
 232         case NAND_CTL_CLRNCE:
 233                 break;
 234
 235         }
 236 }
 237
 238
 239 /*
 240  * rtc_from4_nand_select_chip - hardware specific chip select
 241  * @mtd:        MTD device structure
 242  * @chip:       Chip to select (0 == slot 3, 1 == slot 4)
 243  *
 244  * The chip select is based on address lines A24-A22.
 245  * This driver uses flash slots 3 and 4 (A23-A22).
 246  *
 247  */
 248 static void rtc_from4_nand_select_chip(struct mtd_info *mtd, int chip)
 249 {
 250         struct nand_chip *this = mtd->priv;
 251
 252         this->IO_ADDR_R = (void __iomem *)((unsigned long)this->IO_ADDR_R & ~RTC_FROM4_NAND_ADDR_MASK);
 253         this->IO_ADDR_W = (void __iomem *)((unsigned long)this->IO_ADDR_W & ~RTC_FROM4_NAND_ADDR_MASK);
 254
 255         switch(chip) {
 256
 257         case 0:         /* select slot 3 chip */
 258                 this->IO_ADDR_R = (void __iomem *)((unsigned long)this->IO_ADDR_R | RTC_FROM4_NAND_ADDR_SLOT3);
 259                 this->IO_ADDR_W = (void __iomem *)((unsigned long)this->IO_ADDR_W | RTC_FROM4_NAND_ADDR_SLOT3);
 260                 break;
 261         case 1:         /* select slot 4 chip */
 262                 this->IO_ADDR_R = (void __iomem *)((unsigned long)this->IO_ADDR_R | RTC_FROM4_NAND_ADDR_SLOT4);
 263                 this->IO_ADDR_W = (void __iomem *)((unsigned long)this->IO_ADDR_W | RTC_FROM4_NAND_ADDR_SLOT4);
 264                 break;
 265
 266         }
 267 }
 268
 269
 270
 271 /*
 272  * rtc_from4_nand_device_ready - hardware specific ready/busy check
 273  * @mtd:        MTD device structure
 274  *
 275  * This board provides the Ready/Busy state in the status register
 276  * of the FPGA.  Bit zero indicates the RDY(1)/BSY(0) signal.
 277  *
 278  */
 279 static int rtc_from4_nand_device_ready(struct mtd_info *mtd)
 280 {
 281         unsigned short status;
 282
 283         status = *((volatile unsigned short *)(rtc_from4_fio_base + RTC_FROM4_FPGA_SR));
 284
 285         return (status & RTC_FROM4_DEVICE_READY);
 286
 287 }
 288
 289 #ifdef RTC_FROM4_HWECC
 290 /*
 291  * rtc_from4_enable_hwecc - hardware specific hardware ECC enable function
 292  * @mtd:        MTD device structure
 293  * @mode:       I/O mode; read or write
 294  *
 295  * enable hardware ECC for data read or write
 296  *
 297  */
 298 static void rtc_from4_enable_hwecc(struct mtd_info *mtd, int mode)
 299 {
 300         volatile unsigned short * rs_ecc_ctl = (volatile unsigned short *)(rtc_from4_fio_base + RTC_FROM4_RS_ECC_CTL);
 301         unsigned short status;
 302
 303         switch (mode) {
 304             case NAND_ECC_READ :
 305                 status =  RTC_FROM4_RS_ECC_CTL_CLR
 306                         | RTC_FROM4_RS_ECC_CTL_FD_E;
 307
 308                 *rs_ecc_ctl = status;
 309                 break;
 310
 311             case NAND_ECC_READSYN :
 312                 status =  0x00;
 313
 314                 *rs_ecc_ctl = status;
 315                 break;
 316
 317             case NAND_ECC_WRITE :
 318                 status =  RTC_FROM4_RS_ECC_CTL_CLR
 319                         | RTC_FROM4_RS_ECC_CTL_GEN
 320                         | RTC_FROM4_RS_ECC_CTL_FD_E;
 321
 322                 *rs_ecc_ctl = status;
 323                 break;
 324
 325             default:
 326                 BUG();
 327                 break;
 328         }
 329
 330 }
 331
 332 /*
 333  * rtc_from4_calculate_ecc - hardware specific code to read ECC code
 334  * @mtd:        MTD device structure
 335  * @dat:        buffer containing the data to generate ECC codes
 336  * @ecc_code    ECC codes calculated
 337  *
 338  * The ECC code is calculated by the FPGA.  All we have to do is read the values
 339  * from the FPGA registers.
 340  *
 341  * Note: We read from the inverted registers, since data is inverted before
 342  * the code is calculated. So all 0xff data (blank page) results in all 0xff rs code
 343  *
 344  */
 345 static void rtc_from4_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code)
 346 {
 347         volatile unsigned short * rs_eccn = (volatile unsigned short *)(rtc_from4_fio_base + RTC_FROM4_RS_ECCN);
 348         unsigned short value;
 349         int i;
 350
 351         for (i = 0; i < 8; i++) {
 352                 value = *rs_eccn;
 353                 ecc_code[i] = (unsigned char)value;
 354                 rs_eccn++;
 355         }
 356         ecc_code[7] |= 0x0f;    /* set the last four bits (not used) */
 357 }
 358
 359 /*
 360  * rtc_from4_correct_data - hardware specific code to correct data using ECC code
 361  * @mtd:        MTD device structure
 362  * @buf:        buffer containing the data to generate ECC codes
 363  * @ecc1        ECC codes read
 364  * @ecc2        ECC codes calculated
 365  *
 366  * The FPGA tells us fast, if there's an error or not. If no, we go back happy
 367  * else we read the ecc results from the fpga and call the rs library to decode
 368  * and hopefully correct the error
 369  *
 370  * For now I use the code, which we read from the FLASH to use the RS lib,
 371  * as the syndrom conversion has a unresolved issue.
 372  */
 373 static int rtc_from4_correct_data(struct mtd_info *mtd, const u_char *buf, u_char *ecc1, u_char *ecc2)
 374 {
 375         int i, j, res;
 376         unsigned short status;
 377         uint16_t par[6], syn[6], tmp;
 378         uint8_t ecc[8];
 379         volatile unsigned short *rs_ecc;
 380
 381         status = *((volatile unsigned short *)(rtc_from4_fio_base + RTC_FROM4_RS_ECC_CHK));
 382
 383         if (!(status & RTC_FROM4_RS_ECC_CHK_ERROR)) {
 384                 return 0;
 385         }
 386
 387         /* Read the syndrom pattern from the FPGA and correct the bitorder */
 388         rs_ecc = (volatile unsigned short *)(rtc_from4_fio_base + RTC_FROM4_RS_ECC);
 389         for (i = 0; i < 8; i++) {
 390                 ecc[i] = revbits[(*rs_ecc) & 0xFF];
 391                 rs_ecc++;
 392         }
 393
 394         /* convert into 6 10bit syndrome fields */
 395         par[5] = rs_decoder->index_of[(((uint16_t)ecc[0] >> 0) & 0x0ff) |
 396                                       (((uint16_t)ecc[1] << 8) & 0x300)];
 397         par[4] = rs_decoder->index_of[(((uint16_t)ecc[1] >> 2) & 0x03f) |
 398                                       (((uint16_t)ecc[2] << 6) & 0x3c0)];
 399         par[3] = rs_decoder->index_of[(((uint16_t)ecc[2] >> 4) & 0x00f) |
 400                                       (((uint16_t)ecc[3] << 4) & 0x3f0)];
 401         par[2] = rs_decoder->index_of[(((uint16_t)ecc[3] >> 6) & 0x003) |
 402                                       (((uint16_t)ecc[4] << 2) & 0x3fc)];
 403         par[1] = rs_decoder->index_of[(((uint16_t)ecc[5] >> 0) & 0x0ff) |
 404                                       (((uint16_t)ecc[6] << 8) & 0x300)];
 405         par[0] = (((uint16_t)ecc[6] >> 2) & 0x03f) | (((uint16_t)ecc[7] << 6) & 0x3c0);
 406
 407         /* Convert to computable syndrome */
 408         for (i = 0; i < 6; i++) {
 409                 syn[i] = par[0];
 410                 for (j = 1; j < 6; j++)
 411                         if (par[j] != rs_decoder->nn)
 412                                 syn[i] ^= rs_decoder->alpha_to[rs_modnn(rs_decoder, par[j] + i * j)];
 413
 414                 /* Convert to index form */
 415                 syn[i] = rs_decoder->index_of[syn[i]];
 416         }
 417
 418         /* Let the library code do its magic.*/
 419         res = decode_rs8(rs_decoder, buf, par, 512, syn, 0, NULL, 0xff, NULL);
 420         if (res > 0) {
 421                 DEBUG (MTD_DEBUG_LEVEL0, "rtc_from4_correct_data: "
 422                         "ECC corrected %d errors on read\n", res);
 423         }
 424         return res;
 425 }
 426 #endif
 427
 428 /*
 429  * Main initialization routine
 430  */
 431 int __init rtc_from4_init (void)
 432 {
 433         struct nand_chip *this;
 434         unsigned short bcr1, bcr2, wcr2;
 435
 436         /* Allocate memory for MTD device structure and private data */
 437         rtc_from4_mtd = kmalloc(sizeof(struct mtd_info) + sizeof (struct nand_chip),
 438                                 GFP_KERNEL);
 439         if (!rtc_from4_mtd) {
 440                 printk ("Unable to allocate Renesas NAND MTD device structure.\n");
 441                 return -ENOMEM;
 442         }
 443
 444         /* Get pointer to private data */
 445         this = (struct nand_chip *) (&rtc_from4_mtd[1]);
 446
 447         /* Initialize structures */
 448         memset((char *) rtc_from4_mtd, 0, sizeof(struct mtd_info));
 449         memset((char *) this, 0, sizeof(struct nand_chip));
 450
 451         /* Link the private data with the MTD structure */
 452         rtc_from4_mtd->priv = this;
 453
 454         /* set area 5 as PCMCIA mode to clear the spec of tDH(Data hold time;9ns min) */
 455         bcr1 = *SH77X9_BCR1 & ~0x0002;
 456         bcr1 |= 0x0002;
 457         *SH77X9_BCR1 = bcr1;
 458
 459         /* set */
 460         bcr2 = *SH77X9_BCR2 & ~0x0c00;
 461         bcr2 |= 0x0800;
 462         *SH77X9_BCR2 = bcr2;
 463
 464         /* set area 5 wait states */
 465         wcr2 = *SH77X9_WCR2 & ~0x1c00;
 466         wcr2 |= 0x1c00;
 467         *SH77X9_WCR2 = wcr2;
 468
 469         /* Set address of NAND IO lines */
 470         this->IO_ADDR_R = rtc_from4_fio_base;
 471         this->IO_ADDR_W = rtc_from4_fio_base;
 472         /* Set address of hardware control function */
 473         this->hwcontrol = rtc_from4_hwcontrol;
 474         /* Set address of chip select function */
 475         this->select_chip = rtc_from4_nand_select_chip;
 476         /* command delay time (in us) */
 477         this->chip_delay = 100;
 478         /* return the status of the Ready/Busy line */
 479         this->dev_ready = rtc_from4_nand_device_ready;
 480
 481 #ifdef RTC_FROM4_HWECC
 482         printk(KERN_INFO "rtc_from4_init: using hardware ECC detection.\n");
 483
 484         this->eccmode = NAND_ECC_HW8_512;
 485         this->options |= NAND_HWECC_SYNDROME;
 486         /* set the nand_oobinfo to support FPGA H/W error detection */
 487         this->autooob = &rtc_from4_nand_oobinfo;
 488         this->enable_hwecc = rtc_from4_enable_hwecc;
 489         this->calculate_ecc = rtc_from4_calculate_ecc;
 490         this->correct_data = rtc_from4_correct_data;
 491 #else
 492         printk(KERN_INFO "rtc_from4_init: using software ECC detection.\n");
 493
 494         this->eccmode = NAND_ECC_SOFT;
 495 #endif
 496
 497         /* set the bad block tables to support debugging */
 498         this->bbt_td = &rtc_from4_bbt_main_descr;
 499         this->bbt_md = &rtc_from4_bbt_mirror_descr;
 500
 501         /* Scan to find existence of the device */
 502         if (nand_scan(rtc_from4_mtd, RTC_FROM4_MAX_CHIPS)) {
 503                 kfree(rtc_from4_mtd);
 504                 return -ENXIO;
 505         }
 506
 507         /* Register the partitions */
 508         add_mtd_partitions(rtc_from4_mtd, partition_info, NUM_PARTITIONS);
 509
 510 #ifdef RTC_FROM4_HWECC
 511         /* We could create the decoder on demand, if memory is a concern.
 512          * This way we have it handy, if an error happens
 513          *
 514          * Symbolsize is 10 (bits)
 515          * Primitve polynomial is x^10+x^3+1
 516          * first consecutive root is 0
 517          * primitve element to generate roots = 1
 518          * generator polinomial degree = 6
 519          */
 520         rs_decoder = init_rs(10, 0x409, 0, 1, 6);
 521         if (!rs_decoder) {
 522                 printk (KERN_ERR "Could not create a RS decoder\n");
 523                 nand_release(rtc_from4_mtd);
 524                 kfree(rtc_from4_mtd);
 525                 return -ENOMEM;
 526         }
 527 #endif
 528         /* Return happy */
 529         return 0;
 530 }
 531 module_init(rtc_from4_init);
 532
 533
 534 /*
 535  * Clean up routine
 536  */
 537 #ifdef MODULE
 538 static void __exit rtc_from4_cleanup (void)
 539 {
 540         /* Release resource, unregister partitions */
 541         nand_release(rtc_from4_mtd);
 542
 543         /* Free the MTD device structure */
 544         kfree (rtc_from4_mtd);
 545
 546 #ifdef RTC_FROM4_HWECC
 547         /* Free the reed solomon resources */
 548         if (rs_decoder) {
 549                 free_rs(rs_decoder);
 550         }
 551 #endif
 552 }
 553 module_exit(rtc_from4_cleanup);
 554 #endif
 555
 556 MODULE_LICENSE("GPL");
 557 MODULE_AUTHOR("d.marlin <dmarlin@redhat.com");
 558 MODULE_DESCRIPTION("Board-specific glue layer for AG-AND flash on Renesas FROM_BOARD4");
 559