drivers/net/dgrs_plx9060.h

   1 /*
   2  *      PLX 9060 PCI Interface chip
   3  */
   4
   5 /*
   6  *      PCI configuration registers, same offset on local and PCI sides,
   7  *      but on PCI side, must use PCI BIOS calls to read/write.
   8  */
   9 #define PCI_PLXREGS_BASE_ADDR   0x10
  10
  11 #define PCI_PLXREGS_IO_ADDR     0x14
  12
  13 #define PCI_SPACE0_BASE_ADDR    0x18
  14
  15 #define PCI_ROM_BASE_ADDR       0x30
  16 #       define PCI_ROM_ENABLED          0x00000001
  17
  18 #define PCI_INT_LINE            0x3C
  19
  20 /*
  21  *      Registers accessible directly from PCI and local side.
  22  *      Offset is from PCI side.  Add PLX_LCL_OFFSET for local address.
  23  */
  24 #define PLX_LCL_OFFSET  0x80    /* Offset of regs from local side */
  25
  26 /*
  27  *      Local Configuration Registers
  28  */
  29 #define PLX_SPACE0_RANGE        0x00    /* Range for PCI to Lcl Addr Space 0 */
  30 #define PLX_SPACE0_BASE_ADDR    0x04    /* Lcl Base address remap */
  31
  32 #define PLX_ROM_RANGE           0x10    /* Range for expansion ROM (DMA) */
  33 #define PLX_ROM_BASE_ADDR       0x14    /* Lcl base address remap for ROM */
  34
  35 #define PLX_BUS_REGION          0x18    /* Bus Region Descriptors */
  36
  37 /*
  38  *      Shared Run Time Registers
  39  */
  40 #define PLX_MBOX0               0x40
  41 #define PLX_MBOX1               0x44
  42 #define PLX_MBOX2               0x48
  43 #define PLX_MBOX3               0x4C
  44 #define PLX_MBOX4               0x50
  45 #define PLX_MBOX5               0x54
  46 #define PLX_MBOX6               0x58
  47 #define PLX_MBOX7               0x5C
  48
  49 #define PLX_PCI2LCL_DOORBELL    0x60
  50
  51 #define PLX_LCL2PCI_DOORBELL    0x64
  52
  53 #define PLX_INT_CSR             0x68    /* Interrupt Control/Status */
  54 #       define  PLX_LSERR_ENABLE        0x00000001
  55 #       define  PLX_LSERR_PE            0x00000002
  56 #       define  PLX_SERR                0x00000004
  57 #       undef  PLX_UNUSED /*            0x00000008                      */
  58 #       undef  PLX_UNUSED /*            0x00000010                      */
  59 #       undef  PLX_UNUSED /*            0x00000020                      */
  60 #       undef  PLX_UNUSED /*            0x00000040                      */
  61 #       undef  PLX_UNUSED /*            0x00000080                      */
  62 #       define PLX_PCI_IE               0x00000100
  63 #       define  PLX_PCI_DOORBELL_IE     0x00000200
  64 #       define  PLX_PCI_ABORT_IE        0x00000400
  65 #       define  PLX_PCI_LOCAL_IE        0x00000800
  66 #       define  PLX_RETRY_ABORT_ENABLE  0x00001000
  67 #       define  PLX_PCI_DOORBELL_INT    0x00002000
  68 #       define  PLX_PCI_ABORT_INT       0x00004000
  69 #       define  PLX_PCI_LOCAL_INT       0x00008000
  70 #       define  PLX_LCL_IE              0x00010000
  71 #       define  PLX_LCL_DOORBELL_IE     0x00020000
  72 #       define  PLX_LCL_DMA0_IE         0x00040000
  73 #       define  PLX_LCL_DMA1_IE         0x00080000
  74 #       define  PLX_LCL_DOORBELL_INT    0x00100000
  75 #       define  PLX_LCL_DMA0_INT        0x00200000
  76 #       define  PLX_LCL_DMA1_INT        0x00400000
  77 #       define  PLX_LCL_BIST_INT        0x00800000
  78 #       define  PLX_BM_DIRECT_          0x01000000
  79 #       define  PLX_BM_DMA0_            0x02000000
  80 #       define  PLX_BM_DMA1_            0x04000000
  81 #       define  PLX_BM_ABORT_           0x08000000
  82 #       undef  PLX_UNUSED /*            0x10000000                      */
  83 #       undef  PLX_UNUSED /*            0x20000000                      */
  84 #       undef  PLX_UNUSED /*            0x40000000                      */
  85 #       undef  PLX_UNUSED /*            0x80000000                      */
  86
  87 #define PLX_MISC_CSR            0x6c    /* EEPROM,PCI,User,Init Control/Status*/
  88 #       define PLX_USEROUT              0x00010000
  89 #       define PLX_USERIN               0x00020000
  90 #       define PLX_EECK                 0x01000000
  91 #       define PLX_EECS                 0x02000000
  92 #       define PLX_EEWD                 0x04000000
  93 #       define PLX_EERD                 0x08000000
  94
  95 /*
  96  *      DMA registers.  Offset is from local side
  97  */
  98 #define PLX_DMA0_MODE           0x100
  99 #       define PLX_DMA_MODE_WIDTH32     0x00000003
 100 #       define PLX_DMA_MODE_WAITSTATES(X)       ((X)<<2)
 101 #       define PLX_DMA_MODE_NOREADY     0x00000000
 102 #       define PLX_DMA_MODE_READY       0x00000040
 103 #       define PLX_DMA_MODE_NOBTERM     0x00000000
 104 #       define PLX_DMA_MODE_BTERM       0x00000080
 105 #       define PLX_DMA_MODE_NOBURST     0x00000000
 106 #       define PLX_DMA_MODE_BURST       0x00000100
 107 #       define PLX_DMA_MODE_NOCHAIN     0x00000000
 108 #       define PLX_DMA_MODE_CHAIN       0x00000200
 109 #       define PLX_DMA_MODE_DONE_IE     0x00000400
 110 #       define PLX_DMA_MODE_ADDR_HOLD   0x00000800
 111
 112 #define PLX_DMA0_PCI_ADDR       0x104
 113                                         /* non-chaining mode PCI address */
 114
 115 #define PLX_DMA0_LCL_ADDR       0x108
 116                                         /* non-chaining mode local address */
 117
 118 #define PLX_DMA0_SIZE           0x10C
 119                                         /* non-chaining mode length */
 120
 121 #define PLX_DMA0_DESCRIPTOR     0x110
 122 #       define  PLX_DMA_DESC_EOC        0x00000002
 123 #       define  PLX_DMA_DESC_TC_IE      0x00000004
 124 #       define  PLX_DMA_DESC_TO_HOST    0x00000008
 125 #       define  PLX_DMA_DESC_TO_BOARD   0x00000000
 126 #       define  PLX_DMA_DESC_NEXTADDR   0xFFFFfff0
 127
 128 #define PLX_DMA1_MODE           0x114
 129 #define PLX_DMA1_PCI_ADDR       0x118
 130 #define PLX_DMA1_LCL_ADDR       0x11C
 131 #define PLX_DMA1_SIZE           0x110
 132 #define PLX_DMA1_DESCRIPTOR     0x124
 133
 134 #define PLX_DMA_CSR             0x128
 135 #       define PLX_DMA_CSR_0_ENABLE     0x00000001
 136 #       define PLX_DMA_CSR_0_START      0x00000002
 137 #       define PLX_DMA_CSR_0_ABORT      0x00000004
 138 #       define PLX_DMA_CSR_0_CLR_INTR   0x00000008
 139 #       define PLX_DMA_CSR_0_DONE       0x00000010
 140 #       define PLX_DMA_CSR_1_ENABLE     0x00000100
 141 #       define PLX_DMA_CSR_1_START      0x00000200
 142 #       define PLX_DMA_CSR_1_ABORT      0x00000400
 143 #       define PLX_DMA_CSR_1_CLR_INTR   0x00000800
 144 #       define PLX_DMA_CSR_1_DONE       0x00001000
 145
 146 #define PLX_DMA_ARB0            0x12C
 147 #       define PLX_DMA_ARB0_LATENCY_T   0x000000FF
 148 #       define PLX_DMA_ARB0_PAUSE_T     0x0000FF00
 149 #       define PLX_DMA_ARB0_LATENCY_EN  0x00010000
 150 #       define PLX_DMA_ARB0_PAUSE_EN    0x00020000
 151 #       define PLX_DMA_ARB0_BREQ_EN     0x00040000
 152 #       define PLX_DMA_ARB0_PRI         0x00180000
 153 #       define PLX_DMA_ARB0_PRI_ROUND   0x00000000
 154 #       define PLX_DMA_ARB0_PRI_0       0x00080000
 155 #       define PLX_DMA_ARB0_PRI_1       0x00100000
 156
 157 #define PLX_DMA_ARB1            0x130
 158                                                 /* Chan 0: FIFO DEPTH=16 */
 159 #       define PLX_DMA_ARB1_0_P2L_LW_TRIG(X)    ( ((X)&15) <<  0 )
 160 #       define PLX_DMA_ARB1_0_L2P_LR_TRIG(X)    ( ((X)&15) <<  4 )
 161 #       define PLX_DMA_ARB1_0_L2P_PW_TRIG(X)    ( ((X)&15) <<  8 )
 162 #       define PLX_DMA_ARB1_0_P2L_PR_TRIG(X)    ( ((X)&15) << 12 )
 163                                                 /* Chan 1: FIFO DEPTH=8 */
 164 #       define PLX_DMA_ARB1_1_P2L_LW_TRIG(X)    ( ((X)& 7) << 16 )
 165 #       define PLX_DMA_ARB1_1_L2P_LR_TRIG(X)    ( ((X)& 7) << 20 )
 166 #       define PLX_DMA_ARB1_1_L2P_PW_TRIG(X)    ( ((X)& 7) << 24 )
 167 #       define PLX_DMA_ARB1_1_P2L_PR_TRIG(X)    ( ((X)& 7) << 28 )
 168
 169 typedef struct _dmachain
 170 {
 171         ulong           pciaddr;
 172         ulong           lcladdr;
 173         ulong           len;
 174         ulong           next;
 175 } DMACHAIN;