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[TG3]: Set minimal hw interrupt mitigation.
[linux-2.6/verdex.git] / drivers / net / pci-skeleton.c
blob4a391ea0f58aaa4771975a5eff2e0ce338e9dd54
1 /*
2
3 drivers/net/pci-skeleton.c
4
5 Maintained by Jeff Garzik <jgarzik@pobox.com>
6
7 Original code came from 8139too.c, which in turns was based
8 originally on Donald Becker's rtl8139.c driver, versions 1.11
9 and older. This driver was originally based on rtl8139.c
10 version 1.07. Header of rtl8139.c version 1.11:
11
12 -----<snip>-----
13
14 Written 1997-2000 by Donald Becker.
15 This software may be used and distributed according to the
16 terms of the GNU General Public License (GPL), incorporated
17 herein by reference. Drivers based on or derived from this
18 code fall under the GPL and must retain the authorship,
19 copyright and license notice. This file is not a complete
20 program and may only be used when the entire operating
21 system is licensed under the GPL.
22
23 This driver is for boards based on the RTL8129 and RTL8139
24 PCI ethernet chips.
25
26 The author may be reached as becker@scyld.com, or C/O Scyld
27 Computing Corporation 410 Severn Ave., Suite 210 Annapolis
28 MD 21403
29
30 Support and updates available at
31 http://www.scyld.com/network/rtl8139.html
32
33 Twister-tuning table provided by Kinston
34 <shangh@realtek.com.tw>.
35
36 -----<snip>-----
37
38 This software may be used and distributed according to the terms
39 of the GNU General Public License, incorporated herein by reference.
40
41
42 -----------------------------------------------------------------------------
43
44 Theory of Operation
45
46 I. Board Compatibility
47
48 This device driver is designed for the RealTek RTL8139 series, the RealTek
49 Fast Ethernet controllers for PCI and CardBus. This chip is used on many
50 low-end boards, sometimes with its markings changed.
51
52
53 II. Board-specific settings
54
55 PCI bus devices are configured by the system at boot time, so no jumpers
56 need to be set on the board. The system BIOS will assign the
57 PCI INTA signal to a (preferably otherwise unused) system IRQ line.
58
59 III. Driver operation
60
61 IIIa. Rx Ring buffers
62
63 The receive unit uses a single linear ring buffer rather than the more
64 common (and more efficient) descriptor-based architecture. Incoming frames
65 are sequentially stored into the Rx region, and the host copies them into
66 skbuffs.
67
68 Comment: While it is theoretically possible to process many frames in place,
69 any delay in Rx processing would cause us to drop frames. More importantly,
70 the Linux protocol stack is not designed to operate in this manner.
71
72 IIIb. Tx operation
73
74 The RTL8139 uses a fixed set of four Tx descriptors in register space.
75 In a stunningly bad design choice, Tx frames must be 32 bit aligned. Linux
76 aligns the IP header on word boundaries, and 14 byte ethernet header means
77 that almost all frames will need to be copied to an alignment buffer.
78
79 IVb. References
80
81 http://www.realtek.com.tw/cn/cn.html
82 http://www.scyld.com/expert/NWay.html
83
84 IVc. Errata
85
86 */
87
88 #include <linux/config.h>
89 #include <linux/module.h>
90 #include <linux/kernel.h>
91 #include <linux/pci.h>
92 #include <linux/init.h>
93 #include <linux/ioport.h>
94 #include <linux/netdevice.h>
95 #include <linux/etherdevice.h>
96 #include <linux/delay.h>
97 #include <linux/ethtool.h>
98 #include <linux/mii.h>
99 #include <linux/crc32.h>
100 #include <asm/io.h>
101
102 #define NETDRV_VERSION "1.0.0"
103 #define MODNAME "netdrv"
104 #define NETDRV_DRIVER_LOAD_MSG "MyVendor Fast Ethernet driver " NETDRV_VERSION " loaded"
105 #define PFX MODNAME ": "
106
107 static char version[] __devinitdata =
108 KERN_INFO NETDRV_DRIVER_LOAD_MSG "\n"
109 KERN_INFO " Support available from http://foo.com/bar/baz.html\n";
110
111 /* define to 1 to enable PIO instead of MMIO */
112 #undef USE_IO_OPS
113
114 /* define to 1 to enable copious debugging info */
115 #undef NETDRV_DEBUG
116
117 /* define to 1 to disable lightweight runtime debugging checks */
118 #undef NETDRV_NDEBUG
119
120
121 #ifdef NETDRV_DEBUG
122 /* note: prints function name for you */
123 # define DPRINTK(fmt, args...) printk(KERN_DEBUG "%s: " fmt, __FUNCTION__ , ## args)
124 #else
125 # define DPRINTK(fmt, args...)
126 #endif
127
128 #ifdef NETDRV_NDEBUG
129 # define assert(expr) do {} while (0)
130 #else
131 # define assert(expr) \
132 if(!(expr)) { \
133 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
134 #expr,__FILE__,__FUNCTION__,__LINE__); \
135 }
136 #endif
137
138
139 /* A few user-configurable values. */
140 /* media options */
141 static int media[] = {-1, -1, -1, -1, -1, -1, -1, -1};
142
143 /* Maximum events (Rx packets, etc.) to handle at each interrupt. */
144 static int max_interrupt_work = 20;
145
146 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
147 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
148 static int multicast_filter_limit = 32;
149
150 /* Size of the in-memory receive ring. */
151 #define RX_BUF_LEN_IDX 2 /* 0==8K, 1==16K, 2==32K, 3==64K */
152 #define RX_BUF_LEN (8192 << RX_BUF_LEN_IDX)
153 #define RX_BUF_PAD 16
154 #define RX_BUF_WRAP_PAD 2048 /* spare padding to handle lack of packet wrap */
155 #define RX_BUF_TOT_LEN (RX_BUF_LEN + RX_BUF_PAD + RX_BUF_WRAP_PAD)
156
157 /* Number of Tx descriptor registers. */
158 #define NUM_TX_DESC 4
159
160 /* max supported ethernet frame size -- must be at least (dev->mtu+14+4).*/
161 #define MAX_ETH_FRAME_SIZE 1536
162
163 /* Size of the Tx bounce buffers -- must be at least (dev->mtu+14+4). */
164 #define TX_BUF_SIZE MAX_ETH_FRAME_SIZE
165 #define TX_BUF_TOT_LEN (TX_BUF_SIZE * NUM_TX_DESC)
166
167 /* PCI Tuning Parameters
168 Threshold is bytes transferred to chip before transmission starts. */
169 #define TX_FIFO_THRESH 256 /* In bytes, rounded down to 32 byte units. */
170
171 /* The following settings are log_2(bytes)-4: 0 == 16 bytes .. 6==1024, 7==end of packet. */
172 #define RX_FIFO_THRESH 6 /* Rx buffer level before first PCI xfer. */
173 #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
174 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
175
176
177 /* Operational parameters that usually are not changed. */
178 /* Time in jiffies before concluding the transmitter is hung. */
179 #define TX_TIMEOUT (6*HZ)
180
181
182 enum {
183 HAS_CHIP_XCVR = 0x020000,
184 HAS_LNK_CHNG = 0x040000,
185 };
186
187 #define NETDRV_MIN_IO_SIZE 0x80
188 #define RTL8139B_IO_SIZE 256
189
190 #define NETDRV_CAPS HAS_CHIP_XCVR|HAS_LNK_CHNG
191
192 typedef enum {
193 RTL8139 = 0,
194 NETDRV_CB,
195 SMC1211TX,
196 /*MPX5030,*/
197 DELTA8139,
198 ADDTRON8139,
199 } board_t;
200
201
202 /* indexed by board_t, above */
203 static struct {
204 const char *name;
205 } board_info[] __devinitdata = {
206 { "RealTek RTL8139 Fast Ethernet" },
207 { "RealTek RTL8139B PCI/CardBus" },
208 { "SMC1211TX EZCard 10/100 (RealTek RTL8139)" },
209 /* { MPX5030, "Accton MPX5030 (RealTek RTL8139)" },*/
210 { "Delta Electronics 8139 10/100BaseTX" },
211 { "Addtron Technolgy 8139 10/100BaseTX" },
212 };
213
214
215 static struct pci_device_id netdrv_pci_tbl[] = {
216 {0x10ec, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
217 {0x10ec, 0x8138, PCI_ANY_ID, PCI_ANY_ID, 0, 0, NETDRV_CB },
218 {0x1113, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, SMC1211TX },
219 /* {0x1113, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MPX5030 },*/
220 {0x1500, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DELTA8139 },
221 {0x4033, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ADDTRON8139 },
222 {0,}
223 };
224 MODULE_DEVICE_TABLE (pci, netdrv_pci_tbl);
225
226
227 /* The rest of these values should never change. */
228
229 /* Symbolic offsets to registers. */
230 enum NETDRV_registers {
231 MAC0 = 0, /* Ethernet hardware address. */
232 MAR0 = 8, /* Multicast filter. */
233 TxStatus0 = 0x10, /* Transmit status (Four 32bit registers). */
234 TxAddr0 = 0x20, /* Tx descriptors (also four 32bit). */
235 RxBuf = 0x30,
236 RxEarlyCnt = 0x34,
237 RxEarlyStatus = 0x36,
238 ChipCmd = 0x37,
239 RxBufPtr = 0x38,
240 RxBufAddr = 0x3A,
241 IntrMask = 0x3C,
242 IntrStatus = 0x3E,
243 TxConfig = 0x40,
244 ChipVersion = 0x43,
245 RxConfig = 0x44,
246 Timer = 0x48, /* A general-purpose counter. */
247 RxMissed = 0x4C, /* 24 bits valid, write clears. */
248 Cfg9346 = 0x50,
249 Config0 = 0x51,
250 Config1 = 0x52,
251 FlashReg = 0x54,
252 MediaStatus = 0x58,
253 Config3 = 0x59,
254 Config4 = 0x5A, /* absent on RTL-8139A */
255 HltClk = 0x5B,
256 MultiIntr = 0x5C,
257 TxSummary = 0x60,
258 BasicModeCtrl = 0x62,
259 BasicModeStatus = 0x64,
260 NWayAdvert = 0x66,
261 NWayLPAR = 0x68,
262 NWayExpansion = 0x6A,
263 /* Undocumented registers, but required for proper operation. */
264 FIFOTMS = 0x70, /* FIFO Control and test. */
265 CSCR = 0x74, /* Chip Status and Configuration Register. */
266 PARA78 = 0x78,
267 PARA7c = 0x7c, /* Magic transceiver parameter register. */
268 Config5 = 0xD8, /* absent on RTL-8139A */
269 };
270
271 enum ClearBitMasks {
272 MultiIntrClear = 0xF000,
273 ChipCmdClear = 0xE2,
274 Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1),
275 };
276
277 enum ChipCmdBits {
278 CmdReset = 0x10,
279 CmdRxEnb = 0x08,
280 CmdTxEnb = 0x04,
281 RxBufEmpty = 0x01,
282 };
283
284 /* Interrupt register bits, using my own meaningful names. */
285 enum IntrStatusBits {
286 PCIErr = 0x8000,
287 PCSTimeout = 0x4000,
288 RxFIFOOver = 0x40,
289 RxUnderrun = 0x20,
290 RxOverflow = 0x10,
291 TxErr = 0x08,
292 TxOK = 0x04,
293 RxErr = 0x02,
294 RxOK = 0x01,
295 };
296 enum TxStatusBits {
297 TxHostOwns = 0x2000,
298 TxUnderrun = 0x4000,
299 TxStatOK = 0x8000,
300 TxOutOfWindow = 0x20000000,
301 TxAborted = 0x40000000,
302 TxCarrierLost = 0x80000000,
303 };
304 enum RxStatusBits {
305 RxMulticast = 0x8000,
306 RxPhysical = 0x4000,
307 RxBroadcast = 0x2000,
308 RxBadSymbol = 0x0020,
309 RxRunt = 0x0010,
310 RxTooLong = 0x0008,
311 RxCRCErr = 0x0004,
312 RxBadAlign = 0x0002,
313 RxStatusOK = 0x0001,
314 };
315
316 /* Bits in RxConfig. */
317 enum rx_mode_bits {
318 AcceptErr = 0x20,
319 AcceptRunt = 0x10,
320 AcceptBroadcast = 0x08,
321 AcceptMulticast = 0x04,
322 AcceptMyPhys = 0x02,
323 AcceptAllPhys = 0x01,
324 };
325
326 /* Bits in TxConfig. */
327 enum tx_config_bits {
328 TxIFG1 = (1 << 25), /* Interframe Gap Time */
329 TxIFG0 = (1 << 24), /* Enabling these bits violates IEEE 802.3 */
330 TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */
331 TxCRC = (1 << 16), /* DISABLE appending CRC to end of Tx packets */
332 TxClearAbt = (1 << 0), /* Clear abort (WO) */
333 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
334
335 TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */
336 };
337
338 /* Bits in Config1 */
339 enum Config1Bits {
340 Cfg1_PM_Enable = 0x01,
341 Cfg1_VPD_Enable = 0x02,
342 Cfg1_PIO = 0x04,
343 Cfg1_MMIO = 0x08,
344 Cfg1_LWAKE = 0x10,
345 Cfg1_Driver_Load = 0x20,
346 Cfg1_LED0 = 0x40,
347 Cfg1_LED1 = 0x80,
348 };
349
350 enum RxConfigBits {
351 /* Early Rx threshold, none or X/16 */
352 RxCfgEarlyRxNone = 0,
353 RxCfgEarlyRxShift = 24,
354
355 /* rx fifo threshold */
356 RxCfgFIFOShift = 13,
357 RxCfgFIFONone = (7 << RxCfgFIFOShift),
358
359 /* Max DMA burst */
360 RxCfgDMAShift = 8,
361 RxCfgDMAUnlimited = (7 << RxCfgDMAShift),
362
363 /* rx ring buffer length */
364 RxCfgRcv8K = 0,
365 RxCfgRcv16K = (1 << 11),
366 RxCfgRcv32K = (1 << 12),
367 RxCfgRcv64K = (1 << 11) | (1 << 12),
368
369 /* Disable packet wrap at end of Rx buffer */
370 RxNoWrap = (1 << 7),
371 };
372
373
374 /* Twister tuning parameters from RealTek.
375 Completely undocumented, but required to tune bad links. */
376 enum CSCRBits {
377 CSCR_LinkOKBit = 0x0400,
378 CSCR_LinkChangeBit = 0x0800,
379 CSCR_LinkStatusBits = 0x0f000,
380 CSCR_LinkDownOffCmd = 0x003c0,
381 CSCR_LinkDownCmd = 0x0f3c0,
382 };
383
384
385 enum Cfg9346Bits {
386 Cfg9346_Lock = 0x00,
387 Cfg9346_Unlock = 0xC0,
388 };
389
390
391 #define PARA78_default 0x78fa8388
392 #define PARA7c_default 0xcb38de43 /* param[0][3] */
393 #define PARA7c_xxx 0xcb38de43
394 static const unsigned long param[4][4] = {
395 {0xcb39de43, 0xcb39ce43, 0xfb38de03, 0xcb38de43},
396 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
397 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
398 {0xbb39de43, 0xbb39ce43, 0xbb39ce83, 0xbb39ce83}
399 };
400
401 struct ring_info {
402 struct sk_buff *skb;
403 dma_addr_t mapping;
404 };
405
406
407 typedef enum {
408 CH_8139 = 0,
409 CH_8139_K,
410 CH_8139A,
411 CH_8139B,
412 CH_8130,
413 CH_8139C,
414 } chip_t;
415
416
417 /* directly indexed by chip_t, above */
418 const static struct {
419 const char *name;
420 u8 version; /* from RTL8139C docs */
421 u32 RxConfigMask; /* should clear the bits supported by this chip */
422 } rtl_chip_info[] = {
423 { "RTL-8139",
424 0x40,
425 0xf0fe0040, /* XXX copied from RTL8139A, verify */
426 },
427
428 { "RTL-8139 rev K",
429 0x60,
430 0xf0fe0040,
431 },
432
433 { "RTL-8139A",
434 0x70,
435 0xf0fe0040,
436 },
437
438 { "RTL-8139B",
439 0x78,
440 0xf0fc0040
441 },
442
443 { "RTL-8130",
444 0x7C,
445 0xf0fe0040, /* XXX copied from RTL8139A, verify */
446 },
447
448 { "RTL-8139C",
449 0x74,
450 0xf0fc0040, /* XXX copied from RTL8139B, verify */
451 },
452
453 };
454
455
456 struct netdrv_private {
457 board_t board;
458 void *mmio_addr;
459 int drv_flags;
460 struct pci_dev *pci_dev;
461 struct net_device_stats stats;
462 struct timer_list timer; /* Media selection timer. */
463 unsigned char *rx_ring;
464 unsigned int cur_rx; /* Index into the Rx buffer of next Rx pkt. */
465 unsigned int tx_flag;
466 atomic_t cur_tx;
467 atomic_t dirty_tx;
468 /* The saved address of a sent-in-place packet/buffer, for skfree(). */
469 struct ring_info tx_info[NUM_TX_DESC];
470 unsigned char *tx_buf[NUM_TX_DESC]; /* Tx bounce buffers */
471 unsigned char *tx_bufs; /* Tx bounce buffer region. */
472 dma_addr_t rx_ring_dma;
473 dma_addr_t tx_bufs_dma;
474 char phys[4]; /* MII device addresses. */
475 char twistie, twist_row, twist_col; /* Twister tune state. */
476 unsigned int full_duplex:1; /* Full-duplex operation requested. */
477 unsigned int duplex_lock:1;
478 unsigned int default_port:4; /* Last dev->if_port value. */
479 unsigned int media2:4; /* Secondary monitored media port. */
480 unsigned int medialock:1; /* Don't sense media type. */
481 unsigned int mediasense:1; /* Media sensing in progress. */
482 spinlock_t lock;
483 chip_t chipset;
484 };
485
486 MODULE_AUTHOR ("Jeff Garzik <jgarzik@pobox.com>");
487 MODULE_DESCRIPTION ("Skeleton for a PCI Fast Ethernet driver");
488 MODULE_LICENSE("GPL");
489 MODULE_PARM (multicast_filter_limit, "i");
490 MODULE_PARM (max_interrupt_work, "i");
491 MODULE_PARM (media, "1-" __MODULE_STRING(8) "i");
492 MODULE_PARM_DESC (multicast_filter_limit, "pci-skeleton maximum number of filtered multicast addresses");
493 MODULE_PARM_DESC (max_interrupt_work, "pci-skeleton maximum events handled per interrupt");
494 MODULE_PARM_DESC (media, "pci-skeleton: Bits 0-3: media type, bit 17: full duplex");
495
496 static int read_eeprom (void *ioaddr, int location, int addr_len);
497 static int netdrv_open (struct net_device *dev);
498 static int mdio_read (struct net_device *dev, int phy_id, int location);
499 static void mdio_write (struct net_device *dev, int phy_id, int location,
500 int val);
501 static void netdrv_timer (unsigned long data);
502 static void netdrv_tx_timeout (struct net_device *dev);
503 static void netdrv_init_ring (struct net_device *dev);
504 static int netdrv_start_xmit (struct sk_buff *skb,
505 struct net_device *dev);
506 static irqreturn_t netdrv_interrupt (int irq, void *dev_instance,
507 struct pt_regs *regs);
508 static int netdrv_close (struct net_device *dev);
509 static int netdrv_ioctl (struct net_device *dev, struct ifreq *rq, int cmd);
510 static struct net_device_stats *netdrv_get_stats (struct net_device *dev);
511 static void netdrv_set_rx_mode (struct net_device *dev);
512 static void netdrv_hw_start (struct net_device *dev);
513
514
515 #ifdef USE_IO_OPS
516
517 #define NETDRV_R8(reg) inb (((unsigned long)ioaddr) + (reg))
518 #define NETDRV_R16(reg) inw (((unsigned long)ioaddr) + (reg))
519 #define NETDRV_R32(reg) ((unsigned long) inl (((unsigned long)ioaddr) + (reg)))
520 #define NETDRV_W8(reg, val8) outb ((val8), ((unsigned long)ioaddr) + (reg))
521 #define NETDRV_W16(reg, val16) outw ((val16), ((unsigned long)ioaddr) + (reg))
522 #define NETDRV_W32(reg, val32) outl ((val32), ((unsigned long)ioaddr) + (reg))
523 #define NETDRV_W8_F NETDRV_W8
524 #define NETDRV_W16_F NETDRV_W16
525 #define NETDRV_W32_F NETDRV_W32
526 #undef readb
527 #undef readw
528 #undef readl
529 #undef writeb
530 #undef writew
531 #undef writel
532 #define readb(addr) inb((unsigned long)(addr))
533 #define readw(addr) inw((unsigned long)(addr))
534 #define readl(addr) inl((unsigned long)(addr))
535 #define writeb(val,addr) outb((val),(unsigned long)(addr))
536 #define writew(val,addr) outw((val),(unsigned long)(addr))
537 #define writel(val,addr) outl((val),(unsigned long)(addr))
538
539 #else
540
541 /* write MMIO register, with flush */
542 /* Flush avoids rtl8139 bug w/ posted MMIO writes */
543 #define NETDRV_W8_F(reg, val8) do { writeb ((val8), ioaddr + (reg)); readb (ioaddr + (reg)); } while (0)
544 #define NETDRV_W16_F(reg, val16) do { writew ((val16), ioaddr + (reg)); readw (ioaddr + (reg)); } while (0)
545 #define NETDRV_W32_F(reg, val32) do { writel ((val32), ioaddr + (reg)); readl (ioaddr + (reg)); } while (0)
546
547
548 #if MMIO_FLUSH_AUDIT_COMPLETE
549
550 /* write MMIO register */
551 #define NETDRV_W8(reg, val8) writeb ((val8), ioaddr + (reg))
552 #define NETDRV_W16(reg, val16) writew ((val16), ioaddr + (reg))
553 #define NETDRV_W32(reg, val32) writel ((val32), ioaddr + (reg))
554
555 #else
556
557 /* write MMIO register, then flush */
558 #define NETDRV_W8 NETDRV_W8_F
559 #define NETDRV_W16 NETDRV_W16_F
560 #define NETDRV_W32 NETDRV_W32_F
561
562 #endif /* MMIO_FLUSH_AUDIT_COMPLETE */
563
564 /* read MMIO register */
565 #define NETDRV_R8(reg) readb (ioaddr + (reg))
566 #define NETDRV_R16(reg) readw (ioaddr + (reg))
567 #define NETDRV_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
568
569 #endif /* USE_IO_OPS */
570
571
572 static const u16 netdrv_intr_mask =
573 PCIErr | PCSTimeout | RxUnderrun | RxOverflow | RxFIFOOver |
574 TxErr | TxOK | RxErr | RxOK;
575
576 static const unsigned int netdrv_rx_config =
577 RxCfgEarlyRxNone | RxCfgRcv32K | RxNoWrap |
578 (RX_FIFO_THRESH << RxCfgFIFOShift) |
579 (RX_DMA_BURST << RxCfgDMAShift);
580
581
582 static int __devinit netdrv_init_board (struct pci_dev *pdev,
583 struct net_device **dev_out,
584 void **ioaddr_out)
585 {
586 void *ioaddr = NULL;
587 struct net_device *dev;
588 struct netdrv_private *tp;
589 int rc, i;
590 u32 pio_start, pio_end, pio_flags, pio_len;
591 unsigned long mmio_start, mmio_end, mmio_flags, mmio_len;
592 u32 tmp;
593
594 DPRINTK ("ENTER\n");
595
596 assert (pdev != NULL);
597 assert (ioaddr_out != NULL);
598
599 *ioaddr_out = NULL;
600 *dev_out = NULL;
601
602 /* dev zeroed in alloc_etherdev */
603 dev = alloc_etherdev (sizeof (*tp));
604 if (dev == NULL) {
605 printk (KERN_ERR PFX "unable to alloc new ethernet\n");
606 DPRINTK ("EXIT, returning -ENOMEM\n");
607 return -ENOMEM;
608 }
609 SET_MODULE_OWNER(dev);
610 SET_NETDEV_DEV(dev, &pdev->dev);
611 tp = dev->priv;
612
613 /* enable device (incl. PCI PM wakeup), and bus-mastering */
614 rc = pci_enable_device (pdev);
615 if (rc)
616 goto err_out;
617
618 pio_start = pci_resource_start (pdev, 0);
619 pio_end = pci_resource_end (pdev, 0);
620 pio_flags = pci_resource_flags (pdev, 0);
621 pio_len = pci_resource_len (pdev, 0);
622
623 mmio_start = pci_resource_start (pdev, 1);
624 mmio_end = pci_resource_end (pdev, 1);
625 mmio_flags = pci_resource_flags (pdev, 1);
626 mmio_len = pci_resource_len (pdev, 1);
627
628 /* set this immediately, we need to know before
629 * we talk to the chip directly */
630 DPRINTK("PIO region size == 0x%02X\n", pio_len);
631 DPRINTK("MMIO region size == 0x%02lX\n", mmio_len);
632
633 /* make sure PCI base addr 0 is PIO */
634 if (!(pio_flags & IORESOURCE_IO)) {
635 printk (KERN_ERR PFX "region #0 not a PIO resource, aborting\n");
636 rc = -ENODEV;
637 goto err_out;
638 }
639
640 /* make sure PCI base addr 1 is MMIO */
641 if (!(mmio_flags & IORESOURCE_MEM)) {
642 printk (KERN_ERR PFX "region #1 not an MMIO resource, aborting\n");
643 rc = -ENODEV;
644 goto err_out;
645 }
646
647 /* check for weird/broken PCI region reporting */
648 if ((pio_len < NETDRV_MIN_IO_SIZE) ||
649 (mmio_len < NETDRV_MIN_IO_SIZE)) {
650 printk (KERN_ERR PFX "Invalid PCI region size(s), aborting\n");
651 rc = -ENODEV;
652 goto err_out;
653 }
654
655 rc = pci_request_regions (pdev, "pci-skeleton");
656 if (rc)
657 goto err_out;
658
659 pci_set_master (pdev);
660
661 #ifdef USE_IO_OPS
662 ioaddr = (void *) pio_start;
663 #else
664 /* ioremap MMIO region */
665 ioaddr = ioremap (mmio_start, mmio_len);
666 if (ioaddr == NULL) {
667 printk (KERN_ERR PFX "cannot remap MMIO, aborting\n");
668 rc = -EIO;
669 goto err_out_free_res;
670 }
671 #endif /* USE_IO_OPS */
672
673 /* Soft reset the chip. */
674 NETDRV_W8 (ChipCmd, (NETDRV_R8 (ChipCmd) & ChipCmdClear) | CmdReset);
675
676 /* Check that the chip has finished the reset. */
677 for (i = 1000; i > 0; i--)
678 if ((NETDRV_R8 (ChipCmd) & CmdReset) == 0)
679 break;
680 else
681 udelay (10);
682
683 /* Bring the chip out of low-power mode. */
684 /* <insert device-specific code here> */
685
686 #ifndef USE_IO_OPS
687 /* sanity checks -- ensure PIO and MMIO registers agree */
688 assert (inb (pio_start+Config0) == readb (ioaddr+Config0));
689 assert (inb (pio_start+Config1) == readb (ioaddr+Config1));
690 assert (inb (pio_start+TxConfig) == readb (ioaddr+TxConfig));
691 assert (inb (pio_start+RxConfig) == readb (ioaddr+RxConfig));
692 #endif /* !USE_IO_OPS */
693
694 /* identify chip attached to board */
695 tmp = NETDRV_R8 (ChipVersion);
696 for (i = ARRAY_SIZE (rtl_chip_info) - 1; i >= 0; i--)
697 if (tmp == rtl_chip_info[i].version) {
698 tp->chipset = i;
699 goto match;
700 }
701
702 /* if unknown chip, assume array element #0, original RTL-8139 in this case */
703 printk (KERN_DEBUG PFX "PCI device %s: unknown chip version, assuming RTL-8139\n",
704 pci_name(pdev));
705 printk (KERN_DEBUG PFX "PCI device %s: TxConfig = 0x%lx\n", pci_name(pdev), NETDRV_R32 (TxConfig));
706 tp->chipset = 0;
707
708 match:
709 DPRINTK ("chipset id (%d) == index %d, '%s'\n",
710 tmp,
711 tp->chipset,
712 rtl_chip_info[tp->chipset].name);
713
714 i = register_netdev (dev);
715 if (i)
716 goto err_out_unmap;
717
718 DPRINTK ("EXIT, returning 0\n");
719 *ioaddr_out = ioaddr;
720 *dev_out = dev;
721 return 0;
722
723 err_out_unmap:
724 #ifndef USE_IO_OPS
725 iounmap(ioaddr);
726 err_out_free_res:
727 #endif
728 pci_release_regions (pdev);
729 err_out:
730 free_netdev (dev);
731 DPRINTK ("EXIT, returning %d\n", rc);
732 return rc;
733 }
734
735
736 static int __devinit netdrv_init_one (struct pci_dev *pdev,
737 const struct pci_device_id *ent)
738 {
739 struct net_device *dev = NULL;
740 struct netdrv_private *tp;
741 int i, addr_len, option;
742 void *ioaddr = NULL;
743 static int board_idx = -1;
744
745 /* when built into the kernel, we only print version if device is found */
746 #ifndef MODULE
747 static int printed_version;
748 if (!printed_version++)
749 printk(version);
750 #endif
751
752 DPRINTK ("ENTER\n");
753
754 assert (pdev != NULL);
755 assert (ent != NULL);
756
757 board_idx++;
758
759 i = netdrv_init_board (pdev, &dev, &ioaddr);
760 if (i < 0) {
761 DPRINTK ("EXIT, returning %d\n", i);
762 return i;
763 }
764
765 tp = dev->priv;
766
767 assert (ioaddr != NULL);
768 assert (dev != NULL);
769 assert (tp != NULL);
770
771 addr_len = read_eeprom (ioaddr, 0, 8) == 0x8129 ? 8 : 6;
772 for (i = 0; i < 3; i++)
773 ((u16 *) (dev->dev_addr))[i] =
774 le16_to_cpu (read_eeprom (ioaddr, i + 7, addr_len));
775
776 /* The Rtl8139-specific entries in the device structure. */
777 dev->open = netdrv_open;
778 dev->hard_start_xmit = netdrv_start_xmit;
779 dev->stop = netdrv_close;
780 dev->get_stats = netdrv_get_stats;
781 dev->set_multicast_list = netdrv_set_rx_mode;
782 dev->do_ioctl = netdrv_ioctl;
783 dev->tx_timeout = netdrv_tx_timeout;
784 dev->watchdog_timeo = TX_TIMEOUT;
785
786 dev->irq = pdev->irq;
787 dev->base_addr = (unsigned long) ioaddr;
788
789 /* dev->priv/tp zeroed and aligned in alloc_etherdev */
790 tp = dev->priv;
791
792 /* note: tp->chipset set in netdrv_init_board */
793 tp->drv_flags = PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
794 PCI_COMMAND_MASTER | NETDRV_CAPS;
795 tp->pci_dev = pdev;
796 tp->board = ent->driver_data;
797 tp->mmio_addr = ioaddr;
798 spin_lock_init(&tp->lock);
799
800 pci_set_drvdata(pdev, dev);
801
802 tp->phys[0] = 32;
803
804 printk (KERN_INFO "%s: %s at 0x%lx, "
805 "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
806 "IRQ %d\n",
807 dev->name,
808 board_info[ent->driver_data].name,
809 dev->base_addr,
810 dev->dev_addr[0], dev->dev_addr[1],
811 dev->dev_addr[2], dev->dev_addr[3],
812 dev->dev_addr[4], dev->dev_addr[5],
813 dev->irq);
814
815 printk (KERN_DEBUG "%s: Identified 8139 chip type '%s'\n",
816 dev->name, rtl_chip_info[tp->chipset].name);
817
818 /* Put the chip into low-power mode. */
819 NETDRV_W8_F (Cfg9346, Cfg9346_Unlock);
820
821 /* The lower four bits are the media type. */
822 option = (board_idx > 7) ? 0 : media[board_idx];
823 if (option > 0) {
824 tp->full_duplex = (option & 0x200) ? 1 : 0;
825 tp->default_port = option & 15;
826 if (tp->default_port)
827 tp->medialock = 1;
828 }
829
830 if (tp->full_duplex) {
831 printk (KERN_INFO
832 "%s: Media type forced to Full Duplex.\n",
833 dev->name);
834 mdio_write (dev, tp->phys[0], MII_ADVERTISE, ADVERTISE_FULL);
835 tp->duplex_lock = 1;
836 }
837
838 DPRINTK ("EXIT - returning 0\n");
839 return 0;
840 }
841
842
843 static void __devexit netdrv_remove_one (struct pci_dev *pdev)
844 {
845 struct net_device *dev = pci_get_drvdata (pdev);
846 struct netdrv_private *np;
847
848 DPRINTK ("ENTER\n");
849
850 assert (dev != NULL);
851
852 np = dev->priv;
853 assert (np != NULL);
854
855 unregister_netdev (dev);
856
857 #ifndef USE_IO_OPS
858 iounmap (np->mmio_addr);
859 #endif /* !USE_IO_OPS */
860
861 pci_release_regions (pdev);
862
863 free_netdev (dev);
864
865 pci_set_drvdata (pdev, NULL);
866
867 pci_disable_device (pdev);
868
869 DPRINTK ("EXIT\n");
870 }
871
872
873 /* Serial EEPROM section. */
874
875 /* EEPROM_Ctrl bits. */
876 #define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */
877 #define EE_CS 0x08 /* EEPROM chip select. */
878 #define EE_DATA_WRITE 0x02 /* EEPROM chip data in. */
879 #define EE_WRITE_0 0x00
880 #define EE_WRITE_1 0x02
881 #define EE_DATA_READ 0x01 /* EEPROM chip data out. */
882 #define EE_ENB (0x80 | EE_CS)
883
884 /* Delay between EEPROM clock transitions.
885 No extra delay is needed with 33Mhz PCI, but 66Mhz may change this.
886 */
887
888 #define eeprom_delay() readl(ee_addr)
889
890 /* The EEPROM commands include the alway-set leading bit. */
891 #define EE_WRITE_CMD (5)
892 #define EE_READ_CMD (6)
893 #define EE_ERASE_CMD (7)
894
895 static int __devinit read_eeprom (void *ioaddr, int location, int addr_len)
896 {
897 int i;
898 unsigned retval = 0;
899 void *ee_addr = ioaddr + Cfg9346;
900 int read_cmd = location | (EE_READ_CMD << addr_len);
901
902 DPRINTK ("ENTER\n");
903
904 writeb (EE_ENB & ~EE_CS, ee_addr);
905 writeb (EE_ENB, ee_addr);
906 eeprom_delay ();
907
908 /* Shift the read command bits out. */
909 for (i = 4 + addr_len; i >= 0; i--) {
910 int dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
911 writeb (EE_ENB | dataval, ee_addr);
912 eeprom_delay ();
913 writeb (EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
914 eeprom_delay ();
915 }
916 writeb (EE_ENB, ee_addr);
917 eeprom_delay ();
918
919 for (i = 16; i > 0; i--) {
920 writeb (EE_ENB | EE_SHIFT_CLK, ee_addr);
921 eeprom_delay ();
922 retval =
923 (retval << 1) | ((readb (ee_addr) & EE_DATA_READ) ? 1 :
924 0);
925 writeb (EE_ENB, ee_addr);
926 eeprom_delay ();
927 }
928
929 /* Terminate the EEPROM access. */
930 writeb (~EE_CS, ee_addr);
931 eeprom_delay ();
932
933 DPRINTK ("EXIT - returning %d\n", retval);
934 return retval;
935 }
936
937 /* MII serial management: mostly bogus for now. */
938 /* Read and write the MII management registers using software-generated
939 serial MDIO protocol.
940 The maximum data clock rate is 2.5 Mhz. The minimum timing is usually
941 met by back-to-back PCI I/O cycles, but we insert a delay to avoid
942 "overclocking" issues. */
943 #define MDIO_DIR 0x80
944 #define MDIO_DATA_OUT 0x04
945 #define MDIO_DATA_IN 0x02
946 #define MDIO_CLK 0x01
947 #define MDIO_WRITE0 (MDIO_DIR)
948 #define MDIO_WRITE1 (MDIO_DIR | MDIO_DATA_OUT)
949
950 #define mdio_delay() readb(mdio_addr)
951
952
953 static char mii_2_8139_map[8] = {
954 BasicModeCtrl,
955 BasicModeStatus,
956 0,
957 0,
958 NWayAdvert,
959 NWayLPAR,
960 NWayExpansion,
961 0
962 };
963
964
965 /* Syncronize the MII management interface by shifting 32 one bits out. */
966 static void mdio_sync (void *mdio_addr)
967 {
968 int i;
969
970 DPRINTK ("ENTER\n");
971
972 for (i = 32; i >= 0; i--) {
973 writeb (MDIO_WRITE1, mdio_addr);
974 mdio_delay ();
975 writeb (MDIO_WRITE1 | MDIO_CLK, mdio_addr);
976 mdio_delay ();
977 }
978
979 DPRINTK ("EXIT\n");
980 }
981
982
983 static int mdio_read (struct net_device *dev, int phy_id, int location)
984 {
985 struct netdrv_private *tp = dev->priv;
986 void *mdio_addr = tp->mmio_addr + Config4;
987 int mii_cmd = (0xf6 << 10) | (phy_id << 5) | location;
988 int retval = 0;
989 int i;
990
991 DPRINTK ("ENTER\n");
992
993 if (phy_id > 31) { /* Really a 8139. Use internal registers. */
994 DPRINTK ("EXIT after directly using 8139 internal regs\n");
995 return location < 8 && mii_2_8139_map[location] ?
996 readw (tp->mmio_addr + mii_2_8139_map[location]) : 0;
997 }
998 mdio_sync (mdio_addr);
999 /* Shift the read command bits out. */
1000 for (i = 15; i >= 0; i--) {
1001 int dataval = (mii_cmd & (1 << i)) ? MDIO_DATA_OUT : 0;
1002
1003 writeb (MDIO_DIR | dataval, mdio_addr);
1004 mdio_delay ();
1005 writeb (MDIO_DIR | dataval | MDIO_CLK, mdio_addr);
1006 mdio_delay ();
1007 }
1008
1009 /* Read the two transition, 16 data, and wire-idle bits. */
1010 for (i = 19; i > 0; i--) {
1011 writeb (0, mdio_addr);
1012 mdio_delay ();
1013 retval =
1014 (retval << 1) | ((readb (mdio_addr) & MDIO_DATA_IN) ? 1
1015 : 0);
1016 writeb (MDIO_CLK, mdio_addr);
1017 mdio_delay ();
1018 }
1019
1020 DPRINTK ("EXIT, returning %d\n", (retval >> 1) & 0xffff);
1021 return (retval >> 1) & 0xffff;
1022 }
1023
1024
1025 static void mdio_write (struct net_device *dev, int phy_id, int location,
1026 int value)
1027 {
1028 struct netdrv_private *tp = dev->priv;
1029 void *mdio_addr = tp->mmio_addr + Config4;
1030 int mii_cmd =
1031 (0x5002 << 16) | (phy_id << 23) | (location << 18) | value;
1032 int i;
1033
1034 DPRINTK ("ENTER\n");
1035
1036 if (phy_id > 31) { /* Really a 8139. Use internal registers. */
1037 if (location < 8 && mii_2_8139_map[location]) {
1038 writew (value,
1039 tp->mmio_addr + mii_2_8139_map[location]);
1040 readw (tp->mmio_addr + mii_2_8139_map[location]);
1041 }
1042 DPRINTK ("EXIT after directly using 8139 internal regs\n");
1043 return;
1044 }
1045 mdio_sync (mdio_addr);
1046
1047 /* Shift the command bits out. */
1048 for (i = 31; i >= 0; i--) {
1049 int dataval =
1050 (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0;
1051 writeb (dataval, mdio_addr);
1052 mdio_delay ();
1053 writeb (dataval | MDIO_CLK, mdio_addr);
1054 mdio_delay ();
1055 }
1056
1057 /* Clear out extra bits. */
1058 for (i = 2; i > 0; i--) {
1059 writeb (0, mdio_addr);
1060 mdio_delay ();
1061 writeb (MDIO_CLK, mdio_addr);
1062 mdio_delay ();
1063 }
1064
1065 DPRINTK ("EXIT\n");
1066 }
1067
1068
1069 static int netdrv_open (struct net_device *dev)
1070 {
1071 struct netdrv_private *tp = dev->priv;
1072 int retval;
1073 #ifdef NETDRV_DEBUG
1074 void *ioaddr = tp->mmio_addr;
1075 #endif
1076
1077 DPRINTK ("ENTER\n");
1078
1079 retval = request_irq (dev->irq, netdrv_interrupt, SA_SHIRQ, dev->name, dev);
1080 if (retval) {
1081 DPRINTK ("EXIT, returning %d\n", retval);
1082 return retval;
1083 }
1084
1085 tp->tx_bufs = pci_alloc_consistent(tp->pci_dev, TX_BUF_TOT_LEN,
1086 &tp->tx_bufs_dma);
1087 tp->rx_ring = pci_alloc_consistent(tp->pci_dev, RX_BUF_TOT_LEN,
1088 &tp->rx_ring_dma);
1089 if (tp->tx_bufs == NULL || tp->rx_ring == NULL) {
1090 free_irq(dev->irq, dev);
1091
1092 if (tp->tx_bufs)
1093 pci_free_consistent(tp->pci_dev, TX_BUF_TOT_LEN,
1094 tp->tx_bufs, tp->tx_bufs_dma);
1095 if (tp->rx_ring)
1096 pci_free_consistent(tp->pci_dev, RX_BUF_TOT_LEN,
1097 tp->rx_ring, tp->rx_ring_dma);
1098
1099 DPRINTK ("EXIT, returning -ENOMEM\n");
1100 return -ENOMEM;
1101
1102 }
1103
1104 tp->full_duplex = tp->duplex_lock;
1105 tp->tx_flag = (TX_FIFO_THRESH << 11) & 0x003f0000;
1106
1107 netdrv_init_ring (dev);
1108 netdrv_hw_start (dev);
1109
1110 DPRINTK ("%s: netdrv_open() ioaddr %#lx IRQ %d"
1111 " GP Pins %2.2x %s-duplex.\n",
1112 dev->name, pci_resource_start (tp->pci_dev, 1),
1113 dev->irq, NETDRV_R8 (MediaStatus),
1114 tp->full_duplex ? "full" : "half");
1115
1116 /* Set the timer to switch to check for link beat and perhaps switch
1117 to an alternate media type. */
1118 init_timer (&tp->timer);
1119 tp->timer.expires = jiffies + 3 * HZ;
1120 tp->timer.data = (unsigned long) dev;
1121 tp->timer.function = &netdrv_timer;
1122 add_timer (&tp->timer);
1123
1124 DPRINTK ("EXIT, returning 0\n");
1125 return 0;
1126 }
1127
1128
1129 /* Start the hardware at open or resume. */
1130 static void netdrv_hw_start (struct net_device *dev)
1131 {
1132 struct netdrv_private *tp = dev->priv;
1133 void *ioaddr = tp->mmio_addr;
1134 u32 i;
1135
1136 DPRINTK ("ENTER\n");
1137
1138 /* Soft reset the chip. */
1139 NETDRV_W8 (ChipCmd, (NETDRV_R8 (ChipCmd) & ChipCmdClear) | CmdReset);
1140 udelay (100);
1141
1142 /* Check that the chip has finished the reset. */
1143 for (i = 1000; i > 0; i--)
1144 if ((NETDRV_R8 (ChipCmd) & CmdReset) == 0)
1145 break;
1146
1147 /* Restore our idea of the MAC address. */
1148 NETDRV_W32_F (MAC0 + 0, cpu_to_le32 (*(u32 *) (dev->dev_addr + 0)));
1149 NETDRV_W32_F (MAC0 + 4, cpu_to_le32 (*(u32 *) (dev->dev_addr + 4)));
1150
1151 /* Must enable Tx/Rx before setting transfer thresholds! */
1152 NETDRV_W8_F (ChipCmd, (NETDRV_R8 (ChipCmd) & ChipCmdClear) |
1153 CmdRxEnb | CmdTxEnb);
1154
1155 i = netdrv_rx_config |
1156 (NETDRV_R32 (RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
1157 NETDRV_W32_F (RxConfig, i);
1158
1159 /* Check this value: the documentation for IFG contradicts ifself. */
1160 NETDRV_W32 (TxConfig, (TX_DMA_BURST << TxDMAShift));
1161
1162 /* unlock Config[01234] and BMCR register writes */
1163 NETDRV_W8_F (Cfg9346, Cfg9346_Unlock);
1164 udelay (10);
1165
1166 tp->cur_rx = 0;
1167
1168 /* Lock Config[01234] and BMCR register writes */
1169 NETDRV_W8_F (Cfg9346, Cfg9346_Lock);
1170 udelay (10);
1171
1172 /* init Rx ring buffer DMA address */
1173 NETDRV_W32_F (RxBuf, tp->rx_ring_dma);
1174
1175 /* init Tx buffer DMA addresses */
1176 for (i = 0; i < NUM_TX_DESC; i++)
1177 NETDRV_W32_F (TxAddr0 + (i * 4), tp->tx_bufs_dma + (tp->tx_buf[i] - tp->tx_bufs));
1178
1179 NETDRV_W32_F (RxMissed, 0);
1180
1181 netdrv_set_rx_mode (dev);
1182
1183 /* no early-rx interrupts */
1184 NETDRV_W16 (MultiIntr, NETDRV_R16 (MultiIntr) & MultiIntrClear);
1185
1186 /* make sure RxTx has started */
1187 NETDRV_W8_F (ChipCmd, (NETDRV_R8 (ChipCmd) & ChipCmdClear) |
1188 CmdRxEnb | CmdTxEnb);
1189
1190 /* Enable all known interrupts by setting the interrupt mask. */
1191 NETDRV_W16_F (IntrMask, netdrv_intr_mask);
1192
1193 netif_start_queue (dev);
1194
1195 DPRINTK ("EXIT\n");
1196 }
1197
1198
1199 /* Initialize the Rx and Tx rings, along with various 'dev' bits. */
1200 static void netdrv_init_ring (struct net_device *dev)
1201 {
1202 struct netdrv_private *tp = dev->priv;
1203 int i;
1204
1205 DPRINTK ("ENTER\n");
1206
1207 tp->cur_rx = 0;
1208 atomic_set (&tp->cur_tx, 0);
1209 atomic_set (&tp->dirty_tx, 0);
1210
1211 for (i = 0; i < NUM_TX_DESC; i++) {
1212 tp->tx_info[i].skb = NULL;
1213 tp->tx_info[i].mapping = 0;
1214 tp->tx_buf[i] = &tp->tx_bufs[i * TX_BUF_SIZE];
1215 }
1216
1217 DPRINTK ("EXIT\n");
1218 }
1219
1220
1221 static void netdrv_timer (unsigned long data)
1222 {
1223 struct net_device *dev = (struct net_device *) data;
1224 struct netdrv_private *tp = dev->priv;
1225 void *ioaddr = tp->mmio_addr;
1226 int next_tick = 60 * HZ;
1227 int mii_lpa;
1228
1229 mii_lpa = mdio_read (dev, tp->phys[0], MII_LPA);
1230
1231 if (!tp->duplex_lock && mii_lpa != 0xffff) {
1232 int duplex = (mii_lpa & LPA_100FULL)
1233 || (mii_lpa & 0x01C0) == 0x0040;
1234 if (tp->full_duplex != duplex) {
1235 tp->full_duplex = duplex;
1236 printk (KERN_INFO
1237 "%s: Setting %s-duplex based on MII #%d link"
1238 " partner ability of %4.4x.\n", dev->name,
1239 tp->full_duplex ? "full" : "half",
1240 tp->phys[0], mii_lpa);
1241 NETDRV_W8 (Cfg9346, Cfg9346_Unlock);
1242 NETDRV_W8 (Config1, tp->full_duplex ? 0x60 : 0x20);
1243 NETDRV_W8 (Cfg9346, Cfg9346_Lock);
1244 }
1245 }
1246
1247 DPRINTK ("%s: Media selection tick, Link partner %4.4x.\n",
1248 dev->name, NETDRV_R16 (NWayLPAR));
1249 DPRINTK ("%s: Other registers are IntMask %4.4x IntStatus %4.4x"
1250 " RxStatus %4.4x.\n", dev->name,
1251 NETDRV_R16 (IntrMask),
1252 NETDRV_R16 (IntrStatus),
1253 NETDRV_R32 (RxEarlyStatus));
1254 DPRINTK ("%s: Chip config %2.2x %2.2x.\n",
1255 dev->name, NETDRV_R8 (Config0),
1256 NETDRV_R8 (Config1));
1257
1258 tp->timer.expires = jiffies + next_tick;
1259 add_timer (&tp->timer);
1260 }
1261
1262
1263 static void netdrv_tx_clear (struct netdrv_private *tp)
1264 {
1265 int i;
1266
1267 atomic_set (&tp->cur_tx, 0);
1268 atomic_set (&tp->dirty_tx, 0);
1269
1270 /* Dump the unsent Tx packets. */
1271 for (i = 0; i < NUM_TX_DESC; i++) {
1272 struct ring_info *rp = &tp->tx_info[i];
1273 if (rp->mapping != 0) {
1274 pci_unmap_single (tp->pci_dev, rp->mapping,
1275 rp->skb->len, PCI_DMA_TODEVICE);
1276 rp->mapping = 0;
1277 }
1278 if (rp->skb) {
1279 dev_kfree_skb (rp->skb);
1280 rp->skb = NULL;
1281 tp->stats.tx_dropped++;
1282 }
1283 }
1284 }
1285
1286
1287 static void netdrv_tx_timeout (struct net_device *dev)
1288 {
1289 struct netdrv_private *tp = dev->priv;
1290 void *ioaddr = tp->mmio_addr;
1291 int i;
1292 u8 tmp8;
1293 unsigned long flags;
1294
1295 DPRINTK ("%s: Transmit timeout, status %2.2x %4.4x "
1296 "media %2.2x.\n", dev->name,
1297 NETDRV_R8 (ChipCmd),
1298 NETDRV_R16 (IntrStatus),
1299 NETDRV_R8 (MediaStatus));
1300
1301 /* disable Tx ASAP, if not already */
1302 tmp8 = NETDRV_R8 (ChipCmd);
1303 if (tmp8 & CmdTxEnb)
1304 NETDRV_W8 (ChipCmd, tmp8 & ~CmdTxEnb);
1305
1306 /* Disable interrupts by clearing the interrupt mask. */
1307 NETDRV_W16 (IntrMask, 0x0000);
1308
1309 /* Emit info to figure out what went wrong. */
1310 printk (KERN_DEBUG "%s: Tx queue start entry %d dirty entry %d.\n",
1311 dev->name, atomic_read (&tp->cur_tx),
1312 atomic_read (&tp->dirty_tx));
1313 for (i = 0; i < NUM_TX_DESC; i++)
1314 printk (KERN_DEBUG "%s: Tx descriptor %d is %8.8lx.%s\n",
1315 dev->name, i, NETDRV_R32 (TxStatus0 + (i * 4)),
1316 i == atomic_read (&tp->dirty_tx) % NUM_TX_DESC ?
1317 " (queue head)" : "");
1318
1319 /* Stop a shared interrupt from scavenging while we are. */
1320 spin_lock_irqsave (&tp->lock, flags);
1321
1322 netdrv_tx_clear (tp);
1323
1324 spin_unlock_irqrestore (&tp->lock, flags);
1325
1326 /* ...and finally, reset everything */
1327 netdrv_hw_start (dev);
1328
1329 netif_wake_queue (dev);
1330 }
1331
1332
1333
1334 static int netdrv_start_xmit (struct sk_buff *skb, struct net_device *dev)
1335 {
1336 struct netdrv_private *tp = dev->priv;
1337 void *ioaddr = tp->mmio_addr;
1338 int entry;
1339
1340 /* Calculate the next Tx descriptor entry. */
1341 entry = atomic_read (&tp->cur_tx) % NUM_TX_DESC;
1342
1343 assert (tp->tx_info[entry].skb == NULL);
1344 assert (tp->tx_info[entry].mapping == 0);
1345
1346 tp->tx_info[entry].skb = skb;
1347 /* tp->tx_info[entry].mapping = 0; */
1348 memcpy (tp->tx_buf[entry], skb->data, skb->len);
1349
1350 /* Note: the chip doesn't have auto-pad! */
1351 NETDRV_W32 (TxStatus0 + (entry * sizeof(u32)),
1352 tp->tx_flag | (skb->len >= ETH_ZLEN ? skb->len : ETH_ZLEN));
1353
1354 dev->trans_start = jiffies;
1355 atomic_inc (&tp->cur_tx);
1356 if ((atomic_read (&tp->cur_tx) - atomic_read (&tp->dirty_tx)) >= NUM_TX_DESC)
1357 netif_stop_queue (dev);
1358
1359 DPRINTK ("%s: Queued Tx packet at %p size %u to slot %d.\n",
1360 dev->name, skb->data, skb->len, entry);
1361
1362 return 0;
1363 }
1364
1365
1366 static void netdrv_tx_interrupt (struct net_device *dev,
1367 struct netdrv_private *tp,
1368 void *ioaddr)
1369 {
1370 int cur_tx, dirty_tx, tx_left;
1371
1372 assert (dev != NULL);
1373 assert (tp != NULL);
1374 assert (ioaddr != NULL);
1375
1376 dirty_tx = atomic_read (&tp->dirty_tx);
1377
1378 cur_tx = atomic_read (&tp->cur_tx);
1379 tx_left = cur_tx - dirty_tx;
1380 while (tx_left > 0) {
1381 int entry = dirty_tx % NUM_TX_DESC;
1382 int txstatus;
1383
1384 txstatus = NETDRV_R32 (TxStatus0 + (entry * sizeof (u32)));
1385
1386 if (!(txstatus & (TxStatOK | TxUnderrun | TxAborted)))
1387 break; /* It still hasn't been Txed */
1388
1389 /* Note: TxCarrierLost is always asserted at 100mbps. */
1390 if (txstatus & (TxOutOfWindow | TxAborted)) {
1391 /* There was an major error, log it. */
1392 DPRINTK ("%s: Transmit error, Tx status %8.8x.\n",
1393 dev->name, txstatus);
1394 tp->stats.tx_errors++;
1395 if (txstatus & TxAborted) {
1396 tp->stats.tx_aborted_errors++;
1397 NETDRV_W32 (TxConfig, TxClearAbt | (TX_DMA_BURST << TxDMAShift));
1398 }
1399 if (txstatus & TxCarrierLost)
1400 tp->stats.tx_carrier_errors++;
1401 if (txstatus & TxOutOfWindow)
1402 tp->stats.tx_window_errors++;
1403 } else {
1404 if (txstatus & TxUnderrun) {
1405 /* Add 64 to the Tx FIFO threshold. */
1406 if (tp->tx_flag < 0x00300000)
1407 tp->tx_flag += 0x00020000;
1408 tp->stats.tx_fifo_errors++;
1409 }
1410 tp->stats.collisions += (txstatus >> 24) & 15;
1411 tp->stats.tx_bytes += txstatus & 0x7ff;
1412 tp->stats.tx_packets++;
1413 }
1414
1415 /* Free the original skb. */
1416 if (tp->tx_info[entry].mapping != 0) {
1417 pci_unmap_single(tp->pci_dev,
1418 tp->tx_info[entry].mapping,
1419 tp->tx_info[entry].skb->len,
1420 PCI_DMA_TODEVICE);
1421 tp->tx_info[entry].mapping = 0;
1422 }
1423 dev_kfree_skb_irq (tp->tx_info[entry].skb);
1424 tp->tx_info[entry].skb = NULL;
1425 dirty_tx++;
1426 if (dirty_tx < 0) { /* handle signed int overflow */
1427 atomic_sub (cur_tx, &tp->cur_tx); /* XXX racy? */
1428 dirty_tx = cur_tx - tx_left + 1;
1429 }
1430 if (netif_queue_stopped (dev))
1431 netif_wake_queue (dev);
1432
1433 cur_tx = atomic_read (&tp->cur_tx);
1434 tx_left = cur_tx - dirty_tx;
1435
1436 }
1437
1438 #ifndef NETDRV_NDEBUG
1439 if (atomic_read (&tp->cur_tx) - dirty_tx > NUM_TX_DESC) {
1440 printk (KERN_ERR
1441 "%s: Out-of-sync dirty pointer, %d vs. %d.\n",
1442 dev->name, dirty_tx, atomic_read (&tp->cur_tx));
1443 dirty_tx += NUM_TX_DESC;
1444 }
1445 #endif /* NETDRV_NDEBUG */
1446
1447 atomic_set (&tp->dirty_tx, dirty_tx);
1448 }
1449
1450
1451 /* TODO: clean this up! Rx reset need not be this intensive */
1452 static void netdrv_rx_err (u32 rx_status, struct net_device *dev,
1453 struct netdrv_private *tp, void *ioaddr)
1454 {
1455 u8 tmp8;
1456 int tmp_work = 1000;
1457
1458 DPRINTK ("%s: Ethernet frame had errors, status %8.8x.\n",
1459 dev->name, rx_status);
1460 if (rx_status & RxTooLong) {
1461 DPRINTK ("%s: Oversized Ethernet frame, status %4.4x!\n",
1462 dev->name, rx_status);
1463 /* A.C.: The chip hangs here. */
1464 }
1465 tp->stats.rx_errors++;
1466 if (rx_status & (RxBadSymbol | RxBadAlign))
1467 tp->stats.rx_frame_errors++;
1468 if (rx_status & (RxRunt | RxTooLong))
1469 tp->stats.rx_length_errors++;
1470 if (rx_status & RxCRCErr)
1471 tp->stats.rx_crc_errors++;
1472 /* Reset the receiver, based on RealTek recommendation. (Bug?) */
1473 tp->cur_rx = 0;
1474
1475 /* disable receive */
1476 tmp8 = NETDRV_R8 (ChipCmd) & ChipCmdClear;
1477 NETDRV_W8_F (ChipCmd, tmp8 | CmdTxEnb);
1478
1479 /* A.C.: Reset the multicast list. */
1480 netdrv_set_rx_mode (dev);
1481
1482 /* XXX potentially temporary hack to
1483 * restart hung receiver */
1484 while (--tmp_work > 0) {
1485 tmp8 = NETDRV_R8 (ChipCmd);
1486 if ((tmp8 & CmdRxEnb) && (tmp8 & CmdTxEnb))
1487 break;
1488 NETDRV_W8_F (ChipCmd,
1489 (tmp8 & ChipCmdClear) | CmdRxEnb | CmdTxEnb);
1490 }
1491
1492 /* G.S.: Re-enable receiver */
1493 /* XXX temporary hack to work around receiver hang */
1494 netdrv_set_rx_mode (dev);
1495
1496 if (tmp_work <= 0)
1497 printk (KERN_WARNING PFX "tx/rx enable wait too long\n");
1498 }
1499
1500
1501 /* The data sheet doesn't describe the Rx ring at all, so I'm guessing at the
1502 field alignments and semantics. */
1503 static void netdrv_rx_interrupt (struct net_device *dev,
1504 struct netdrv_private *tp, void *ioaddr)
1505 {
1506 unsigned char *rx_ring;
1507 u16 cur_rx;
1508
1509 assert (dev != NULL);
1510 assert (tp != NULL);
1511 assert (ioaddr != NULL);
1512
1513 rx_ring = tp->rx_ring;
1514 cur_rx = tp->cur_rx;
1515
1516 DPRINTK ("%s: In netdrv_rx(), current %4.4x BufAddr %4.4x,"
1517 " free to %4.4x, Cmd %2.2x.\n", dev->name, cur_rx,
1518 NETDRV_R16 (RxBufAddr),
1519 NETDRV_R16 (RxBufPtr), NETDRV_R8 (ChipCmd));
1520
1521 while ((NETDRV_R8 (ChipCmd) & RxBufEmpty) == 0) {
1522 int ring_offset = cur_rx % RX_BUF_LEN;
1523 u32 rx_status;
1524 unsigned int rx_size;
1525 unsigned int pkt_size;
1526 struct sk_buff *skb;
1527
1528 /* read size+status of next frame from DMA ring buffer */
1529 rx_status = le32_to_cpu (*(u32 *) (rx_ring + ring_offset));
1530 rx_size = rx_status >> 16;
1531 pkt_size = rx_size - 4;
1532
1533 DPRINTK ("%s: netdrv_rx() status %4.4x, size %4.4x,"
1534 " cur %4.4x.\n", dev->name, rx_status,
1535 rx_size, cur_rx);
1536 #if NETDRV_DEBUG > 2
1537 {
1538 int i;
1539 DPRINTK ("%s: Frame contents ", dev->name);
1540 for (i = 0; i < 70; i++)
1541 printk (" %2.2x",
1542 rx_ring[ring_offset + i]);
1543 printk (".\n");
1544 }
1545 #endif
1546
1547 /* If Rx err or invalid rx_size/rx_status received
1548 * (which happens if we get lost in the ring),
1549 * Rx process gets reset, so we abort any further
1550 * Rx processing.
1551 */
1552 if ((rx_size > (MAX_ETH_FRAME_SIZE+4)) ||
1553 (!(rx_status & RxStatusOK))) {
1554 netdrv_rx_err (rx_status, dev, tp, ioaddr);
1555 return;
1556 }
1557
1558 /* Malloc up new buffer, compatible with net-2e. */
1559 /* Omit the four octet CRC from the length. */
1560
1561 /* TODO: consider allocating skb's outside of
1562 * interrupt context, both to speed interrupt processing,
1563 * and also to reduce the chances of having to
1564 * drop packets here under memory pressure.
1565 */
1566
1567 skb = dev_alloc_skb (pkt_size + 2);
1568 if (skb) {
1569 skb->dev = dev;
1570 skb_reserve (skb, 2); /* 16 byte align the IP fields. */
1571
1572 eth_copy_and_sum (skb, &rx_ring[ring_offset + 4], pkt_size, 0);
1573 skb_put (skb, pkt_size);
1574
1575 skb->protocol = eth_type_trans (skb, dev);
1576 netif_rx (skb);
1577 dev->last_rx = jiffies;
1578 tp->stats.rx_bytes += pkt_size;
1579 tp->stats.rx_packets++;
1580 } else {
1581 printk (KERN_WARNING
1582 "%s: Memory squeeze, dropping packet.\n",
1583 dev->name);
1584 tp->stats.rx_dropped++;
1585 }
1586
1587 cur_rx = (cur_rx + rx_size + 4 + 3) & ~3;
1588 NETDRV_W16_F (RxBufPtr, cur_rx - 16);
1589 }
1590
1591 DPRINTK ("%s: Done netdrv_rx(), current %4.4x BufAddr %4.4x,"
1592 " free to %4.4x, Cmd %2.2x.\n", dev->name, cur_rx,
1593 NETDRV_R16 (RxBufAddr),
1594 NETDRV_R16 (RxBufPtr), NETDRV_R8 (ChipCmd));
1595
1596 tp->cur_rx = cur_rx;
1597 }
1598
1599
1600 static void netdrv_weird_interrupt (struct net_device *dev,
1601 struct netdrv_private *tp,
1602 void *ioaddr,
1603 int status, int link_changed)
1604 {
1605 printk (KERN_DEBUG "%s: Abnormal interrupt, status %8.8x.\n",
1606 dev->name, status);
1607
1608 assert (dev != NULL);
1609 assert (tp != NULL);
1610 assert (ioaddr != NULL);
1611
1612 /* Update the error count. */
1613 tp->stats.rx_missed_errors += NETDRV_R32 (RxMissed);
1614 NETDRV_W32 (RxMissed, 0);
1615
1616 if ((status & RxUnderrun) && link_changed &&
1617 (tp->drv_flags & HAS_LNK_CHNG)) {
1618 /* Really link-change on new chips. */
1619 int lpar = NETDRV_R16 (NWayLPAR);
1620 int duplex = (lpar & 0x0100) || (lpar & 0x01C0) == 0x0040
1621 || tp->duplex_lock;
1622 if (tp->full_duplex != duplex) {
1623 tp->full_duplex = duplex;
1624 NETDRV_W8 (Cfg9346, Cfg9346_Unlock);
1625 NETDRV_W8 (Config1, tp->full_duplex ? 0x60 : 0x20);
1626 NETDRV_W8 (Cfg9346, Cfg9346_Lock);
1627 }
1628 status &= ~RxUnderrun;
1629 }
1630
1631 /* XXX along with netdrv_rx_err, are we double-counting errors? */
1632 if (status &
1633 (RxUnderrun | RxOverflow | RxErr | RxFIFOOver))
1634 tp->stats.rx_errors++;
1635
1636 if (status & (PCSTimeout))
1637 tp->stats.rx_length_errors++;
1638 if (status & (RxUnderrun | RxFIFOOver))
1639 tp->stats.rx_fifo_errors++;
1640 if (status & RxOverflow) {
1641 tp->stats.rx_over_errors++;
1642 tp->cur_rx = NETDRV_R16 (RxBufAddr) % RX_BUF_LEN;
1643 NETDRV_W16_F (RxBufPtr, tp->cur_rx - 16);
1644 }
1645 if (status & PCIErr) {
1646 u16 pci_cmd_status;
1647 pci_read_config_word (tp->pci_dev, PCI_STATUS, &pci_cmd_status);
1648
1649 printk (KERN_ERR "%s: PCI Bus error %4.4x.\n",
1650 dev->name, pci_cmd_status);
1651 }
1652 }
1653
1654
1655 /* The interrupt handler does all of the Rx thread work and cleans up
1656 after the Tx thread. */
1657 static irqreturn_t netdrv_interrupt (int irq, void *dev_instance,
1658 struct pt_regs *regs)
1659 {
1660 struct net_device *dev = (struct net_device *) dev_instance;
1661 struct netdrv_private *tp = dev->priv;
1662 int boguscnt = max_interrupt_work;
1663 void *ioaddr = tp->mmio_addr;
1664 int status = 0, link_changed = 0; /* avoid bogus "uninit" warning */
1665 int handled = 0;
1666
1667 spin_lock (&tp->lock);
1668
1669 do {
1670 status = NETDRV_R16 (IntrStatus);
1671
1672 /* h/w no longer present (hotplug?) or major error, bail */
1673 if (status == 0xFFFF)
1674 break;
1675
1676 handled = 1;
1677 /* Acknowledge all of the current interrupt sources ASAP */
1678 NETDRV_W16_F (IntrStatus, status);
1679
1680 DPRINTK ("%s: interrupt status=%#4.4x new intstat=%#4.4x.\n",
1681 dev->name, status,
1682 NETDRV_R16 (IntrStatus));
1683
1684 if ((status &
1685 (PCIErr | PCSTimeout | RxUnderrun | RxOverflow |
1686 RxFIFOOver | TxErr | TxOK | RxErr | RxOK)) == 0)
1687 break;
1688
1689 /* Check uncommon events with one test. */
1690 if (status & (PCIErr | PCSTimeout | RxUnderrun | RxOverflow |
1691 RxFIFOOver | TxErr | RxErr))
1692 netdrv_weird_interrupt (dev, tp, ioaddr,
1693 status, link_changed);
1694
1695 if (status & (RxOK | RxUnderrun | RxOverflow | RxFIFOOver)) /* Rx interrupt */
1696 netdrv_rx_interrupt (dev, tp, ioaddr);
1697
1698 if (status & (TxOK | TxErr))
1699 netdrv_tx_interrupt (dev, tp, ioaddr);
1700
1701 boguscnt--;
1702 } while (boguscnt > 0);
1703
1704 if (boguscnt <= 0) {
1705 printk (KERN_WARNING
1706 "%s: Too much work at interrupt, "
1707 "IntrStatus=0x%4.4x.\n", dev->name,
1708 status);
1709
1710 /* Clear all interrupt sources. */
1711 NETDRV_W16 (IntrStatus, 0xffff);
1712 }
1713
1714 spin_unlock (&tp->lock);
1715
1716 DPRINTK ("%s: exiting interrupt, intr_status=%#4.4x.\n",
1717 dev->name, NETDRV_R16 (IntrStatus));
1718 return IRQ_RETVAL(handled);
1719 }
1720
1721
1722 static int netdrv_close (struct net_device *dev)
1723 {
1724 struct netdrv_private *tp = dev->priv;
1725 void *ioaddr = tp->mmio_addr;
1726 unsigned long flags;
1727
1728 DPRINTK ("ENTER\n");
1729
1730 netif_stop_queue (dev);
1731
1732 DPRINTK ("%s: Shutting down ethercard, status was 0x%4.4x.\n",
1733 dev->name, NETDRV_R16 (IntrStatus));
1734
1735 del_timer_sync (&tp->timer);
1736
1737 spin_lock_irqsave (&tp->lock, flags);
1738
1739 /* Stop the chip's Tx and Rx DMA processes. */
1740 NETDRV_W8 (ChipCmd, (NETDRV_R8 (ChipCmd) & ChipCmdClear));
1741
1742 /* Disable interrupts by clearing the interrupt mask. */
1743 NETDRV_W16 (IntrMask, 0x0000);
1744
1745 /* Update the error counts. */
1746 tp->stats.rx_missed_errors += NETDRV_R32 (RxMissed);
1747 NETDRV_W32 (RxMissed, 0);
1748
1749 spin_unlock_irqrestore (&tp->lock, flags);
1750
1751 synchronize_irq ();
1752 free_irq (dev->irq, dev);
1753
1754 netdrv_tx_clear (tp);
1755
1756 pci_free_consistent(tp->pci_dev, RX_BUF_TOT_LEN,
1757 tp->rx_ring, tp->rx_ring_dma);
1758 pci_free_consistent(tp->pci_dev, TX_BUF_TOT_LEN,
1759 tp->tx_bufs, tp->tx_bufs_dma);
1760 tp->rx_ring = NULL;
1761 tp->tx_bufs = NULL;
1762
1763 /* Green! Put the chip in low-power mode. */
1764 NETDRV_W8 (Cfg9346, Cfg9346_Unlock);
1765 NETDRV_W8 (Config1, 0x03);
1766 NETDRV_W8 (Cfg9346, Cfg9346_Lock);
1767
1768 DPRINTK ("EXIT\n");
1769 return 0;
1770 }
1771
1772
1773 static int netdrv_ioctl (struct net_device *dev, struct ifreq *rq, int cmd)
1774 {
1775 struct netdrv_private *tp = dev->priv;
1776 struct mii_ioctl_data *data = if_mii(rq);
1777 unsigned long flags;
1778 int rc = 0;
1779
1780 DPRINTK ("ENTER\n");
1781
1782 switch (cmd) {
1783 case SIOCGMIIPHY: /* Get address of MII PHY in use. */
1784 data->phy_id = tp->phys[0] & 0x3f;
1785 /* Fall Through */
1786
1787 case SIOCGMIIREG: /* Read MII PHY register. */
1788 spin_lock_irqsave (&tp->lock, flags);
1789 data->val_out = mdio_read (dev, data->phy_id & 0x1f, data->reg_num & 0x1f);
1790 spin_unlock_irqrestore (&tp->lock, flags);
1791 break;
1792
1793 case SIOCSMIIREG: /* Write MII PHY register. */
1794 if (!capable (CAP_NET_ADMIN)) {
1795 rc = -EPERM;
1796 break;
1797 }
1798
1799 spin_lock_irqsave (&tp->lock, flags);
1800 mdio_write (dev, data->phy_id & 0x1f, data->reg_num & 0x1f, data->val_in);
1801 spin_unlock_irqrestore (&tp->lock, flags);
1802 break;
1803
1804 default:
1805 rc = -EOPNOTSUPP;
1806 break;
1807 }
1808
1809 DPRINTK ("EXIT, returning %d\n", rc);
1810 return rc;
1811 }
1812
1813
1814 static struct net_device_stats *netdrv_get_stats (struct net_device *dev)
1815 {
1816 struct netdrv_private *tp = dev->priv;
1817 void *ioaddr = tp->mmio_addr;
1818
1819 DPRINTK ("ENTER\n");
1820
1821 assert (tp != NULL);
1822
1823 if (netif_running(dev)) {
1824 unsigned long flags;
1825
1826 spin_lock_irqsave (&tp->lock, flags);
1827
1828 tp->stats.rx_missed_errors += NETDRV_R32 (RxMissed);
1829 NETDRV_W32 (RxMissed, 0);
1830
1831 spin_unlock_irqrestore (&tp->lock, flags);
1832 }
1833
1834 DPRINTK ("EXIT\n");
1835 return &tp->stats;
1836 }
1837
1838 /* Set or clear the multicast filter for this adaptor.
1839 This routine is not state sensitive and need not be SMP locked. */
1840
1841 static void netdrv_set_rx_mode (struct net_device *dev)
1842 {
1843 struct netdrv_private *tp = dev->priv;
1844 void *ioaddr = tp->mmio_addr;
1845 u32 mc_filter[2]; /* Multicast hash filter */
1846 int i, rx_mode;
1847 u32 tmp;
1848
1849 DPRINTK ("ENTER\n");
1850
1851 DPRINTK ("%s: netdrv_set_rx_mode(%4.4x) done -- Rx config %8.8x.\n",
1852 dev->name, dev->flags, NETDRV_R32 (RxConfig));
1853
1854 /* Note: do not reorder, GCC is clever about common statements. */
1855 if (dev->flags & IFF_PROMISC) {
1856 /* Unconditionally log net taps. */
1857 printk (KERN_NOTICE "%s: Promiscuous mode enabled.\n",
1858 dev->name);
1859 rx_mode =
1860 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
1861 AcceptAllPhys;
1862 mc_filter[1] = mc_filter[0] = 0xffffffff;
1863 } else if ((dev->mc_count > multicast_filter_limit)
1864 || (dev->flags & IFF_ALLMULTI)) {
1865 /* Too many to filter perfectly -- accept all multicasts. */
1866 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
1867 mc_filter[1] = mc_filter[0] = 0xffffffff;
1868 } else {
1869 struct dev_mc_list *mclist;
1870 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
1871 mc_filter[1] = mc_filter[0] = 0;
1872 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
1873 i++, mclist = mclist->next) {
1874 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
1875
1876 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
1877 }
1878 }
1879
1880 /* if called from irq handler, lock already acquired */
1881 if (!in_irq ())
1882 spin_lock_irq (&tp->lock);
1883
1884 /* We can safely update without stopping the chip. */
1885 tmp = netdrv_rx_config | rx_mode |
1886 (NETDRV_R32 (RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
1887 NETDRV_W32_F (RxConfig, tmp);
1888 NETDRV_W32_F (MAR0 + 0, mc_filter[0]);
1889 NETDRV_W32_F (MAR0 + 4, mc_filter[1]);
1890
1891 if (!in_irq ())
1892 spin_unlock_irq (&tp->lock);
1893
1894 DPRINTK ("EXIT\n");
1895 }
1896
1897
1898 #ifdef CONFIG_PM
1899
1900 static int netdrv_suspend (struct pci_dev *pdev, pm_message_t state)
1901 {
1902 struct net_device *dev = pci_get_drvdata (pdev);
1903 struct netdrv_private *tp = dev->priv;
1904 void *ioaddr = tp->mmio_addr;
1905 unsigned long flags;
1906
1907 if (!netif_running(dev))
1908 return 0;
1909 netif_device_detach (dev);
1910
1911 spin_lock_irqsave (&tp->lock, flags);
1912
1913 /* Disable interrupts, stop Tx and Rx. */
1914 NETDRV_W16 (IntrMask, 0x0000);
1915 NETDRV_W8 (ChipCmd, (NETDRV_R8 (ChipCmd) & ChipCmdClear));
1916
1917 /* Update the error counts. */
1918 tp->stats.rx_missed_errors += NETDRV_R32 (RxMissed);
1919 NETDRV_W32 (RxMissed, 0);
1920
1921 spin_unlock_irqrestore (&tp->lock, flags);
1922
1923 pci_save_state (pdev);
1924 pci_set_power_state (pdev, PCI_D3hot);
1925
1926 return 0;
1927 }
1928
1929
1930 static int netdrv_resume (struct pci_dev *pdev)
1931 {
1932 struct net_device *dev = pci_get_drvdata (pdev);
1933 struct netdrv_private *tp = dev->priv;
1934
1935 if (!netif_running(dev))
1936 return 0;
1937 pci_set_power_state (pdev, PCI_D0);
1938 pci_restore_state (pdev);
1939 netif_device_attach (dev);
1940 netdrv_hw_start (dev);
1941
1942 return 0;
1943 }
1944
1945 #endif /* CONFIG_PM */
1946
1947
1948 static struct pci_driver netdrv_pci_driver = {
1949 .name = MODNAME,
1950 .id_table = netdrv_pci_tbl,
1951 .probe = netdrv_init_one,
1952 .remove = __devexit_p(netdrv_remove_one),
1953 #ifdef CONFIG_PM
1954 .suspend = netdrv_suspend,
1955 .resume = netdrv_resume,
1956 #endif /* CONFIG_PM */
1957 };
1958
1959
1960 static int __init netdrv_init_module (void)
1961 {
1962 /* when a module, this is printed whether or not devices are found in probe */
1963 #ifdef MODULE
1964 printk(version);
1965 #endif
1966 return pci_module_init (&netdrv_pci_driver);
1967 }
1968
1969
1970 static void __exit netdrv_cleanup_module (void)
1971 {
1972 pci_unregister_driver (&netdrv_pci_driver);
1973 }
1974
1975
1976 module_init(netdrv_init_module);
1977 module_exit(netdrv_cleanup_module);
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