[TG3]: Set minimal hw interrupt mitigation.
[linux-2.6/verdex.git] / drivers / net / skfp / h / skfbiinc.h
blob79d55ad2cd2a7818d85fec6ad2fc5f5f6253a391
1 /******************************************************************************
3 * (C)Copyright 1998,1999 SysKonnect,
4 * a business unit of Schneider & Koch & Co. Datensysteme GmbH.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * The information in this file is provided "AS IS" without warranty.
13 ******************************************************************************/
15 #ifndef _SKFBIINC_
16 #define _SKFBIINC_
18 #include "h/supern_2.h"
21 * special defines for use into .asm files
23 #define ERR_FLAGS (FS_MSRABT | FS_SEAC2 | FS_SFRMERR | FS_SFRMTY1)
25 #ifdef ISA
26 #define DMA_BUSY_CHECK CSRA
27 #define IMASK_FAST (IS_PLINT1 | IS_PLINT2 | IS_TIMINT)
28 #define HRQR (RQAA+(RQ_RRQ<<1))
29 #define HRQW (RQAA+(RQ_WA2<<1))
30 #define HRQA0 (RQAA+(RQ_WA0<<1))
31 #define HRQSQ (RQAA+(RQ_WSQ<<1))
32 #endif
34 #ifdef EISA
35 #define DMA_BUSY_CHECK CSRA
36 #define DMA_HIGH_WORD 0x0400
37 #define DMA_MASK_M 0x0a
38 #define DMA_MODE_M 0x0b
39 #define DMA_BYTE_PTR_M 0x0c
40 #define DMA_MASK_S 0x0d4
41 #define DMA_MODE_S 0x0d6
42 #define DMA_BYTE_PTR_S 0x0d8
43 #define IMASK_FAST (IS_PLINT1 | IS_PLINT2 | IS_TIMINT | IS_TC)
44 #endif /* EISA */
46 #ifdef MCA
47 #define IMASK_FAST (IS_PLINT1 | IS_PLINT2 | IS_TIMINT | IS_TOKEN | \
48 IS_CHCK_L | IS_BUSERR)
49 #endif
51 #ifdef PCI
52 #define IMASK_FAST (IS_PLINT1 | IS_PLINT2 | IS_TIMINT | IS_TOKEN | \
53 IS_MINTR2 | IS_MINTR3 | IS_R1_P | \
54 IS_R1_C | IS_XA_C | IS_XS_C)
55 #endif
57 #ifdef PCI
58 #define ISR_MASK (IS_MINTR1 | IS_R1_F | IS_XS_F| IS_XA_F | IMASK_FAST)
59 #else
60 #define ISR_MASK (IS_MINTR1 | IS_MINTR2 | IMASK_FAST)
61 #endif
63 #define FMA_FM_CMDREG1 FMA(FM_CMDREG1)
64 #define FMA_FM_CMDREG2 FMA(FM_CMDREG2)
65 #define FMA_FM_STMCHN FMA(FM_STMCHN)
66 #define FMA_FM_RPR FMA(FM_RPR)
67 #define FMA_FM_WPXA0 FMA(FM_WPXA0)
68 #define FMA_FM_WPXA2 FMA(FM_WPXA2)
69 #define FMA_FM_MARR FMA(FM_MARR)
70 #define FMA_FM_MARW FMA(FM_MARW)
71 #define FMA_FM_MDRU FMA(FM_MDRU)
72 #define FMA_FM_MDRL FMA(FM_MDRL)
73 #define FMA_ST1L FMA(FM_ST1L)
74 #define FMA_ST1U FMA(FM_ST1U)
75 #define FMA_ST2L FMA(FM_ST2L)
76 #define FMA_ST2U FMA(FM_ST2U)
77 #ifdef SUPERNET_3
78 #define FMA_ST3L FMA(FM_ST3L)
79 #define FMA_ST3U FMA(FM_ST3U)
80 #endif
82 #define TMODE_RRQ RQ_RRQ
83 #define TMODE_WAQ2 RQ_WA2
84 #define HSRA HSR(0)
87 #define FMA_FM_ST1L FMA_ST1L
88 #define FMA_FM_ST1U FMA_ST1U
89 #define FMA_FM_ST2L FMA_ST2L
90 #define FMA_FM_ST2U FMA_ST2U
91 #ifdef SUPERNET_3
92 #define FMA_FM_ST3L FMA_ST3L
93 #define FMA_FM_ST3U FMA_ST3U
94 #endif
96 #define FMA_FM_SWPR FMA(FM_SWPR)
98 #define FMA_FM_RPXA0 FMA(FM_RPXA0)
100 #define FMA_FM_RPXS FMA(FM_RPXS)
101 #define FMA_FM_WPXS FMA(FM_WPXS)
103 #define FMA_FM_IMSK1U FMA(FM_IMSK1U)
104 #define FMA_FM_IMSK1L FMA(FM_IMSK1L)
106 #define FMA_FM_EAS FMA(FM_EAS)
107 #define FMA_FM_EAA0 FMA(FM_EAA0)
109 #define TMODE_WAQ0 RQ_WA0
110 #define TMODE_WSQ RQ_WSQ
112 /* Define default for DRV_PCM_STATE_CHANGE */
113 #ifndef DRV_PCM_STATE_CHANGE
114 #define DRV_PCM_STATE_CHANGE(smc,plc,p_state) /* nothing */
115 #endif
117 /* Define default for DRV_RMT_INDICATION */
118 #ifndef DRV_RMT_INDICATION
119 #define DRV_RMT_INDICATION(smc,i) /* nothing */
120 #endif
122 #endif /* n_SKFBIINC_ */