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[TG3]: Set minimal hw interrupt mitigation.
[linux-2.6/verdex.git] / drivers / net / skfp / hwmtm.c
blob18d429021edbbbe188b1dee75b79806804987a7f
1 /******************************************************************************
2 *
3 * (C)Copyright 1998,1999 SysKonnect,
4 * a business unit of Schneider & Koch & Co. Datensysteme GmbH.
5 *
6 * See the file "skfddi.c" for further information.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * The information in this file is provided "AS IS" without warranty.
14 *
15 ******************************************************************************/
16
17 #ifndef lint
18 static char const ID_sccs[] = "@(#)hwmtm.c 1.40 99/05/31 (C) SK" ;
19 #endif
20
21 #define HWMTM
22
23 #ifndef FDDI
24 #define FDDI
25 #endif
26
27 #include "h/types.h"
28 #include "h/fddi.h"
29 #include "h/smc.h"
30 #include "h/supern_2.h"
31 #include "h/skfbiinc.h"
32
33 /*
34 -------------------------------------------------------------
35 DOCUMENTATION
36 -------------------------------------------------------------
37 BEGIN_MANUAL_ENTRY(DOCUMENTATION)
38
39 T B D
40
41 END_MANUAL_ENTRY
42 */
43 /*
44 -------------------------------------------------------------
45 LOCAL VARIABLES:
46 -------------------------------------------------------------
47 */
48 #ifdef COMMON_MB_POOL
49 static SMbuf *mb_start = 0 ;
50 static SMbuf *mb_free = 0 ;
51 static int mb_init = FALSE ;
52 static int call_count = 0 ;
53 #endif
54
55 /*
56 -------------------------------------------------------------
57 EXTERNE VARIABLES:
58 -------------------------------------------------------------
59 */
60
61 #ifdef DEBUG
62 #ifndef DEBUG_BRD
63 extern struct smt_debug debug ;
64 #endif
65 #endif
66
67 #ifdef NDIS_OS2
68 extern u_char offDepth ;
69 extern u_char force_irq_pending ;
70 #endif
71
72 /*
73 -------------------------------------------------------------
74 LOCAL FUNCTIONS:
75 -------------------------------------------------------------
76 */
77
78 static void queue_llc_rx(struct s_smc *smc, SMbuf *mb);
79 static void smt_to_llc(struct s_smc *smc, SMbuf *mb);
80 static void init_txd_ring(struct s_smc *smc);
81 static void init_rxd_ring(struct s_smc *smc);
82 static void queue_txd_mb(struct s_smc *smc, SMbuf *mb);
83 static u_long init_descr_ring(struct s_smc *smc, union s_fp_descr volatile *start,
84 int count);
85 static u_long repair_txd_ring(struct s_smc *smc, struct s_smt_tx_queue *queue);
86 static u_long repair_rxd_ring(struct s_smc *smc, struct s_smt_rx_queue *queue);
87 static SMbuf* get_llc_rx(struct s_smc *smc);
88 static SMbuf* get_txd_mb(struct s_smc *smc);
89
90 /*
91 -------------------------------------------------------------
92 EXTERNAL FUNCTIONS:
93 -------------------------------------------------------------
94 */
95 /* The external SMT functions are listed in cmtdef.h */
96
97 extern void* mac_drv_get_space(struct s_smc *smc, unsigned int size);
98 extern void* mac_drv_get_desc_mem(struct s_smc *smc, unsigned int size);
99 extern void init_board(struct s_smc *smc, u_char *mac_addr);
100 extern void mac_drv_fill_rxd(struct s_smc *smc);
101 extern void plc1_irq(struct s_smc *smc);
102 extern void mac_drv_tx_complete(struct s_smc *smc,
103 volatile struct s_smt_fp_txd *txd);
104 extern void plc2_irq(struct s_smc *smc);
105 extern void mac1_irq(struct s_smc *smc, u_short stu, u_short stl);
106 extern void mac2_irq(struct s_smc *smc, u_short code_s2u, u_short code_s2l);
107 extern void mac3_irq(struct s_smc *smc, u_short code_s3u, u_short code_s3l);
108 extern void timer_irq(struct s_smc *smc);
109 extern void mac_drv_rx_complete(struct s_smc *smc,
110 volatile struct s_smt_fp_rxd *rxd,
111 int frag_count, int len);
112 extern void mac_drv_requeue_rxd(struct s_smc *smc,
113 volatile struct s_smt_fp_rxd *rxd,
114 int frag_count);
115 extern void init_plc(struct s_smc *smc);
116 extern void mac_drv_clear_rxd(struct s_smc *smc,
117 volatile struct s_smt_fp_rxd *rxd, int frag_count);
118
119 #ifdef USE_OS_CPY
120 extern void hwm_cpy_rxd2mb(void);
121 extern void hwm_cpy_txd2mb(void);
122 #endif
123
124 #ifdef ALL_RX_COMPLETE
125 extern void mac_drv_all_receives_complete(void);
126 #endif
127
128 extern u_long mac_drv_virt2phys(struct s_smc *smc, void *virt);
129 extern u_long dma_master(struct s_smc *smc, void *virt, int len, int flag);
130
131 #ifdef NDIS_OS2
132 extern void post_proc(void);
133 #else
134 extern void dma_complete(struct s_smc *smc, volatile union s_fp_descr *descr,
135 int flag);
136 #endif
137
138 extern int init_fplus(struct s_smc *smc);
139 extern int mac_drv_rx_init(struct s_smc *smc, int len, int fc, char *look_ahead,
140 int la_len);
141
142 /*
143 -------------------------------------------------------------
144 PUBLIC FUNCTIONS:
145 -------------------------------------------------------------
146 */
147 void process_receive(struct s_smc *smc);
148 void fddi_isr(struct s_smc *smc);
149 void mac_drv_clear_txd(struct s_smc *smc);
150 void smt_free_mbuf(struct s_smc *smc, SMbuf *mb);
151 void init_driver_fplus(struct s_smc *smc);
152 void mac_drv_rx_mode(struct s_smc *smc, int mode);
153 void init_fddi_driver(struct s_smc *smc, u_char *mac_addr);
154 void mac_drv_clear_tx_queue(struct s_smc *smc);
155 void mac_drv_clear_rx_queue(struct s_smc *smc);
156 void hwm_tx_frag(struct s_smc *smc, char far *virt, u_long phys, int len,
157 int frame_status);
158 void hwm_rx_frag(struct s_smc *smc, char far *virt, u_long phys, int len,
159 int frame_status);
160
161 int mac_drv_rx_frag(struct s_smc *smc, void far *virt, int len);
162 int mac_drv_init(struct s_smc *smc);
163 int hwm_tx_init(struct s_smc *smc, u_char fc, int frag_count, int frame_len,
164 int frame_status);
165
166 u_int mac_drv_check_space(void);
167
168 SMbuf* smt_get_mbuf(struct s_smc *smc);
169
170 #ifdef DEBUG
171 void mac_drv_debug_lev(void);
172 #endif
173
174 /*
175 -------------------------------------------------------------
176 MACROS:
177 -------------------------------------------------------------
178 */
179 #ifndef UNUSED
180 #ifdef lint
181 #define UNUSED(x) (x) = (x)
182 #else
183 #define UNUSED(x)
184 #endif
185 #endif
186
187 #ifdef USE_CAN_ADDR
188 #define MA smc->hw.fddi_canon_addr.a
189 #define GROUP_ADDR_BIT 0x01
190 #else
191 #define MA smc->hw.fddi_home_addr.a
192 #define GROUP_ADDR_BIT 0x80
193 #endif
194
195 #define RXD_TXD_COUNT (HWM_ASYNC_TXD_COUNT+HWM_SYNC_TXD_COUNT+\
196 SMT_R1_RXD_COUNT+SMT_R2_RXD_COUNT)
197
198 #ifdef MB_OUTSIDE_SMC
199 #define EXT_VIRT_MEM ((RXD_TXD_COUNT+1)*sizeof(struct s_smt_fp_txd) +\
200 MAX_MBUF*sizeof(SMbuf))
201 #define EXT_VIRT_MEM_2 ((RXD_TXD_COUNT+1)*sizeof(struct s_smt_fp_txd))
202 #else
203 #define EXT_VIRT_MEM ((RXD_TXD_COUNT+1)*sizeof(struct s_smt_fp_txd))
204 #endif
205
206 /*
207 * define critical read for 16 Bit drivers
208 */
209 #if defined(NDIS_OS2) || defined(ODI2)
210 #define CR_READ(var) ((var) & 0xffff0000 | ((var) & 0xffff))
211 #else
212 #define CR_READ(var) (u_long)(var)
213 #endif
214
215 #define IMASK_SLOW (IS_PLINT1 | IS_PLINT2 | IS_TIMINT | IS_TOKEN | \
216 IS_MINTR1 | IS_MINTR2 | IS_MINTR3 | IS_R1_P | \
217 IS_R1_C | IS_XA_C | IS_XS_C)
218
219 /*
220 -------------------------------------------------------------
221 INIT- AND SMT FUNCTIONS:
222 -------------------------------------------------------------
223 */
224
225
226 /*
227 * BEGIN_MANUAL_ENTRY(mac_drv_check_space)
228 * u_int mac_drv_check_space()
229 *
230 * function DOWNCALL (drvsr.c)
231 * This function calculates the needed non virtual
232 * memory for MBufs, RxD and TxD descriptors etc.
233 * needed by the driver.
234 *
235 * return u_int memory in bytes
236 *
237 * END_MANUAL_ENTRY
238 */
239 u_int mac_drv_check_space(void)
240 {
241 #ifdef MB_OUTSIDE_SMC
242 #ifdef COMMON_MB_POOL
243 call_count++ ;
244 if (call_count == 1) {
245 return(EXT_VIRT_MEM) ;
246 }
247 else {
248 return(EXT_VIRT_MEM_2) ;
249 }
250 #else
251 return (EXT_VIRT_MEM) ;
252 #endif
253 #else
254 return (0) ;
255 #endif
256 }
257
258 /*
259 * BEGIN_MANUAL_ENTRY(mac_drv_init)
260 * void mac_drv_init(smc)
261 *
262 * function DOWNCALL (drvsr.c)
263 * In this function the hardware module allocates it's
264 * memory.
265 * The operating system dependent module should call
266 * mac_drv_init once, after the adatper is detected.
267 * END_MANUAL_ENTRY
268 */
269 int mac_drv_init(struct s_smc *smc)
270 {
271 if (sizeof(struct s_smt_fp_rxd) % 16) {
272 SMT_PANIC(smc,HWM_E0001,HWM_E0001_MSG) ;
273 }
274 if (sizeof(struct s_smt_fp_txd) % 16) {
275 SMT_PANIC(smc,HWM_E0002,HWM_E0002_MSG) ;
276 }
277
278 /*
279 * get the required memory for the RxDs and TxDs
280 */
281 if (!(smc->os.hwm.descr_p = (union s_fp_descr volatile *)
282 mac_drv_get_desc_mem(smc,(u_int)
283 (RXD_TXD_COUNT+1)*sizeof(struct s_smt_fp_txd)))) {
284 return(1) ; /* no space the hwm modul can't work */
285 }
286
287 /*
288 * get the memory for the SMT MBufs
289 */
290 #ifndef MB_OUTSIDE_SMC
291 smc->os.hwm.mbuf_pool.mb_start=(SMbuf *)(&smc->os.hwm.mbuf_pool.mb[0]) ;
292 #else
293 #ifndef COMMON_MB_POOL
294 if (!(smc->os.hwm.mbuf_pool.mb_start = (SMbuf *) mac_drv_get_space(smc,
295 MAX_MBUF*sizeof(SMbuf)))) {
296 return(1) ; /* no space the hwm modul can't work */
297 }
298 #else
299 if (!mb_start) {
300 if (!(mb_start = (SMbuf *) mac_drv_get_space(smc,
301 MAX_MBUF*sizeof(SMbuf)))) {
302 return(1) ; /* no space the hwm modul can't work */
303 }
304 }
305 #endif
306 #endif
307 return (0) ;
308 }
309
310 /*
311 * BEGIN_MANUAL_ENTRY(init_driver_fplus)
312 * init_driver_fplus(smc)
313 *
314 * Sets hardware modul specific values for the mode register 2
315 * (e.g. the byte alignment for the received frames, the position of the
316 * least significant byte etc.)
317 * END_MANUAL_ENTRY
318 */
319 void init_driver_fplus(struct s_smc *smc)
320 {
321 smc->hw.fp.mdr2init = FM_LSB | FM_BMMODE | FM_ENNPRQ | FM_ENHSRQ | 3 ;
322
323 #ifdef PCI
324 smc->hw.fp.mdr2init |= FM_CHKPAR | FM_PARITY ;
325 #endif
326 smc->hw.fp.mdr3init = FM_MENRQAUNLCK | FM_MENRS ;
327
328 #ifdef USE_CAN_ADDR
329 /* enable address bit swapping */
330 smc->hw.fp.frselreg_init = FM_ENXMTADSWAP | FM_ENRCVADSWAP ;
331 #endif
332 }
333
334 static u_long init_descr_ring(struct s_smc *smc,
335 union s_fp_descr volatile *start,
336 int count)
337 {
338 int i ;
339 union s_fp_descr volatile *d1 ;
340 union s_fp_descr volatile *d2 ;
341 u_long phys ;
342
343 DB_GEN("descr ring starts at = %x ",(void *)start,0,3) ;
344 for (i=count-1, d1=start; i ; i--) {
345 d2 = d1 ;
346 d1++ ; /* descr is owned by the host */
347 d2->r.rxd_rbctrl = AIX_REVERSE(BMU_CHECK) ;
348 d2->r.rxd_next = &d1->r ;
349 phys = mac_drv_virt2phys(smc,(void *)d1) ;
350 d2->r.rxd_nrdadr = AIX_REVERSE(phys) ;
351 }
352 DB_GEN("descr ring ends at = %x ",(void *)d1,0,3) ;
353 d1->r.rxd_rbctrl = AIX_REVERSE(BMU_CHECK) ;
354 d1->r.rxd_next = &start->r ;
355 phys = mac_drv_virt2phys(smc,(void *)start) ;
356 d1->r.rxd_nrdadr = AIX_REVERSE(phys) ;
357
358 for (i=count, d1=start; i ; i--) {
359 DRV_BUF_FLUSH(&d1->r,DDI_DMA_SYNC_FORDEV) ;
360 d1++;
361 }
362 return(phys) ;
363 }
364
365 static void init_txd_ring(struct s_smc *smc)
366 {
367 struct s_smt_fp_txd volatile *ds ;
368 struct s_smt_tx_queue *queue ;
369 u_long phys ;
370
371 /*
372 * initialize the transmit descriptors
373 */
374 ds = (struct s_smt_fp_txd volatile *) ((char *)smc->os.hwm.descr_p +
375 SMT_R1_RXD_COUNT*sizeof(struct s_smt_fp_rxd)) ;
376 queue = smc->hw.fp.tx[QUEUE_A0] ;
377 DB_GEN("Init async TxD ring, %d TxDs ",HWM_ASYNC_TXD_COUNT,0,3) ;
378 (void)init_descr_ring(smc,(union s_fp_descr volatile *)ds,
379 HWM_ASYNC_TXD_COUNT) ;
380 phys = AIX_REVERSE(ds->txd_ntdadr) ;
381 ds++ ;
382 queue->tx_curr_put = queue->tx_curr_get = ds ;
383 ds-- ;
384 queue->tx_free = HWM_ASYNC_TXD_COUNT ;
385 queue->tx_used = 0 ;
386 outpd(ADDR(B5_XA_DA),phys) ;
387
388 ds = (struct s_smt_fp_txd volatile *) ((char *)ds +
389 HWM_ASYNC_TXD_COUNT*sizeof(struct s_smt_fp_txd)) ;
390 queue = smc->hw.fp.tx[QUEUE_S] ;
391 DB_GEN("Init sync TxD ring, %d TxDs ",HWM_SYNC_TXD_COUNT,0,3) ;
392 (void)init_descr_ring(smc,(union s_fp_descr volatile *)ds,
393 HWM_SYNC_TXD_COUNT) ;
394 phys = AIX_REVERSE(ds->txd_ntdadr) ;
395 ds++ ;
396 queue->tx_curr_put = queue->tx_curr_get = ds ;
397 queue->tx_free = HWM_SYNC_TXD_COUNT ;
398 queue->tx_used = 0 ;
399 outpd(ADDR(B5_XS_DA),phys) ;
400 }
401
402 static void init_rxd_ring(struct s_smc *smc)
403 {
404 struct s_smt_fp_rxd volatile *ds ;
405 struct s_smt_rx_queue *queue ;
406 u_long phys ;
407
408 /*
409 * initialize the receive descriptors
410 */
411 ds = (struct s_smt_fp_rxd volatile *) smc->os.hwm.descr_p ;
412 queue = smc->hw.fp.rx[QUEUE_R1] ;
413 DB_GEN("Init RxD ring, %d RxDs ",SMT_R1_RXD_COUNT,0,3) ;
414 (void)init_descr_ring(smc,(union s_fp_descr volatile *)ds,
415 SMT_R1_RXD_COUNT) ;
416 phys = AIX_REVERSE(ds->rxd_nrdadr) ;
417 ds++ ;
418 queue->rx_curr_put = queue->rx_curr_get = ds ;
419 queue->rx_free = SMT_R1_RXD_COUNT ;
420 queue->rx_used = 0 ;
421 outpd(ADDR(B4_R1_DA),phys) ;
422 }
423
424 /*
425 * BEGIN_MANUAL_ENTRY(init_fddi_driver)
426 * void init_fddi_driver(smc,mac_addr)
427 *
428 * initializes the driver and it's variables
429 *
430 * END_MANUAL_ENTRY
431 */
432 void init_fddi_driver(struct s_smc *smc, u_char *mac_addr)
433 {
434 SMbuf *mb ;
435 int i ;
436
437 init_board(smc,mac_addr) ;
438 (void)init_fplus(smc) ;
439
440 /*
441 * initialize the SMbufs for the SMT
442 */
443 #ifndef COMMON_MB_POOL
444 mb = smc->os.hwm.mbuf_pool.mb_start ;
445 smc->os.hwm.mbuf_pool.mb_free = (SMbuf *)NULL ;
446 for (i = 0; i < MAX_MBUF; i++) {
447 mb->sm_use_count = 1 ;
448 smt_free_mbuf(smc,mb) ;
449 mb++ ;
450 }
451 #else
452 mb = mb_start ;
453 if (!mb_init) {
454 mb_free = 0 ;
455 for (i = 0; i < MAX_MBUF; i++) {
456 mb->sm_use_count = 1 ;
457 smt_free_mbuf(smc,mb) ;
458 mb++ ;
459 }
460 mb_init = TRUE ;
461 }
462 #endif
463
464 /*
465 * initialize the other variables
466 */
467 smc->os.hwm.llc_rx_pipe = smc->os.hwm.llc_rx_tail = (SMbuf *)NULL ;
468 smc->os.hwm.txd_tx_pipe = smc->os.hwm.txd_tx_tail = NULL ;
469 smc->os.hwm.pass_SMT = smc->os.hwm.pass_NSA = smc->os.hwm.pass_DB = 0 ;
470 smc->os.hwm.pass_llc_promisc = TRUE ;
471 smc->os.hwm.queued_rx_frames = smc->os.hwm.queued_txd_mb = 0 ;
472 smc->os.hwm.detec_count = 0 ;
473 smc->os.hwm.rx_break = 0 ;
474 smc->os.hwm.rx_len_error = 0 ;
475 smc->os.hwm.isr_flag = FALSE ;
476
477 /*
478 * make sure that the start pointer is 16 byte aligned
479 */
480 i = 16 - ((long)smc->os.hwm.descr_p & 0xf) ;
481 if (i != 16) {
482 DB_GEN("i = %d",i,0,3) ;
483 smc->os.hwm.descr_p = (union s_fp_descr volatile *)
484 ((char *)smc->os.hwm.descr_p+i) ;
485 }
486 DB_GEN("pt to descr area = %x",(void *)smc->os.hwm.descr_p,0,3) ;
487
488 init_txd_ring(smc) ;
489 init_rxd_ring(smc) ;
490 mac_drv_fill_rxd(smc) ;
491
492 init_plc(smc) ;
493 }
494
495
496 SMbuf *smt_get_mbuf(struct s_smc *smc)
497 {
498 register SMbuf *mb ;
499
500 #ifndef COMMON_MB_POOL
501 mb = smc->os.hwm.mbuf_pool.mb_free ;
502 #else
503 mb = mb_free ;
504 #endif
505 if (mb) {
506 #ifndef COMMON_MB_POOL
507 smc->os.hwm.mbuf_pool.mb_free = mb->sm_next ;
508 #else
509 mb_free = mb->sm_next ;
510 #endif
511 mb->sm_off = 8 ;
512 mb->sm_use_count = 1 ;
513 }
514 DB_GEN("get SMbuf: mb = %x",(void *)mb,0,3) ;
515 return (mb) ; /* May be NULL */
516 }
517
518 void smt_free_mbuf(struct s_smc *smc, SMbuf *mb)
519 {
520
521 if (mb) {
522 mb->sm_use_count-- ;
523 DB_GEN("free_mbuf: sm_use_count = %d",mb->sm_use_count,0,3) ;
524 /*
525 * If the use_count is != zero the MBuf is queued
526 * more than once and must not queued into the
527 * free MBuf queue
528 */
529 if (!mb->sm_use_count) {
530 DB_GEN("free SMbuf: mb = %x",(void *)mb,0,3) ;
531 #ifndef COMMON_MB_POOL
532 mb->sm_next = smc->os.hwm.mbuf_pool.mb_free ;
533 smc->os.hwm.mbuf_pool.mb_free = mb ;
534 #else
535 mb->sm_next = mb_free ;
536 mb_free = mb ;
537 #endif
538 }
539 }
540 else
541 SMT_PANIC(smc,HWM_E0003,HWM_E0003_MSG) ;
542 }
543
544
545 /*
546 * BEGIN_MANUAL_ENTRY(mac_drv_repair_descr)
547 * void mac_drv_repair_descr(smc)
548 *
549 * function called from SMT (HWM / hwmtm.c)
550 * The BMU is idle when this function is called.
551 * Mac_drv_repair_descr sets up the physical address
552 * for all receive and transmit queues where the BMU
553 * should continue.
554 * It may be that the BMU was reseted during a fragmented
555 * transfer. In this case there are some fragments which will
556 * never completed by the BMU. The OWN bit of this fragments
557 * must be switched to be owned by the host.
558 *
559 * Give a start command to the receive BMU.
560 * Start the transmit BMUs if transmit frames pending.
561 *
562 * END_MANUAL_ENTRY
563 */
564 void mac_drv_repair_descr(struct s_smc *smc)
565 {
566 u_long phys ;
567
568 if (smc->hw.hw_state != STOPPED) {
569 SK_BREAK() ;
570 SMT_PANIC(smc,HWM_E0013,HWM_E0013_MSG) ;
571 return ;
572 }
573
574 /*
575 * repair tx queues: don't start
576 */
577 phys = repair_txd_ring(smc,smc->hw.fp.tx[QUEUE_A0]) ;
578 outpd(ADDR(B5_XA_DA),phys) ;
579 if (smc->hw.fp.tx_q[QUEUE_A0].tx_used) {
580 outpd(ADDR(B0_XA_CSR),CSR_START) ;
581 }
582 phys = repair_txd_ring(smc,smc->hw.fp.tx[QUEUE_S]) ;
583 outpd(ADDR(B5_XS_DA),phys) ;
584 if (smc->hw.fp.tx_q[QUEUE_S].tx_used) {
585 outpd(ADDR(B0_XS_CSR),CSR_START) ;
586 }
587
588 /*
589 * repair rx queues
590 */
591 phys = repair_rxd_ring(smc,smc->hw.fp.rx[QUEUE_R1]) ;
592 outpd(ADDR(B4_R1_DA),phys) ;
593 outpd(ADDR(B0_R1_CSR),CSR_START) ;
594 }
595
596 static u_long repair_txd_ring(struct s_smc *smc, struct s_smt_tx_queue *queue)
597 {
598 int i ;
599 int tx_used ;
600 u_long phys ;
601 u_long tbctrl ;
602 struct s_smt_fp_txd volatile *t ;
603
604 SK_UNUSED(smc) ;
605
606 t = queue->tx_curr_get ;
607 tx_used = queue->tx_used ;
608 for (i = tx_used+queue->tx_free-1 ; i ; i-- ) {
609 t = t->txd_next ;
610 }
611 phys = AIX_REVERSE(t->txd_ntdadr) ;
612
613 t = queue->tx_curr_get ;
614 while (tx_used) {
615 DRV_BUF_FLUSH(t,DDI_DMA_SYNC_FORCPU) ;
616 tbctrl = AIX_REVERSE(t->txd_tbctrl) ;
617
618 if (tbctrl & BMU_OWN) {
619 if (tbctrl & BMU_STF) {
620 break ; /* exit the loop */
621 }
622 else {
623 /*
624 * repair the descriptor
625 */
626 t->txd_tbctrl &= AIX_REVERSE(~BMU_OWN) ;
627 }
628 }
629 phys = AIX_REVERSE(t->txd_ntdadr) ;
630 DRV_BUF_FLUSH(t,DDI_DMA_SYNC_FORDEV) ;
631 t = t->txd_next ;
632 tx_used-- ;
633 }
634 return(phys) ;
635 }
636
637 /*
638 * Repairs the receive descriptor ring and returns the physical address
639 * where the BMU should continue working.
640 *
641 * o The physical address where the BMU was stopped has to be
642 * determined. This is the next RxD after rx_curr_get with an OWN
643 * bit set.
644 * o The BMU should start working at beginning of the next frame.
645 * RxDs with an OWN bit set but with a reset STF bit should be
646 * skipped and owned by the driver (OWN = 0).
647 */
648 static u_long repair_rxd_ring(struct s_smc *smc, struct s_smt_rx_queue *queue)
649 {
650 int i ;
651 int rx_used ;
652 u_long phys ;
653 u_long rbctrl ;
654 struct s_smt_fp_rxd volatile *r ;
655
656 SK_UNUSED(smc) ;
657
658 r = queue->rx_curr_get ;
659 rx_used = queue->rx_used ;
660 for (i = SMT_R1_RXD_COUNT-1 ; i ; i-- ) {
661 r = r->rxd_next ;
662 }
663 phys = AIX_REVERSE(r->rxd_nrdadr) ;
664
665 r = queue->rx_curr_get ;
666 while (rx_used) {
667 DRV_BUF_FLUSH(r,DDI_DMA_SYNC_FORCPU) ;
668 rbctrl = AIX_REVERSE(r->rxd_rbctrl) ;
669
670 if (rbctrl & BMU_OWN) {
671 if (rbctrl & BMU_STF) {
672 break ; /* exit the loop */
673 }
674 else {
675 /*
676 * repair the descriptor
677 */
678 r->rxd_rbctrl &= AIX_REVERSE(~BMU_OWN) ;
679 }
680 }
681 phys = AIX_REVERSE(r->rxd_nrdadr) ;
682 DRV_BUF_FLUSH(r,DDI_DMA_SYNC_FORDEV) ;
683 r = r->rxd_next ;
684 rx_used-- ;
685 }
686 return(phys) ;
687 }
688
689
690 /*
691 -------------------------------------------------------------
692 INTERRUPT SERVICE ROUTINE:
693 -------------------------------------------------------------
694 */
695
696 /*
697 * BEGIN_MANUAL_ENTRY(fddi_isr)
698 * void fddi_isr(smc)
699 *
700 * function DOWNCALL (drvsr.c)
701 * interrupt service routine, handles the interrupt requests
702 * generated by the FDDI adapter.
703 *
704 * NOTE: The operating system dependent module must garantee that the
705 * interrupts of the adapter are disabled when it calls fddi_isr.
706 *
707 * About the USE_BREAK_ISR mechanismn:
708 *
709 * The main requirement of this mechanismn is to force an timer IRQ when
710 * leaving process_receive() with leave_isr set. process_receive() may
711 * be called at any time from anywhere!
712 * To be sure we don't miss such event we set 'force_irq' per default.
713 * We have to force and Timer IRQ if 'smc->os.hwm.leave_isr' AND
714 * 'force_irq' are set. 'force_irq' may be reset if a receive complete
715 * IRQ is pending.
716 *
717 * END_MANUAL_ENTRY
718 */
719 void fddi_isr(struct s_smc *smc)
720 {
721 u_long is ; /* ISR source */
722 u_short stu, stl ;
723 SMbuf *mb ;
724
725 #ifdef USE_BREAK_ISR
726 int force_irq ;
727 #endif
728
729 #ifdef ODI2
730 if (smc->os.hwm.rx_break) {
731 mac_drv_fill_rxd(smc) ;
732 if (smc->hw.fp.rx_q[QUEUE_R1].rx_used > 0) {
733 smc->os.hwm.rx_break = 0 ;
734 process_receive(smc) ;
735 }
736 else {
737 smc->os.hwm.detec_count = 0 ;
738 smt_force_irq(smc) ;
739 }
740 }
741 #endif
742 smc->os.hwm.isr_flag = TRUE ;
743
744 #ifdef USE_BREAK_ISR
745 force_irq = TRUE ;
746 if (smc->os.hwm.leave_isr) {
747 smc->os.hwm.leave_isr = FALSE ;
748 process_receive(smc) ;
749 }
750 #endif
751
752 while ((is = GET_ISR() & ISR_MASK)) {
753 NDD_TRACE("CH0B",is,0,0) ;
754 DB_GEN("ISA = 0x%x",is,0,7) ;
755
756 if (is & IMASK_SLOW) {
757 NDD_TRACE("CH1b",is,0,0) ;
758 if (is & IS_PLINT1) { /* PLC1 */
759 plc1_irq(smc) ;
760 }
761 if (is & IS_PLINT2) { /* PLC2 */
762 plc2_irq(smc) ;
763 }
764 if (is & IS_MINTR1) { /* FORMAC+ STU1(U/L) */
765 stu = inpw(FM_A(FM_ST1U)) ;
766 stl = inpw(FM_A(FM_ST1L)) ;
767 DB_GEN("Slow transmit complete",0,0,6) ;
768 mac1_irq(smc,stu,stl) ;
769 }
770 if (is & IS_MINTR2) { /* FORMAC+ STU2(U/L) */
771 stu= inpw(FM_A(FM_ST2U)) ;
772 stl= inpw(FM_A(FM_ST2L)) ;
773 DB_GEN("Slow receive complete",0,0,6) ;
774 DB_GEN("stl = %x : stu = %x",stl,stu,7) ;
775 mac2_irq(smc,stu,stl) ;
776 }
777 if (is & IS_MINTR3) { /* FORMAC+ STU3(U/L) */
778 stu= inpw(FM_A(FM_ST3U)) ;
779 stl= inpw(FM_A(FM_ST3L)) ;
780 DB_GEN("FORMAC Mode Register 3",0,0,6) ;
781 mac3_irq(smc,stu,stl) ;
782 }
783 if (is & IS_TIMINT) { /* Timer 82C54-2 */
784 timer_irq(smc) ;
785 #ifdef NDIS_OS2
786 force_irq_pending = 0 ;
787 #endif
788 /*
789 * out of RxD detection
790 */
791 if (++smc->os.hwm.detec_count > 4) {
792 /*
793 * check out of RxD condition
794 */
795 process_receive(smc) ;
796 }
797 }
798 if (is & IS_TOKEN) { /* Restricted Token Monitor */
799 rtm_irq(smc) ;
800 }
801 if (is & IS_R1_P) { /* Parity error rx queue 1 */
802 /* clear IRQ */
803 outpd(ADDR(B4_R1_CSR),CSR_IRQ_CL_P) ;
804 SMT_PANIC(smc,HWM_E0004,HWM_E0004_MSG) ;
805 }
806 if (is & IS_R1_C) { /* Encoding error rx queue 1 */
807 /* clear IRQ */
808 outpd(ADDR(B4_R1_CSR),CSR_IRQ_CL_C) ;
809 SMT_PANIC(smc,HWM_E0005,HWM_E0005_MSG) ;
810 }
811 if (is & IS_XA_C) { /* Encoding error async tx q */
812 /* clear IRQ */
813 outpd(ADDR(B5_XA_CSR),CSR_IRQ_CL_C) ;
814 SMT_PANIC(smc,HWM_E0006,HWM_E0006_MSG) ;
815 }
816 if (is & IS_XS_C) { /* Encoding error sync tx q */
817 /* clear IRQ */
818 outpd(ADDR(B5_XS_CSR),CSR_IRQ_CL_C) ;
819 SMT_PANIC(smc,HWM_E0007,HWM_E0007_MSG) ;
820 }
821 }
822
823 /*
824 * Fast Tx complete Async/Sync Queue (BMU service)
825 */
826 if (is & (IS_XS_F|IS_XA_F)) {
827 DB_GEN("Fast tx complete queue",0,0,6) ;
828 /*
829 * clear IRQ, Note: no IRQ is lost, because
830 * we always service both queues
831 */
832 outpd(ADDR(B5_XS_CSR),CSR_IRQ_CL_F) ;
833 outpd(ADDR(B5_XA_CSR),CSR_IRQ_CL_F) ;
834 mac_drv_clear_txd(smc) ;
835 llc_restart_tx(smc) ;
836 }
837
838 /*
839 * Fast Rx Complete (BMU service)
840 */
841 if (is & IS_R1_F) {
842 DB_GEN("Fast receive complete",0,0,6) ;
843 /* clear IRQ */
844 #ifndef USE_BREAK_ISR
845 outpd(ADDR(B4_R1_CSR),CSR_IRQ_CL_F) ;
846 process_receive(smc) ;
847 #else
848 process_receive(smc) ;
849 if (smc->os.hwm.leave_isr) {
850 force_irq = FALSE ;
851 } else {
852 outpd(ADDR(B4_R1_CSR),CSR_IRQ_CL_F) ;
853 process_receive(smc) ;
854 }
855 #endif
856 }
857
858 #ifndef NDIS_OS2
859 while ((mb = get_llc_rx(smc))) {
860 smt_to_llc(smc,mb) ;
861 }
862 #else
863 if (offDepth)
864 post_proc() ;
865
866 while (!offDepth && (mb = get_llc_rx(smc))) {
867 smt_to_llc(smc,mb) ;
868 }
869
870 if (!offDepth && smc->os.hwm.rx_break) {
871 process_receive(smc) ;
872 }
873 #endif
874 if (smc->q.ev_get != smc->q.ev_put) {
875 NDD_TRACE("CH2a",0,0,0) ;
876 ev_dispatcher(smc) ;
877 }
878 #ifdef NDIS_OS2
879 post_proc() ;
880 if (offDepth) { /* leave fddi_isr because */
881 break ; /* indications not allowed */
882 }
883 #endif
884 #ifdef USE_BREAK_ISR
885 if (smc->os.hwm.leave_isr) {
886 break ; /* leave fddi_isr */
887 }
888 #endif
889
890 /* NOTE: when the isr is left, no rx is pending */
891 } /* end of interrupt source polling loop */
892
893 #ifdef USE_BREAK_ISR
894 if (smc->os.hwm.leave_isr && force_irq) {
895 smt_force_irq(smc) ;
896 }
897 #endif
898 smc->os.hwm.isr_flag = FALSE ;
899 NDD_TRACE("CH0E",0,0,0) ;
900 }
901
902
903 /*
904 -------------------------------------------------------------
905 RECEIVE FUNCTIONS:
906 -------------------------------------------------------------
907 */
908
909 #ifndef NDIS_OS2
910 /*
911 * BEGIN_MANUAL_ENTRY(mac_drv_rx_mode)
912 * void mac_drv_rx_mode(smc,mode)
913 *
914 * function DOWNCALL (fplus.c)
915 * Corresponding to the parameter mode, the operating system
916 * dependent module can activate several receive modes.
917 *
918 * para mode = 1: RX_ENABLE_ALLMULTI enable all multicasts
919 * = 2: RX_DISABLE_ALLMULTI disable "enable all multicasts"
920 * = 3: RX_ENABLE_PROMISC enable promiscuous
921 * = 4: RX_DISABLE_PROMISC disable promiscuous
922 * = 5: RX_ENABLE_NSA enable rec. of all NSA frames
923 * (disabled after 'driver reset' & 'set station address')
924 * = 6: RX_DISABLE_NSA disable rec. of all NSA frames
925 *
926 * = 21: RX_ENABLE_PASS_SMT ( see description )
927 * = 22: RX_DISABLE_PASS_SMT ( " " )
928 * = 23: RX_ENABLE_PASS_NSA ( " " )
929 * = 24: RX_DISABLE_PASS_NSA ( " " )
930 * = 25: RX_ENABLE_PASS_DB ( " " )
931 * = 26: RX_DISABLE_PASS_DB ( " " )
932 * = 27: RX_DISABLE_PASS_ALL ( " " )
933 * = 28: RX_DISABLE_LLC_PROMISC ( " " )
934 * = 29: RX_ENABLE_LLC_PROMISC ( " " )
935 *
936 *
937 * RX_ENABLE_PASS_SMT / RX_DISABLE_PASS_SMT
938 *
939 * If the operating system dependent module activates the
940 * mode RX_ENABLE_PASS_SMT, the hardware module
941 * duplicates all SMT frames with the frame control
942 * FC_SMT_INFO and passes them to the LLC receive channel
943 * by calling mac_drv_rx_init.
944 * The SMT Frames which are sent by the local SMT and the NSA
945 * frames whose A- and C-Indicator is not set are also duplicated
946 * and passed.
947 * The receive mode RX_DISABLE_PASS_SMT disables the passing
948 * of SMT frames.
949 *
950 * RX_ENABLE_PASS_NSA / RX_DISABLE_PASS_NSA
951 *
952 * If the operating system dependent module activates the
953 * mode RX_ENABLE_PASS_NSA, the hardware module
954 * duplicates all NSA frames with frame control FC_SMT_NSA
955 * and a set A-Indicator and passed them to the LLC
956 * receive channel by calling mac_drv_rx_init.
957 * All NSA Frames which are sent by the local SMT
958 * are also duplicated and passed.
959 * The receive mode RX_DISABLE_PASS_NSA disables the passing
960 * of NSA frames with the A- or C-Indicator set.
961 *
962 * NOTE: For fear that the hardware module receives NSA frames with
963 * a reset A-Indicator, the operating system dependent module
964 * has to call mac_drv_rx_mode with the mode RX_ENABLE_NSA
965 * before activate the RX_ENABLE_PASS_NSA mode and after every
966 * 'driver reset' and 'set station address'.
967 *
968 * RX_ENABLE_PASS_DB / RX_DISABLE_PASS_DB
969 *
970 * If the operating system dependent module activates the
971 * mode RX_ENABLE_PASS_DB, direct BEACON frames
972 * (FC_BEACON frame control) are passed to the LLC receive
973 * channel by mac_drv_rx_init.
974 * The receive mode RX_DISABLE_PASS_DB disables the passing
975 * of direct BEACON frames.
976 *
977 * RX_DISABLE_PASS_ALL
978 *
979 * Disables all special receives modes. It is equal to
980 * call mac_drv_set_rx_mode successively with the
981 * parameters RX_DISABLE_NSA, RX_DISABLE_PASS_SMT,
982 * RX_DISABLE_PASS_NSA and RX_DISABLE_PASS_DB.
983 *
984 * RX_ENABLE_LLC_PROMISC
985 *
986 * (default) all received LLC frames and all SMT/NSA/DBEACON
987 * frames depending on the attitude of the flags
988 * PASS_SMT/PASS_NSA/PASS_DBEACON will be delivered to the
989 * LLC layer
990 *
991 * RX_DISABLE_LLC_PROMISC
992 *
993 * all received SMT/NSA/DBEACON frames depending on the
994 * attitude of the flags PASS_SMT/PASS_NSA/PASS_DBEACON
995 * will be delivered to the LLC layer.
996 * all received LLC frames with a directed address, Multicast
997 * or Broadcast address will be delivered to the LLC
998 * layer too.
999 *
1000 * END_MANUAL_ENTRY
1001 */
1002 void mac_drv_rx_mode(struct s_smc *smc, int mode)
1003 {
1004 switch(mode) {
1005 case RX_ENABLE_PASS_SMT:
1006 smc->os.hwm.pass_SMT = TRUE ;
1007 break ;
1008 case RX_DISABLE_PASS_SMT:
1009 smc->os.hwm.pass_SMT = FALSE ;
1010 break ;
1011 case RX_ENABLE_PASS_NSA:
1012 smc->os.hwm.pass_NSA = TRUE ;
1013 break ;
1014 case RX_DISABLE_PASS_NSA:
1015 smc->os.hwm.pass_NSA = FALSE ;
1016 break ;
1017 case RX_ENABLE_PASS_DB:
1018 smc->os.hwm.pass_DB = TRUE ;
1019 break ;
1020 case RX_DISABLE_PASS_DB:
1021 smc->os.hwm.pass_DB = FALSE ;
1022 break ;
1023 case RX_DISABLE_PASS_ALL:
1024 smc->os.hwm.pass_SMT = smc->os.hwm.pass_NSA = FALSE ;
1025 smc->os.hwm.pass_DB = FALSE ;
1026 smc->os.hwm.pass_llc_promisc = TRUE ;
1027 mac_set_rx_mode(smc,RX_DISABLE_NSA) ;
1028 break ;
1029 case RX_DISABLE_LLC_PROMISC:
1030 smc->os.hwm.pass_llc_promisc = FALSE ;
1031 break ;
1032 case RX_ENABLE_LLC_PROMISC:
1033 smc->os.hwm.pass_llc_promisc = TRUE ;
1034 break ;
1035 case RX_ENABLE_ALLMULTI:
1036 case RX_DISABLE_ALLMULTI:
1037 case RX_ENABLE_PROMISC:
1038 case RX_DISABLE_PROMISC:
1039 case RX_ENABLE_NSA:
1040 case RX_DISABLE_NSA:
1041 default:
1042 mac_set_rx_mode(smc,mode) ;
1043 break ;
1044 }
1045 }
1046 #endif /* ifndef NDIS_OS2 */
1047
1048 /*
1049 * process receive queue
1050 */
1051 void process_receive(struct s_smc *smc)
1052 {
1053 int i ;
1054 int n ;
1055 int frag_count ; /* number of RxDs of the curr rx buf */
1056 int used_frags ; /* number of RxDs of the curr frame */
1057 struct s_smt_rx_queue *queue ; /* points to the queue ctl struct */
1058 struct s_smt_fp_rxd volatile *r ; /* rxd pointer */
1059 struct s_smt_fp_rxd volatile *rxd ; /* first rxd of rx frame */
1060 u_long rbctrl ; /* receive buffer control word */
1061 u_long rfsw ; /* receive frame status word */
1062 u_short rx_used ;
1063 u_char far *virt ;
1064 char far *data ;
1065 SMbuf *mb ;
1066 u_char fc ; /* Frame control */
1067 int len ; /* Frame length */
1068
1069 smc->os.hwm.detec_count = 0 ;
1070 queue = smc->hw.fp.rx[QUEUE_R1] ;
1071 NDD_TRACE("RHxB",0,0,0) ;
1072 for ( ; ; ) {
1073 r = queue->rx_curr_get ;
1074 rx_used = queue->rx_used ;
1075 frag_count = 0 ;
1076
1077 #ifdef USE_BREAK_ISR
1078 if (smc->os.hwm.leave_isr) {
1079 goto rx_end ;
1080 }
1081 #endif
1082 #ifdef NDIS_OS2
1083 if (offDepth) {
1084 smc->os.hwm.rx_break = 1 ;
1085 goto rx_end ;
1086 }
1087 smc->os.hwm.rx_break = 0 ;
1088 #endif
1089 #ifdef ODI2
1090 if (smc->os.hwm.rx_break) {
1091 goto rx_end ;
1092 }
1093 #endif
1094 n = 0 ;
1095 do {
1096 DB_RX("Check RxD %x for OWN and EOF",(void *)r,0,5) ;
1097 DRV_BUF_FLUSH(r,DDI_DMA_SYNC_FORCPU) ;
1098 rbctrl = CR_READ(r->rxd_rbctrl) ;
1099 rbctrl = AIX_REVERSE(rbctrl) ;
1100
1101 if (rbctrl & BMU_OWN) {
1102 NDD_TRACE("RHxE",r,rfsw,rbctrl) ;
1103 DB_RX("End of RxDs",0,0,4) ;
1104 goto rx_end ;
1105 }
1106 /*
1107 * out of RxD detection
1108 */
1109 if (!rx_used) {
1110 SK_BREAK() ;
1111 SMT_PANIC(smc,HWM_E0009,HWM_E0009_MSG) ;
1112 /* Either we don't have an RxD or all
1113 * RxDs are filled. Therefore it's allowed
1114 * for to set the STOPPED flag */
1115 smc->hw.hw_state = STOPPED ;
1116 mac_drv_clear_rx_queue(smc) ;
1117 smc->hw.hw_state = STARTED ;
1118 mac_drv_fill_rxd(smc) ;
1119 smc->os.hwm.detec_count = 0 ;
1120 goto rx_end ;
1121 }
1122 rfsw = AIX_REVERSE(r->rxd_rfsw) ;
1123 if ((rbctrl & BMU_STF) != ((rbctrl & BMU_ST_BUF) <<5)) {
1124 /*
1125 * The BMU_STF bit is deleted, 1 frame is
1126 * placed into more than 1 rx buffer
1127 *
1128 * skip frame by setting the rx len to 0
1129 *
1130 * if fragment count == 0
1131 * The missing STF bit belongs to the
1132 * current frame, search for the
1133 * EOF bit to complete the frame
1134 * else
1135 * the fragment belongs to the next frame,
1136 * exit the loop and process the frame
1137 */
1138 SK_BREAK() ;
1139 rfsw = 0 ;
1140 if (frag_count) {
1141 break ;
1142 }
1143 }
1144 n += rbctrl & 0xffff ;
1145 r = r->rxd_next ;
1146 frag_count++ ;
1147 rx_used-- ;
1148 } while (!(rbctrl & BMU_EOF)) ;
1149 used_frags = frag_count ;
1150 DB_RX("EOF set in RxD, used_frags = %d ",used_frags,0,5) ;
1151
1152 /* may be next 2 DRV_BUF_FLUSH() can be skipped, because */
1153 /* BMU_ST_BUF will not be changed by the ASIC */
1154 DRV_BUF_FLUSH(r,DDI_DMA_SYNC_FORCPU) ;
1155 while (rx_used && !(r->rxd_rbctrl & AIX_REVERSE(BMU_ST_BUF))) {
1156 DB_RX("Check STF bit in %x",(void *)r,0,5) ;
1157 r = r->rxd_next ;
1158 DRV_BUF_FLUSH(r,DDI_DMA_SYNC_FORCPU) ;
1159 frag_count++ ;
1160 rx_used-- ;
1161 }
1162 DB_RX("STF bit found",0,0,5) ;
1163
1164 /*
1165 * The received frame is finished for the process receive
1166 */
1167 rxd = queue->rx_curr_get ;
1168 queue->rx_curr_get = r ;
1169 queue->rx_free += frag_count ;
1170 queue->rx_used = rx_used ;
1171
1172 /*
1173 * ASIC Errata no. 7 (STF - Bit Bug)
1174 */
1175 rxd->rxd_rbctrl &= AIX_REVERSE(~BMU_STF) ;
1176
1177 for (r=rxd, i=frag_count ; i ; r=r->rxd_next, i--){
1178 DB_RX("dma_complete for RxD %x",(void *)r,0,5) ;
1179 dma_complete(smc,(union s_fp_descr volatile *)r,DMA_WR);
1180 }
1181 smc->hw.fp.err_stats.err_valid++ ;
1182 smc->mib.m[MAC0].fddiMACCopied_Ct++ ;
1183
1184 /* the length of the data including the FC */
1185 len = (rfsw & RD_LENGTH) - 4 ;
1186
1187 DB_RX("frame length = %d",len,0,4) ;
1188 /*
1189 * check the frame_lenght and all error flags
1190 */
1191 if (rfsw & (RX_MSRABT|RX_FS_E|RX_FS_CRC|RX_FS_IMPL)){
1192 if (rfsw & RD_S_MSRABT) {
1193 DB_RX("Frame aborted by the FORMAC",0,0,2) ;
1194 smc->hw.fp.err_stats.err_abort++ ;
1195 }
1196 /*
1197 * check frame status
1198 */
1199 if (rfsw & RD_S_SEAC2) {
1200 DB_RX("E-Indicator set",0,0,2) ;
1201 smc->hw.fp.err_stats.err_e_indicator++ ;
1202 }
1203 if (rfsw & RD_S_SFRMERR) {
1204 DB_RX("CRC error",0,0,2) ;
1205 smc->hw.fp.err_stats.err_crc++ ;
1206 }
1207 if (rfsw & RX_FS_IMPL) {
1208 DB_RX("Implementer frame",0,0,2) ;
1209 smc->hw.fp.err_stats.err_imp_frame++ ;
1210 }
1211 goto abort_frame ;
1212 }
1213 if (len > FDDI_RAW_MTU-4) {
1214 DB_RX("Frame too long error",0,0,2) ;
1215 smc->hw.fp.err_stats.err_too_long++ ;
1216 goto abort_frame ;
1217 }
1218 /*
1219 * SUPERNET 3 Bug: FORMAC delivers status words
1220 * of aborded frames to the BMU
1221 */
1222 if (len <= 4) {
1223 DB_RX("Frame length = 0",0,0,2) ;
1224 goto abort_frame ;
1225 }
1226
1227 if (len != (n-4)) {
1228 DB_RX("BMU: rx len differs: [%d:%d]",len,n,4);
1229 smc->os.hwm.rx_len_error++ ;
1230 goto abort_frame ;
1231 }
1232
1233 /*
1234 * Check SA == MA
1235 */
1236 virt = (u_char far *) rxd->rxd_virt ;
1237 DB_RX("FC = %x",*virt,0,2) ;
1238 if (virt[12] == MA[5] &&
1239 virt[11] == MA[4] &&
1240 virt[10] == MA[3] &&
1241 virt[9] == MA[2] &&
1242 virt[8] == MA[1] &&
1243 (virt[7] & ~GROUP_ADDR_BIT) == MA[0]) {
1244 goto abort_frame ;
1245 }
1246
1247 /*
1248 * test if LLC frame
1249 */
1250 if (rfsw & RX_FS_LLC) {
1251 /*
1252 * if pass_llc_promisc is disable
1253 * if DA != Multicast or Broadcast or DA!=MA
1254 * abort the frame
1255 */
1256 if (!smc->os.hwm.pass_llc_promisc) {
1257 if(!(virt[1] & GROUP_ADDR_BIT)) {
1258 if (virt[6] != MA[5] ||
1259 virt[5] != MA[4] ||
1260 virt[4] != MA[3] ||
1261 virt[3] != MA[2] ||
1262 virt[2] != MA[1] ||
1263 virt[1] != MA[0]) {
1264 DB_RX("DA != MA and not multi- or broadcast",0,0,2) ;
1265 goto abort_frame ;
1266 }
1267 }
1268 }
1269
1270 /*
1271 * LLC frame received
1272 */
1273 DB_RX("LLC - receive",0,0,4) ;
1274 mac_drv_rx_complete(smc,rxd,frag_count,len) ;
1275 }
1276 else {
1277 if (!(mb = smt_get_mbuf(smc))) {
1278 smc->hw.fp.err_stats.err_no_buf++ ;
1279 DB_RX("No SMbuf; receive terminated",0,0,4) ;
1280 goto abort_frame ;
1281 }
1282 data = smtod(mb,char *) - 1 ;
1283
1284 /*
1285 * copy the frame into a SMT_MBuf
1286 */
1287 #ifdef USE_OS_CPY
1288 hwm_cpy_rxd2mb(rxd,data,len) ;
1289 #else
1290 for (r=rxd, i=used_frags ; i ; r=r->rxd_next, i--){
1291 n = AIX_REVERSE(r->rxd_rbctrl) & RD_LENGTH ;
1292 DB_RX("cp SMT frame to mb: len = %d",n,0,6) ;
1293 memcpy(data,r->rxd_virt,n) ;
1294 data += n ;
1295 }
1296 data = smtod(mb,char *) - 1 ;
1297 #endif
1298 fc = *(char *)mb->sm_data = *data ;
1299 mb->sm_len = len - 1 ; /* len - fc */
1300 data++ ;
1301
1302 /*
1303 * SMT frame received
1304 */
1305 switch(fc) {
1306 case FC_SMT_INFO :
1307 smc->hw.fp.err_stats.err_smt_frame++ ;
1308 DB_RX("SMT frame received ",0,0,5) ;
1309
1310 if (smc->os.hwm.pass_SMT) {
1311 DB_RX("pass SMT frame ",0,0,5) ;
1312 mac_drv_rx_complete(smc, rxd,
1313 frag_count,len) ;
1314 }
1315 else {
1316 DB_RX("requeue RxD",0,0,5) ;
1317 mac_drv_requeue_rxd(smc,rxd,frag_count);
1318 }
1319
1320 smt_received_pack(smc,mb,(int)(rfsw>>25)) ;
1321 break ;
1322 case FC_SMT_NSA :
1323 smc->hw.fp.err_stats.err_smt_frame++ ;
1324 DB_RX("SMT frame received ",0,0,5) ;
1325
1326 /* if pass_NSA set pass the NSA frame or */
1327 /* pass_SMT set and the A-Indicator */
1328 /* is not set, pass the NSA frame */
1329 if (smc->os.hwm.pass_NSA ||
1330 (smc->os.hwm.pass_SMT &&
1331 !(rfsw & A_INDIC))) {
1332 DB_RX("pass SMT frame ",0,0,5) ;
1333 mac_drv_rx_complete(smc, rxd,
1334 frag_count,len) ;
1335 }
1336 else {
1337 DB_RX("requeue RxD",0,0,5) ;
1338 mac_drv_requeue_rxd(smc,rxd,frag_count);
1339 }
1340
1341 smt_received_pack(smc,mb,(int)(rfsw>>25)) ;
1342 break ;
1343 case FC_BEACON :
1344 if (smc->os.hwm.pass_DB) {
1345 DB_RX("pass DB frame ",0,0,5) ;
1346 mac_drv_rx_complete(smc, rxd,
1347 frag_count,len) ;
1348 }
1349 else {
1350 DB_RX("requeue RxD",0,0,5) ;
1351 mac_drv_requeue_rxd(smc,rxd,frag_count);
1352 }
1353 smt_free_mbuf(smc,mb) ;
1354 break ;
1355 default :
1356 /*
1357 * unknown FC abord the frame
1358 */
1359 DB_RX("unknown FC error",0,0,2) ;
1360 smt_free_mbuf(smc,mb) ;
1361 DB_RX("requeue RxD",0,0,5) ;
1362 mac_drv_requeue_rxd(smc,rxd,frag_count) ;
1363 if ((fc & 0xf0) == FC_MAC)
1364 smc->hw.fp.err_stats.err_mac_frame++ ;
1365 else
1366 smc->hw.fp.err_stats.err_imp_frame++ ;
1367
1368 break ;
1369 }
1370 }
1371
1372 DB_RX("next RxD is %x ",queue->rx_curr_get,0,3) ;
1373 NDD_TRACE("RHx1",queue->rx_curr_get,0,0) ;
1374
1375 continue ;
1376 /*--------------------------------------------------------------------*/
1377 abort_frame:
1378 DB_RX("requeue RxD",0,0,5) ;
1379 mac_drv_requeue_rxd(smc,rxd,frag_count) ;
1380
1381 DB_RX("next RxD is %x ",queue->rx_curr_get,0,3) ;
1382 NDD_TRACE("RHx2",queue->rx_curr_get,0,0) ;
1383 }
1384 rx_end:
1385 #ifdef ALL_RX_COMPLETE
1386 mac_drv_all_receives_complete(smc) ;
1387 #endif
1388 return ; /* lint bug: needs return detect end of function */
1389 }
1390
1391 static void smt_to_llc(struct s_smc *smc, SMbuf *mb)
1392 {
1393 u_char fc ;
1394
1395 DB_RX("send a queued frame to the llc layer",0,0,4) ;
1396 smc->os.hwm.r.len = mb->sm_len ;
1397 smc->os.hwm.r.mb_pos = smtod(mb,char *) ;
1398 fc = *smc->os.hwm.r.mb_pos ;
1399 (void)mac_drv_rx_init(smc,(int)mb->sm_len,(int)fc,
1400 smc->os.hwm.r.mb_pos,(int)mb->sm_len) ;
1401 smt_free_mbuf(smc,mb) ;
1402 }
1403
1404 /*
1405 * BEGIN_MANUAL_ENTRY(hwm_rx_frag)
1406 * void hwm_rx_frag(smc,virt,phys,len,frame_status)
1407 *
1408 * function MACRO (hardware module, hwmtm.h)
1409 * This function calls dma_master for preparing the
1410 * system hardware for the DMA transfer and initializes
1411 * the current RxD with the length and the physical and
1412 * virtual address of the fragment. Furthermore, it sets the
1413 * STF and EOF bits depending on the frame status byte,
1414 * switches the OWN flag of the RxD, so that it is owned by the
1415 * adapter and issues an rx_start.
1416 *
1417 * para virt virtual pointer to the fragment
1418 * len the length of the fragment
1419 * frame_status status of the frame, see design description
1420 *
1421 * NOTE: It is possible to call this function with a fragment length
1422 * of zero.
1423 *
1424 * END_MANUAL_ENTRY
1425 */
1426 void hwm_rx_frag(struct s_smc *smc, char far *virt, u_long phys, int len,
1427 int frame_status)
1428 {
1429 struct s_smt_fp_rxd volatile *r ;
1430 u_int rbctrl ;
1431
1432 NDD_TRACE("RHfB",virt,len,frame_status) ;
1433 DB_RX("hwm_rx_frag: len = %d, frame_status = %x\n",len,frame_status,2) ;
1434 r = smc->hw.fp.rx_q[QUEUE_R1].rx_curr_put ;
1435 r->rxd_virt = virt ;
1436 r->rxd_rbadr = AIX_REVERSE(phys) ;
1437 rbctrl = AIX_REVERSE( (((u_long)frame_status &
1438 (FIRST_FRAG|LAST_FRAG))<<26) |
1439 (((u_long) frame_status & FIRST_FRAG) << 21) |
1440 BMU_OWN | BMU_CHECK | BMU_EN_IRQ_EOF | len) ;
1441 r->rxd_rbctrl = rbctrl ;
1442
1443 DRV_BUF_FLUSH(r,DDI_DMA_SYNC_FORDEV) ;
1444 outpd(ADDR(B0_R1_CSR),CSR_START) ;
1445 smc->hw.fp.rx_q[QUEUE_R1].rx_free-- ;
1446 smc->hw.fp.rx_q[QUEUE_R1].rx_used++ ;
1447 smc->hw.fp.rx_q[QUEUE_R1].rx_curr_put = r->rxd_next ;
1448 NDD_TRACE("RHfE",r,AIX_REVERSE(r->rxd_rbadr),0) ;
1449 }
1450
1451 #ifndef NDIS_OS2
1452 /*
1453 * BEGIN_MANUAL_ENTRY(mac_drv_rx_frag)
1454 * int mac_drv_rx_frag(smc,virt,len)
1455 *
1456 * function DOWNCALL (hwmtm.c)
1457 * mac_drv_rx_frag fills the fragment with a part of the frame.
1458 *
1459 * para virt the virtual address of the fragment
1460 * len the length in bytes of the fragment
1461 *
1462 * return 0: success code, no errors possible
1463 *
1464 * END_MANUAL_ENTRY
1465 */
1466 int mac_drv_rx_frag(struct s_smc *smc, void far *virt, int len)
1467 {
1468 NDD_TRACE("RHSB",virt,len,smc->os.hwm.r.mb_pos) ;
1469
1470 DB_RX("receive from queue: len/virt: = %d/%x",len,virt,4) ;
1471 memcpy((char far *)virt,smc->os.hwm.r.mb_pos,len) ;
1472 smc->os.hwm.r.mb_pos += len ;
1473
1474 NDD_TRACE("RHSE",smc->os.hwm.r.mb_pos,0,0) ;
1475 return(0) ;
1476 }
1477 #endif
1478
1479
1480 /*
1481 * BEGINN_MANUAL_ENTRY(mac_drv_clear_rx_queue)
1482 *
1483 * void mac_drv_clear_rx_queue(smc)
1484 * struct s_smc *smc ;
1485 *
1486 * function DOWNCALL (hardware module, hwmtm.c)
1487 * mac_drv_clear_rx_queue is called by the OS-specific module
1488 * after it has issued a card_stop.
1489 * In this case, the frames in the receive queue are obsolete and
1490 * should be removed. For removing mac_drv_clear_rx_queue
1491 * calls dma_master for each RxD and mac_drv_clear_rxd for each
1492 * receive buffer.
1493 *
1494 * NOTE: calling sequence card_stop:
1495 * CLI_FBI(), card_stop(),
1496 * mac_drv_clear_tx_queue(), mac_drv_clear_rx_queue(),
1497 *
1498 * NOTE: The caller is responsible that the BMUs are idle
1499 * when this function is called.
1500 *
1501 * END_MANUAL_ENTRY
1502 */
1503 void mac_drv_clear_rx_queue(struct s_smc *smc)
1504 {
1505 struct s_smt_fp_rxd volatile *r ;
1506 struct s_smt_fp_rxd volatile *next_rxd ;
1507 struct s_smt_rx_queue *queue ;
1508 int frag_count ;
1509 int i ;
1510
1511 if (smc->hw.hw_state != STOPPED) {
1512 SK_BREAK() ;
1513 SMT_PANIC(smc,HWM_E0012,HWM_E0012_MSG) ;
1514 return ;
1515 }
1516
1517 queue = smc->hw.fp.rx[QUEUE_R1] ;
1518 DB_RX("clear_rx_queue",0,0,5) ;
1519
1520 /*
1521 * dma_complete and mac_drv_clear_rxd for all RxDs / receive buffers
1522 */
1523 r = queue->rx_curr_get ;
1524 while (queue->rx_used) {
1525 DRV_BUF_FLUSH(r,DDI_DMA_SYNC_FORCPU) ;
1526 DB_RX("switch OWN bit of RxD 0x%x ",r,0,5) ;
1527 r->rxd_rbctrl &= AIX_REVERSE(~BMU_OWN) ;
1528 frag_count = 1 ;
1529 DRV_BUF_FLUSH(r,DDI_DMA_SYNC_FORDEV) ;
1530 r = r->rxd_next ;
1531 DRV_BUF_FLUSH(r,DDI_DMA_SYNC_FORCPU) ;
1532 while (r != queue->rx_curr_put &&
1533 !(r->rxd_rbctrl & AIX_REVERSE(BMU_ST_BUF))) {
1534 DB_RX("Check STF bit in %x",(void *)r,0,5) ;
1535 r->rxd_rbctrl &= AIX_REVERSE(~BMU_OWN) ;
1536 DRV_BUF_FLUSH(r,DDI_DMA_SYNC_FORDEV) ;
1537 r = r->rxd_next ;
1538 DRV_BUF_FLUSH(r,DDI_DMA_SYNC_FORCPU) ;
1539 frag_count++ ;
1540 }
1541 DB_RX("STF bit found",0,0,5) ;
1542 next_rxd = r ;
1543
1544 for (r=queue->rx_curr_get,i=frag_count; i ; r=r->rxd_next,i--){
1545 DB_RX("dma_complete for RxD %x",(void *)r,0,5) ;
1546 dma_complete(smc,(union s_fp_descr volatile *)r,DMA_WR);
1547 }
1548
1549 DB_RX("mac_drv_clear_rxd: RxD %x frag_count %d ",
1550 (void *)queue->rx_curr_get,frag_count,5) ;
1551 mac_drv_clear_rxd(smc,queue->rx_curr_get,frag_count) ;
1552
1553 queue->rx_curr_get = next_rxd ;
1554 queue->rx_used -= frag_count ;
1555 queue->rx_free += frag_count ;
1556 }
1557 }
1558
1559
1560 /*
1561 -------------------------------------------------------------
1562 SEND FUNCTIONS:
1563 -------------------------------------------------------------
1564 */
1565
1566 /*
1567 * BEGIN_MANUAL_ENTRY(hwm_tx_init)
1568 * int hwm_tx_init(smc,fc,frag_count,frame_len,frame_status)
1569 *
1570 * function DOWN_CALL (hardware module, hwmtm.c)
1571 * hwm_tx_init checks if the frame can be sent through the
1572 * corresponding send queue.
1573 *
1574 * para fc the frame control. To determine through which
1575 * send queue the frame should be transmitted.
1576 * 0x50 - 0x57: asynchronous LLC frame
1577 * 0xD0 - 0xD7: synchronous LLC frame
1578 * 0x41, 0x4F: SMT frame to the network
1579 * 0x42: SMT frame to the network and to the local SMT
1580 * 0x43: SMT frame to the local SMT
1581 * frag_count count of the fragments for this frame
1582 * frame_len length of the frame
1583 * frame_status status of the frame, the send queue bit is already
1584 * specified
1585 *
1586 * return frame_status
1587 *
1588 * END_MANUAL_ENTRY
1589 */
1590 int hwm_tx_init(struct s_smc *smc, u_char fc, int frag_count, int frame_len,
1591 int frame_status)
1592 {
1593 NDD_TRACE("THiB",fc,frag_count,frame_len) ;
1594 smc->os.hwm.tx_p = smc->hw.fp.tx[frame_status & QUEUE_A0] ;
1595 smc->os.hwm.tx_descr = TX_DESCRIPTOR | (((u_long)(frame_len-1)&3)<<27) ;
1596 smc->os.hwm.tx_len = frame_len ;
1597 DB_TX("hwm_tx_init: fc = %x, len = %d",fc,frame_len,3) ;
1598 if ((fc & ~(FC_SYNC_BIT|FC_LLC_PRIOR)) == FC_ASYNC_LLC) {
1599 frame_status |= LAN_TX ;
1600 }
1601 else {
1602 switch (fc) {
1603 case FC_SMT_INFO :
1604 case FC_SMT_NSA :
1605 frame_status |= LAN_TX ;
1606 break ;
1607 case FC_SMT_LOC :
1608 frame_status |= LOC_TX ;
1609 break ;
1610 case FC_SMT_LAN_LOC :
1611 frame_status |= LAN_TX | LOC_TX ;
1612 break ;
1613 default :
1614 SMT_PANIC(smc,HWM_E0010,HWM_E0010_MSG) ;
1615 }
1616 }
1617 if (!smc->hw.mac_ring_is_up) {
1618 frame_status &= ~LAN_TX ;
1619 frame_status |= RING_DOWN ;
1620 DB_TX("Ring is down: terminate LAN_TX",0,0,2) ;
1621 }
1622 if (frag_count > smc->os.hwm.tx_p->tx_free) {
1623 #ifndef NDIS_OS2
1624 mac_drv_clear_txd(smc) ;
1625 if (frag_count > smc->os.hwm.tx_p->tx_free) {
1626 DB_TX("Out of TxDs, terminate LAN_TX",0,0,2) ;
1627 frame_status &= ~LAN_TX ;
1628 frame_status |= OUT_OF_TXD ;
1629 }
1630 #else
1631 DB_TX("Out of TxDs, terminate LAN_TX",0,0,2) ;
1632 frame_status &= ~LAN_TX ;
1633 frame_status |= OUT_OF_TXD ;
1634 #endif
1635 }
1636 DB_TX("frame_status = %x",frame_status,0,3) ;
1637 NDD_TRACE("THiE",frame_status,smc->os.hwm.tx_p->tx_free,0) ;
1638 return(frame_status) ;
1639 }
1640
1641 /*
1642 * BEGIN_MANUAL_ENTRY(hwm_tx_frag)
1643 * void hwm_tx_frag(smc,virt,phys,len,frame_status)
1644 *
1645 * function DOWNCALL (hardware module, hwmtm.c)
1646 * If the frame should be sent to the LAN, this function calls
1647 * dma_master, fills the current TxD with the virtual and the
1648 * physical address, sets the STF and EOF bits dependent on
1649 * the frame status, and requests the BMU to start the
1650 * transmit.
1651 * If the frame should be sent to the local SMT, an SMT_MBuf
1652 * is allocated if the FIRST_FRAG bit is set in the frame_status.
1653 * The fragment of the frame is copied into the SMT MBuf.
1654 * The function smt_received_pack is called if the LAST_FRAG
1655 * bit is set in the frame_status word.
1656 *
1657 * para virt virtual pointer to the fragment
1658 * len the length of the fragment
1659 * frame_status status of the frame, see design description
1660 *
1661 * return nothing returned, no parameter is modified
1662 *
1663 * NOTE: It is possible to invoke this macro with a fragment length
1664 * of zero.
1665 *
1666 * END_MANUAL_ENTRY
1667 */
1668 void hwm_tx_frag(struct s_smc *smc, char far *virt, u_long phys, int len,
1669 int frame_status)
1670 {
1671 struct s_smt_fp_txd volatile *t ;
1672 struct s_smt_tx_queue *queue ;
1673 u_int tbctrl ;
1674
1675 queue = smc->os.hwm.tx_p ;
1676
1677 NDD_TRACE("THfB",virt,len,frame_status) ;
1678 /* Bug fix: AF / May 31 1999 (#missing)
1679 * snmpinfo problem reported by IBM is caused by invalid
1680 * t-pointer (txd) if LAN_TX is not set but LOC_TX only.
1681 * Set: t = queue->tx_curr_put here !
1682 */
1683 t = queue->tx_curr_put ;
1684
1685 DB_TX("hwm_tx_frag: len = %d, frame_status = %x ",len,frame_status,2) ;
1686 if (frame_status & LAN_TX) {
1687 /* '*t' is already defined */
1688 DB_TX("LAN_TX: TxD = %x, virt = %x ",t,virt,3) ;
1689 t->txd_virt = virt ;
1690 t->txd_txdscr = AIX_REVERSE(smc->os.hwm.tx_descr) ;
1691 t->txd_tbadr = AIX_REVERSE(phys) ;
1692 tbctrl = AIX_REVERSE((((u_long)frame_status &
1693 (FIRST_FRAG|LAST_FRAG|EN_IRQ_EOF))<< 26) |
1694 BMU_OWN|BMU_CHECK |len) ;
1695 t->txd_tbctrl = tbctrl ;
1696
1697 #ifndef AIX
1698 DRV_BUF_FLUSH(t,DDI_DMA_SYNC_FORDEV) ;
1699 outpd(queue->tx_bmu_ctl,CSR_START) ;
1700 #else /* ifndef AIX */
1701 DRV_BUF_FLUSH(t,DDI_DMA_SYNC_FORDEV) ;
1702 if (frame_status & QUEUE_A0) {
1703 outpd(ADDR(B0_XA_CSR),CSR_START) ;
1704 }
1705 else {
1706 outpd(ADDR(B0_XS_CSR),CSR_START) ;
1707 }
1708 #endif
1709 queue->tx_free-- ;
1710 queue->tx_used++ ;
1711 queue->tx_curr_put = t->txd_next ;
1712 if (frame_status & LAST_FRAG) {
1713 smc->mib.m[MAC0].fddiMACTransmit_Ct++ ;
1714 }
1715 }
1716 if (frame_status & LOC_TX) {
1717 DB_TX("LOC_TX: ",0,0,3) ;
1718 if (frame_status & FIRST_FRAG) {
1719 if(!(smc->os.hwm.tx_mb = smt_get_mbuf(smc))) {
1720 smc->hw.fp.err_stats.err_no_buf++ ;
1721 DB_TX("No SMbuf; transmit terminated",0,0,4) ;
1722 }
1723 else {
1724 smc->os.hwm.tx_data =
1725 smtod(smc->os.hwm.tx_mb,char *) - 1 ;
1726 #ifdef USE_OS_CPY
1727 #ifdef PASS_1ST_TXD_2_TX_COMP
1728 hwm_cpy_txd2mb(t,smc->os.hwm.tx_data,
1729 smc->os.hwm.tx_len) ;
1730 #endif
1731 #endif
1732 }
1733 }
1734 if (smc->os.hwm.tx_mb) {
1735 #ifndef USE_OS_CPY
1736 DB_TX("copy fragment into MBuf ",0,0,3) ;
1737 memcpy(smc->os.hwm.tx_data,virt,len) ;
1738 smc->os.hwm.tx_data += len ;
1739 #endif
1740 if (frame_status & LAST_FRAG) {
1741 #ifdef USE_OS_CPY
1742 #ifndef PASS_1ST_TXD_2_TX_COMP
1743 /*
1744 * hwm_cpy_txd2mb(txd,data,len) copies 'len'
1745 * bytes from the virtual pointer in 'rxd'
1746 * to 'data'. The virtual pointer of the
1747 * os-specific tx-buffer should be written
1748 * in the LAST txd.
1749 */
1750 hwm_cpy_txd2mb(t,smc->os.hwm.tx_data,
1751 smc->os.hwm.tx_len) ;
1752 #endif /* nPASS_1ST_TXD_2_TX_COMP */
1753 #endif /* USE_OS_CPY */
1754 smc->os.hwm.tx_data =
1755 smtod(smc->os.hwm.tx_mb,char *) - 1 ;
1756 *(char *)smc->os.hwm.tx_mb->sm_data =
1757 *smc->os.hwm.tx_data ;
1758 smc->os.hwm.tx_data++ ;
1759 smc->os.hwm.tx_mb->sm_len =
1760 smc->os.hwm.tx_len - 1 ;
1761 DB_TX("pass LLC frame to SMT ",0,0,3) ;
1762 smt_received_pack(smc,smc->os.hwm.tx_mb,
1763 RD_FS_LOCAL) ;
1764 }
1765 }
1766 }
1767 NDD_TRACE("THfE",t,queue->tx_free,0) ;
1768 }
1769
1770
1771 /*
1772 * queues a receive for later send
1773 */
1774 static void queue_llc_rx(struct s_smc *smc, SMbuf *mb)
1775 {
1776 DB_GEN("queue_llc_rx: mb = %x",(void *)mb,0,4) ;
1777 smc->os.hwm.queued_rx_frames++ ;
1778 mb->sm_next = (SMbuf *)NULL ;
1779 if (smc->os.hwm.llc_rx_pipe == 0) {
1780 smc->os.hwm.llc_rx_pipe = mb ;
1781 }
1782 else {
1783 smc->os.hwm.llc_rx_tail->sm_next = mb ;
1784 }
1785 smc->os.hwm.llc_rx_tail = mb ;
1786
1787 /*
1788 * force an timer IRQ to receive the data
1789 */
1790 if (!smc->os.hwm.isr_flag) {
1791 smt_force_irq(smc) ;
1792 }
1793 }
1794
1795 /*
1796 * get a SMbuf from the llc_rx_queue
1797 */
1798 static SMbuf *get_llc_rx(struct s_smc *smc)
1799 {
1800 SMbuf *mb ;
1801
1802 if ((mb = smc->os.hwm.llc_rx_pipe)) {
1803 smc->os.hwm.queued_rx_frames-- ;
1804 smc->os.hwm.llc_rx_pipe = mb->sm_next ;
1805 }
1806 DB_GEN("get_llc_rx: mb = 0x%x",(void *)mb,0,4) ;
1807 return(mb) ;
1808 }
1809
1810 /*
1811 * queues a transmit SMT MBuf during the time were the MBuf is
1812 * queued the TxD ring
1813 */
1814 static void queue_txd_mb(struct s_smc *smc, SMbuf *mb)
1815 {
1816 DB_GEN("_rx: queue_txd_mb = %x",(void *)mb,0,4) ;
1817 smc->os.hwm.queued_txd_mb++ ;
1818 mb->sm_next = (SMbuf *)NULL ;
1819 if (smc->os.hwm.txd_tx_pipe == 0) {
1820 smc->os.hwm.txd_tx_pipe = mb ;
1821 }
1822 else {
1823 smc->os.hwm.txd_tx_tail->sm_next = mb ;
1824 }
1825 smc->os.hwm.txd_tx_tail = mb ;
1826 }
1827
1828 /*
1829 * get a SMbuf from the txd_tx_queue
1830 */
1831 static SMbuf *get_txd_mb(struct s_smc *smc)
1832 {
1833 SMbuf *mb ;
1834
1835 if ((mb = smc->os.hwm.txd_tx_pipe)) {
1836 smc->os.hwm.queued_txd_mb-- ;
1837 smc->os.hwm.txd_tx_pipe = mb->sm_next ;
1838 }
1839 DB_GEN("get_txd_mb: mb = 0x%x",(void *)mb,0,4) ;
1840 return(mb) ;
1841 }
1842
1843 /*
1844 * SMT Send function
1845 */
1846 void smt_send_mbuf(struct s_smc *smc, SMbuf *mb, int fc)
1847 {
1848 char far *data ;
1849 int len ;
1850 int n ;
1851 int i ;
1852 int frag_count ;
1853 int frame_status ;
1854 SK_LOC_DECL(char far,*virt[3]) ;
1855 int frag_len[3] ;
1856 struct s_smt_tx_queue *queue ;
1857 struct s_smt_fp_txd volatile *t ;
1858 u_long phys ;
1859 u_int tbctrl ;
1860
1861 NDD_TRACE("THSB",mb,fc,0) ;
1862 DB_TX("smt_send_mbuf: mb = 0x%x, fc = 0x%x",mb,fc,4) ;
1863
1864 mb->sm_off-- ; /* set to fc */
1865 mb->sm_len++ ; /* + fc */
1866 data = smtod(mb,char *) ;
1867 *data = fc ;
1868 if (fc == FC_SMT_LOC)
1869 *data = FC_SMT_INFO ;
1870
1871 /*
1872 * determine the frag count and the virt addresses of the frags
1873 */
1874 frag_count = 0 ;
1875 len = mb->sm_len ;
1876 while (len) {
1877 n = SMT_PAGESIZE - ((long)data & (SMT_PAGESIZE-1)) ;
1878 if (n >= len) {
1879 n = len ;
1880 }
1881 DB_TX("frag: virt/len = 0x%x/%d ",(void *)data,n,5) ;
1882 virt[frag_count] = data ;
1883 frag_len[frag_count] = n ;
1884 frag_count++ ;
1885 len -= n ;
1886 data += n ;
1887 }
1888
1889 /*
1890 * determine the frame status
1891 */
1892 queue = smc->hw.fp.tx[QUEUE_A0] ;
1893 if (fc == FC_BEACON || fc == FC_SMT_LOC) {
1894 frame_status = LOC_TX ;
1895 }
1896 else {
1897 frame_status = LAN_TX ;
1898 if ((smc->os.hwm.pass_NSA &&(fc == FC_SMT_NSA)) ||
1899 (smc->os.hwm.pass_SMT &&(fc == FC_SMT_INFO)))
1900 frame_status |= LOC_TX ;
1901 }
1902
1903 if (!smc->hw.mac_ring_is_up || frag_count > queue->tx_free) {
1904 frame_status &= ~LAN_TX;
1905 if (frame_status) {
1906 DB_TX("Ring is down: terminate LAN_TX",0,0,2) ;
1907 }
1908 else {
1909 DB_TX("Ring is down: terminate transmission",0,0,2) ;
1910 smt_free_mbuf(smc,mb) ;
1911 return ;
1912 }
1913 }
1914 DB_TX("frame_status = 0x%x ",frame_status,0,5) ;
1915
1916 if ((frame_status & LAN_TX) && (frame_status & LOC_TX)) {
1917 mb->sm_use_count = 2 ;
1918 }
1919
1920 if (frame_status & LAN_TX) {
1921 t = queue->tx_curr_put ;
1922 frame_status |= FIRST_FRAG ;
1923 for (i = 0; i < frag_count; i++) {
1924 DB_TX("init TxD = 0x%x",(void *)t,0,5) ;
1925 if (i == frag_count-1) {
1926 frame_status |= LAST_FRAG ;
1927 t->txd_txdscr = AIX_REVERSE(TX_DESCRIPTOR |
1928 (((u_long)(mb->sm_len-1)&3) << 27)) ;
1929 }
1930 t->txd_virt = virt[i] ;
1931 phys = dma_master(smc, (void far *)virt[i],
1932 frag_len[i], DMA_RD|SMT_BUF) ;
1933 t->txd_tbadr = AIX_REVERSE(phys) ;
1934 tbctrl = AIX_REVERSE((((u_long) frame_status &
1935 (FIRST_FRAG|LAST_FRAG)) << 26) |
1936 BMU_OWN | BMU_CHECK | BMU_SMT_TX |frag_len[i]) ;
1937 t->txd_tbctrl = tbctrl ;
1938 #ifndef AIX
1939 DRV_BUF_FLUSH(t,DDI_DMA_SYNC_FORDEV) ;
1940 outpd(queue->tx_bmu_ctl,CSR_START) ;
1941 #else
1942 DRV_BUF_FLUSH(t,DDI_DMA_SYNC_FORDEV) ;
1943 outpd(ADDR(B0_XA_CSR),CSR_START) ;
1944 #endif
1945 frame_status &= ~FIRST_FRAG ;
1946 queue->tx_curr_put = t = t->txd_next ;
1947 queue->tx_free-- ;
1948 queue->tx_used++ ;
1949 }
1950 smc->mib.m[MAC0].fddiMACTransmit_Ct++ ;
1951 queue_txd_mb(smc,mb) ;
1952 }
1953
1954 if (frame_status & LOC_TX) {
1955 DB_TX("pass Mbuf to LLC queue",0,0,5) ;
1956 queue_llc_rx(smc,mb) ;
1957 }
1958
1959 /*
1960 * We need to unqueue the free SMT_MBUFs here, because it may
1961 * be that the SMT want's to send more than 1 frame for one down call
1962 */
1963 mac_drv_clear_txd(smc) ;
1964 NDD_TRACE("THSE",t,queue->tx_free,frag_count) ;
1965 }
1966
1967 /* BEGIN_MANUAL_ENTRY(mac_drv_clear_txd)
1968 * void mac_drv_clear_txd(smc)
1969 *
1970 * function DOWNCALL (hardware module, hwmtm.c)
1971 * mac_drv_clear_txd searches in both send queues for TxD's
1972 * which were finished by the adapter. It calls dma_complete
1973 * for each TxD. If the last fragment of an LLC frame is
1974 * reached, it calls mac_drv_tx_complete to release the
1975 * send buffer.
1976 *
1977 * return nothing
1978 *
1979 * END_MANUAL_ENTRY
1980 */
1981 void mac_drv_clear_txd(struct s_smc *smc)
1982 {
1983 struct s_smt_tx_queue *queue ;
1984 struct s_smt_fp_txd volatile *t1 ;
1985 struct s_smt_fp_txd volatile *t2 = NULL ;
1986 SMbuf *mb ;
1987 u_long tbctrl ;
1988 int i ;
1989 int frag_count ;
1990 int n ;
1991
1992 NDD_TRACE("THcB",0,0,0) ;
1993 for (i = QUEUE_S; i <= QUEUE_A0; i++) {
1994 queue = smc->hw.fp.tx[i] ;
1995 t1 = queue->tx_curr_get ;
1996 DB_TX("clear_txd: QUEUE = %d (0=sync/1=async)",i,0,5) ;
1997
1998 for ( ; ; ) {
1999 frag_count = 0 ;
2000
2001 do {
2002 DRV_BUF_FLUSH(t1,DDI_DMA_SYNC_FORCPU) ;
2003 DB_TX("check OWN/EOF bit of TxD 0x%x",t1,0,5) ;
2004 tbctrl = CR_READ(t1->txd_tbctrl) ;
2005 tbctrl = AIX_REVERSE(tbctrl) ;
2006
2007 if (tbctrl & BMU_OWN || !queue->tx_used){
2008 DB_TX("End of TxDs queue %d",i,0,4) ;
2009 goto free_next_queue ; /* next queue */
2010 }
2011 t1 = t1->txd_next ;
2012 frag_count++ ;
2013 } while (!(tbctrl & BMU_EOF)) ;
2014
2015 t1 = queue->tx_curr_get ;
2016 for (n = frag_count; n; n--) {
2017 tbctrl = AIX_REVERSE(t1->txd_tbctrl) ;
2018 dma_complete(smc,
2019 (union s_fp_descr volatile *) t1,
2020 (int) (DMA_RD |
2021 ((tbctrl & BMU_SMT_TX) >> 18))) ;
2022 t2 = t1 ;
2023 t1 = t1->txd_next ;
2024 }
2025
2026 if (tbctrl & BMU_SMT_TX) {
2027 mb = get_txd_mb(smc) ;
2028 smt_free_mbuf(smc,mb) ;
2029 }
2030 else {
2031 #ifndef PASS_1ST_TXD_2_TX_COMP
2032 DB_TX("mac_drv_tx_comp for TxD 0x%x",t2,0,4) ;
2033 mac_drv_tx_complete(smc,t2) ;
2034 #else
2035 DB_TX("mac_drv_tx_comp for TxD 0x%x",
2036 queue->tx_curr_get,0,4) ;
2037 mac_drv_tx_complete(smc,queue->tx_curr_get) ;
2038 #endif
2039 }
2040 queue->tx_curr_get = t1 ;
2041 queue->tx_free += frag_count ;
2042 queue->tx_used -= frag_count ;
2043 }
2044 free_next_queue: ;
2045 }
2046 NDD_TRACE("THcE",0,0,0) ;
2047 }
2048
2049 /*
2050 * BEGINN_MANUAL_ENTRY(mac_drv_clear_tx_queue)
2051 *
2052 * void mac_drv_clear_tx_queue(smc)
2053 * struct s_smc *smc ;
2054 *
2055 * function DOWNCALL (hardware module, hwmtm.c)
2056 * mac_drv_clear_tx_queue is called from the SMT when
2057 * the RMT state machine has entered the ISOLATE state.
2058 * This function is also called by the os-specific module
2059 * after it has called the function card_stop().
2060 * In this case, the frames in the send queues are obsolete and
2061 * should be removed.
2062 *
2063 * note calling sequence:
2064 * CLI_FBI(), card_stop(),
2065 * mac_drv_clear_tx_queue(), mac_drv_clear_rx_queue(),
2066 *
2067 * NOTE: The caller is responsible that the BMUs are idle
2068 * when this function is called.
2069 *
2070 * END_MANUAL_ENTRY
2071 */
2072 void mac_drv_clear_tx_queue(struct s_smc *smc)
2073 {
2074 struct s_smt_fp_txd volatile *t ;
2075 struct s_smt_tx_queue *queue ;
2076 int tx_used ;
2077 int i ;
2078
2079 if (smc->hw.hw_state != STOPPED) {
2080 SK_BREAK() ;
2081 SMT_PANIC(smc,HWM_E0011,HWM_E0011_MSG) ;
2082 return ;
2083 }
2084
2085 for (i = QUEUE_S; i <= QUEUE_A0; i++) {
2086 queue = smc->hw.fp.tx[i] ;
2087 DB_TX("clear_tx_queue: QUEUE = %d (0=sync/1=async)",i,0,5) ;
2088
2089 /*
2090 * switch the OWN bit of all pending frames to the host
2091 */
2092 t = queue->tx_curr_get ;
2093 tx_used = queue->tx_used ;
2094 while (tx_used) {
2095 DRV_BUF_FLUSH(t,DDI_DMA_SYNC_FORCPU) ;
2096 DB_TX("switch OWN bit of TxD 0x%x ",t,0,5) ;
2097 t->txd_tbctrl &= AIX_REVERSE(~BMU_OWN) ;
2098 DRV_BUF_FLUSH(t,DDI_DMA_SYNC_FORDEV) ;
2099 t = t->txd_next ;
2100 tx_used-- ;
2101 }
2102 }
2103
2104 /*
2105 * release all TxD's for both send queues
2106 */
2107 mac_drv_clear_txd(smc) ;
2108
2109 for (i = QUEUE_S; i <= QUEUE_A0; i++) {
2110 queue = smc->hw.fp.tx[i] ;
2111 t = queue->tx_curr_get ;
2112
2113 /*
2114 * write the phys pointer of the NEXT descriptor into the
2115 * BMU's current address descriptor pointer and set
2116 * tx_curr_get and tx_curr_put to this position
2117 */
2118 if (i == QUEUE_S) {
2119 outpd(ADDR(B5_XS_DA),AIX_REVERSE(t->txd_ntdadr)) ;
2120 }
2121 else {
2122 outpd(ADDR(B5_XA_DA),AIX_REVERSE(t->txd_ntdadr)) ;
2123 }
2124
2125 queue->tx_curr_put = queue->tx_curr_get->txd_next ;
2126 queue->tx_curr_get = queue->tx_curr_put ;
2127 }
2128 }
2129
2130
2131 /*
2132 -------------------------------------------------------------
2133 TEST FUNCTIONS:
2134 -------------------------------------------------------------
2135 */
2136
2137 #ifdef DEBUG
2138 /*
2139 * BEGIN_MANUAL_ENTRY(mac_drv_debug_lev)
2140 * void mac_drv_debug_lev(smc,flag,lev)
2141 *
2142 * function DOWNCALL (drvsr.c)
2143 * To get a special debug info the user can assign a debug level
2144 * to any debug flag.
2145 *
2146 * para flag debug flag, possible values are:
2147 * = 0: reset all debug flags (the defined level is
2148 * ignored)
2149 * = 1: debug.d_smtf
2150 * = 2: debug.d_smt
2151 * = 3: debug.d_ecm
2152 * = 4: debug.d_rmt
2153 * = 5: debug.d_cfm
2154 * = 6: debug.d_pcm
2155 *
2156 * = 10: debug.d_os.hwm_rx (hardware module receive path)
2157 * = 11: debug.d_os.hwm_tx(hardware module transmit path)
2158 * = 12: debug.d_os.hwm_gen(hardware module general flag)
2159 *
2160 * lev debug level
2161 *
2162 * END_MANUAL_ENTRY
2163 */
2164 void mac_drv_debug_lev(struct s_smc *smc, int flag, int lev)
2165 {
2166 switch(flag) {
2167 case (int)NULL:
2168 DB_P.d_smtf = DB_P.d_smt = DB_P.d_ecm = DB_P.d_rmt = 0 ;
2169 DB_P.d_cfm = 0 ;
2170 DB_P.d_os.hwm_rx = DB_P.d_os.hwm_tx = DB_P.d_os.hwm_gen = 0 ;
2171 #ifdef SBA
2172 DB_P.d_sba = 0 ;
2173 #endif
2174 #ifdef ESS
2175 DB_P.d_ess = 0 ;
2176 #endif
2177 break ;
2178 case DEBUG_SMTF:
2179 DB_P.d_smtf = lev ;
2180 break ;
2181 case DEBUG_SMT:
2182 DB_P.d_smt = lev ;
2183 break ;
2184 case DEBUG_ECM:
2185 DB_P.d_ecm = lev ;
2186 break ;
2187 case DEBUG_RMT:
2188 DB_P.d_rmt = lev ;
2189 break ;
2190 case DEBUG_CFM:
2191 DB_P.d_cfm = lev ;
2192 break ;
2193 case DEBUG_PCM:
2194 DB_P.d_pcm = lev ;
2195 break ;
2196 case DEBUG_SBA:
2197 #ifdef SBA
2198 DB_P.d_sba = lev ;
2199 #endif
2200 break ;
2201 case DEBUG_ESS:
2202 #ifdef ESS
2203 DB_P.d_ess = lev ;
2204 #endif
2205 break ;
2206 case DB_HWM_RX:
2207 DB_P.d_os.hwm_rx = lev ;
2208 break ;
2209 case DB_HWM_TX:
2210 DB_P.d_os.hwm_tx = lev ;
2211 break ;
2212 case DB_HWM_GEN:
2213 DB_P.d_os.hwm_gen = lev ;
2214 break ;
2215 default:
2216 break ;
2217 }
2218 }
2219 #endif
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