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[TG3]: Set minimal hw interrupt mitigation.
[linux-2.6/verdex.git] / drivers / net / tulip / media.c
blobedae09a4b021e353ab4fbba756e31492fbb8fd2e
1 /*
2 drivers/net/tulip/media.c
3
4 Maintained by Jeff Garzik <jgarzik@pobox.com>
5 Copyright 2000,2001 The Linux Kernel Team
6 Written/copyright 1994-2001 by Donald Becker.
7
8 This software may be used and distributed according to the terms
9 of the GNU General Public License, incorporated herein by reference.
10
11 Please refer to Documentation/DocBook/tulip-user.{pdf,ps,html}
12 for more information on this driver, or visit the project
13 Web page at http://sourceforge.net/projects/tulip/
14
15 */
16
17 #include <linux/kernel.h>
18 #include <linux/mii.h>
19 #include <linux/init.h>
20 #include <linux/delay.h>
21 #include <linux/pci.h>
22 #include "tulip.h"
23
24
25 /* The maximum data clock rate is 2.5 Mhz. The minimum timing is usually
26 met by back-to-back PCI I/O cycles, but we insert a delay to avoid
27 "overclocking" issues or future 66Mhz PCI. */
28 #define mdio_delay() ioread32(mdio_addr)
29
30 /* Read and write the MII registers using software-generated serial
31 MDIO protocol. It is just different enough from the EEPROM protocol
32 to not share code. The maxium data clock rate is 2.5 Mhz. */
33 #define MDIO_SHIFT_CLK 0x10000
34 #define MDIO_DATA_WRITE0 0x00000
35 #define MDIO_DATA_WRITE1 0x20000
36 #define MDIO_ENB 0x00000 /* Ignore the 0x02000 databook setting. */
37 #define MDIO_ENB_IN 0x40000
38 #define MDIO_DATA_READ 0x80000
39
40 static const unsigned char comet_miireg2offset[32] = {
41 0xB4, 0xB8, 0xBC, 0xC0, 0xC4, 0xC8, 0xCC, 0, 0,0,0,0, 0,0,0,0,
42 0,0xD0,0,0, 0,0,0,0, 0,0,0,0, 0, 0xD4, 0xD8, 0xDC, };
43
44
45 /* MII transceiver control section.
46 Read and write the MII registers using software-generated serial
47 MDIO protocol. See the MII specifications or DP83840A data sheet
48 for details. */
49
50 int tulip_mdio_read(struct net_device *dev, int phy_id, int location)
51 {
52 struct tulip_private *tp = netdev_priv(dev);
53 int i;
54 int read_cmd = (0xf6 << 10) | ((phy_id & 0x1f) << 5) | location;
55 int retval = 0;
56 void __iomem *ioaddr = tp->base_addr;
57 void __iomem *mdio_addr = ioaddr + CSR9;
58 unsigned long flags;
59
60 if (location & ~0x1f)
61 return 0xffff;
62
63 if (tp->chip_id == COMET && phy_id == 30) {
64 if (comet_miireg2offset[location])
65 return ioread32(ioaddr + comet_miireg2offset[location]);
66 return 0xffff;
67 }
68
69 spin_lock_irqsave(&tp->mii_lock, flags);
70 if (tp->chip_id == LC82C168) {
71 int i = 1000;
72 iowrite32(0x60020000 + (phy_id<<23) + (location<<18), ioaddr + 0xA0);
73 ioread32(ioaddr + 0xA0);
74 ioread32(ioaddr + 0xA0);
75 while (--i > 0) {
76 barrier();
77 if ( ! ((retval = ioread32(ioaddr + 0xA0)) & 0x80000000))
78 break;
79 }
80 spin_unlock_irqrestore(&tp->mii_lock, flags);
81 return retval & 0xffff;
82 }
83
84 if(tp->chip_id == ULI526X && tp->revision >= 0x40) {
85 int value;
86 int i = 1000;
87
88 value = ioread32(ioaddr + CSR9);
89 iowrite32(value & 0xFFEFFFFF, ioaddr + CSR9);
90
91 value = (phy_id << 21) | (location << 16) | 0x08000000;
92 iowrite32(value, ioaddr + CSR10);
93
94 while(--i > 0) {
95 mdio_delay();
96 if(ioread32(ioaddr + CSR10) & 0x10000000)
97 break;
98 }
99 retval = ioread32(ioaddr + CSR10);
100 spin_unlock_irqrestore(&tp->mii_lock, flags);
101 return retval & 0xFFFF;
102 }
103 /* Establish sync by sending at least 32 logic ones. */
104 for (i = 32; i >= 0; i--) {
105 iowrite32(MDIO_ENB | MDIO_DATA_WRITE1, mdio_addr);
106 mdio_delay();
107 iowrite32(MDIO_ENB | MDIO_DATA_WRITE1 | MDIO_SHIFT_CLK, mdio_addr);
108 mdio_delay();
109 }
110 /* Shift the read command bits out. */
111 for (i = 15; i >= 0; i--) {
112 int dataval = (read_cmd & (1 << i)) ? MDIO_DATA_WRITE1 : 0;
113
114 iowrite32(MDIO_ENB | dataval, mdio_addr);
115 mdio_delay();
116 iowrite32(MDIO_ENB | dataval | MDIO_SHIFT_CLK, mdio_addr);
117 mdio_delay();
118 }
119 /* Read the two transition, 16 data, and wire-idle bits. */
120 for (i = 19; i > 0; i--) {
121 iowrite32(MDIO_ENB_IN, mdio_addr);
122 mdio_delay();
123 retval = (retval << 1) | ((ioread32(mdio_addr) & MDIO_DATA_READ) ? 1 : 0);
124 iowrite32(MDIO_ENB_IN | MDIO_SHIFT_CLK, mdio_addr);
125 mdio_delay();
126 }
127
128 spin_unlock_irqrestore(&tp->mii_lock, flags);
129 return (retval>>1) & 0xffff;
130 }
131
132 void tulip_mdio_write(struct net_device *dev, int phy_id, int location, int val)
133 {
134 struct tulip_private *tp = netdev_priv(dev);
135 int i;
136 int cmd = (0x5002 << 16) | ((phy_id & 0x1f) << 23) | (location<<18) | (val & 0xffff);
137 void __iomem *ioaddr = tp->base_addr;
138 void __iomem *mdio_addr = ioaddr + CSR9;
139 unsigned long flags;
140
141 if (location & ~0x1f)
142 return;
143
144 if (tp->chip_id == COMET && phy_id == 30) {
145 if (comet_miireg2offset[location])
146 iowrite32(val, ioaddr + comet_miireg2offset[location]);
147 return;
148 }
149
150 spin_lock_irqsave(&tp->mii_lock, flags);
151 if (tp->chip_id == LC82C168) {
152 int i = 1000;
153 iowrite32(cmd, ioaddr + 0xA0);
154 do {
155 barrier();
156 if ( ! (ioread32(ioaddr + 0xA0) & 0x80000000))
157 break;
158 } while (--i > 0);
159 spin_unlock_irqrestore(&tp->mii_lock, flags);
160 return;
161 }
162 if (tp->chip_id == ULI526X && tp->revision >= 0x40) {
163 int value;
164 int i = 1000;
165
166 value = ioread32(ioaddr + CSR9);
167 iowrite32(value & 0xFFEFFFFF, ioaddr + CSR9);
168
169 value = (phy_id << 21) | (location << 16) | 0x04000000 | (val & 0xFFFF);
170 iowrite32(value, ioaddr + CSR10);
171
172 while(--i > 0) {
173 if (ioread32(ioaddr + CSR10) & 0x10000000)
174 break;
175 }
176 spin_unlock_irqrestore(&tp->mii_lock, flags);
177 }
178
179 /* Establish sync by sending 32 logic ones. */
180 for (i = 32; i >= 0; i--) {
181 iowrite32(MDIO_ENB | MDIO_DATA_WRITE1, mdio_addr);
182 mdio_delay();
183 iowrite32(MDIO_ENB | MDIO_DATA_WRITE1 | MDIO_SHIFT_CLK, mdio_addr);
184 mdio_delay();
185 }
186 /* Shift the command bits out. */
187 for (i = 31; i >= 0; i--) {
188 int dataval = (cmd & (1 << i)) ? MDIO_DATA_WRITE1 : 0;
189 iowrite32(MDIO_ENB | dataval, mdio_addr);
190 mdio_delay();
191 iowrite32(MDIO_ENB | dataval | MDIO_SHIFT_CLK, mdio_addr);
192 mdio_delay();
193 }
194 /* Clear out extra bits. */
195 for (i = 2; i > 0; i--) {
196 iowrite32(MDIO_ENB_IN, mdio_addr);
197 mdio_delay();
198 iowrite32(MDIO_ENB_IN | MDIO_SHIFT_CLK, mdio_addr);
199 mdio_delay();
200 }
201
202 spin_unlock_irqrestore(&tp->mii_lock, flags);
203 }
204
205
206 /* Set up the transceiver control registers for the selected media type. */
207 void tulip_select_media(struct net_device *dev, int startup)
208 {
209 struct tulip_private *tp = netdev_priv(dev);
210 void __iomem *ioaddr = tp->base_addr;
211 struct mediatable *mtable = tp->mtable;
212 u32 new_csr6;
213 int i;
214
215 if (mtable) {
216 struct medialeaf *mleaf = &mtable->mleaf[tp->cur_index];
217 unsigned char *p = mleaf->leafdata;
218 switch (mleaf->type) {
219 case 0: /* 21140 non-MII xcvr. */
220 if (tulip_debug > 1)
221 printk(KERN_DEBUG "%s: Using a 21140 non-MII transceiver"
222 " with control setting %2.2x.\n",
223 dev->name, p[1]);
224 dev->if_port = p[0];
225 if (startup)
226 iowrite32(mtable->csr12dir | 0x100, ioaddr + CSR12);
227 iowrite32(p[1], ioaddr + CSR12);
228 new_csr6 = 0x02000000 | ((p[2] & 0x71) << 18);
229 break;
230 case 2: case 4: {
231 u16 setup[5];
232 u32 csr13val, csr14val, csr15dir, csr15val;
233 for (i = 0; i < 5; i++)
234 setup[i] = get_u16(&p[i*2 + 1]);
235
236 dev->if_port = p[0] & MEDIA_MASK;
237 if (tulip_media_cap[dev->if_port] & MediaAlwaysFD)
238 tp->full_duplex = 1;
239
240 if (startup && mtable->has_reset) {
241 struct medialeaf *rleaf = &mtable->mleaf[mtable->has_reset];
242 unsigned char *rst = rleaf->leafdata;
243 if (tulip_debug > 1)
244 printk(KERN_DEBUG "%s: Resetting the transceiver.\n",
245 dev->name);
246 for (i = 0; i < rst[0]; i++)
247 iowrite32(get_u16(rst + 1 + (i<<1)) << 16, ioaddr + CSR15);
248 }
249 if (tulip_debug > 1)
250 printk(KERN_DEBUG "%s: 21143 non-MII %s transceiver control "
251 "%4.4x/%4.4x.\n",
252 dev->name, medianame[dev->if_port], setup[0], setup[1]);
253 if (p[0] & 0x40) { /* SIA (CSR13-15) setup values are provided. */
254 csr13val = setup[0];
255 csr14val = setup[1];
256 csr15dir = (setup[3]<<16) | setup[2];
257 csr15val = (setup[4]<<16) | setup[2];
258 iowrite32(0, ioaddr + CSR13);
259 iowrite32(csr14val, ioaddr + CSR14);
260 iowrite32(csr15dir, ioaddr + CSR15); /* Direction */
261 iowrite32(csr15val, ioaddr + CSR15); /* Data */
262 iowrite32(csr13val, ioaddr + CSR13);
263 } else {
264 csr13val = 1;
265 csr14val = 0;
266 csr15dir = (setup[0]<<16) | 0x0008;
267 csr15val = (setup[1]<<16) | 0x0008;
268 if (dev->if_port <= 4)
269 csr14val = t21142_csr14[dev->if_port];
270 if (startup) {
271 iowrite32(0, ioaddr + CSR13);
272 iowrite32(csr14val, ioaddr + CSR14);
273 }
274 iowrite32(csr15dir, ioaddr + CSR15); /* Direction */
275 iowrite32(csr15val, ioaddr + CSR15); /* Data */
276 if (startup) iowrite32(csr13val, ioaddr + CSR13);
277 }
278 if (tulip_debug > 1)
279 printk(KERN_DEBUG "%s: Setting CSR15 to %8.8x/%8.8x.\n",
280 dev->name, csr15dir, csr15val);
281 if (mleaf->type == 4)
282 new_csr6 = 0x82020000 | ((setup[2] & 0x71) << 18);
283 else
284 new_csr6 = 0x82420000;
285 break;
286 }
287 case 1: case 3: {
288 int phy_num = p[0];
289 int init_length = p[1];
290 u16 *misc_info, tmp_info;
291
292 dev->if_port = 11;
293 new_csr6 = 0x020E0000;
294 if (mleaf->type == 3) { /* 21142 */
295 u16 *init_sequence = (u16*)(p+2);
296 u16 *reset_sequence = &((u16*)(p+3))[init_length];
297 int reset_length = p[2 + init_length*2];
298 misc_info = reset_sequence + reset_length;
299 if (startup)
300 for (i = 0; i < reset_length; i++)
301 iowrite32(get_u16(&reset_sequence[i]) << 16, ioaddr + CSR15);
302 for (i = 0; i < init_length; i++)
303 iowrite32(get_u16(&init_sequence[i]) << 16, ioaddr + CSR15);
304 } else {
305 u8 *init_sequence = p + 2;
306 u8 *reset_sequence = p + 3 + init_length;
307 int reset_length = p[2 + init_length];
308 misc_info = (u16*)(reset_sequence + reset_length);
309 if (startup) {
310 iowrite32(mtable->csr12dir | 0x100, ioaddr + CSR12);
311 for (i = 0; i < reset_length; i++)
312 iowrite32(reset_sequence[i], ioaddr + CSR12);
313 }
314 for (i = 0; i < init_length; i++)
315 iowrite32(init_sequence[i], ioaddr + CSR12);
316 }
317 tmp_info = get_u16(&misc_info[1]);
318 if (tmp_info)
319 tp->advertising[phy_num] = tmp_info | 1;
320 if (tmp_info && startup < 2) {
321 if (tp->mii_advertise == 0)
322 tp->mii_advertise = tp->advertising[phy_num];
323 if (tulip_debug > 1)
324 printk(KERN_DEBUG "%s: Advertising %4.4x on MII %d.\n",
325 dev->name, tp->mii_advertise, tp->phys[phy_num]);
326 tulip_mdio_write(dev, tp->phys[phy_num], 4, tp->mii_advertise);
327 }
328 break;
329 }
330 case 5: case 6: {
331 u16 setup[5];
332
333 new_csr6 = 0; /* FIXME */
334
335 for (i = 0; i < 5; i++)
336 setup[i] = get_u16(&p[i*2 + 1]);
337
338 if (startup && mtable->has_reset) {
339 struct medialeaf *rleaf = &mtable->mleaf[mtable->has_reset];
340 unsigned char *rst = rleaf->leafdata;
341 if (tulip_debug > 1)
342 printk(KERN_DEBUG "%s: Resetting the transceiver.\n",
343 dev->name);
344 for (i = 0; i < rst[0]; i++)
345 iowrite32(get_u16(rst + 1 + (i<<1)) << 16, ioaddr + CSR15);
346 }
347
348 break;
349 }
350 default:
351 printk(KERN_DEBUG "%s: Invalid media table selection %d.\n",
352 dev->name, mleaf->type);
353 new_csr6 = 0x020E0000;
354 }
355 if (tulip_debug > 1)
356 printk(KERN_DEBUG "%s: Using media type %s, CSR12 is %2.2x.\n",
357 dev->name, medianame[dev->if_port],
358 ioread32(ioaddr + CSR12) & 0xff);
359 } else if (tp->chip_id == LC82C168) {
360 if (startup && ! tp->medialock)
361 dev->if_port = tp->mii_cnt ? 11 : 0;
362 if (tulip_debug > 1)
363 printk(KERN_DEBUG "%s: PNIC PHY status is %3.3x, media %s.\n",
364 dev->name, ioread32(ioaddr + 0xB8), medianame[dev->if_port]);
365 if (tp->mii_cnt) {
366 new_csr6 = 0x810C0000;
367 iowrite32(0x0001, ioaddr + CSR15);
368 iowrite32(0x0201B07A, ioaddr + 0xB8);
369 } else if (startup) {
370 /* Start with 10mbps to do autonegotiation. */
371 iowrite32(0x32, ioaddr + CSR12);
372 new_csr6 = 0x00420000;
373 iowrite32(0x0001B078, ioaddr + 0xB8);
374 iowrite32(0x0201B078, ioaddr + 0xB8);
375 } else if (dev->if_port == 3 || dev->if_port == 5) {
376 iowrite32(0x33, ioaddr + CSR12);
377 new_csr6 = 0x01860000;
378 /* Trigger autonegotiation. */
379 iowrite32(startup ? 0x0201F868 : 0x0001F868, ioaddr + 0xB8);
380 } else {
381 iowrite32(0x32, ioaddr + CSR12);
382 new_csr6 = 0x00420000;
383 iowrite32(0x1F078, ioaddr + 0xB8);
384 }
385 } else { /* Unknown chip type with no media table. */
386 if (tp->default_port == 0)
387 dev->if_port = tp->mii_cnt ? 11 : 3;
388 if (tulip_media_cap[dev->if_port] & MediaIsMII) {
389 new_csr6 = 0x020E0000;
390 } else if (tulip_media_cap[dev->if_port] & MediaIsFx) {
391 new_csr6 = 0x02860000;
392 } else
393 new_csr6 = 0x03860000;
394 if (tulip_debug > 1)
395 printk(KERN_DEBUG "%s: No media description table, assuming "
396 "%s transceiver, CSR12 %2.2x.\n",
397 dev->name, medianame[dev->if_port],
398 ioread32(ioaddr + CSR12));
399 }
400
401 tp->csr6 = new_csr6 | (tp->csr6 & 0xfdff) | (tp->full_duplex ? 0x0200 : 0);
402 return;
403 }
404
405 /*
406 Check the MII negotiated duplex and change the CSR6 setting if
407 required.
408 Return 0 if everything is OK.
409 Return < 0 if the transceiver is missing or has no link beat.
410 */
411 int tulip_check_duplex(struct net_device *dev)
412 {
413 struct tulip_private *tp = netdev_priv(dev);
414 unsigned int bmsr, lpa, negotiated, new_csr6;
415
416 bmsr = tulip_mdio_read(dev, tp->phys[0], MII_BMSR);
417 lpa = tulip_mdio_read(dev, tp->phys[0], MII_LPA);
418 if (tulip_debug > 1)
419 printk(KERN_INFO "%s: MII status %4.4x, Link partner report "
420 "%4.4x.\n", dev->name, bmsr, lpa);
421 if (bmsr == 0xffff)
422 return -2;
423 if ((bmsr & BMSR_LSTATUS) == 0) {
424 int new_bmsr = tulip_mdio_read(dev, tp->phys[0], MII_BMSR);
425 if ((new_bmsr & BMSR_LSTATUS) == 0) {
426 if (tulip_debug > 1)
427 printk(KERN_INFO "%s: No link beat on the MII interface,"
428 " status %4.4x.\n", dev->name, new_bmsr);
429 return -1;
430 }
431 }
432 negotiated = lpa & tp->advertising[0];
433 tp->full_duplex = mii_duplex(tp->full_duplex_lock, negotiated);
434
435 new_csr6 = tp->csr6;
436
437 if (negotiated & LPA_100) new_csr6 &= ~TxThreshold;
438 else new_csr6 |= TxThreshold;
439 if (tp->full_duplex) new_csr6 |= FullDuplex;
440 else new_csr6 &= ~FullDuplex;
441
442 if (new_csr6 != tp->csr6) {
443 tp->csr6 = new_csr6;
444 tulip_restart_rxtx(tp);
445
446 if (tulip_debug > 0)
447 printk(KERN_INFO "%s: Setting %s-duplex based on MII"
448 "#%d link partner capability of %4.4x.\n",
449 dev->name, tp->full_duplex ? "full" : "half",
450 tp->phys[0], lpa);
451 return 1;
452 }
453
454 return 0;
455 }
456
457 void __devinit tulip_find_mii (struct net_device *dev, int board_idx)
458 {
459 struct tulip_private *tp = netdev_priv(dev);
460 int phyn, phy_idx = 0;
461 int mii_reg0;
462 int mii_advert;
463 unsigned int to_advert, new_bmcr, ane_switch;
464
465 /* Find the connected MII xcvrs.
466 Doing this in open() would allow detecting external xcvrs later,
467 but takes much time. */
468 for (phyn = 1; phyn <= 32 && phy_idx < sizeof (tp->phys); phyn++) {
469 int phy = phyn & 0x1f;
470 int mii_status = tulip_mdio_read (dev, phy, MII_BMSR);
471 if ((mii_status & 0x8301) == 0x8001 ||
472 ((mii_status & BMSR_100BASE4) == 0
473 && (mii_status & 0x7800) != 0)) {
474 /* preserve Becker logic, gain indentation level */
475 } else {
476 continue;
477 }
478
479 mii_reg0 = tulip_mdio_read (dev, phy, MII_BMCR);
480 mii_advert = tulip_mdio_read (dev, phy, MII_ADVERTISE);
481 ane_switch = 0;
482
483 /* if not advertising at all, gen an
484 * advertising value from the capability
485 * bits in BMSR
486 */
487 if ((mii_advert & ADVERTISE_ALL) == 0) {
488 unsigned int tmpadv = tulip_mdio_read (dev, phy, MII_BMSR);
489 mii_advert = ((tmpadv >> 6) & 0x3e0) | 1;
490 }
491
492 if (tp->mii_advertise) {
493 tp->advertising[phy_idx] =
494 to_advert = tp->mii_advertise;
495 } else if (tp->advertising[phy_idx]) {
496 to_advert = tp->advertising[phy_idx];
497 } else {
498 tp->advertising[phy_idx] =
499 tp->mii_advertise =
500 to_advert = mii_advert;
501 }
502
503 tp->phys[phy_idx++] = phy;
504
505 printk (KERN_INFO "tulip%d: MII transceiver #%d "
506 "config %4.4x status %4.4x advertising %4.4x.\n",
507 board_idx, phy, mii_reg0, mii_status, mii_advert);
508
509 /* Fixup for DLink with miswired PHY. */
510 if (mii_advert != to_advert) {
511 printk (KERN_DEBUG "tulip%d: Advertising %4.4x on PHY %d,"
512 " previously advertising %4.4x.\n",
513 board_idx, to_advert, phy, mii_advert);
514 tulip_mdio_write (dev, phy, 4, to_advert);
515 }
516
517 /* Enable autonegotiation: some boards default to off. */
518 if (tp->default_port == 0) {
519 new_bmcr = mii_reg0 | BMCR_ANENABLE;
520 if (new_bmcr != mii_reg0) {
521 new_bmcr |= BMCR_ANRESTART;
522 ane_switch = 1;
523 }
524 }
525 /* ...or disable nway, if forcing media */
526 else {
527 new_bmcr = mii_reg0 & ~BMCR_ANENABLE;
528 if (new_bmcr != mii_reg0)
529 ane_switch = 1;
530 }
531
532 /* clear out bits we never want at this point */
533 new_bmcr &= ~(BMCR_CTST | BMCR_FULLDPLX | BMCR_ISOLATE |
534 BMCR_PDOWN | BMCR_SPEED100 | BMCR_LOOPBACK |
535 BMCR_RESET);
536
537 if (tp->full_duplex)
538 new_bmcr |= BMCR_FULLDPLX;
539 if (tulip_media_cap[tp->default_port] & MediaIs100)
540 new_bmcr |= BMCR_SPEED100;
541
542 if (new_bmcr != mii_reg0) {
543 /* some phys need the ANE switch to
544 * happen before forced media settings
545 * will "take." However, we write the
546 * same value twice in order not to
547 * confuse the sane phys.
548 */
549 if (ane_switch) {
550 tulip_mdio_write (dev, phy, MII_BMCR, new_bmcr);
551 udelay (10);
552 }
553 tulip_mdio_write (dev, phy, MII_BMCR, new_bmcr);
554 }
555 }
556 tp->mii_cnt = phy_idx;
557 if (tp->mtable && tp->mtable->has_mii && phy_idx == 0) {
558 printk (KERN_INFO "tulip%d: ***WARNING***: No MII transceiver found!\n",
559 board_idx);
560 tp->phys[0] = 1;
561 }
562 }
Verdex Pro support