drivers/net/tulip/tulip.h

   1 /*
   2         drivers/net/tulip/tulip.h
   3
   4         Copyright 2000,2001  The Linux Kernel Team
   5         Written/copyright 1994-2001 by Donald Becker.
   6
   7         This software may be used and distributed according to the terms
   8         of the GNU General Public License, incorporated herein by reference.
   9
  10         Please refer to Documentation/DocBook/tulip-user.{pdf,ps,html}
  11         for more information on this driver, or visit the project
  12         Web page at http://sourceforge.net/projects/tulip/
  13
  14 */
  15
  16 #ifndef __NET_TULIP_H__
  17 #define __NET_TULIP_H__
  18
  19 #include <linux/config.h>
  20 #include <linux/kernel.h>
  21 #include <linux/types.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/netdevice.h>
  24 #include <linux/timer.h>
  25 #include <linux/delay.h>
  26 #include <asm/io.h>
  27 #include <asm/irq.h>
  28
  29
  30
  31 /* undefine, or define to various debugging levels (>4 == obscene levels) */
  32 #define TULIP_DEBUG 1
  33
  34 /* undefine USE_IO_OPS for MMIO, define for PIO */
  35 #ifdef CONFIG_TULIP_MMIO
  36 # undef USE_IO_OPS
  37 #else
  38 # define USE_IO_OPS 1
  39 #endif
  40
  41
  42
  43 struct tulip_chip_table {
  44         char *chip_name;
  45         int io_size;
  46         int valid_intrs;        /* CSR7 interrupt enable settings */
  47         int flags;
  48         void (*media_timer) (unsigned long data);
  49 };
  50
  51
  52 enum tbl_flag {
  53         HAS_MII                 = 0x0001,
  54         HAS_MEDIA_TABLE         = 0x0002,
  55         CSR12_IN_SROM           = 0x0004,
  56         ALWAYS_CHECK_MII        = 0x0008,
  57         HAS_ACPI                = 0x0010,
  58         MC_HASH_ONLY            = 0x0020, /* Hash-only multicast filter. */
  59         HAS_PNICNWAY            = 0x0080,
  60         HAS_NWAY                = 0x0040, /* Uses internal NWay xcvr. */
  61         HAS_INTR_MITIGATION     = 0x0100,
  62         IS_ASIX                 = 0x0200,
  63         HAS_8023X               = 0x0400,
  64         COMET_MAC_ADDR          = 0x0800,
  65         HAS_PCI_MWI             = 0x1000,
  66         HAS_PHY_IRQ             = 0x2000,
  67         HAS_SWAPPED_SEEPROM     = 0x4000,
  68         NEEDS_FAKE_MEDIA_TABLE  = 0x8000,
  69 };
  70
  71
  72 /* chip types.  careful!  order is VERY IMPORTANT here, as these
  73  * are used throughout the driver as indices into arrays */
  74 /* Note 21142 == 21143. */
  75 enum chips {
  76         DC21040 = 0,
  77         DC21041 = 1,
  78         DC21140 = 2,
  79         DC21142 = 3, DC21143 = 3,
  80         LC82C168,
  81         MX98713,
  82         MX98715,
  83         MX98725,
  84         AX88140,
  85         PNIC2,
  86         COMET,
  87         COMPEX9881,
  88         I21145,
  89         DM910X,
  90         CONEXANT,
  91         ULI526X
  92 };
  93
  94
  95 enum MediaIs {
  96         MediaIsFD = 1,
  97         MediaAlwaysFD = 2,
  98         MediaIsMII = 4,
  99         MediaIsFx = 8,
 100         MediaIs100 = 16
 101 };
 102
 103
 104 /* Offsets to the Command and Status Registers, "CSRs".  All accesses
 105    must be longword instructions and quadword aligned. */
 106 enum tulip_offsets {
 107         CSR0 = 0,
 108         CSR1 = 0x08,
 109         CSR2 = 0x10,
 110         CSR3 = 0x18,
 111         CSR4 = 0x20,
 112         CSR5 = 0x28,
 113         CSR6 = 0x30,
 114         CSR7 = 0x38,
 115         CSR8 = 0x40,
 116         CSR9 = 0x48,
 117         CSR10 = 0x50,
 118         CSR11 = 0x58,
 119         CSR12 = 0x60,
 120         CSR13 = 0x68,
 121         CSR14 = 0x70,
 122         CSR15 = 0x78,
 123 };
 124
 125 /* register offset and bits for CFDD PCI config reg */
 126 enum pci_cfg_driver_reg {
 127         CFDD = 0x40,
 128         CFDD_Sleep = (1 << 31),
 129         CFDD_Snooze = (1 << 30),
 130 };
 131
 132 #define RxPollInt (RxIntr|RxNoBuf|RxDied|RxJabber)
 133
 134 /* The bits in the CSR5 status registers, mostly interrupt sources. */
 135 enum status_bits {
 136         TimerInt = 0x800,
 137         SytemError = 0x2000,
 138         TPLnkFail = 0x1000,
 139         TPLnkPass = 0x10,
 140         NormalIntr = 0x10000,
 141         AbnormalIntr = 0x8000,
 142         RxJabber = 0x200,
 143         RxDied = 0x100,
 144         RxNoBuf = 0x80,
 145         RxIntr = 0x40,
 146         TxFIFOUnderflow = 0x20,
 147         TxJabber = 0x08,
 148         TxNoBuf = 0x04,
 149         TxDied = 0x02,
 150         TxIntr = 0x01,
 151 };
 152
 153 /* bit mask for CSR5 TX/RX process state */
 154 #define CSR5_TS 0x00700000
 155 #define CSR5_RS 0x000e0000
 156
 157 enum tulip_mode_bits {
 158         TxThreshold             = (1 << 22),
 159         FullDuplex              = (1 << 9),
 160         TxOn                    = 0x2000,
 161         AcceptBroadcast         = 0x0100,
 162         AcceptAllMulticast      = 0x0080,
 163         AcceptAllPhys           = 0x0040,
 164         AcceptRunt              = 0x0008,
 165         RxOn                    = 0x0002,
 166         RxTx                    = (TxOn | RxOn),
 167 };
 168
 169
 170 enum tulip_busconfig_bits {
 171         MWI                     = (1 << 24),
 172         MRL                     = (1 << 23),
 173         MRM                     = (1 << 21),
 174         CALShift                = 14,
 175         BurstLenShift           = 8,
 176 };
 177
 178
 179 /* The Tulip Rx and Tx buffer descriptors. */
 180 struct tulip_rx_desc {
 181         s32 status;
 182         s32 length;
 183         u32 buffer1;
 184         u32 buffer2;
 185 };
 186
 187
 188 struct tulip_tx_desc {
 189         s32 status;
 190         s32 length;
 191         u32 buffer1;
 192         u32 buffer2;            /* We use only buffer 1.  */
 193 };
 194
 195
 196 enum desc_status_bits {
 197         DescOwned = 0x80000000,
 198         RxDescFatalErr = 0x8000,
 199         RxWholePkt = 0x0300,
 200 };
 201
 202
 203 enum t21143_csr6_bits {
 204         csr6_sc = (1<<31),
 205         csr6_ra = (1<<30),
 206         csr6_ign_dest_msb = (1<<26),
 207         csr6_mbo = (1<<25),
 208         csr6_scr = (1<<24),  /* scramble mode flag: can't be set */
 209         csr6_pcs = (1<<23),  /* Enables PCS functions (symbol mode requires csr6_ps be set) default is set */
 210         csr6_ttm = (1<<22),  /* Transmit Threshold Mode, set for 10baseT, 0 for 100BaseTX */
 211         csr6_sf = (1<<21),   /* Store and forward. If set ignores TR bits */
 212         csr6_hbd = (1<<19),  /* Heart beat disable. Disables SQE function in 10baseT */
 213         csr6_ps = (1<<18),   /* Port Select. 0 (defualt) = 10baseT, 1 = 100baseTX: can't be set */
 214         csr6_ca = (1<<17),   /* Collision Offset Enable. If set uses special algorithm in low collision situations */
 215         csr6_trh = (1<<15),  /* Transmit Threshold high bit */
 216         csr6_trl = (1<<14),  /* Transmit Threshold low bit */
 217
 218         /***************************************************************
 219          * This table shows transmit threshold values based on media   *
 220          * and these two registers (from PNIC1 & 2 docs) Note: this is *
 221          * all meaningless if sf is set.                               *
 222          ***************************************************************/
 223
 224         /***********************************
 225          * (trh,trl) * 100BaseTX * 10BaseT *
 226          ***********************************
 227          *   (0,0)   *     128   *    72   *
 228          *   (0,1)   *     256   *    96   *
 229          *   (1,0)   *     512   *   128   *
 230          *   (1,1)   *    1024   *   160   *
 231          ***********************************/
 232
 233         csr6_fc = (1<<12),   /* Forces a collision in next transmission (for testing in loopback mode) */
 234         csr6_om_int_loop = (1<<10), /* internal (FIFO) loopback flag */
 235         csr6_om_ext_loop = (1<<11), /* external (PMD) loopback flag */
 236         /* set both and you get (PHY) loopback */
 237         csr6_fd = (1<<9),    /* Full duplex mode, disables hearbeat, no loopback */
 238         csr6_pm = (1<<7),    /* Pass All Multicast */
 239         csr6_pr = (1<<6),    /* Promiscuous mode */
 240         csr6_sb = (1<<5),    /* Start(1)/Stop(0) backoff counter */
 241         csr6_if = (1<<4),    /* Inverse Filtering, rejects only addresses in address table: can't be set */
 242         csr6_pb = (1<<3),    /* Pass Bad Frames, (1) causes even bad frames to be passed on */
 243         csr6_ho = (1<<2),    /* Hash-only filtering mode: can't be set */
 244         csr6_hp = (1<<0),    /* Hash/Perfect Receive Filtering Mode: can't be set */
 245
 246         csr6_mask_capture = (csr6_sc | csr6_ca),
 247         csr6_mask_defstate = (csr6_mask_capture | csr6_mbo),
 248         csr6_mask_hdcap = (csr6_mask_defstate | csr6_hbd | csr6_ps),
 249         csr6_mask_hdcaptt = (csr6_mask_hdcap  | csr6_trh | csr6_trl),
 250         csr6_mask_fullcap = (csr6_mask_hdcaptt | csr6_fd),
 251         csr6_mask_fullpromisc = (csr6_pr | csr6_pm),
 252         csr6_mask_filters = (csr6_hp | csr6_ho | csr6_if),
 253         csr6_mask_100bt = (csr6_scr | csr6_pcs | csr6_hbd),
 254 };
 255
 256
 257 /* Keep the ring sizes a power of two for efficiency.
 258    Making the Tx ring too large decreases the effectiveness of channel
 259    bonding and packet priority.
 260    There are no ill effects from too-large receive rings. */
 261
 262 #define TX_RING_SIZE    32
 263 #define RX_RING_SIZE    128
 264 #define MEDIA_MASK     31
 265
 266 #define PKT_BUF_SZ              1536    /* Size of each temporary Rx buffer. */
 267
 268 #define TULIP_MIN_CACHE_LINE    8       /* in units of 32-bit words */
 269
 270 #if defined(__sparc__) || defined(__hppa__)
 271 /* The UltraSparc PCI controllers will disconnect at every 64-byte
 272  * crossing anyways so it makes no sense to tell Tulip to burst
 273  * any more than that.
 274  */
 275 #define TULIP_MAX_CACHE_LINE    16      /* in units of 32-bit words */
 276 #else
 277 #define TULIP_MAX_CACHE_LINE    32      /* in units of 32-bit words */
 278 #endif
 279
 280
 281 /* Ring-wrap flag in length field, use for last ring entry.
 282         0x01000000 means chain on buffer2 address,
 283         0x02000000 means use the ring start address in CSR2/3.
 284    Note: Some work-alike chips do not function correctly in chained mode.
 285    The ASIX chip works only in chained mode.
 286    Thus we indicates ring mode, but always write the 'next' field for
 287    chained mode as well.
 288 */
 289 #define DESC_RING_WRAP 0x02000000
 290
 291
 292 #define EEPROM_SIZE 512         /* 2 << EEPROM_ADDRLEN */
 293
 294
 295 #define RUN_AT(x) (jiffies + (x))
 296
 297 #if defined(__i386__)                   /* AKA get_unaligned() */
 298 #define get_u16(ptr) (*(u16 *)(ptr))
 299 #else
 300 #define get_u16(ptr) (((u8*)(ptr))[0] + (((u8*)(ptr))[1]<<8))
 301 #endif
 302
 303 struct medialeaf {
 304         u8 type;
 305         u8 media;
 306         unsigned char *leafdata;
 307 };
 308
 309
 310 struct mediatable {
 311         u16 defaultmedia;
 312         u8 leafcount;
 313         u8 csr12dir;            /* General purpose pin directions. */
 314         unsigned has_mii:1;
 315         unsigned has_nonmii:1;
 316         unsigned has_reset:6;
 317         u32 csr15dir;
 318         u32 csr15val;           /* 21143 NWay setting. */
 319         struct medialeaf mleaf[0];
 320 };
 321
 322
 323 struct mediainfo {
 324         struct mediainfo *next;
 325         int info_type;
 326         int index;
 327         unsigned char *info;
 328 };
 329
 330 struct ring_info {
 331         struct sk_buff  *skb;
 332         dma_addr_t      mapping;
 333 };
 334
 335
 336 struct tulip_private {
 337         const char *product_name;
 338         struct net_device *next_module;
 339         struct tulip_rx_desc *rx_ring;
 340         struct tulip_tx_desc *tx_ring;
 341         dma_addr_t rx_ring_dma;
 342         dma_addr_t tx_ring_dma;
 343         /* The saved address of a sent-in-place packet/buffer, for skfree(). */
 344         struct ring_info tx_buffers[TX_RING_SIZE];
 345         /* The addresses of receive-in-place skbuffs. */
 346         struct ring_info rx_buffers[RX_RING_SIZE];
 347         u16 setup_frame[96];    /* Pseudo-Tx frame to init address table. */
 348         int chip_id;
 349         int revision;
 350         int flags;
 351         struct net_device_stats stats;
 352         struct timer_list timer;        /* Media selection timer. */
 353         struct timer_list oom_timer;    /* Out of memory timer. */
 354         u32 mc_filter[2];
 355         spinlock_t lock;
 356         spinlock_t mii_lock;
 357         unsigned int cur_rx, cur_tx;    /* The next free ring entry */
 358         unsigned int dirty_rx, dirty_tx;        /* The ring entries to be free()ed. */
 359
 360 #ifdef  CONFIG_TULIP_NAPI_HW_MITIGATION
 361         int mit_on;
 362 #endif
 363         unsigned int full_duplex:1;     /* Full-duplex operation requested. */
 364         unsigned int full_duplex_lock:1;
 365         unsigned int fake_addr:1;       /* Multiport board faked address. */
 366         unsigned int default_port:4;    /* Last dev->if_port value. */
 367         unsigned int media2:4;  /* Secondary monitored media port. */
 368         unsigned int medialock:1;       /* Don't sense media type. */
 369         unsigned int mediasense:1;      /* Media sensing in progress. */
 370         unsigned int nway:1, nwayset:1;         /* 21143 internal NWay. */
 371         unsigned int csr0;      /* CSR0 setting. */
 372         unsigned int csr6;      /* Current CSR6 control settings. */
 373         unsigned char eeprom[EEPROM_SIZE];      /* Serial EEPROM contents. */
 374         void (*link_change) (struct net_device * dev, int csr5);
 375         u16 sym_advertise, mii_advertise; /* NWay capabilities advertised.  */
 376         u16 lpar;               /* 21143 Link partner ability. */
 377         u16 advertising[4];
 378         signed char phys[4], mii_cnt;   /* MII device addresses. */
 379         struct mediatable *mtable;
 380         int cur_index;          /* Current media index. */
 381         int saved_if_port;
 382         struct pci_dev *pdev;
 383         int ttimer;
 384         int susp_rx;
 385         unsigned long nir;
 386         void __iomem *base_addr;
 387         int csr12_shadow;
 388         int pad0;               /* Used for 8-byte alignment */
 389 };
 390
 391
 392 struct eeprom_fixup {
 393         char *name;
 394         unsigned char addr0;
 395         unsigned char addr1;
 396         unsigned char addr2;
 397         u16 newtable[32];       /* Max length below. */
 398 };
 399
 400
 401 /* 21142.c */
 402 extern u16 t21142_csr14[];
 403 void t21142_timer(unsigned long data);
 404 void t21142_start_nway(struct net_device *dev);
 405 void t21142_lnk_change(struct net_device *dev, int csr5);
 406
 407
 408 /* PNIC2.c */
 409 void pnic2_lnk_change(struct net_device *dev, int csr5);
 410 void pnic2_timer(unsigned long data);
 411 void pnic2_start_nway(struct net_device *dev);
 412 void pnic2_lnk_change(struct net_device *dev, int csr5);
 413
 414 /* eeprom.c */
 415 void tulip_parse_eeprom(struct net_device *dev);
 416 int tulip_read_eeprom(struct net_device *dev, int location, int addr_len);
 417
 418 /* interrupt.c */
 419 extern unsigned int tulip_max_interrupt_work;
 420 extern int tulip_rx_copybreak;
 421 irqreturn_t tulip_interrupt(int irq, void *dev_instance, struct pt_regs *regs);
 422 int tulip_refill_rx(struct net_device *dev);
 423 #ifdef CONFIG_TULIP_NAPI
 424 int tulip_poll(struct net_device *dev, int *budget);
 425 #endif
 426
 427
 428 /* media.c */
 429 int tulip_mdio_read(struct net_device *dev, int phy_id, int location);
 430 void tulip_mdio_write(struct net_device *dev, int phy_id, int location, int value);
 431 void tulip_select_media(struct net_device *dev, int startup);
 432 int tulip_check_duplex(struct net_device *dev);
 433 void tulip_find_mii (struct net_device *dev, int board_idx);
 434
 435 /* pnic.c */
 436 void pnic_do_nway(struct net_device *dev);
 437 void pnic_lnk_change(struct net_device *dev, int csr5);
 438 void pnic_timer(unsigned long data);
 439
 440 /* timer.c */
 441 void tulip_timer(unsigned long data);
 442 void mxic_timer(unsigned long data);
 443 void comet_timer(unsigned long data);
 444
 445 /* tulip_core.c */
 446 extern int tulip_debug;
 447 extern const char * const medianame[];
 448 extern const char tulip_media_cap[];
 449 extern struct tulip_chip_table tulip_tbl[];
 450 void oom_timer(unsigned long data);
 451 extern u8 t21040_csr13[];
 452
 453 static inline void tulip_start_rxtx(struct tulip_private *tp)
 454 {
 455         void __iomem *ioaddr = tp->base_addr;
 456         iowrite32(tp->csr6 | RxTx, ioaddr + CSR6);
 457         barrier();
 458         (void) ioread32(ioaddr + CSR6); /* mmio sync */
 459 }
 460
 461 static inline void tulip_stop_rxtx(struct tulip_private *tp)
 462 {
 463         void __iomem *ioaddr = tp->base_addr;
 464         u32 csr6 = ioread32(ioaddr + CSR6);
 465
 466         if (csr6 & RxTx) {
 467                 unsigned i=1300/10;
 468                 iowrite32(csr6 & ~RxTx, ioaddr + CSR6);
 469                 barrier();
 470                 /* wait until in-flight frame completes.
 471                  * Max time @ 10BT: 1500*8b/10Mbps == 1200us (+ 100us margin)
 472                  * Typically expect this loop to end in < 50 us on 100BT.
 473                  */
 474                 while (--i && (ioread32(ioaddr + CSR5) & (CSR5_TS|CSR5_RS)))
 475                         udelay(10);
 476
 477                 if (!i)
 478                         printk(KERN_DEBUG "%s: tulip_stop_rxtx() failed\n",
 479                                         pci_name(tp->pdev));
 480         }
 481 }
 482
 483 static inline void tulip_restart_rxtx(struct tulip_private *tp)
 484 {
 485         if(!(tp->chip_id == ULI526X &&
 486                 (tp->revision == 0x40 || tp->revision == 0x50))) {
 487                 tulip_stop_rxtx(tp);
 488                 udelay(5);
 489         }
 490         tulip_start_rxtx(tp);
 491 }
 492
 493 #endif /* __NET_TULIP_H__ */