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[TG3]: Set minimal hw interrupt mitigation.
[linux-2.6/verdex.git] / drivers / net / tulip / tulip_core.c
blobe0ae3ed6e5785832794a8cb32dec13d1d592f5cc
1 /* tulip_core.c: A DEC 21x4x-family ethernet driver for Linux. */
2
3 /*
4 Maintained by Jeff Garzik <jgarzik@pobox.com>
5 Copyright 2000,2001 The Linux Kernel Team
6 Written/copyright 1994-2001 by Donald Becker.
7
8 This software may be used and distributed according to the terms
9 of the GNU General Public License, incorporated herein by reference.
10
11 Please refer to Documentation/DocBook/tulip-user.{pdf,ps,html}
12 for more information on this driver, or visit the project
13 Web page at http://sourceforge.net/projects/tulip/
14
15 */
16
17 #include <linux/config.h>
18
19 #define DRV_NAME "tulip"
20 #ifdef CONFIG_TULIP_NAPI
21 #define DRV_VERSION "1.1.13-NAPI" /* Keep at least for test */
22 #else
23 #define DRV_VERSION "1.1.13"
24 #endif
25 #define DRV_RELDATE "May 11, 2002"
26
27
28 #include <linux/module.h>
29 #include <linux/pci.h>
30 #include "tulip.h"
31 #include <linux/init.h>
32 #include <linux/etherdevice.h>
33 #include <linux/delay.h>
34 #include <linux/mii.h>
35 #include <linux/ethtool.h>
36 #include <linux/crc32.h>
37 #include <asm/unaligned.h>
38 #include <asm/uaccess.h>
39
40 #ifdef __sparc__
41 #include <asm/pbm.h>
42 #endif
43
44 static char version[] __devinitdata =
45 "Linux Tulip driver version " DRV_VERSION " (" DRV_RELDATE ")\n";
46
47
48 /* A few user-configurable values. */
49
50 /* Maximum events (Rx packets, etc.) to handle at each interrupt. */
51 static unsigned int max_interrupt_work = 25;
52
53 #define MAX_UNITS 8
54 /* Used to pass the full-duplex flag, etc. */
55 static int full_duplex[MAX_UNITS];
56 static int options[MAX_UNITS];
57 static int mtu[MAX_UNITS]; /* Jumbo MTU for interfaces. */
58
59 /* The possible media types that can be set in options[] are: */
60 const char * const medianame[32] = {
61 "10baseT", "10base2", "AUI", "100baseTx",
62 "10baseT-FDX", "100baseTx-FDX", "100baseT4", "100baseFx",
63 "100baseFx-FDX", "MII 10baseT", "MII 10baseT-FDX", "MII",
64 "10baseT(forced)", "MII 100baseTx", "MII 100baseTx-FDX", "MII 100baseT4",
65 "MII 100baseFx-HDX", "MII 100baseFx-FDX", "Home-PNA 1Mbps", "Invalid-19",
66 "","","","", "","","","", "","","","Transceiver reset",
67 };
68
69 /* Set the copy breakpoint for the copy-only-tiny-buffer Rx structure. */
70 #if defined(__alpha__) || defined(__arm__) || defined(__hppa__) \
71 || defined(__sparc_) || defined(__ia64__) \
72 || defined(__sh__) || defined(__mips__)
73 static int rx_copybreak = 1518;
74 #else
75 static int rx_copybreak = 100;
76 #endif
77
78 /*
79 Set the bus performance register.
80 Typical: Set 16 longword cache alignment, no burst limit.
81 Cache alignment bits 15:14 Burst length 13:8
82 0000 No alignment 0x00000000 unlimited 0800 8 longwords
83 4000 8 longwords 0100 1 longword 1000 16 longwords
84 8000 16 longwords 0200 2 longwords 2000 32 longwords
85 C000 32 longwords 0400 4 longwords
86 Warning: many older 486 systems are broken and require setting 0x00A04800
87 8 longword cache alignment, 8 longword burst.
88 ToDo: Non-Intel setting could be better.
89 */
90
91 #if defined(__alpha__) || defined(__ia64__)
92 static int csr0 = 0x01A00000 | 0xE000;
93 #elif defined(__i386__) || defined(__powerpc__) || defined(__x86_64__)
94 static int csr0 = 0x01A00000 | 0x8000;
95 #elif defined(__sparc__) || defined(__hppa__)
96 /* The UltraSparc PCI controllers will disconnect at every 64-byte
97 * crossing anyways so it makes no sense to tell Tulip to burst
98 * any more than that.
99 */
100 static int csr0 = 0x01A00000 | 0x9000;
101 #elif defined(__arm__) || defined(__sh__)
102 static int csr0 = 0x01A00000 | 0x4800;
103 #elif defined(__mips__)
104 static int csr0 = 0x00200000 | 0x4000;
105 #else
106 #warning Processor architecture undefined!
107 static int csr0 = 0x00A00000 | 0x4800;
108 #endif
109
110 /* Operational parameters that usually are not changed. */
111 /* Time in jiffies before concluding the transmitter is hung. */
112 #define TX_TIMEOUT (4*HZ)
113
114
115 MODULE_AUTHOR("The Linux Kernel Team");
116 MODULE_DESCRIPTION("Digital 21*4* Tulip ethernet driver");
117 MODULE_LICENSE("GPL");
118 MODULE_VERSION(DRV_VERSION);
119 module_param(tulip_debug, int, 0);
120 module_param(max_interrupt_work, int, 0);
121 module_param(rx_copybreak, int, 0);
122 module_param(csr0, int, 0);
123 module_param_array(options, int, NULL, 0);
124 module_param_array(full_duplex, int, NULL, 0);
125
126 #define PFX DRV_NAME ": "
127
128 #ifdef TULIP_DEBUG
129 int tulip_debug = TULIP_DEBUG;
130 #else
131 int tulip_debug = 1;
132 #endif
133
134
135
136 /*
137 * This table use during operation for capabilities and media timer.
138 *
139 * It is indexed via the values in 'enum chips'
140 */
141
142 struct tulip_chip_table tulip_tbl[] = {
143 { }, /* placeholder for array, slot unused currently */
144 { }, /* placeholder for array, slot unused currently */
145
146 /* DC21140 */
147 { "Digital DS21140 Tulip", 128, 0x0001ebef,
148 HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM | HAS_PCI_MWI, tulip_timer },
149
150 /* DC21142, DC21143 */
151 { "Digital DS21143 Tulip", 128, 0x0801fbff,
152 HAS_MII | HAS_MEDIA_TABLE | ALWAYS_CHECK_MII | HAS_ACPI | HAS_NWAY
153 | HAS_INTR_MITIGATION | HAS_PCI_MWI, t21142_timer },
154
155 /* LC82C168 */
156 { "Lite-On 82c168 PNIC", 256, 0x0001fbef,
157 HAS_MII | HAS_PNICNWAY, pnic_timer },
158
159 /* MX98713 */
160 { "Macronix 98713 PMAC", 128, 0x0001ebef,
161 HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM, mxic_timer },
162
163 /* MX98715 */
164 { "Macronix 98715 PMAC", 256, 0x0001ebef,
165 HAS_MEDIA_TABLE, mxic_timer },
166
167 /* MX98725 */
168 { "Macronix 98725 PMAC", 256, 0x0001ebef,
169 HAS_MEDIA_TABLE, mxic_timer },
170
171 /* AX88140 */
172 { "ASIX AX88140", 128, 0x0001fbff,
173 HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM | MC_HASH_ONLY
174 | IS_ASIX, tulip_timer },
175
176 /* PNIC2 */
177 { "Lite-On PNIC-II", 256, 0x0801fbff,
178 HAS_MII | HAS_NWAY | HAS_8023X | HAS_PCI_MWI, pnic2_timer },
179
180 /* COMET */
181 { "ADMtek Comet", 256, 0x0001abef,
182 HAS_MII | MC_HASH_ONLY | COMET_MAC_ADDR, comet_timer },
183
184 /* COMPEX9881 */
185 { "Compex 9881 PMAC", 128, 0x0001ebef,
186 HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM, mxic_timer },
187
188 /* I21145 */
189 { "Intel DS21145 Tulip", 128, 0x0801fbff,
190 HAS_MII | HAS_MEDIA_TABLE | ALWAYS_CHECK_MII | HAS_ACPI
191 | HAS_NWAY | HAS_PCI_MWI, t21142_timer },
192
193 /* DM910X */
194 { "Davicom DM9102/DM9102A", 128, 0x0001ebef,
195 HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM | HAS_ACPI,
196 tulip_timer },
197
198 /* RS7112 */
199 { "Conexant LANfinity", 256, 0x0001ebef,
200 HAS_MII | HAS_ACPI, tulip_timer },
201
202 /* ULi526X */
203 { "ULi M5261/M5263", 128, 0x0001ebef,
204 HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM | HAS_ACPI, tulip_timer },
205 };
206
207
208 static struct pci_device_id tulip_pci_tbl[] = {
209 { 0x1011, 0x0009, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DC21140 },
210 { 0x1011, 0x0019, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DC21143 },
211 { 0x11AD, 0x0002, PCI_ANY_ID, PCI_ANY_ID, 0, 0, LC82C168 },
212 { 0x10d9, 0x0512, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MX98713 },
213 { 0x10d9, 0x0531, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MX98715 },
214 /* { 0x10d9, 0x0531, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MX98725 },*/
215 { 0x125B, 0x1400, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AX88140 },
216 { 0x11AD, 0xc115, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PNIC2 },
217 { 0x1317, 0x0981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
218 { 0x1317, 0x0985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
219 { 0x1317, 0x1985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
220 { 0x1317, 0x9511, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
221 { 0x13D1, 0xAB02, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
222 { 0x13D1, 0xAB03, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
223 { 0x13D1, 0xAB08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
224 { 0x104A, 0x0981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
225 { 0x104A, 0x2774, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
226 { 0x1259, 0xa120, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
227 { 0x11F6, 0x9881, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMPEX9881 },
228 { 0x8086, 0x0039, PCI_ANY_ID, PCI_ANY_ID, 0, 0, I21145 },
229 { 0x1282, 0x9100, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DM910X },
230 { 0x1282, 0x9102, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DM910X },
231 { 0x1113, 0x1216, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
232 { 0x1113, 0x1217, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MX98715 },
233 { 0x1113, 0x9511, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
234 { 0x1186, 0x1541, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
235 { 0x1186, 0x1561, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
236 { 0x1186, 0x1591, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
237 { 0x14f1, 0x1803, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CONEXANT },
238 { 0x1626, 0x8410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
239 { 0x1737, 0xAB09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
240 { 0x1737, 0xAB08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
241 { 0x17B3, 0xAB08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
242 { 0x10b9, 0x5261, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ULI526X }, /* ALi 1563 integrated ethernet */
243 { 0x10b9, 0x5263, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ULI526X }, /* ALi 1563 integrated ethernet */
244 { 0x10b7, 0x9300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET }, /* 3Com 3CSOHO100B-TX */
245 { } /* terminate list */
246 };
247 MODULE_DEVICE_TABLE(pci, tulip_pci_tbl);
248
249
250 /* A full-duplex map for media types. */
251 const char tulip_media_cap[32] =
252 {0,0,0,16, 3,19,16,24, 27,4,7,5, 0,20,23,20, 28,31,0,0, };
253
254 static void tulip_tx_timeout(struct net_device *dev);
255 static void tulip_init_ring(struct net_device *dev);
256 static int tulip_start_xmit(struct sk_buff *skb, struct net_device *dev);
257 static int tulip_open(struct net_device *dev);
258 static int tulip_close(struct net_device *dev);
259 static void tulip_up(struct net_device *dev);
260 static void tulip_down(struct net_device *dev);
261 static struct net_device_stats *tulip_get_stats(struct net_device *dev);
262 static int private_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
263 static void set_rx_mode(struct net_device *dev);
264 #ifdef CONFIG_NET_POLL_CONTROLLER
265 static void poll_tulip(struct net_device *dev);
266 #endif
267
268 static void tulip_set_power_state (struct tulip_private *tp,
269 int sleep, int snooze)
270 {
271 if (tp->flags & HAS_ACPI) {
272 u32 tmp, newtmp;
273 pci_read_config_dword (tp->pdev, CFDD, &tmp);
274 newtmp = tmp & ~(CFDD_Sleep | CFDD_Snooze);
275 if (sleep)
276 newtmp |= CFDD_Sleep;
277 else if (snooze)
278 newtmp |= CFDD_Snooze;
279 if (tmp != newtmp)
280 pci_write_config_dword (tp->pdev, CFDD, newtmp);
281 }
282
283 }
284
285
286 static void tulip_up(struct net_device *dev)
287 {
288 struct tulip_private *tp = netdev_priv(dev);
289 void __iomem *ioaddr = tp->base_addr;
290 int next_tick = 3*HZ;
291 int i;
292
293 /* Wake the chip from sleep/snooze mode. */
294 tulip_set_power_state (tp, 0, 0);
295
296 /* On some chip revs we must set the MII/SYM port before the reset!? */
297 if (tp->mii_cnt || (tp->mtable && tp->mtable->has_mii))
298 iowrite32(0x00040000, ioaddr + CSR6);
299
300 /* Reset the chip, holding bit 0 set at least 50 PCI cycles. */
301 iowrite32(0x00000001, ioaddr + CSR0);
302 udelay(100);
303
304 /* Deassert reset.
305 Wait the specified 50 PCI cycles after a reset by initializing
306 Tx and Rx queues and the address filter list. */
307 iowrite32(tp->csr0, ioaddr + CSR0);
308 udelay(100);
309
310 if (tulip_debug > 1)
311 printk(KERN_DEBUG "%s: tulip_up(), irq==%d.\n", dev->name, dev->irq);
312
313 iowrite32(tp->rx_ring_dma, ioaddr + CSR3);
314 iowrite32(tp->tx_ring_dma, ioaddr + CSR4);
315 tp->cur_rx = tp->cur_tx = 0;
316 tp->dirty_rx = tp->dirty_tx = 0;
317
318 if (tp->flags & MC_HASH_ONLY) {
319 u32 addr_low = le32_to_cpu(get_unaligned((u32 *)dev->dev_addr));
320 u32 addr_high = le16_to_cpu(get_unaligned((u16 *)(dev->dev_addr+4)));
321 if (tp->chip_id == AX88140) {
322 iowrite32(0, ioaddr + CSR13);
323 iowrite32(addr_low, ioaddr + CSR14);
324 iowrite32(1, ioaddr + CSR13);
325 iowrite32(addr_high, ioaddr + CSR14);
326 } else if (tp->flags & COMET_MAC_ADDR) {
327 iowrite32(addr_low, ioaddr + 0xA4);
328 iowrite32(addr_high, ioaddr + 0xA8);
329 iowrite32(0, ioaddr + 0xAC);
330 iowrite32(0, ioaddr + 0xB0);
331 }
332 } else {
333 /* This is set_rx_mode(), but without starting the transmitter. */
334 u16 *eaddrs = (u16 *)dev->dev_addr;
335 u16 *setup_frm = &tp->setup_frame[15*6];
336 dma_addr_t mapping;
337
338 /* 21140 bug: you must add the broadcast address. */
339 memset(tp->setup_frame, 0xff, sizeof(tp->setup_frame));
340 /* Fill the final entry of the table with our physical address. */
341 *setup_frm++ = eaddrs[0]; *setup_frm++ = eaddrs[0];
342 *setup_frm++ = eaddrs[1]; *setup_frm++ = eaddrs[1];
343 *setup_frm++ = eaddrs[2]; *setup_frm++ = eaddrs[2];
344
345 mapping = pci_map_single(tp->pdev, tp->setup_frame,
346 sizeof(tp->setup_frame),
347 PCI_DMA_TODEVICE);
348 tp->tx_buffers[tp->cur_tx].skb = NULL;
349 tp->tx_buffers[tp->cur_tx].mapping = mapping;
350
351 /* Put the setup frame on the Tx list. */
352 tp->tx_ring[tp->cur_tx].length = cpu_to_le32(0x08000000 | 192);
353 tp->tx_ring[tp->cur_tx].buffer1 = cpu_to_le32(mapping);
354 tp->tx_ring[tp->cur_tx].status = cpu_to_le32(DescOwned);
355
356 tp->cur_tx++;
357 }
358
359 tp->saved_if_port = dev->if_port;
360 if (dev->if_port == 0)
361 dev->if_port = tp->default_port;
362
363 /* Allow selecting a default media. */
364 i = 0;
365 if (tp->mtable == NULL)
366 goto media_picked;
367 if (dev->if_port) {
368 int looking_for = tulip_media_cap[dev->if_port] & MediaIsMII ? 11 :
369 (dev->if_port == 12 ? 0 : dev->if_port);
370 for (i = 0; i < tp->mtable->leafcount; i++)
371 if (tp->mtable->mleaf[i].media == looking_for) {
372 printk(KERN_INFO "%s: Using user-specified media %s.\n",
373 dev->name, medianame[dev->if_port]);
374 goto media_picked;
375 }
376 }
377 if ((tp->mtable->defaultmedia & 0x0800) == 0) {
378 int looking_for = tp->mtable->defaultmedia & MEDIA_MASK;
379 for (i = 0; i < tp->mtable->leafcount; i++)
380 if (tp->mtable->mleaf[i].media == looking_for) {
381 printk(KERN_INFO "%s: Using EEPROM-set media %s.\n",
382 dev->name, medianame[looking_for]);
383 goto media_picked;
384 }
385 }
386 /* Start sensing first non-full-duplex media. */
387 for (i = tp->mtable->leafcount - 1;
388 (tulip_media_cap[tp->mtable->mleaf[i].media] & MediaAlwaysFD) && i > 0; i--)
389 ;
390 media_picked:
391
392 tp->csr6 = 0;
393 tp->cur_index = i;
394 tp->nwayset = 0;
395
396 if (dev->if_port) {
397 if (tp->chip_id == DC21143 &&
398 (tulip_media_cap[dev->if_port] & MediaIsMII)) {
399 /* We must reset the media CSRs when we force-select MII mode. */
400 iowrite32(0x0000, ioaddr + CSR13);
401 iowrite32(0x0000, ioaddr + CSR14);
402 iowrite32(0x0008, ioaddr + CSR15);
403 }
404 tulip_select_media(dev, 1);
405 } else if (tp->chip_id == DC21142) {
406 if (tp->mii_cnt) {
407 tulip_select_media(dev, 1);
408 if (tulip_debug > 1)
409 printk(KERN_INFO "%s: Using MII transceiver %d, status "
410 "%4.4x.\n",
411 dev->name, tp->phys[0], tulip_mdio_read(dev, tp->phys[0], 1));
412 iowrite32(csr6_mask_defstate, ioaddr + CSR6);
413 tp->csr6 = csr6_mask_hdcap;
414 dev->if_port = 11;
415 iowrite32(0x0000, ioaddr + CSR13);
416 iowrite32(0x0000, ioaddr + CSR14);
417 } else
418 t21142_start_nway(dev);
419 } else if (tp->chip_id == PNIC2) {
420 /* for initial startup advertise 10/100 Full and Half */
421 tp->sym_advertise = 0x01E0;
422 /* enable autonegotiate end interrupt */
423 iowrite32(ioread32(ioaddr+CSR5)| 0x00008010, ioaddr + CSR5);
424 iowrite32(ioread32(ioaddr+CSR7)| 0x00008010, ioaddr + CSR7);
425 pnic2_start_nway(dev);
426 } else if (tp->chip_id == LC82C168 && ! tp->medialock) {
427 if (tp->mii_cnt) {
428 dev->if_port = 11;
429 tp->csr6 = 0x814C0000 | (tp->full_duplex ? 0x0200 : 0);
430 iowrite32(0x0001, ioaddr + CSR15);
431 } else if (ioread32(ioaddr + CSR5) & TPLnkPass)
432 pnic_do_nway(dev);
433 else {
434 /* Start with 10mbps to do autonegotiation. */
435 iowrite32(0x32, ioaddr + CSR12);
436 tp->csr6 = 0x00420000;
437 iowrite32(0x0001B078, ioaddr + 0xB8);
438 iowrite32(0x0201B078, ioaddr + 0xB8);
439 next_tick = 1*HZ;
440 }
441 } else if ((tp->chip_id == MX98713 || tp->chip_id == COMPEX9881)
442 && ! tp->medialock) {
443 dev->if_port = 0;
444 tp->csr6 = 0x01880000 | (tp->full_duplex ? 0x0200 : 0);
445 iowrite32(0x0f370000 | ioread16(ioaddr + 0x80), ioaddr + 0x80);
446 } else if (tp->chip_id == MX98715 || tp->chip_id == MX98725) {
447 /* Provided by BOLO, Macronix - 12/10/1998. */
448 dev->if_port = 0;
449 tp->csr6 = 0x01a80200;
450 iowrite32(0x0f370000 | ioread16(ioaddr + 0x80), ioaddr + 0x80);
451 iowrite32(0x11000 | ioread16(ioaddr + 0xa0), ioaddr + 0xa0);
452 } else if (tp->chip_id == COMET || tp->chip_id == CONEXANT) {
453 /* Enable automatic Tx underrun recovery. */
454 iowrite32(ioread32(ioaddr + 0x88) | 1, ioaddr + 0x88);
455 dev->if_port = tp->mii_cnt ? 11 : 0;
456 tp->csr6 = 0x00040000;
457 } else if (tp->chip_id == AX88140) {
458 tp->csr6 = tp->mii_cnt ? 0x00040100 : 0x00000100;
459 } else
460 tulip_select_media(dev, 1);
461
462 /* Start the chip's Tx to process setup frame. */
463 tulip_stop_rxtx(tp);
464 barrier();
465 udelay(5);
466 iowrite32(tp->csr6 | TxOn, ioaddr + CSR6);
467
468 /* Enable interrupts by setting the interrupt mask. */
469 iowrite32(tulip_tbl[tp->chip_id].valid_intrs, ioaddr + CSR5);
470 iowrite32(tulip_tbl[tp->chip_id].valid_intrs, ioaddr + CSR7);
471 tulip_start_rxtx(tp);
472 iowrite32(0, ioaddr + CSR2); /* Rx poll demand */
473
474 if (tulip_debug > 2) {
475 printk(KERN_DEBUG "%s: Done tulip_up(), CSR0 %8.8x, CSR5 %8.8x CSR6 %8.8x.\n",
476 dev->name, ioread32(ioaddr + CSR0), ioread32(ioaddr + CSR5),
477 ioread32(ioaddr + CSR6));
478 }
479
480 /* Set the timer to switch to check for link beat and perhaps switch
481 to an alternate media type. */
482 tp->timer.expires = RUN_AT(next_tick);
483 add_timer(&tp->timer);
484 #ifdef CONFIG_TULIP_NAPI
485 init_timer(&tp->oom_timer);
486 tp->oom_timer.data = (unsigned long)dev;
487 tp->oom_timer.function = oom_timer;
488 #endif
489 }
490
491 static int
492 tulip_open(struct net_device *dev)
493 {
494 int retval;
495
496 if ((retval = request_irq(dev->irq, &tulip_interrupt, SA_SHIRQ, dev->name, dev)))
497 return retval;
498
499 tulip_init_ring (dev);
500
501 tulip_up (dev);
502
503 netif_start_queue (dev);
504
505 return 0;
506 }
507
508
509 static void tulip_tx_timeout(struct net_device *dev)
510 {
511 struct tulip_private *tp = netdev_priv(dev);
512 void __iomem *ioaddr = tp->base_addr;
513 unsigned long flags;
514
515 spin_lock_irqsave (&tp->lock, flags);
516
517 if (tulip_media_cap[dev->if_port] & MediaIsMII) {
518 /* Do nothing -- the media monitor should handle this. */
519 if (tulip_debug > 1)
520 printk(KERN_WARNING "%s: Transmit timeout using MII device.\n",
521 dev->name);
522 } else if (tp->chip_id == DC21140 || tp->chip_id == DC21142
523 || tp->chip_id == MX98713 || tp->chip_id == COMPEX9881
524 || tp->chip_id == DM910X || tp->chip_id == ULI526X) {
525 printk(KERN_WARNING "%s: 21140 transmit timed out, status %8.8x, "
526 "SIA %8.8x %8.8x %8.8x %8.8x, resetting...\n",
527 dev->name, ioread32(ioaddr + CSR5), ioread32(ioaddr + CSR12),
528 ioread32(ioaddr + CSR13), ioread32(ioaddr + CSR14), ioread32(ioaddr + CSR15));
529 if ( ! tp->medialock && tp->mtable) {
530 do
531 --tp->cur_index;
532 while (tp->cur_index >= 0
533 && (tulip_media_cap[tp->mtable->mleaf[tp->cur_index].media]
534 & MediaIsFD));
535 if (--tp->cur_index < 0) {
536 /* We start again, but should instead look for default. */
537 tp->cur_index = tp->mtable->leafcount - 1;
538 }
539 tulip_select_media(dev, 0);
540 printk(KERN_WARNING "%s: transmit timed out, switching to %s "
541 "media.\n", dev->name, medianame[dev->if_port]);
542 }
543 } else if (tp->chip_id == PNIC2) {
544 printk(KERN_WARNING "%s: PNIC2 transmit timed out, status %8.8x, "
545 "CSR6/7 %8.8x / %8.8x CSR12 %8.8x, resetting...\n",
546 dev->name, (int)ioread32(ioaddr + CSR5), (int)ioread32(ioaddr + CSR6),
547 (int)ioread32(ioaddr + CSR7), (int)ioread32(ioaddr + CSR12));
548 } else {
549 printk(KERN_WARNING "%s: Transmit timed out, status %8.8x, CSR12 "
550 "%8.8x, resetting...\n",
551 dev->name, ioread32(ioaddr + CSR5), ioread32(ioaddr + CSR12));
552 dev->if_port = 0;
553 }
554
555 #if defined(way_too_many_messages)
556 if (tulip_debug > 3) {
557 int i;
558 for (i = 0; i < RX_RING_SIZE; i++) {
559 u8 *buf = (u8 *)(tp->rx_ring[i].buffer1);
560 int j;
561 printk(KERN_DEBUG "%2d: %8.8x %8.8x %8.8x %8.8x "
562 "%2.2x %2.2x %2.2x.\n",
563 i, (unsigned int)tp->rx_ring[i].status,
564 (unsigned int)tp->rx_ring[i].length,
565 (unsigned int)tp->rx_ring[i].buffer1,
566 (unsigned int)tp->rx_ring[i].buffer2,
567 buf[0], buf[1], buf[2]);
568 for (j = 0; buf[j] != 0xee && j < 1600; j++)
569 if (j < 100) printk(" %2.2x", buf[j]);
570 printk(" j=%d.\n", j);
571 }
572 printk(KERN_DEBUG " Rx ring %8.8x: ", (int)tp->rx_ring);
573 for (i = 0; i < RX_RING_SIZE; i++)
574 printk(" %8.8x", (unsigned int)tp->rx_ring[i].status);
575 printk("\n" KERN_DEBUG " Tx ring %8.8x: ", (int)tp->tx_ring);
576 for (i = 0; i < TX_RING_SIZE; i++)
577 printk(" %8.8x", (unsigned int)tp->tx_ring[i].status);
578 printk("\n");
579 }
580 #endif
581
582 /* Stop and restart the chip's Tx processes . */
583
584 tulip_restart_rxtx(tp);
585 /* Trigger an immediate transmit demand. */
586 iowrite32(0, ioaddr + CSR1);
587
588 tp->stats.tx_errors++;
589
590 spin_unlock_irqrestore (&tp->lock, flags);
591 dev->trans_start = jiffies;
592 netif_wake_queue (dev);
593 }
594
595
596 /* Initialize the Rx and Tx rings, along with various 'dev' bits. */
597 static void tulip_init_ring(struct net_device *dev)
598 {
599 struct tulip_private *tp = netdev_priv(dev);
600 int i;
601
602 tp->susp_rx = 0;
603 tp->ttimer = 0;
604 tp->nir = 0;
605
606 for (i = 0; i < RX_RING_SIZE; i++) {
607 tp->rx_ring[i].status = 0x00000000;
608 tp->rx_ring[i].length = cpu_to_le32(PKT_BUF_SZ);
609 tp->rx_ring[i].buffer2 = cpu_to_le32(tp->rx_ring_dma + sizeof(struct tulip_rx_desc) * (i + 1));
610 tp->rx_buffers[i].skb = NULL;
611 tp->rx_buffers[i].mapping = 0;
612 }
613 /* Mark the last entry as wrapping the ring. */
614 tp->rx_ring[i-1].length = cpu_to_le32(PKT_BUF_SZ | DESC_RING_WRAP);
615 tp->rx_ring[i-1].buffer2 = cpu_to_le32(tp->rx_ring_dma);
616
617 for (i = 0; i < RX_RING_SIZE; i++) {
618 dma_addr_t mapping;
619
620 /* Note the receive buffer must be longword aligned.
621 dev_alloc_skb() provides 16 byte alignment. But do *not*
622 use skb_reserve() to align the IP header! */
623 struct sk_buff *skb = dev_alloc_skb(PKT_BUF_SZ);
624 tp->rx_buffers[i].skb = skb;
625 if (skb == NULL)
626 break;
627 mapping = pci_map_single(tp->pdev, skb->tail,
628 PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
629 tp->rx_buffers[i].mapping = mapping;
630 skb->dev = dev; /* Mark as being used by this device. */
631 tp->rx_ring[i].status = cpu_to_le32(DescOwned); /* Owned by Tulip chip */
632 tp->rx_ring[i].buffer1 = cpu_to_le32(mapping);
633 }
634 tp->dirty_rx = (unsigned int)(i - RX_RING_SIZE);
635
636 /* The Tx buffer descriptor is filled in as needed, but we
637 do need to clear the ownership bit. */
638 for (i = 0; i < TX_RING_SIZE; i++) {
639 tp->tx_buffers[i].skb = NULL;
640 tp->tx_buffers[i].mapping = 0;
641 tp->tx_ring[i].status = 0x00000000;
642 tp->tx_ring[i].buffer2 = cpu_to_le32(tp->tx_ring_dma + sizeof(struct tulip_tx_desc) * (i + 1));
643 }
644 tp->tx_ring[i-1].buffer2 = cpu_to_le32(tp->tx_ring_dma);
645 }
646
647 static int
648 tulip_start_xmit(struct sk_buff *skb, struct net_device *dev)
649 {
650 struct tulip_private *tp = netdev_priv(dev);
651 int entry;
652 u32 flag;
653 dma_addr_t mapping;
654
655 spin_lock_irq(&tp->lock);
656
657 /* Calculate the next Tx descriptor entry. */
658 entry = tp->cur_tx % TX_RING_SIZE;
659
660 tp->tx_buffers[entry].skb = skb;
661 mapping = pci_map_single(tp->pdev, skb->data,
662 skb->len, PCI_DMA_TODEVICE);
663 tp->tx_buffers[entry].mapping = mapping;
664 tp->tx_ring[entry].buffer1 = cpu_to_le32(mapping);
665
666 if (tp->cur_tx - tp->dirty_tx < TX_RING_SIZE/2) {/* Typical path */
667 flag = 0x60000000; /* No interrupt */
668 } else if (tp->cur_tx - tp->dirty_tx == TX_RING_SIZE/2) {
669 flag = 0xe0000000; /* Tx-done intr. */
670 } else if (tp->cur_tx - tp->dirty_tx < TX_RING_SIZE - 2) {
671 flag = 0x60000000; /* No Tx-done intr. */
672 } else { /* Leave room for set_rx_mode() to fill entries. */
673 flag = 0xe0000000; /* Tx-done intr. */
674 netif_stop_queue(dev);
675 }
676 if (entry == TX_RING_SIZE-1)
677 flag = 0xe0000000 | DESC_RING_WRAP;
678
679 tp->tx_ring[entry].length = cpu_to_le32(skb->len | flag);
680 /* if we were using Transmit Automatic Polling, we would need a
681 * wmb() here. */
682 tp->tx_ring[entry].status = cpu_to_le32(DescOwned);
683 wmb();
684
685 tp->cur_tx++;
686
687 /* Trigger an immediate transmit demand. */
688 iowrite32(0, tp->base_addr + CSR1);
689
690 spin_unlock_irq(&tp->lock);
691
692 dev->trans_start = jiffies;
693
694 return 0;
695 }
696
697 static void tulip_clean_tx_ring(struct tulip_private *tp)
698 {
699 unsigned int dirty_tx;
700
701 for (dirty_tx = tp->dirty_tx ; tp->cur_tx - dirty_tx > 0;
702 dirty_tx++) {
703 int entry = dirty_tx % TX_RING_SIZE;
704 int status = le32_to_cpu(tp->tx_ring[entry].status);
705
706 if (status < 0) {
707 tp->stats.tx_errors++; /* It wasn't Txed */
708 tp->tx_ring[entry].status = 0;
709 }
710
711 /* Check for Tx filter setup frames. */
712 if (tp->tx_buffers[entry].skb == NULL) {
713 /* test because dummy frames not mapped */
714 if (tp->tx_buffers[entry].mapping)
715 pci_unmap_single(tp->pdev,
716 tp->tx_buffers[entry].mapping,
717 sizeof(tp->setup_frame),
718 PCI_DMA_TODEVICE);
719 continue;
720 }
721
722 pci_unmap_single(tp->pdev, tp->tx_buffers[entry].mapping,
723 tp->tx_buffers[entry].skb->len,
724 PCI_DMA_TODEVICE);
725
726 /* Free the original skb. */
727 dev_kfree_skb_irq(tp->tx_buffers[entry].skb);
728 tp->tx_buffers[entry].skb = NULL;
729 tp->tx_buffers[entry].mapping = 0;
730 }
731 }
732
733 static void tulip_down (struct net_device *dev)
734 {
735 struct tulip_private *tp = netdev_priv(dev);
736 void __iomem *ioaddr = tp->base_addr;
737 unsigned long flags;
738
739 del_timer_sync (&tp->timer);
740 #ifdef CONFIG_TULIP_NAPI
741 del_timer_sync (&tp->oom_timer);
742 #endif
743 spin_lock_irqsave (&tp->lock, flags);
744
745 /* Disable interrupts by clearing the interrupt mask. */
746 iowrite32 (0x00000000, ioaddr + CSR7);
747
748 /* Stop the Tx and Rx processes. */
749 tulip_stop_rxtx(tp);
750
751 /* prepare receive buffers */
752 tulip_refill_rx(dev);
753
754 /* release any unconsumed transmit buffers */
755 tulip_clean_tx_ring(tp);
756
757 if (ioread32 (ioaddr + CSR6) != 0xffffffff)
758 tp->stats.rx_missed_errors += ioread32 (ioaddr + CSR8) & 0xffff;
759
760 spin_unlock_irqrestore (&tp->lock, flags);
761
762 init_timer(&tp->timer);
763 tp->timer.data = (unsigned long)dev;
764 tp->timer.function = tulip_tbl[tp->chip_id].media_timer;
765
766 dev->if_port = tp->saved_if_port;
767
768 /* Leave the driver in snooze, not sleep, mode. */
769 tulip_set_power_state (tp, 0, 1);
770 }
771
772
773 static int tulip_close (struct net_device *dev)
774 {
775 struct tulip_private *tp = netdev_priv(dev);
776 void __iomem *ioaddr = tp->base_addr;
777 int i;
778
779 netif_stop_queue (dev);
780
781 tulip_down (dev);
782
783 if (tulip_debug > 1)
784 printk (KERN_DEBUG "%s: Shutting down ethercard, status was %2.2x.\n",
785 dev->name, ioread32 (ioaddr + CSR5));
786
787 free_irq (dev->irq, dev);
788
789 /* Free all the skbuffs in the Rx queue. */
790 for (i = 0; i < RX_RING_SIZE; i++) {
791 struct sk_buff *skb = tp->rx_buffers[i].skb;
792 dma_addr_t mapping = tp->rx_buffers[i].mapping;
793
794 tp->rx_buffers[i].skb = NULL;
795 tp->rx_buffers[i].mapping = 0;
796
797 tp->rx_ring[i].status = 0; /* Not owned by Tulip chip. */
798 tp->rx_ring[i].length = 0;
799 tp->rx_ring[i].buffer1 = 0xBADF00D0; /* An invalid address. */
800 if (skb) {
801 pci_unmap_single(tp->pdev, mapping, PKT_BUF_SZ,
802 PCI_DMA_FROMDEVICE);
803 dev_kfree_skb (skb);
804 }
805 }
806 for (i = 0; i < TX_RING_SIZE; i++) {
807 struct sk_buff *skb = tp->tx_buffers[i].skb;
808
809 if (skb != NULL) {
810 pci_unmap_single(tp->pdev, tp->tx_buffers[i].mapping,
811 skb->len, PCI_DMA_TODEVICE);
812 dev_kfree_skb (skb);
813 }
814 tp->tx_buffers[i].skb = NULL;
815 tp->tx_buffers[i].mapping = 0;
816 }
817
818 return 0;
819 }
820
821 static struct net_device_stats *tulip_get_stats(struct net_device *dev)
822 {
823 struct tulip_private *tp = netdev_priv(dev);
824 void __iomem *ioaddr = tp->base_addr;
825
826 if (netif_running(dev)) {
827 unsigned long flags;
828
829 spin_lock_irqsave (&tp->lock, flags);
830
831 tp->stats.rx_missed_errors += ioread32(ioaddr + CSR8) & 0xffff;
832
833 spin_unlock_irqrestore(&tp->lock, flags);
834 }
835
836 return &tp->stats;
837 }
838
839
840 static void tulip_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
841 {
842 struct tulip_private *np = netdev_priv(dev);
843 strcpy(info->driver, DRV_NAME);
844 strcpy(info->version, DRV_VERSION);
845 strcpy(info->bus_info, pci_name(np->pdev));
846 }
847
848 static struct ethtool_ops ops = {
849 .get_drvinfo = tulip_get_drvinfo
850 };
851
852 /* Provide ioctl() calls to examine the MII xcvr state. */
853 static int private_ioctl (struct net_device *dev, struct ifreq *rq, int cmd)
854 {
855 struct tulip_private *tp = netdev_priv(dev);
856 void __iomem *ioaddr = tp->base_addr;
857 struct mii_ioctl_data *data = if_mii(rq);
858 const unsigned int phy_idx = 0;
859 int phy = tp->phys[phy_idx] & 0x1f;
860 unsigned int regnum = data->reg_num;
861
862 switch (cmd) {
863 case SIOCGMIIPHY: /* Get address of MII PHY in use. */
864 if (tp->mii_cnt)
865 data->phy_id = phy;
866 else if (tp->flags & HAS_NWAY)
867 data->phy_id = 32;
868 else if (tp->chip_id == COMET)
869 data->phy_id = 1;
870 else
871 return -ENODEV;
872
873 case SIOCGMIIREG: /* Read MII PHY register. */
874 if (data->phy_id == 32 && (tp->flags & HAS_NWAY)) {
875 int csr12 = ioread32 (ioaddr + CSR12);
876 int csr14 = ioread32 (ioaddr + CSR14);
877 switch (regnum) {
878 case 0:
879 if (((csr14<<5) & 0x1000) ||
880 (dev->if_port == 5 && tp->nwayset))
881 data->val_out = 0x1000;
882 else
883 data->val_out = (tulip_media_cap[dev->if_port]&MediaIs100 ? 0x2000 : 0)
884 | (tulip_media_cap[dev->if_port]&MediaIsFD ? 0x0100 : 0);
885 break;
886 case 1:
887 data->val_out =
888 0x1848 +
889 ((csr12&0x7000) == 0x5000 ? 0x20 : 0) +
890 ((csr12&0x06) == 6 ? 0 : 4);
891 data->val_out |= 0x6048;
892 break;
893 case 4:
894 /* Advertised value, bogus 10baseTx-FD value from CSR6. */
895 data->val_out =
896 ((ioread32(ioaddr + CSR6) >> 3) & 0x0040) +
897 ((csr14 >> 1) & 0x20) + 1;
898 data->val_out |= ((csr14 >> 9) & 0x03C0);
899 break;
900 case 5: data->val_out = tp->lpar; break;
901 default: data->val_out = 0; break;
902 }
903 } else {
904 data->val_out = tulip_mdio_read (dev, data->phy_id & 0x1f, regnum);
905 }
906 return 0;
907
908 case SIOCSMIIREG: /* Write MII PHY register. */
909 if (!capable (CAP_NET_ADMIN))
910 return -EPERM;
911 if (regnum & ~0x1f)
912 return -EINVAL;
913 if (data->phy_id == phy) {
914 u16 value = data->val_in;
915 switch (regnum) {
916 case 0: /* Check for autonegotiation on or reset. */
917 tp->full_duplex_lock = (value & 0x9000) ? 0 : 1;
918 if (tp->full_duplex_lock)
919 tp->full_duplex = (value & 0x0100) ? 1 : 0;
920 break;
921 case 4:
922 tp->advertising[phy_idx] =
923 tp->mii_advertise = data->val_in;
924 break;
925 }
926 }
927 if (data->phy_id == 32 && (tp->flags & HAS_NWAY)) {
928 u16 value = data->val_in;
929 if (regnum == 0) {
930 if ((value & 0x1200) == 0x1200) {
931 if (tp->chip_id == PNIC2) {
932 pnic2_start_nway (dev);
933 } else {
934 t21142_start_nway (dev);
935 }
936 }
937 } else if (regnum == 4)
938 tp->sym_advertise = value;
939 } else {
940 tulip_mdio_write (dev, data->phy_id & 0x1f, regnum, data->val_in);
941 }
942 return 0;
943 default:
944 return -EOPNOTSUPP;
945 }
946
947 return -EOPNOTSUPP;
948 }
949
950
951 /* Set or clear the multicast filter for this adaptor.
952 Note that we only use exclusion around actually queueing the
953 new frame, not around filling tp->setup_frame. This is non-deterministic
954 when re-entered but still correct. */
955
956 #undef set_bit_le
957 #define set_bit_le(i,p) do { ((char *)(p))[(i)/8] |= (1<<((i)%8)); } while(0)
958
959 static void build_setup_frame_hash(u16 *setup_frm, struct net_device *dev)
960 {
961 struct tulip_private *tp = netdev_priv(dev);
962 u16 hash_table[32];
963 struct dev_mc_list *mclist;
964 int i;
965 u16 *eaddrs;
966
967 memset(hash_table, 0, sizeof(hash_table));
968 set_bit_le(255, hash_table); /* Broadcast entry */
969 /* This should work on big-endian machines as well. */
970 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
971 i++, mclist = mclist->next) {
972 int index = ether_crc_le(ETH_ALEN, mclist->dmi_addr) & 0x1ff;
973
974 set_bit_le(index, hash_table);
975
976 }
977 for (i = 0; i < 32; i++) {
978 *setup_frm++ = hash_table[i];
979 *setup_frm++ = hash_table[i];
980 }
981 setup_frm = &tp->setup_frame[13*6];
982
983 /* Fill the final entry with our physical address. */
984 eaddrs = (u16 *)dev->dev_addr;
985 *setup_frm++ = eaddrs[0]; *setup_frm++ = eaddrs[0];
986 *setup_frm++ = eaddrs[1]; *setup_frm++ = eaddrs[1];
987 *setup_frm++ = eaddrs[2]; *setup_frm++ = eaddrs[2];
988 }
989
990 static void build_setup_frame_perfect(u16 *setup_frm, struct net_device *dev)
991 {
992 struct tulip_private *tp = netdev_priv(dev);
993 struct dev_mc_list *mclist;
994 int i;
995 u16 *eaddrs;
996
997 /* We have <= 14 addresses so we can use the wonderful
998 16 address perfect filtering of the Tulip. */
999 for (i = 0, mclist = dev->mc_list; i < dev->mc_count;
1000 i++, mclist = mclist->next) {
1001 eaddrs = (u16 *)mclist->dmi_addr;
1002 *setup_frm++ = *eaddrs; *setup_frm++ = *eaddrs++;
1003 *setup_frm++ = *eaddrs; *setup_frm++ = *eaddrs++;
1004 *setup_frm++ = *eaddrs; *setup_frm++ = *eaddrs++;
1005 }
1006 /* Fill the unused entries with the broadcast address. */
1007 memset(setup_frm, 0xff, (15-i)*12);
1008 setup_frm = &tp->setup_frame[15*6];
1009
1010 /* Fill the final entry with our physical address. */
1011 eaddrs = (u16 *)dev->dev_addr;
1012 *setup_frm++ = eaddrs[0]; *setup_frm++ = eaddrs[0];
1013 *setup_frm++ = eaddrs[1]; *setup_frm++ = eaddrs[1];
1014 *setup_frm++ = eaddrs[2]; *setup_frm++ = eaddrs[2];
1015 }
1016
1017
1018 static void set_rx_mode(struct net_device *dev)
1019 {
1020 struct tulip_private *tp = netdev_priv(dev);
1021 void __iomem *ioaddr = tp->base_addr;
1022 int csr6;
1023
1024 csr6 = ioread32(ioaddr + CSR6) & ~0x00D5;
1025
1026 tp->csr6 &= ~0x00D5;
1027 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1028 tp->csr6 |= AcceptAllMulticast | AcceptAllPhys;
1029 csr6 |= AcceptAllMulticast | AcceptAllPhys;
1030 /* Unconditionally log net taps. */
1031 printk(KERN_INFO "%s: Promiscuous mode enabled.\n", dev->name);
1032 } else if ((dev->mc_count > 1000) || (dev->flags & IFF_ALLMULTI)) {
1033 /* Too many to filter well -- accept all multicasts. */
1034 tp->csr6 |= AcceptAllMulticast;
1035 csr6 |= AcceptAllMulticast;
1036 } else if (tp->flags & MC_HASH_ONLY) {
1037 /* Some work-alikes have only a 64-entry hash filter table. */
1038 /* Should verify correctness on big-endian/__powerpc__ */
1039 struct dev_mc_list *mclist;
1040 int i;
1041 if (dev->mc_count > 64) { /* Arbitrary non-effective limit. */
1042 tp->csr6 |= AcceptAllMulticast;
1043 csr6 |= AcceptAllMulticast;
1044 } else {
1045 u32 mc_filter[2] = {0, 0}; /* Multicast hash filter */
1046 int filterbit;
1047 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
1048 i++, mclist = mclist->next) {
1049 if (tp->flags & COMET_MAC_ADDR)
1050 filterbit = ether_crc_le(ETH_ALEN, mclist->dmi_addr);
1051 else
1052 filterbit = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
1053 filterbit &= 0x3f;
1054 mc_filter[filterbit >> 5] |= 1 << (filterbit & 31);
1055 if (tulip_debug > 2) {
1056 printk(KERN_INFO "%s: Added filter for %2.2x:%2.2x:%2.2x:"
1057 "%2.2x:%2.2x:%2.2x %8.8x bit %d.\n", dev->name,
1058 mclist->dmi_addr[0], mclist->dmi_addr[1],
1059 mclist->dmi_addr[2], mclist->dmi_addr[3],
1060 mclist->dmi_addr[4], mclist->dmi_addr[5],
1061 ether_crc(ETH_ALEN, mclist->dmi_addr), filterbit);
1062 }
1063 }
1064 if (mc_filter[0] == tp->mc_filter[0] &&
1065 mc_filter[1] == tp->mc_filter[1])
1066 ; /* No change. */
1067 else if (tp->flags & IS_ASIX) {
1068 iowrite32(2, ioaddr + CSR13);
1069 iowrite32(mc_filter[0], ioaddr + CSR14);
1070 iowrite32(3, ioaddr + CSR13);
1071 iowrite32(mc_filter[1], ioaddr + CSR14);
1072 } else if (tp->flags & COMET_MAC_ADDR) {
1073 iowrite32(mc_filter[0], ioaddr + 0xAC);
1074 iowrite32(mc_filter[1], ioaddr + 0xB0);
1075 }
1076 tp->mc_filter[0] = mc_filter[0];
1077 tp->mc_filter[1] = mc_filter[1];
1078 }
1079 } else {
1080 unsigned long flags;
1081 u32 tx_flags = 0x08000000 | 192;
1082
1083 /* Note that only the low-address shortword of setup_frame is valid!
1084 The values are doubled for big-endian architectures. */
1085 if (dev->mc_count > 14) { /* Must use a multicast hash table. */
1086 build_setup_frame_hash(tp->setup_frame, dev);
1087 tx_flags = 0x08400000 | 192;
1088 } else {
1089 build_setup_frame_perfect(tp->setup_frame, dev);
1090 }
1091
1092 spin_lock_irqsave(&tp->lock, flags);
1093
1094 if (tp->cur_tx - tp->dirty_tx > TX_RING_SIZE - 2) {
1095 /* Same setup recently queued, we need not add it. */
1096 } else {
1097 unsigned int entry;
1098 int dummy = -1;
1099
1100 /* Now add this frame to the Tx list. */
1101
1102 entry = tp->cur_tx++ % TX_RING_SIZE;
1103
1104 if (entry != 0) {
1105 /* Avoid a chip errata by prefixing a dummy entry. Don't do
1106 this on the ULI526X as it triggers a different problem */
1107 if (!(tp->chip_id == ULI526X && (tp->revision == 0x40 || tp->revision == 0x50))) {
1108 tp->tx_buffers[entry].skb = NULL;
1109 tp->tx_buffers[entry].mapping = 0;
1110 tp->tx_ring[entry].length =
1111 (entry == TX_RING_SIZE-1) ? cpu_to_le32(DESC_RING_WRAP) : 0;
1112 tp->tx_ring[entry].buffer1 = 0;
1113 /* Must set DescOwned later to avoid race with chip */
1114 dummy = entry;
1115 entry = tp->cur_tx++ % TX_RING_SIZE;
1116 }
1117 }
1118
1119 tp->tx_buffers[entry].skb = NULL;
1120 tp->tx_buffers[entry].mapping =
1121 pci_map_single(tp->pdev, tp->setup_frame,
1122 sizeof(tp->setup_frame),
1123 PCI_DMA_TODEVICE);
1124 /* Put the setup frame on the Tx list. */
1125 if (entry == TX_RING_SIZE-1)
1126 tx_flags |= DESC_RING_WRAP; /* Wrap ring. */
1127 tp->tx_ring[entry].length = cpu_to_le32(tx_flags);
1128 tp->tx_ring[entry].buffer1 =
1129 cpu_to_le32(tp->tx_buffers[entry].mapping);
1130 tp->tx_ring[entry].status = cpu_to_le32(DescOwned);
1131 if (dummy >= 0)
1132 tp->tx_ring[dummy].status = cpu_to_le32(DescOwned);
1133 if (tp->cur_tx - tp->dirty_tx >= TX_RING_SIZE - 2)
1134 netif_stop_queue(dev);
1135
1136 /* Trigger an immediate transmit demand. */
1137 iowrite32(0, ioaddr + CSR1);
1138 }
1139
1140 spin_unlock_irqrestore(&tp->lock, flags);
1141 }
1142
1143 iowrite32(csr6, ioaddr + CSR6);
1144 }
1145
1146 #ifdef CONFIG_TULIP_MWI
1147 static void __devinit tulip_mwi_config (struct pci_dev *pdev,
1148 struct net_device *dev)
1149 {
1150 struct tulip_private *tp = netdev_priv(dev);
1151 u8 cache;
1152 u16 pci_command;
1153 u32 csr0;
1154
1155 if (tulip_debug > 3)
1156 printk(KERN_DEBUG "%s: tulip_mwi_config()\n", pci_name(pdev));
1157
1158 tp->csr0 = csr0 = 0;
1159
1160 /* if we have any cache line size at all, we can do MRM */
1161 csr0 |= MRM;
1162
1163 /* ...and barring hardware bugs, MWI */
1164 if (!(tp->chip_id == DC21143 && tp->revision == 65))
1165 csr0 |= MWI;
1166
1167 /* set or disable MWI in the standard PCI command bit.
1168 * Check for the case where mwi is desired but not available
1169 */
1170 if (csr0 & MWI) pci_set_mwi(pdev);
1171 else pci_clear_mwi(pdev);
1172
1173 /* read result from hardware (in case bit refused to enable) */
1174 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
1175 if ((csr0 & MWI) && (!(pci_command & PCI_COMMAND_INVALIDATE)))
1176 csr0 &= ~MWI;
1177
1178 /* if cache line size hardwired to zero, no MWI */
1179 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cache);
1180 if ((csr0 & MWI) && (cache == 0)) {
1181 csr0 &= ~MWI;
1182 pci_clear_mwi(pdev);
1183 }
1184
1185 /* assign per-cacheline-size cache alignment and
1186 * burst length values
1187 */
1188 switch (cache) {
1189 case 8:
1190 csr0 |= MRL | (1 << CALShift) | (16 << BurstLenShift);
1191 break;
1192 case 16:
1193 csr0 |= MRL | (2 << CALShift) | (16 << BurstLenShift);
1194 break;
1195 case 32:
1196 csr0 |= MRL | (3 << CALShift) | (32 << BurstLenShift);
1197 break;
1198 default:
1199 cache = 0;
1200 break;
1201 }
1202
1203 /* if we have a good cache line size, we by now have a good
1204 * csr0, so save it and exit
1205 */
1206 if (cache)
1207 goto out;
1208
1209 /* we don't have a good csr0 or cache line size, disable MWI */
1210 if (csr0 & MWI) {
1211 pci_clear_mwi(pdev);
1212 csr0 &= ~MWI;
1213 }
1214
1215 /* sane defaults for burst length and cache alignment
1216 * originally from de4x5 driver
1217 */
1218 csr0 |= (8 << BurstLenShift) | (1 << CALShift);
1219
1220 out:
1221 tp->csr0 = csr0;
1222 if (tulip_debug > 2)
1223 printk(KERN_DEBUG "%s: MWI config cacheline=%d, csr0=%08x\n",
1224 pci_name(pdev), cache, csr0);
1225 }
1226 #endif
1227
1228 /*
1229 * Chips that have the MRM/reserved bit quirk and the burst quirk. That
1230 * is the DM910X and the on chip ULi devices
1231 */
1232
1233 static int tulip_uli_dm_quirk(struct pci_dev *pdev)
1234 {
1235 if (pdev->vendor == 0x1282 && pdev->device == 0x9102)
1236 return 1;
1237 if (pdev->vendor == 0x10b9 && pdev->device == 0x5261)
1238 return 1;
1239 if (pdev->vendor == 0x10b9 && pdev->device == 0x5263)
1240 return 1;
1241 return 0;
1242 }
1243
1244 static int __devinit tulip_init_one (struct pci_dev *pdev,
1245 const struct pci_device_id *ent)
1246 {
1247 struct tulip_private *tp;
1248 /* See note below on the multiport cards. */
1249 static unsigned char last_phys_addr[6] = {0x00, 'L', 'i', 'n', 'u', 'x'};
1250 static struct pci_device_id early_486_chipsets[] = {
1251 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82424) },
1252 { PCI_DEVICE(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496) },
1253 { },
1254 };
1255 static int last_irq;
1256 static int multiport_cnt; /* For four-port boards w/one EEPROM */
1257 u8 chip_rev;
1258 int i, irq;
1259 unsigned short sum;
1260 unsigned char *ee_data;
1261 struct net_device *dev;
1262 void __iomem *ioaddr;
1263 static int board_idx = -1;
1264 int chip_idx = ent->driver_data;
1265 const char *chip_name = tulip_tbl[chip_idx].chip_name;
1266 unsigned int eeprom_missing = 0;
1267 unsigned int force_csr0 = 0;
1268
1269 #ifndef MODULE
1270 static int did_version; /* Already printed version info. */
1271 if (tulip_debug > 0 && did_version++ == 0)
1272 printk (KERN_INFO "%s", version);
1273 #endif
1274
1275 board_idx++;
1276
1277 /*
1278 * Lan media wire a tulip chip to a wan interface. Needs a very
1279 * different driver (lmc driver)
1280 */
1281
1282 if (pdev->subsystem_vendor == PCI_VENDOR_ID_LMC) {
1283 printk (KERN_ERR PFX "skipping LMC card.\n");
1284 return -ENODEV;
1285 }
1286
1287 /*
1288 * Early DM9100's need software CRC and the DMFE driver
1289 */
1290
1291 if (pdev->vendor == 0x1282 && pdev->device == 0x9100)
1292 {
1293 u32 dev_rev;
1294 /* Read Chip revision */
1295 pci_read_config_dword(pdev, PCI_REVISION_ID, &dev_rev);
1296 if(dev_rev < 0x02000030)
1297 {
1298 printk(KERN_ERR PFX "skipping early DM9100 with Crc bug (use dmfe)\n");
1299 return -ENODEV;
1300 }
1301 }
1302
1303 /*
1304 * Looks for early PCI chipsets where people report hangs
1305 * without the workarounds being on.
1306 */
1307
1308 /* 1. Intel Saturn. Switch to 8 long words burst, 8 long word cache
1309 aligned. Aries might need this too. The Saturn errata are not
1310 pretty reading but thankfully it's an old 486 chipset.
1311
1312 2. The dreaded SiS496 486 chipset. Same workaround as Intel
1313 Saturn.
1314 */
1315
1316 if (pci_dev_present(early_486_chipsets)) {
1317 csr0 = MRL | MRM | (8 << BurstLenShift) | (1 << CALShift);
1318 force_csr0 = 1;
1319 }
1320
1321 /* bugfix: the ASIX must have a burst limit or horrible things happen. */
1322 if (chip_idx == AX88140) {
1323 if ((csr0 & 0x3f00) == 0)
1324 csr0 |= 0x2000;
1325 }
1326
1327 /* PNIC doesn't have MWI/MRL/MRM... */
1328 if (chip_idx == LC82C168)
1329 csr0 &= ~0xfff10000; /* zero reserved bits 31:20, 16 */
1330
1331 /* DM9102A has troubles with MRM & clear reserved bits 24:22, 20, 16, 7:1 */
1332 if (tulip_uli_dm_quirk(pdev)) {
1333 csr0 &= ~0x01f100ff;
1334 #if defined(__sparc__)
1335 csr0 = (csr0 & ~0xff00) | 0xe000;
1336 #endif
1337 }
1338 /*
1339 * And back to business
1340 */
1341
1342 i = pci_enable_device(pdev);
1343 if (i) {
1344 printk (KERN_ERR PFX
1345 "Cannot enable tulip board #%d, aborting\n",
1346 board_idx);
1347 return i;
1348 }
1349
1350 irq = pdev->irq;
1351
1352 /* alloc_etherdev ensures aligned and zeroed private structures */
1353 dev = alloc_etherdev (sizeof (*tp));
1354 if (!dev) {
1355 printk (KERN_ERR PFX "ether device alloc failed, aborting\n");
1356 return -ENOMEM;
1357 }
1358
1359 SET_MODULE_OWNER(dev);
1360 SET_NETDEV_DEV(dev, &pdev->dev);
1361 if (pci_resource_len (pdev, 0) < tulip_tbl[chip_idx].io_size) {
1362 printk (KERN_ERR PFX "%s: I/O region (0x%lx@0x%lx) too small, "
1363 "aborting\n", pci_name(pdev),
1364 pci_resource_len (pdev, 0),
1365 pci_resource_start (pdev, 0));
1366 goto err_out_free_netdev;
1367 }
1368
1369 /* grab all resources from both PIO and MMIO regions, as we
1370 * don't want anyone else messing around with our hardware */
1371 if (pci_request_regions (pdev, "tulip"))
1372 goto err_out_free_netdev;
1373
1374 #ifndef USE_IO_OPS
1375 ioaddr = pci_iomap(pdev, 1, tulip_tbl[chip_idx].io_size);
1376 #else
1377 ioaddr = pci_iomap(pdev, 0, tulip_tbl[chip_idx].io_size);
1378 #endif
1379 if (!ioaddr)
1380 goto err_out_free_res;
1381
1382 pci_read_config_byte (pdev, PCI_REVISION_ID, &chip_rev);
1383
1384 /*
1385 * initialize private data structure 'tp'
1386 * it is zeroed and aligned in alloc_etherdev
1387 */
1388 tp = netdev_priv(dev);
1389
1390 tp->rx_ring = pci_alloc_consistent(pdev,
1391 sizeof(struct tulip_rx_desc) * RX_RING_SIZE +
1392 sizeof(struct tulip_tx_desc) * TX_RING_SIZE,
1393 &tp->rx_ring_dma);
1394 if (!tp->rx_ring)
1395 goto err_out_mtable;
1396 tp->tx_ring = (struct tulip_tx_desc *)(tp->rx_ring + RX_RING_SIZE);
1397 tp->tx_ring_dma = tp->rx_ring_dma + sizeof(struct tulip_rx_desc) * RX_RING_SIZE;
1398
1399 tp->chip_id = chip_idx;
1400 tp->flags = tulip_tbl[chip_idx].flags;
1401 tp->pdev = pdev;
1402 tp->base_addr = ioaddr;
1403 tp->revision = chip_rev;
1404 tp->csr0 = csr0;
1405 spin_lock_init(&tp->lock);
1406 spin_lock_init(&tp->mii_lock);
1407 init_timer(&tp->timer);
1408 tp->timer.data = (unsigned long)dev;
1409 tp->timer.function = tulip_tbl[tp->chip_id].media_timer;
1410
1411 dev->base_addr = (unsigned long)ioaddr;
1412
1413 #ifdef CONFIG_TULIP_MWI
1414 if (!force_csr0 && (tp->flags & HAS_PCI_MWI))
1415 tulip_mwi_config (pdev, dev);
1416 #else
1417 /* MWI is broken for DC21143 rev 65... */
1418 if (chip_idx == DC21143 && chip_rev == 65)
1419 tp->csr0 &= ~MWI;
1420 #endif
1421
1422 /* Stop the chip's Tx and Rx processes. */
1423 tulip_stop_rxtx(tp);
1424
1425 pci_set_master(pdev);
1426
1427 #ifdef CONFIG_GSC
1428 if (pdev->subsystem_vendor == PCI_VENDOR_ID_HP) {
1429 switch (pdev->subsystem_device) {
1430 default:
1431 break;
1432 case 0x1061:
1433 case 0x1062:
1434 case 0x1063:
1435 case 0x1098:
1436 case 0x1099:
1437 case 0x10EE:
1438 tp->flags |= HAS_SWAPPED_SEEPROM | NEEDS_FAKE_MEDIA_TABLE;
1439 chip_name = "GSC DS21140 Tulip";
1440 }
1441 }
1442 #endif
1443
1444 /* Clear the missed-packet counter. */
1445 ioread32(ioaddr + CSR8);
1446
1447 /* The station address ROM is read byte serially. The register must
1448 be polled, waiting for the value to be read bit serially from the
1449 EEPROM.
1450 */
1451 ee_data = tp->eeprom;
1452 sum = 0;
1453 if (chip_idx == LC82C168) {
1454 for (i = 0; i < 3; i++) {
1455 int value, boguscnt = 100000;
1456 iowrite32(0x600 | i, ioaddr + 0x98);
1457 do
1458 value = ioread32(ioaddr + CSR9);
1459 while (value < 0 && --boguscnt > 0);
1460 put_unaligned(le16_to_cpu(value), ((u16*)dev->dev_addr) + i);
1461 sum += value & 0xffff;
1462 }
1463 } else if (chip_idx == COMET) {
1464 /* No need to read the EEPROM. */
1465 put_unaligned(cpu_to_le32(ioread32(ioaddr + 0xA4)), (u32 *)dev->dev_addr);
1466 put_unaligned(cpu_to_le16(ioread32(ioaddr + 0xA8)), (u16 *)(dev->dev_addr + 4));
1467 for (i = 0; i < 6; i ++)
1468 sum += dev->dev_addr[i];
1469 } else {
1470 /* A serial EEPROM interface, we read now and sort it out later. */
1471 int sa_offset = 0;
1472 int ee_addr_size = tulip_read_eeprom(dev, 0xff, 8) & 0x40000 ? 8 : 6;
1473
1474 for (i = 0; i < sizeof(tp->eeprom); i+=2) {
1475 u16 data = tulip_read_eeprom(dev, i/2, ee_addr_size);
1476 ee_data[i] = data & 0xff;
1477 ee_data[i + 1] = data >> 8;
1478 }
1479
1480 /* DEC now has a specification (see Notes) but early board makers
1481 just put the address in the first EEPROM locations. */
1482 /* This does memcmp(ee_data, ee_data+16, 8) */
1483 for (i = 0; i < 8; i ++)
1484 if (ee_data[i] != ee_data[16+i])
1485 sa_offset = 20;
1486 if (chip_idx == CONEXANT) {
1487 /* Check that the tuple type and length is correct. */
1488 if (ee_data[0x198] == 0x04 && ee_data[0x199] == 6)
1489 sa_offset = 0x19A;
1490 } else if (ee_data[0] == 0xff && ee_data[1] == 0xff &&
1491 ee_data[2] == 0) {
1492 sa_offset = 2; /* Grrr, damn Matrox boards. */
1493 multiport_cnt = 4;
1494 }
1495 #ifdef CONFIG_DDB5476
1496 if ((pdev->bus->number == 0) && (PCI_SLOT(pdev->devfn) == 6)) {
1497 /* DDB5476 MAC address in first EEPROM locations. */
1498 sa_offset = 0;
1499 /* No media table either */
1500 tp->flags &= ~HAS_MEDIA_TABLE;
1501 }
1502 #endif
1503 #ifdef CONFIG_DDB5477
1504 if ((pdev->bus->number == 0) && (PCI_SLOT(pdev->devfn) == 4)) {
1505 /* DDB5477 MAC address in first EEPROM locations. */
1506 sa_offset = 0;
1507 /* No media table either */
1508 tp->flags &= ~HAS_MEDIA_TABLE;
1509 }
1510 #endif
1511 #ifdef CONFIG_MIPS_COBALT
1512 if ((pdev->bus->number == 0) &&
1513 ((PCI_SLOT(pdev->devfn) == 7) ||
1514 (PCI_SLOT(pdev->devfn) == 12))) {
1515 /* Cobalt MAC address in first EEPROM locations. */
1516 sa_offset = 0;
1517 /* No media table either */
1518 tp->flags &= ~HAS_MEDIA_TABLE;
1519 }
1520 #endif
1521 #ifdef CONFIG_GSC
1522 /* Check to see if we have a broken srom */
1523 if (ee_data[0] == 0x61 && ee_data[1] == 0x10) {
1524 /* pci_vendor_id and subsystem_id are swapped */
1525 ee_data[0] = ee_data[2];
1526 ee_data[1] = ee_data[3];
1527 ee_data[2] = 0x61;
1528 ee_data[3] = 0x10;
1529
1530 /* HSC-PCI boards need to be byte-swaped and shifted
1531 * up 1 word. This shift needs to happen at the end
1532 * of the MAC first because of the 2 byte overlap.
1533 */
1534 for (i = 4; i >= 0; i -= 2) {
1535 ee_data[17 + i + 3] = ee_data[17 + i];
1536 ee_data[16 + i + 5] = ee_data[16 + i];
1537 }
1538 }
1539 #endif
1540
1541 for (i = 0; i < 6; i ++) {
1542 dev->dev_addr[i] = ee_data[i + sa_offset];
1543 sum += ee_data[i + sa_offset];
1544 }
1545 }
1546 /* Lite-On boards have the address byte-swapped. */
1547 if ((dev->dev_addr[0] == 0xA0 || dev->dev_addr[0] == 0xC0 || dev->dev_addr[0] == 0x02)
1548 && dev->dev_addr[1] == 0x00)
1549 for (i = 0; i < 6; i+=2) {
1550 char tmp = dev->dev_addr[i];
1551 dev->dev_addr[i] = dev->dev_addr[i+1];
1552 dev->dev_addr[i+1] = tmp;
1553 }
1554 /* On the Zynx 315 Etherarray and other multiport boards only the
1555 first Tulip has an EEPROM.
1556 On Sparc systems the mac address is held in the OBP property
1557 "local-mac-address".
1558 The addresses of the subsequent ports are derived from the first.
1559 Many PCI BIOSes also incorrectly report the IRQ line, so we correct
1560 that here as well. */
1561 if (sum == 0 || sum == 6*0xff) {
1562 #if defined(__sparc__)
1563 struct pcidev_cookie *pcp = pdev->sysdata;
1564 #endif
1565 eeprom_missing = 1;
1566 for (i = 0; i < 5; i++)
1567 dev->dev_addr[i] = last_phys_addr[i];
1568 dev->dev_addr[i] = last_phys_addr[i] + 1;
1569 #if defined(__sparc__)
1570 if ((pcp != NULL) && prom_getproplen(pcp->prom_node,
1571 "local-mac-address") == 6) {
1572 prom_getproperty(pcp->prom_node, "local-mac-address",
1573 dev->dev_addr, 6);
1574 }
1575 #endif
1576 #if defined(__i386__) /* Patch up x86 BIOS bug. */
1577 if (last_irq)
1578 irq = last_irq;
1579 #endif
1580 }
1581
1582 for (i = 0; i < 6; i++)
1583 last_phys_addr[i] = dev->dev_addr[i];
1584 last_irq = irq;
1585 dev->irq = irq;
1586
1587 /* The lower four bits are the media type. */
1588 if (board_idx >= 0 && board_idx < MAX_UNITS) {
1589 if (options[board_idx] & MEDIA_MASK)
1590 tp->default_port = options[board_idx] & MEDIA_MASK;
1591 if ((options[board_idx] & FullDuplex) || full_duplex[board_idx] > 0)
1592 tp->full_duplex = 1;
1593 if (mtu[board_idx] > 0)
1594 dev->mtu = mtu[board_idx];
1595 }
1596 if (dev->mem_start & MEDIA_MASK)
1597 tp->default_port = dev->mem_start & MEDIA_MASK;
1598 if (tp->default_port) {
1599 printk(KERN_INFO "tulip%d: Transceiver selection forced to %s.\n",
1600 board_idx, medianame[tp->default_port & MEDIA_MASK]);
1601 tp->medialock = 1;
1602 if (tulip_media_cap[tp->default_port] & MediaAlwaysFD)
1603 tp->full_duplex = 1;
1604 }
1605 if (tp->full_duplex)
1606 tp->full_duplex_lock = 1;
1607
1608 if (tulip_media_cap[tp->default_port] & MediaIsMII) {
1609 u16 media2advert[] = { 0x20, 0x40, 0x03e0, 0x60, 0x80, 0x100, 0x200 };
1610 tp->mii_advertise = media2advert[tp->default_port - 9];
1611 tp->mii_advertise |= (tp->flags & HAS_8023X); /* Matching bits! */
1612 }
1613
1614 if (tp->flags & HAS_MEDIA_TABLE) {
1615 sprintf(dev->name, "tulip%d", board_idx); /* hack */
1616 tulip_parse_eeprom(dev);
1617 strcpy(dev->name, "eth%d"); /* un-hack */
1618 }
1619
1620 if ((tp->flags & ALWAYS_CHECK_MII) ||
1621 (tp->mtable && tp->mtable->has_mii) ||
1622 ( ! tp->mtable && (tp->flags & HAS_MII))) {
1623 if (tp->mtable && tp->mtable->has_mii) {
1624 for (i = 0; i < tp->mtable->leafcount; i++)
1625 if (tp->mtable->mleaf[i].media == 11) {
1626 tp->cur_index = i;
1627 tp->saved_if_port = dev->if_port;
1628 tulip_select_media(dev, 2);
1629 dev->if_port = tp->saved_if_port;
1630 break;
1631 }
1632 }
1633
1634 /* Find the connected MII xcvrs.
1635 Doing this in open() would allow detecting external xcvrs
1636 later, but takes much time. */
1637 tulip_find_mii (dev, board_idx);
1638 }
1639
1640 /* The Tulip-specific entries in the device structure. */
1641 dev->open = tulip_open;
1642 dev->hard_start_xmit = tulip_start_xmit;
1643 dev->tx_timeout = tulip_tx_timeout;
1644 dev->watchdog_timeo = TX_TIMEOUT;
1645 #ifdef CONFIG_TULIP_NAPI
1646 dev->poll = tulip_poll;
1647 dev->weight = 16;
1648 #endif
1649 dev->stop = tulip_close;
1650 dev->get_stats = tulip_get_stats;
1651 dev->do_ioctl = private_ioctl;
1652 dev->set_multicast_list = set_rx_mode;
1653 #ifdef CONFIG_NET_POLL_CONTROLLER
1654 dev->poll_controller = &poll_tulip;
1655 #endif
1656 SET_ETHTOOL_OPS(dev, &ops);
1657
1658 if (register_netdev(dev))
1659 goto err_out_free_ring;
1660
1661 printk(KERN_INFO "%s: %s rev %d at %p,",
1662 dev->name, chip_name, chip_rev, ioaddr);
1663 pci_set_drvdata(pdev, dev);
1664
1665 if (eeprom_missing)
1666 printk(" EEPROM not present,");
1667 for (i = 0; i < 6; i++)
1668 printk("%c%2.2X", i ? ':' : ' ', dev->dev_addr[i]);
1669 printk(", IRQ %d.\n", irq);
1670
1671 if (tp->chip_id == PNIC2)
1672 tp->link_change = pnic2_lnk_change;
1673 else if (tp->flags & HAS_NWAY)
1674 tp->link_change = t21142_lnk_change;
1675 else if (tp->flags & HAS_PNICNWAY)
1676 tp->link_change = pnic_lnk_change;
1677
1678 /* Reset the xcvr interface and turn on heartbeat. */
1679 switch (chip_idx) {
1680 case DC21140:
1681 case DM910X:
1682 case ULI526X:
1683 default:
1684 if (tp->mtable)
1685 iowrite32(tp->mtable->csr12dir | 0x100, ioaddr + CSR12);
1686 break;
1687 case DC21142:
1688 if (tp->mii_cnt || tulip_media_cap[dev->if_port] & MediaIsMII) {
1689 iowrite32(csr6_mask_defstate, ioaddr + CSR6);
1690 iowrite32(0x0000, ioaddr + CSR13);
1691 iowrite32(0x0000, ioaddr + CSR14);
1692 iowrite32(csr6_mask_hdcap, ioaddr + CSR6);
1693 } else
1694 t21142_start_nway(dev);
1695 break;
1696 case PNIC2:
1697 /* just do a reset for sanity sake */
1698 iowrite32(0x0000, ioaddr + CSR13);
1699 iowrite32(0x0000, ioaddr + CSR14);
1700 break;
1701 case LC82C168:
1702 if ( ! tp->mii_cnt) {
1703 tp->nway = 1;
1704 tp->nwayset = 0;
1705 iowrite32(csr6_ttm | csr6_ca, ioaddr + CSR6);
1706 iowrite32(0x30, ioaddr + CSR12);
1707 iowrite32(0x0001F078, ioaddr + CSR6);
1708 iowrite32(0x0201F078, ioaddr + CSR6); /* Turn on autonegotiation. */
1709 }
1710 break;
1711 case MX98713:
1712 case COMPEX9881:
1713 iowrite32(0x00000000, ioaddr + CSR6);
1714 iowrite32(0x000711C0, ioaddr + CSR14); /* Turn on NWay. */
1715 iowrite32(0x00000001, ioaddr + CSR13);
1716 break;
1717 case MX98715:
1718 case MX98725:
1719 iowrite32(0x01a80000, ioaddr + CSR6);
1720 iowrite32(0xFFFFFFFF, ioaddr + CSR14);
1721 iowrite32(0x00001000, ioaddr + CSR12);
1722 break;
1723 case COMET:
1724 /* No initialization necessary. */
1725 break;
1726 }
1727
1728 /* put the chip in snooze mode until opened */
1729 tulip_set_power_state (tp, 0, 1);
1730
1731 return 0;
1732
1733 err_out_free_ring:
1734 pci_free_consistent (pdev,
1735 sizeof (struct tulip_rx_desc) * RX_RING_SIZE +
1736 sizeof (struct tulip_tx_desc) * TX_RING_SIZE,
1737 tp->rx_ring, tp->rx_ring_dma);
1738
1739 err_out_mtable:
1740 if (tp->mtable)
1741 kfree (tp->mtable);
1742 pci_iounmap(pdev, ioaddr);
1743
1744 err_out_free_res:
1745 pci_release_regions (pdev);
1746
1747 err_out_free_netdev:
1748 free_netdev (dev);
1749 return -ENODEV;
1750 }
1751
1752
1753 #ifdef CONFIG_PM
1754
1755 static int tulip_suspend (struct pci_dev *pdev, pm_message_t state)
1756 {
1757 struct net_device *dev = pci_get_drvdata(pdev);
1758
1759 if (dev && netif_running (dev) && netif_device_present (dev)) {
1760 netif_device_detach (dev);
1761 tulip_down (dev);
1762 /* pci_power_off(pdev, -1); */
1763 }
1764 return 0;
1765 }
1766
1767
1768 static int tulip_resume(struct pci_dev *pdev)
1769 {
1770 struct net_device *dev = pci_get_drvdata(pdev);
1771
1772 if (dev && netif_running (dev) && !netif_device_present (dev)) {
1773 #if 1
1774 pci_enable_device (pdev);
1775 #endif
1776 /* pci_power_on(pdev); */
1777 tulip_up (dev);
1778 netif_device_attach (dev);
1779 }
1780 return 0;
1781 }
1782
1783 #endif /* CONFIG_PM */
1784
1785
1786 static void __devexit tulip_remove_one (struct pci_dev *pdev)
1787 {
1788 struct net_device *dev = pci_get_drvdata (pdev);
1789 struct tulip_private *tp;
1790
1791 if (!dev)
1792 return;
1793
1794 tp = netdev_priv(dev);
1795 unregister_netdev(dev);
1796 pci_free_consistent (pdev,
1797 sizeof (struct tulip_rx_desc) * RX_RING_SIZE +
1798 sizeof (struct tulip_tx_desc) * TX_RING_SIZE,
1799 tp->rx_ring, tp->rx_ring_dma);
1800 if (tp->mtable)
1801 kfree (tp->mtable);
1802 pci_iounmap(pdev, tp->base_addr);
1803 free_netdev (dev);
1804 pci_release_regions (pdev);
1805 pci_set_drvdata (pdev, NULL);
1806
1807 /* pci_power_off (pdev, -1); */
1808 }
1809
1810 #ifdef CONFIG_NET_POLL_CONTROLLER
1811 /*
1812 * Polling 'interrupt' - used by things like netconsole to send skbs
1813 * without having to re-enable interrupts. It's not called while
1814 * the interrupt routine is executing.
1815 */
1816
1817 static void poll_tulip (struct net_device *dev)
1818 {
1819 /* disable_irq here is not very nice, but with the lockless
1820 interrupt handler we have no other choice. */
1821 disable_irq(dev->irq);
1822 tulip_interrupt (dev->irq, dev, NULL);
1823 enable_irq(dev->irq);
1824 }
1825 #endif
1826
1827 static struct pci_driver tulip_driver = {
1828 .name = DRV_NAME,
1829 .id_table = tulip_pci_tbl,
1830 .probe = tulip_init_one,
1831 .remove = __devexit_p(tulip_remove_one),
1832 #ifdef CONFIG_PM
1833 .suspend = tulip_suspend,
1834 .resume = tulip_resume,
1835 #endif /* CONFIG_PM */
1836 };
1837
1838
1839 static int __init tulip_init (void)
1840 {
1841 #ifdef MODULE
1842 printk (KERN_INFO "%s", version);
1843 #endif
1844
1845 /* copy module parms into globals */
1846 tulip_rx_copybreak = rx_copybreak;
1847 tulip_max_interrupt_work = max_interrupt_work;
1848
1849 /* probe for and init boards */
1850 return pci_module_init (&tulip_driver);
1851 }
1852
1853
1854 static void __exit tulip_cleanup (void)
1855 {
1856 pci_unregister_driver (&tulip_driver);
1857 }
1858
1859
1860 module_init(tulip_init);
1861 module_exit(tulip_cleanup);
Verdex Pro support