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[TG3]: Set minimal hw interrupt mitigation.
[linux-2.6/verdex.git] / drivers / net / via-velocity.h
blob1b70b7c975807c4e3b965e00f890940238b250a2
1 /*
2 * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc.
3 * All rights reserved.
4 *
5 * This software may be redistributed and/or modified under
6 * the terms of the GNU General Public License as published by the Free
7 * Software Foundation; either version 2 of the License, or
8 * any later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
12 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * for more details.
14 *
15 * File: via-velocity.h
16 *
17 * Purpose: Header file to define driver's private structures.
18 *
19 * Author: Chuang Liang-Shing, AJ Jiang
20 *
21 * Date: Jan 24, 2003
22 */
23
24
25 #ifndef VELOCITY_H
26 #define VELOCITY_H
27
28 #define VELOCITY_TX_CSUM_SUPPORT
29
30 #define VELOCITY_NAME "via-velocity"
31 #define VELOCITY_FULL_DRV_NAM "VIA Networking Velocity Family Gigabit Ethernet Adapter Driver"
32 #define VELOCITY_VERSION "1.13"
33
34 #define PKT_BUF_SZ 1540
35
36 #define MAX_UNITS 8
37 #define OPTION_DEFAULT { [0 ... MAX_UNITS-1] = -1}
38
39 #define REV_ID_VT6110 (0)
40
41 #define BYTE_REG_BITS_ON(x,p) do { writeb(readb((p))|(x),(p));} while (0)
42 #define WORD_REG_BITS_ON(x,p) do { writew(readw((p))|(x),(p));} while (0)
43 #define DWORD_REG_BITS_ON(x,p) do { writel(readl((p))|(x),(p));} while (0)
44
45 #define BYTE_REG_BITS_IS_ON(x,p) (readb((p)) & (x))
46 #define WORD_REG_BITS_IS_ON(x,p) (readw((p)) & (x))
47 #define DWORD_REG_BITS_IS_ON(x,p) (readl((p)) & (x))
48
49 #define BYTE_REG_BITS_OFF(x,p) do { writeb(readb((p)) & (~(x)),(p));} while (0)
50 #define WORD_REG_BITS_OFF(x,p) do { writew(readw((p)) & (~(x)),(p));} while (0)
51 #define DWORD_REG_BITS_OFF(x,p) do { writel(readl((p)) & (~(x)),(p));} while (0)
52
53 #define BYTE_REG_BITS_SET(x,m,p) do { writeb( (readb((p)) & (~(m))) |(x),(p));} while (0)
54 #define WORD_REG_BITS_SET(x,m,p) do { writew( (readw((p)) & (~(m))) |(x),(p));} while (0)
55 #define DWORD_REG_BITS_SET(x,m,p) do { writel( (readl((p)) & (~(m)))|(x),(p));} while (0)
56
57 #define VAR_USED(p) do {(p)=(p);} while (0)
58
59 /*
60 * Purpose: Structures for MAX RX/TX descriptors.
61 */
62
63
64 #define B_OWNED_BY_CHIP 1
65 #define B_OWNED_BY_HOST 0
66
67 /*
68 * Bits in the RSR0 register
69 */
70
71 #define RSR_DETAG 0x0080
72 #define RSR_SNTAG 0x0040
73 #define RSR_RXER 0x0020
74 #define RSR_RL 0x0010
75 #define RSR_CE 0x0008
76 #define RSR_FAE 0x0004
77 #define RSR_CRC 0x0002
78 #define RSR_VIDM 0x0001
79
80 /*
81 * Bits in the RSR1 register
82 */
83
84 #define RSR_RXOK 0x8000 // rx OK
85 #define RSR_PFT 0x4000 // Perfect filtering address match
86 #define RSR_MAR 0x2000 // MAC accept multicast address packet
87 #define RSR_BAR 0x1000 // MAC accept broadcast address packet
88 #define RSR_PHY 0x0800 // MAC accept physical address packet
89 #define RSR_VTAG 0x0400 // 802.1p/1q tagging packet indicator
90 #define RSR_STP 0x0200 // start of packet
91 #define RSR_EDP 0x0100 // end of packet
92
93 /*
94 * Bits in the RSR1 register
95 */
96
97 #define RSR1_RXOK 0x80 // rx OK
98 #define RSR1_PFT 0x40 // Perfect filtering address match
99 #define RSR1_MAR 0x20 // MAC accept multicast address packet
100 #define RSR1_BAR 0x10 // MAC accept broadcast address packet
101 #define RSR1_PHY 0x08 // MAC accept physical address packet
102 #define RSR1_VTAG 0x04 // 802.1p/1q tagging packet indicator
103 #define RSR1_STP 0x02 // start of packet
104 #define RSR1_EDP 0x01 // end of packet
105
106 /*
107 * Bits in the CSM register
108 */
109
110 #define CSM_IPOK 0x40 //IP Checkusm validatiaon ok
111 #define CSM_TUPOK 0x20 //TCP/UDP Checkusm validatiaon ok
112 #define CSM_FRAG 0x10 //Fragment IP datagram
113 #define CSM_IPKT 0x04 //Received an IP packet
114 #define CSM_TCPKT 0x02 //Received a TCP packet
115 #define CSM_UDPKT 0x01 //Received a UDP packet
116
117 /*
118 * Bits in the TSR0 register
119 */
120
121 #define TSR0_ABT 0x0080 // Tx abort because of excessive collision
122 #define TSR0_OWT 0x0040 // Jumbo frame Tx abort
123 #define TSR0_OWC 0x0020 // Out of window collision
124 #define TSR0_COLS 0x0010 // experience collision in this transmit event
125 #define TSR0_NCR3 0x0008 // collision retry counter[3]
126 #define TSR0_NCR2 0x0004 // collision retry counter[2]
127 #define TSR0_NCR1 0x0002 // collision retry counter[1]
128 #define TSR0_NCR0 0x0001 // collision retry counter[0]
129 #define TSR0_TERR 0x8000 //
130 #define TSR0_FDX 0x4000 // current transaction is serviced by full duplex mode
131 #define TSR0_GMII 0x2000 // current transaction is serviced by GMII mode
132 #define TSR0_LNKFL 0x1000 // packet serviced during link down
133 #define TSR0_SHDN 0x0400 // shutdown case
134 #define TSR0_CRS 0x0200 // carrier sense lost
135 #define TSR0_CDH 0x0100 // AQE test fail (CD heartbeat)
136
137 /*
138 * Bits in the TSR1 register
139 */
140
141 #define TSR1_TERR 0x80 //
142 #define TSR1_FDX 0x40 // current transaction is serviced by full duplex mode
143 #define TSR1_GMII 0x20 // current transaction is serviced by GMII mode
144 #define TSR1_LNKFL 0x10 // packet serviced during link down
145 #define TSR1_SHDN 0x04 // shutdown case
146 #define TSR1_CRS 0x02 // carrier sense lost
147 #define TSR1_CDH 0x01 // AQE test fail (CD heartbeat)
148
149 //
150 // Bits in the TCR0 register
151 //
152 #define TCR0_TIC 0x80 // assert interrupt immediately while descriptor has been send complete
153 #define TCR0_PIC 0x40 // priority interrupt request, INA# is issued over adaptive interrupt scheme
154 #define TCR0_VETAG 0x20 // enable VLAN tag
155 #define TCR0_IPCK 0x10 // request IP checksum calculation.
156 #define TCR0_UDPCK 0x08 // request UDP checksum calculation.
157 #define TCR0_TCPCK 0x04 // request TCP checksum calculation.
158 #define TCR0_JMBO 0x02 // indicate a jumbo packet in GMAC side
159 #define TCR0_CRC 0x01 // disable CRC generation
160
161 #define TCPLS_NORMAL 3
162 #define TCPLS_START 2
163 #define TCPLS_END 1
164 #define TCPLS_MED 0
165
166
167 // max transmit or receive buffer size
168 #define CB_RX_BUF_SIZE 2048UL // max buffer size
169 // NOTE: must be multiple of 4
170
171 #define CB_MAX_RD_NUM 512 // MAX # of RD
172 #define CB_MAX_TD_NUM 256 // MAX # of TD
173
174 #define CB_INIT_RD_NUM_3119 128 // init # of RD, for setup VT3119
175 #define CB_INIT_TD_NUM_3119 64 // init # of TD, for setup VT3119
176
177 #define CB_INIT_RD_NUM 128 // init # of RD, for setup default
178 #define CB_INIT_TD_NUM 64 // init # of TD, for setup default
179
180 // for 3119
181 #define CB_TD_RING_NUM 4 // # of TD rings.
182 #define CB_MAX_SEG_PER_PKT 7 // max data seg per packet (Tx)
183
184
185 /*
186 * If collisions excess 15 times , tx will abort, and
187 * if tx fifo underflow, tx will fail
188 * we should try to resend it
189 */
190
191 #define CB_MAX_TX_ABORT_RETRY 3
192
193 /*
194 * Receive descriptor
195 */
196
197 struct rdesc0 {
198 u16 RSR; /* Receive status */
199 u16 len:14; /* Received packet length */
200 u16 reserved:1;
201 u16 owner:1; /* Who owns this buffer ? */
202 };
203
204 struct rdesc1 {
205 u16 PQTAG;
206 u8 CSM;
207 u8 IPKT;
208 };
209
210 struct rx_desc {
211 struct rdesc0 rdesc0;
212 struct rdesc1 rdesc1;
213 u32 pa_low; /* Low 32 bit PCI address */
214 u16 pa_high; /* Next 16 bit PCI address (48 total) */
215 u16 len:15; /* Frame size */
216 u16 inten:1; /* Enable interrupt */
217 } __attribute__ ((__packed__));
218
219 /*
220 * Transmit descriptor
221 */
222
223 struct tdesc0 {
224 u16 TSR; /* Transmit status register */
225 u16 pktsize:14; /* Size of frame */
226 u16 reserved:1;
227 u16 owner:1; /* Who owns the buffer */
228 };
229
230 struct pqinf { /* Priority queue info */
231 u16 VID:12;
232 u16 CFI:1;
233 u16 priority:3;
234 } __attribute__ ((__packed__));
235
236 struct tdesc1 {
237 struct pqinf pqinf;
238 u8 TCR;
239 u8 TCPLS:2;
240 u8 reserved:2;
241 u8 CMDZ:4;
242 } __attribute__ ((__packed__));
243
244 struct td_buf {
245 u32 pa_low;
246 u16 pa_high;
247 u16 bufsize:14;
248 u16 reserved:1;
249 u16 queue:1;
250 } __attribute__ ((__packed__));
251
252 struct tx_desc {
253 struct tdesc0 tdesc0;
254 struct tdesc1 tdesc1;
255 struct td_buf td_buf[7];
256 };
257
258 struct velocity_rd_info {
259 struct sk_buff *skb;
260 dma_addr_t skb_dma;
261 };
262
263 /**
264 * alloc_rd_info - allocate an rd info block
265 *
266 * Alocate and initialize a receive info structure used for keeping
267 * track of kernel side information related to each receive
268 * descriptor we are using
269 */
270
271 static inline struct velocity_rd_info *alloc_rd_info(void)
272 {
273 struct velocity_rd_info *ptr;
274 if ((ptr = kmalloc(sizeof(struct velocity_rd_info), GFP_ATOMIC)) == NULL)
275 return NULL;
276 else {
277 memset(ptr, 0, sizeof(struct velocity_rd_info));
278 return ptr;
279 }
280 }
281
282 /*
283 * Used to track transmit side buffers.
284 */
285
286 struct velocity_td_info {
287 struct sk_buff *skb;
288 u8 *buf;
289 int nskb_dma;
290 dma_addr_t skb_dma[7];
291 dma_addr_t buf_dma;
292 };
293
294 enum velocity_owner {
295 OWNED_BY_HOST = 0,
296 OWNED_BY_NIC = 1
297 };
298
299
300 /*
301 * MAC registers and macros.
302 */
303
304
305 #define MCAM_SIZE 64
306 #define VCAM_SIZE 64
307 #define TX_QUEUE_NO 4
308
309 #define MAX_HW_MIB_COUNTER 32
310 #define VELOCITY_MIN_MTU (1514-14)
311 #define VELOCITY_MAX_MTU (9000)
312
313 /*
314 * Registers in the MAC
315 */
316
317 #define MAC_REG_PAR 0x00 // physical address
318 #define MAC_REG_RCR 0x06
319 #define MAC_REG_TCR 0x07
320 #define MAC_REG_CR0_SET 0x08
321 #define MAC_REG_CR1_SET 0x09
322 #define MAC_REG_CR2_SET 0x0A
323 #define MAC_REG_CR3_SET 0x0B
324 #define MAC_REG_CR0_CLR 0x0C
325 #define MAC_REG_CR1_CLR 0x0D
326 #define MAC_REG_CR2_CLR 0x0E
327 #define MAC_REG_CR3_CLR 0x0F
328 #define MAC_REG_MAR 0x10
329 #define MAC_REG_CAM 0x10
330 #define MAC_REG_DEC_BASE_HI 0x18
331 #define MAC_REG_DBF_BASE_HI 0x1C
332 #define MAC_REG_ISR_CTL 0x20
333 #define MAC_REG_ISR_HOTMR 0x20
334 #define MAC_REG_ISR_TSUPTHR 0x20
335 #define MAC_REG_ISR_RSUPTHR 0x20
336 #define MAC_REG_ISR_CTL1 0x21
337 #define MAC_REG_TXE_SR 0x22
338 #define MAC_REG_RXE_SR 0x23
339 #define MAC_REG_ISR 0x24
340 #define MAC_REG_ISR0 0x24
341 #define MAC_REG_ISR1 0x25
342 #define MAC_REG_ISR2 0x26
343 #define MAC_REG_ISR3 0x27
344 #define MAC_REG_IMR 0x28
345 #define MAC_REG_IMR0 0x28
346 #define MAC_REG_IMR1 0x29
347 #define MAC_REG_IMR2 0x2A
348 #define MAC_REG_IMR3 0x2B
349 #define MAC_REG_TDCSR_SET 0x30
350 #define MAC_REG_RDCSR_SET 0x32
351 #define MAC_REG_TDCSR_CLR 0x34
352 #define MAC_REG_RDCSR_CLR 0x36
353 #define MAC_REG_RDBASE_LO 0x38
354 #define MAC_REG_RDINDX 0x3C
355 #define MAC_REG_TDBASE_LO 0x40
356 #define MAC_REG_RDCSIZE 0x50
357 #define MAC_REG_TDCSIZE 0x52
358 #define MAC_REG_TDINDX 0x54
359 #define MAC_REG_TDIDX0 0x54
360 #define MAC_REG_TDIDX1 0x56
361 #define MAC_REG_TDIDX2 0x58
362 #define MAC_REG_TDIDX3 0x5A
363 #define MAC_REG_PAUSE_TIMER 0x5C
364 #define MAC_REG_RBRDU 0x5E
365 #define MAC_REG_FIFO_TEST0 0x60
366 #define MAC_REG_FIFO_TEST1 0x64
367 #define MAC_REG_CAMADDR 0x68
368 #define MAC_REG_CAMCR 0x69
369 #define MAC_REG_GFTEST 0x6A
370 #define MAC_REG_FTSTCMD 0x6B
371 #define MAC_REG_MIICFG 0x6C
372 #define MAC_REG_MIISR 0x6D
373 #define MAC_REG_PHYSR0 0x6E
374 #define MAC_REG_PHYSR1 0x6F
375 #define MAC_REG_MIICR 0x70
376 #define MAC_REG_MIIADR 0x71
377 #define MAC_REG_MIIDATA 0x72
378 #define MAC_REG_SOFT_TIMER0 0x74
379 #define MAC_REG_SOFT_TIMER1 0x76
380 #define MAC_REG_CFGA 0x78
381 #define MAC_REG_CFGB 0x79
382 #define MAC_REG_CFGC 0x7A
383 #define MAC_REG_CFGD 0x7B
384 #define MAC_REG_DCFG0 0x7C
385 #define MAC_REG_DCFG1 0x7D
386 #define MAC_REG_MCFG0 0x7E
387 #define MAC_REG_MCFG1 0x7F
388
389 #define MAC_REG_TBIST 0x80
390 #define MAC_REG_RBIST 0x81
391 #define MAC_REG_PMCC 0x82
392 #define MAC_REG_STICKHW 0x83
393 #define MAC_REG_MIBCR 0x84
394 #define MAC_REG_EERSV 0x85
395 #define MAC_REG_REVID 0x86
396 #define MAC_REG_MIBREAD 0x88
397 #define MAC_REG_BPMA 0x8C
398 #define MAC_REG_EEWR_DATA 0x8C
399 #define MAC_REG_BPMD_WR 0x8F
400 #define MAC_REG_BPCMD 0x90
401 #define MAC_REG_BPMD_RD 0x91
402 #define MAC_REG_EECHKSUM 0x92
403 #define MAC_REG_EECSR 0x93
404 #define MAC_REG_EERD_DATA 0x94
405 #define MAC_REG_EADDR 0x96
406 #define MAC_REG_EMBCMD 0x97
407 #define MAC_REG_JMPSR0 0x98
408 #define MAC_REG_JMPSR1 0x99
409 #define MAC_REG_JMPSR2 0x9A
410 #define MAC_REG_JMPSR3 0x9B
411 #define MAC_REG_CHIPGSR 0x9C
412 #define MAC_REG_TESTCFG 0x9D
413 #define MAC_REG_DEBUG 0x9E
414 #define MAC_REG_CHIPGCR 0x9F
415 #define MAC_REG_WOLCR0_SET 0xA0
416 #define MAC_REG_WOLCR1_SET 0xA1
417 #define MAC_REG_PWCFG_SET 0xA2
418 #define MAC_REG_WOLCFG_SET 0xA3
419 #define MAC_REG_WOLCR0_CLR 0xA4
420 #define MAC_REG_WOLCR1_CLR 0xA5
421 #define MAC_REG_PWCFG_CLR 0xA6
422 #define MAC_REG_WOLCFG_CLR 0xA7
423 #define MAC_REG_WOLSR0_SET 0xA8
424 #define MAC_REG_WOLSR1_SET 0xA9
425 #define MAC_REG_WOLSR0_CLR 0xAC
426 #define MAC_REG_WOLSR1_CLR 0xAD
427 #define MAC_REG_PATRN_CRC0 0xB0
428 #define MAC_REG_PATRN_CRC1 0xB2
429 #define MAC_REG_PATRN_CRC2 0xB4
430 #define MAC_REG_PATRN_CRC3 0xB6
431 #define MAC_REG_PATRN_CRC4 0xB8
432 #define MAC_REG_PATRN_CRC5 0xBA
433 #define MAC_REG_PATRN_CRC6 0xBC
434 #define MAC_REG_PATRN_CRC7 0xBE
435 #define MAC_REG_BYTEMSK0_0 0xC0
436 #define MAC_REG_BYTEMSK0_1 0xC4
437 #define MAC_REG_BYTEMSK0_2 0xC8
438 #define MAC_REG_BYTEMSK0_3 0xCC
439 #define MAC_REG_BYTEMSK1_0 0xD0
440 #define MAC_REG_BYTEMSK1_1 0xD4
441 #define MAC_REG_BYTEMSK1_2 0xD8
442 #define MAC_REG_BYTEMSK1_3 0xDC
443 #define MAC_REG_BYTEMSK2_0 0xE0
444 #define MAC_REG_BYTEMSK2_1 0xE4
445 #define MAC_REG_BYTEMSK2_2 0xE8
446 #define MAC_REG_BYTEMSK2_3 0xEC
447 #define MAC_REG_BYTEMSK3_0 0xF0
448 #define MAC_REG_BYTEMSK3_1 0xF4
449 #define MAC_REG_BYTEMSK3_2 0xF8
450 #define MAC_REG_BYTEMSK3_3 0xFC
451
452 /*
453 * Bits in the RCR register
454 */
455
456 #define RCR_AS 0x80
457 #define RCR_AP 0x40
458 #define RCR_AL 0x20
459 #define RCR_PROM 0x10
460 #define RCR_AB 0x08
461 #define RCR_AM 0x04
462 #define RCR_AR 0x02
463 #define RCR_SEP 0x01
464
465 /*
466 * Bits in the TCR register
467 */
468
469 #define TCR_TB2BDIS 0x80
470 #define TCR_COLTMC1 0x08
471 #define TCR_COLTMC0 0x04
472 #define TCR_LB1 0x02 /* loopback[1] */
473 #define TCR_LB0 0x01 /* loopback[0] */
474
475 /*
476 * Bits in the CR0 register
477 */
478
479 #define CR0_TXON 0x00000008UL
480 #define CR0_RXON 0x00000004UL
481 #define CR0_STOP 0x00000002UL /* stop MAC, default = 1 */
482 #define CR0_STRT 0x00000001UL /* start MAC */
483 #define CR0_SFRST 0x00008000UL /* software reset */
484 #define CR0_TM1EN 0x00004000UL
485 #define CR0_TM0EN 0x00002000UL
486 #define CR0_DPOLL 0x00000800UL /* disable rx/tx auto polling */
487 #define CR0_DISAU 0x00000100UL
488 #define CR0_XONEN 0x00800000UL
489 #define CR0_FDXTFCEN 0x00400000UL /* full-duplex TX flow control enable */
490 #define CR0_FDXRFCEN 0x00200000UL /* full-duplex RX flow control enable */
491 #define CR0_HDXFCEN 0x00100000UL /* half-duplex flow control enable */
492 #define CR0_XHITH1 0x00080000UL /* TX XON high threshold 1 */
493 #define CR0_XHITH0 0x00040000UL /* TX XON high threshold 0 */
494 #define CR0_XLTH1 0x00020000UL /* TX pause frame low threshold 1 */
495 #define CR0_XLTH0 0x00010000UL /* TX pause frame low threshold 0 */
496 #define CR0_GSPRST 0x80000000UL
497 #define CR0_FORSRST 0x40000000UL
498 #define CR0_FPHYRST 0x20000000UL
499 #define CR0_DIAG 0x10000000UL
500 #define CR0_INTPCTL 0x04000000UL
501 #define CR0_GINTMSK1 0x02000000UL
502 #define CR0_GINTMSK0 0x01000000UL
503
504 /*
505 * Bits in the CR1 register
506 */
507
508 #define CR1_SFRST 0x80 /* software reset */
509 #define CR1_TM1EN 0x40
510 #define CR1_TM0EN 0x20
511 #define CR1_DPOLL 0x08 /* disable rx/tx auto polling */
512 #define CR1_DISAU 0x01
513
514 /*
515 * Bits in the CR2 register
516 */
517
518 #define CR2_XONEN 0x80
519 #define CR2_FDXTFCEN 0x40 /* full-duplex TX flow control enable */
520 #define CR2_FDXRFCEN 0x20 /* full-duplex RX flow control enable */
521 #define CR2_HDXFCEN 0x10 /* half-duplex flow control enable */
522 #define CR2_XHITH1 0x08 /* TX XON high threshold 1 */
523 #define CR2_XHITH0 0x04 /* TX XON high threshold 0 */
524 #define CR2_XLTH1 0x02 /* TX pause frame low threshold 1 */
525 #define CR2_XLTH0 0x01 /* TX pause frame low threshold 0 */
526
527 /*
528 * Bits in the CR3 register
529 */
530
531 #define CR3_GSPRST 0x80
532 #define CR3_FORSRST 0x40
533 #define CR3_FPHYRST 0x20
534 #define CR3_DIAG 0x10
535 #define CR3_INTPCTL 0x04
536 #define CR3_GINTMSK1 0x02
537 #define CR3_GINTMSK0 0x01
538
539 #define ISRCTL_UDPINT 0x8000
540 #define ISRCTL_TSUPDIS 0x4000
541 #define ISRCTL_RSUPDIS 0x2000
542 #define ISRCTL_PMSK1 0x1000
543 #define ISRCTL_PMSK0 0x0800
544 #define ISRCTL_INTPD 0x0400
545 #define ISRCTL_HCRLD 0x0200
546 #define ISRCTL_SCRLD 0x0100
547
548 /*
549 * Bits in the ISR_CTL1 register
550 */
551
552 #define ISRCTL1_UDPINT 0x80
553 #define ISRCTL1_TSUPDIS 0x40
554 #define ISRCTL1_RSUPDIS 0x20
555 #define ISRCTL1_PMSK1 0x10
556 #define ISRCTL1_PMSK0 0x08
557 #define ISRCTL1_INTPD 0x04
558 #define ISRCTL1_HCRLD 0x02
559 #define ISRCTL1_SCRLD 0x01
560
561 /*
562 * Bits in the TXE_SR register
563 */
564
565 #define TXESR_TFDBS 0x08
566 #define TXESR_TDWBS 0x04
567 #define TXESR_TDRBS 0x02
568 #define TXESR_TDSTR 0x01
569
570 /*
571 * Bits in the RXE_SR register
572 */
573
574 #define RXESR_RFDBS 0x08
575 #define RXESR_RDWBS 0x04
576 #define RXESR_RDRBS 0x02
577 #define RXESR_RDSTR 0x01
578
579 /*
580 * Bits in the ISR register
581 */
582
583 #define ISR_ISR3 0x80000000UL
584 #define ISR_ISR2 0x40000000UL
585 #define ISR_ISR1 0x20000000UL
586 #define ISR_ISR0 0x10000000UL
587 #define ISR_TXSTLI 0x02000000UL
588 #define ISR_RXSTLI 0x01000000UL
589 #define ISR_HFLD 0x00800000UL
590 #define ISR_UDPI 0x00400000UL
591 #define ISR_MIBFI 0x00200000UL
592 #define ISR_SHDNI 0x00100000UL
593 #define ISR_PHYI 0x00080000UL
594 #define ISR_PWEI 0x00040000UL
595 #define ISR_TMR1I 0x00020000UL
596 #define ISR_TMR0I 0x00010000UL
597 #define ISR_SRCI 0x00008000UL
598 #define ISR_LSTPEI 0x00004000UL
599 #define ISR_LSTEI 0x00002000UL
600 #define ISR_OVFI 0x00001000UL
601 #define ISR_FLONI 0x00000800UL
602 #define ISR_RACEI 0x00000400UL
603 #define ISR_TXWB1I 0x00000200UL
604 #define ISR_TXWB0I 0x00000100UL
605 #define ISR_PTX3I 0x00000080UL
606 #define ISR_PTX2I 0x00000040UL
607 #define ISR_PTX1I 0x00000020UL
608 #define ISR_PTX0I 0x00000010UL
609 #define ISR_PTXI 0x00000008UL
610 #define ISR_PRXI 0x00000004UL
611 #define ISR_PPTXI 0x00000002UL
612 #define ISR_PPRXI 0x00000001UL
613
614 /*
615 * Bits in the IMR register
616 */
617
618 #define IMR_TXSTLM 0x02000000UL
619 #define IMR_UDPIM 0x00400000UL
620 #define IMR_MIBFIM 0x00200000UL
621 #define IMR_SHDNIM 0x00100000UL
622 #define IMR_PHYIM 0x00080000UL
623 #define IMR_PWEIM 0x00040000UL
624 #define IMR_TMR1IM 0x00020000UL
625 #define IMR_TMR0IM 0x00010000UL
626
627 #define IMR_SRCIM 0x00008000UL
628 #define IMR_LSTPEIM 0x00004000UL
629 #define IMR_LSTEIM 0x00002000UL
630 #define IMR_OVFIM 0x00001000UL
631 #define IMR_FLONIM 0x00000800UL
632 #define IMR_RACEIM 0x00000400UL
633 #define IMR_TXWB1IM 0x00000200UL
634 #define IMR_TXWB0IM 0x00000100UL
635
636 #define IMR_PTX3IM 0x00000080UL
637 #define IMR_PTX2IM 0x00000040UL
638 #define IMR_PTX1IM 0x00000020UL
639 #define IMR_PTX0IM 0x00000010UL
640 #define IMR_PTXIM 0x00000008UL
641 #define IMR_PRXIM 0x00000004UL
642 #define IMR_PPTXIM 0x00000002UL
643 #define IMR_PPRXIM 0x00000001UL
644
645 /* 0x0013FB0FUL = initial value of IMR */
646
647 #define INT_MASK_DEF (IMR_PPTXIM|IMR_PPRXIM|IMR_PTXIM|IMR_PRXIM|\
648 IMR_PWEIM|IMR_TXWB0IM|IMR_TXWB1IM|IMR_FLONIM|\
649 IMR_OVFIM|IMR_LSTEIM|IMR_LSTPEIM|IMR_SRCIM|IMR_MIBFIM|\
650 IMR_SHDNIM|IMR_TMR1IM|IMR_TMR0IM|IMR_TXSTLM)
651
652 /*
653 * Bits in the TDCSR0/1, RDCSR0 register
654 */
655
656 #define TRDCSR_DEAD 0x0008
657 #define TRDCSR_WAK 0x0004
658 #define TRDCSR_ACT 0x0002
659 #define TRDCSR_RUN 0x0001
660
661 /*
662 * Bits in the CAMADDR register
663 */
664
665 #define CAMADDR_CAMEN 0x80
666 #define CAMADDR_VCAMSL 0x40
667
668 /*
669 * Bits in the CAMCR register
670 */
671
672 #define CAMCR_PS1 0x80
673 #define CAMCR_PS0 0x40
674 #define CAMCR_AITRPKT 0x20
675 #define CAMCR_AITR16 0x10
676 #define CAMCR_CAMRD 0x08
677 #define CAMCR_CAMWR 0x04
678 #define CAMCR_PS_CAM_MASK 0x40
679 #define CAMCR_PS_CAM_DATA 0x80
680 #define CAMCR_PS_MAR 0x00
681
682 /*
683 * Bits in the MIICFG register
684 */
685
686 #define MIICFG_MPO1 0x80
687 #define MIICFG_MPO0 0x40
688 #define MIICFG_MFDC 0x20
689
690 /*
691 * Bits in the MIISR register
692 */
693
694 #define MIISR_MIDLE 0x80
695
696 /*
697 * Bits in the PHYSR0 register
698 */
699
700 #define PHYSR0_PHYRST 0x80
701 #define PHYSR0_LINKGD 0x40
702 #define PHYSR0_FDPX 0x10
703 #define PHYSR0_SPDG 0x08
704 #define PHYSR0_SPD10 0x04
705 #define PHYSR0_RXFLC 0x02
706 #define PHYSR0_TXFLC 0x01
707
708 /*
709 * Bits in the PHYSR1 register
710 */
711
712 #define PHYSR1_PHYTBI 0x01
713
714 /*
715 * Bits in the MIICR register
716 */
717
718 #define MIICR_MAUTO 0x80
719 #define MIICR_RCMD 0x40
720 #define MIICR_WCMD 0x20
721 #define MIICR_MDPM 0x10
722 #define MIICR_MOUT 0x08
723 #define MIICR_MDO 0x04
724 #define MIICR_MDI 0x02
725 #define MIICR_MDC 0x01
726
727 /*
728 * Bits in the MIIADR register
729 */
730
731 #define MIIADR_SWMPL 0x80
732
733 /*
734 * Bits in the CFGA register
735 */
736
737 #define CFGA_PMHCTG 0x08
738 #define CFGA_GPIO1PD 0x04
739 #define CFGA_ABSHDN 0x02
740 #define CFGA_PACPI 0x01
741
742 /*
743 * Bits in the CFGB register
744 */
745
746 #define CFGB_GTCKOPT 0x80
747 #define CFGB_MIIOPT 0x40
748 #define CFGB_CRSEOPT 0x20
749 #define CFGB_OFSET 0x10
750 #define CFGB_CRANDOM 0x08
751 #define CFGB_CAP 0x04
752 #define CFGB_MBA 0x02
753 #define CFGB_BAKOPT 0x01
754
755 /*
756 * Bits in the CFGC register
757 */
758
759 #define CFGC_EELOAD 0x80
760 #define CFGC_BROPT 0x40
761 #define CFGC_DLYEN 0x20
762 #define CFGC_DTSEL 0x10
763 #define CFGC_BTSEL 0x08
764 #define CFGC_BPS2 0x04 /* bootrom select[2] */
765 #define CFGC_BPS1 0x02 /* bootrom select[1] */
766 #define CFGC_BPS0 0x01 /* bootrom select[0] */
767
768 /*
769 * Bits in the CFGD register
770 */
771
772 #define CFGD_IODIS 0x80
773 #define CFGD_MSLVDACEN 0x40
774 #define CFGD_CFGDACEN 0x20
775 #define CFGD_PCI64EN 0x10
776 #define CFGD_HTMRL4 0x08
777
778 /*
779 * Bits in the DCFG1 register
780 */
781
782 #define DCFG_XMWI 0x8000
783 #define DCFG_XMRM 0x4000
784 #define DCFG_XMRL 0x2000
785 #define DCFG_PERDIS 0x1000
786 #define DCFG_MRWAIT 0x0400
787 #define DCFG_MWWAIT 0x0200
788 #define DCFG_LATMEN 0x0100
789
790 /*
791 * Bits in the MCFG0 register
792 */
793
794 #define MCFG_RXARB 0x0080
795 #define MCFG_RFT1 0x0020
796 #define MCFG_RFT0 0x0010
797 #define MCFG_LOWTHOPT 0x0008
798 #define MCFG_PQEN 0x0004
799 #define MCFG_RTGOPT 0x0002
800 #define MCFG_VIDFR 0x0001
801
802 /*
803 * Bits in the MCFG1 register
804 */
805
806 #define MCFG_TXARB 0x8000
807 #define MCFG_TXQBK1 0x0800
808 #define MCFG_TXQBK0 0x0400
809 #define MCFG_TXQNOBK 0x0200
810 #define MCFG_SNAPOPT 0x0100
811
812 /*
813 * Bits in the PMCC register
814 */
815
816 #define PMCC_DSI 0x80
817 #define PMCC_D2_DIS 0x40
818 #define PMCC_D1_DIS 0x20
819 #define PMCC_D3C_EN 0x10
820 #define PMCC_D3H_EN 0x08
821 #define PMCC_D2_EN 0x04
822 #define PMCC_D1_EN 0x02
823 #define PMCC_D0_EN 0x01
824
825 /*
826 * Bits in STICKHW
827 */
828
829 #define STICKHW_SWPTAG 0x10
830 #define STICKHW_WOLSR 0x08
831 #define STICKHW_WOLEN 0x04
832 #define STICKHW_DS1 0x02 /* R/W by software/cfg cycle */
833 #define STICKHW_DS0 0x01 /* suspend well DS write port */
834
835 /*
836 * Bits in the MIBCR register
837 */
838
839 #define MIBCR_MIBISTOK 0x80
840 #define MIBCR_MIBISTGO 0x40
841 #define MIBCR_MIBINC 0x20
842 #define MIBCR_MIBHI 0x10
843 #define MIBCR_MIBFRZ 0x08
844 #define MIBCR_MIBFLSH 0x04
845 #define MIBCR_MPTRINI 0x02
846 #define MIBCR_MIBCLR 0x01
847
848 /*
849 * Bits in the EERSV register
850 */
851
852 #define EERSV_BOOT_RPL ((u8) 0x01) /* Boot method selection for VT6110 */
853
854 #define EERSV_BOOT_MASK ((u8) 0x06)
855 #define EERSV_BOOT_INT19 ((u8) 0x00)
856 #define EERSV_BOOT_INT18 ((u8) 0x02)
857 #define EERSV_BOOT_LOCAL ((u8) 0x04)
858 #define EERSV_BOOT_BEV ((u8) 0x06)
859
860
861 /*
862 * Bits in BPCMD
863 */
864
865 #define BPCMD_BPDNE 0x80
866 #define BPCMD_EBPWR 0x02
867 #define BPCMD_EBPRD 0x01
868
869 /*
870 * Bits in the EECSR register
871 */
872
873 #define EECSR_EMBP 0x40 /* eeprom embeded programming */
874 #define EECSR_RELOAD 0x20 /* eeprom content reload */
875 #define EECSR_DPM 0x10 /* eeprom direct programming */
876 #define EECSR_ECS 0x08 /* eeprom CS pin */
877 #define EECSR_ECK 0x04 /* eeprom CK pin */
878 #define EECSR_EDI 0x02 /* eeprom DI pin */
879 #define EECSR_EDO 0x01 /* eeprom DO pin */
880
881 /*
882 * Bits in the EMBCMD register
883 */
884
885 #define EMBCMD_EDONE 0x80
886 #define EMBCMD_EWDIS 0x08
887 #define EMBCMD_EWEN 0x04
888 #define EMBCMD_EWR 0x02
889 #define EMBCMD_ERD 0x01
890
891 /*
892 * Bits in TESTCFG register
893 */
894
895 #define TESTCFG_HBDIS 0x80
896
897 /*
898 * Bits in CHIPGCR register
899 */
900
901 #define CHIPGCR_FCGMII 0x80
902 #define CHIPGCR_FCFDX 0x40
903 #define CHIPGCR_FCRESV 0x20
904 #define CHIPGCR_FCMODE 0x10
905 #define CHIPGCR_LPSOPT 0x08
906 #define CHIPGCR_TM1US 0x04
907 #define CHIPGCR_TM0US 0x02
908 #define CHIPGCR_PHYINTEN 0x01
909
910 /*
911 * Bits in WOLCR0
912 */
913
914 #define WOLCR_MSWOLEN7 0x0080 /* enable pattern match filtering */
915 #define WOLCR_MSWOLEN6 0x0040
916 #define WOLCR_MSWOLEN5 0x0020
917 #define WOLCR_MSWOLEN4 0x0010
918 #define WOLCR_MSWOLEN3 0x0008
919 #define WOLCR_MSWOLEN2 0x0004
920 #define WOLCR_MSWOLEN1 0x0002
921 #define WOLCR_MSWOLEN0 0x0001
922 #define WOLCR_ARP_EN 0x0001
923
924 /*
925 * Bits in WOLCR1
926 */
927
928 #define WOLCR_LINKOFF_EN 0x0800 /* link off detected enable */
929 #define WOLCR_LINKON_EN 0x0400 /* link on detected enable */
930 #define WOLCR_MAGIC_EN 0x0200 /* magic packet filter enable */
931 #define WOLCR_UNICAST_EN 0x0100 /* unicast filter enable */
932
933
934 /*
935 * Bits in PWCFG
936 */
937
938 #define PWCFG_PHYPWOPT 0x80 /* internal MII I/F timing */
939 #define PWCFG_PCISTICK 0x40 /* PCI sticky R/W enable */
940 #define PWCFG_WOLTYPE 0x20 /* pulse(1) or button (0) */
941 #define PWCFG_LEGCY_WOL 0x10
942 #define PWCFG_PMCSR_PME_SR 0x08
943 #define PWCFG_PMCSR_PME_EN 0x04 /* control by PCISTICK */
944 #define PWCFG_LEGACY_WOLSR 0x02 /* Legacy WOL_SR shadow */
945 #define PWCFG_LEGACY_WOLEN 0x01 /* Legacy WOL_EN shadow */
946
947 /*
948 * Bits in WOLCFG
949 */
950
951 #define WOLCFG_PMEOVR 0x80 /* for legacy use, force PMEEN always */
952 #define WOLCFG_SAM 0x20 /* accept multicast case reset, default=0 */
953 #define WOLCFG_SAB 0x10 /* accept broadcast case reset, default=0 */
954 #define WOLCFG_SMIIACC 0x08 /* ?? */
955 #define WOLCFG_SGENWH 0x02
956 #define WOLCFG_PHYINTEN 0x01 /* 0:PHYINT trigger enable, 1:use internal MII
957 to report status change */
958 /*
959 * Bits in WOLSR1
960 */
961
962 #define WOLSR_LINKOFF_INT 0x0800
963 #define WOLSR_LINKON_INT 0x0400
964 #define WOLSR_MAGIC_INT 0x0200
965 #define WOLSR_UNICAST_INT 0x0100
966
967 /*
968 * Ethernet address filter type
969 */
970
971 #define PKT_TYPE_NONE 0x0000 /* Turn off receiver */
972 #define PKT_TYPE_DIRECTED 0x0001 /* obselete, directed address is always accepted */
973 #define PKT_TYPE_MULTICAST 0x0002
974 #define PKT_TYPE_ALL_MULTICAST 0x0004
975 #define PKT_TYPE_BROADCAST 0x0008
976 #define PKT_TYPE_PROMISCUOUS 0x0020
977 #define PKT_TYPE_LONG 0x2000 /* NOTE.... the definition of LONG is >2048 bytes in our chip */
978 #define PKT_TYPE_RUNT 0x4000
979 #define PKT_TYPE_ERROR 0x8000 /* Accept error packets, e.g. CRC error */
980
981 /*
982 * Loopback mode
983 */
984
985 #define MAC_LB_NONE 0x00
986 #define MAC_LB_INTERNAL 0x01
987 #define MAC_LB_EXTERNAL 0x02
988
989 /*
990 * Enabled mask value of irq
991 */
992
993 #if defined(_SIM)
994 #define IMR_MASK_VALUE 0x0033FF0FUL /* initial value of IMR
995 set IMR0 to 0x0F according to spec */
996
997 #else
998 #define IMR_MASK_VALUE 0x0013FB0FUL /* initial value of IMR
999 ignore MIBFI,RACEI to
1000 reduce intr. frequency
1001 NOTE.... do not enable NoBuf int mask at driver driver
1002 when (1) NoBuf -> RxThreshold = SF
1003 (2) OK -> RxThreshold = original value
1004 */
1005 #endif
1006
1007 /*
1008 * Revision id
1009 */
1010
1011 #define REV_ID_VT3119_A0 0x00
1012 #define REV_ID_VT3119_A1 0x01
1013 #define REV_ID_VT3216_A0 0x10
1014
1015 /*
1016 * Max time out delay time
1017 */
1018
1019 #define W_MAX_TIMEOUT 0x0FFFU
1020
1021
1022 /*
1023 * MAC registers as a structure. Cannot be directly accessed this
1024 * way but generates offsets for readl/writel() calls
1025 */
1026
1027 struct mac_regs {
1028 volatile u8 PAR[6]; /* 0x00 */
1029 volatile u8 RCR;
1030 volatile u8 TCR;
1031
1032 volatile u32 CR0Set; /* 0x08 */
1033 volatile u32 CR0Clr; /* 0x0C */
1034
1035 volatile u8 MARCAM[8]; /* 0x10 */
1036
1037 volatile u32 DecBaseHi; /* 0x18 */
1038 volatile u16 DbfBaseHi; /* 0x1C */
1039 volatile u16 reserved_1E;
1040
1041 volatile u16 ISRCTL; /* 0x20 */
1042 volatile u8 TXESR;
1043 volatile u8 RXESR;
1044
1045 volatile u32 ISR; /* 0x24 */
1046 volatile u32 IMR;
1047
1048 volatile u32 TDStatusPort; /* 0x2C */
1049
1050 volatile u16 TDCSRSet; /* 0x30 */
1051 volatile u8 RDCSRSet;
1052 volatile u8 reserved_33;
1053 volatile u16 TDCSRClr;
1054 volatile u8 RDCSRClr;
1055 volatile u8 reserved_37;
1056
1057 volatile u32 RDBaseLo; /* 0x38 */
1058 volatile u16 RDIdx; /* 0x3C */
1059 volatile u16 reserved_3E;
1060
1061 volatile u32 TDBaseLo[4]; /* 0x40 */
1062
1063 volatile u16 RDCSize; /* 0x50 */
1064 volatile u16 TDCSize; /* 0x52 */
1065 volatile u16 TDIdx[4]; /* 0x54 */
1066 volatile u16 tx_pause_timer; /* 0x5C */
1067 volatile u16 RBRDU; /* 0x5E */
1068
1069 volatile u32 FIFOTest0; /* 0x60 */
1070 volatile u32 FIFOTest1; /* 0x64 */
1071
1072 volatile u8 CAMADDR; /* 0x68 */
1073 volatile u8 CAMCR; /* 0x69 */
1074 volatile u8 GFTEST; /* 0x6A */
1075 volatile u8 FTSTCMD; /* 0x6B */
1076
1077 volatile u8 MIICFG; /* 0x6C */
1078 volatile u8 MIISR;
1079 volatile u8 PHYSR0;
1080 volatile u8 PHYSR1;
1081 volatile u8 MIICR;
1082 volatile u8 MIIADR;
1083 volatile u16 MIIDATA;
1084
1085 volatile u16 SoftTimer0; /* 0x74 */
1086 volatile u16 SoftTimer1;
1087
1088 volatile u8 CFGA; /* 0x78 */
1089 volatile u8 CFGB;
1090 volatile u8 CFGC;
1091 volatile u8 CFGD;
1092
1093 volatile u16 DCFG; /* 0x7C */
1094 volatile u16 MCFG;
1095
1096 volatile u8 TBIST; /* 0x80 */
1097 volatile u8 RBIST;
1098 volatile u8 PMCPORT;
1099 volatile u8 STICKHW;
1100
1101 volatile u8 MIBCR; /* 0x84 */
1102 volatile u8 reserved_85;
1103 volatile u8 rev_id;
1104 volatile u8 PORSTS;
1105
1106 volatile u32 MIBData; /* 0x88 */
1107
1108 volatile u16 EEWrData;
1109
1110 volatile u8 reserved_8E;
1111 volatile u8 BPMDWr;
1112 volatile u8 BPCMD;
1113 volatile u8 BPMDRd;
1114
1115 volatile u8 EECHKSUM; /* 0x92 */
1116 volatile u8 EECSR;
1117
1118 volatile u16 EERdData; /* 0x94 */
1119 volatile u8 EADDR;
1120 volatile u8 EMBCMD;
1121
1122
1123 volatile u8 JMPSR0; /* 0x98 */
1124 volatile u8 JMPSR1;
1125 volatile u8 JMPSR2;
1126 volatile u8 JMPSR3;
1127 volatile u8 CHIPGSR; /* 0x9C */
1128 volatile u8 TESTCFG;
1129 volatile u8 DEBUG;
1130 volatile u8 CHIPGCR;
1131
1132 volatile u16 WOLCRSet; /* 0xA0 */
1133 volatile u8 PWCFGSet;
1134 volatile u8 WOLCFGSet;
1135
1136 volatile u16 WOLCRClr; /* 0xA4 */
1137 volatile u8 PWCFGCLR;
1138 volatile u8 WOLCFGClr;
1139
1140 volatile u16 WOLSRSet; /* 0xA8 */
1141 volatile u16 reserved_AA;
1142
1143 volatile u16 WOLSRClr; /* 0xAC */
1144 volatile u16 reserved_AE;
1145
1146 volatile u16 PatternCRC[8]; /* 0xB0 */
1147 volatile u32 ByteMask[4][4]; /* 0xC0 */
1148 } __attribute__ ((__packed__));
1149
1150
1151 enum hw_mib {
1152 HW_MIB_ifRxAllPkts = 0,
1153 HW_MIB_ifRxOkPkts,
1154 HW_MIB_ifTxOkPkts,
1155 HW_MIB_ifRxErrorPkts,
1156 HW_MIB_ifRxRuntOkPkt,
1157 HW_MIB_ifRxRuntErrPkt,
1158 HW_MIB_ifRx64Pkts,
1159 HW_MIB_ifTx64Pkts,
1160 HW_MIB_ifRx65To127Pkts,
1161 HW_MIB_ifTx65To127Pkts,
1162 HW_MIB_ifRx128To255Pkts,
1163 HW_MIB_ifTx128To255Pkts,
1164 HW_MIB_ifRx256To511Pkts,
1165 HW_MIB_ifTx256To511Pkts,
1166 HW_MIB_ifRx512To1023Pkts,
1167 HW_MIB_ifTx512To1023Pkts,
1168 HW_MIB_ifRx1024To1518Pkts,
1169 HW_MIB_ifTx1024To1518Pkts,
1170 HW_MIB_ifTxEtherCollisions,
1171 HW_MIB_ifRxPktCRCE,
1172 HW_MIB_ifRxJumboPkts,
1173 HW_MIB_ifTxJumboPkts,
1174 HW_MIB_ifRxMacControlFrames,
1175 HW_MIB_ifTxMacControlFrames,
1176 HW_MIB_ifRxPktFAE,
1177 HW_MIB_ifRxLongOkPkt,
1178 HW_MIB_ifRxLongPktErrPkt,
1179 HW_MIB_ifTXSQEErrors,
1180 HW_MIB_ifRxNobuf,
1181 HW_MIB_ifRxSymbolErrors,
1182 HW_MIB_ifInRangeLengthErrors,
1183 HW_MIB_ifLateCollisions,
1184 HW_MIB_SIZE
1185 };
1186
1187 enum chip_type {
1188 CHIP_TYPE_VT6110 = 1,
1189 };
1190
1191 struct velocity_info_tbl {
1192 enum chip_type chip_id;
1193 char *name;
1194 int io_size;
1195 int txqueue;
1196 u32 flags;
1197 };
1198
1199 #define mac_hw_mibs_init(regs) {\
1200 BYTE_REG_BITS_ON(MIBCR_MIBFRZ,&((regs)->MIBCR));\
1201 BYTE_REG_BITS_ON(MIBCR_MIBCLR,&((regs)->MIBCR));\
1202 do {}\
1203 while (BYTE_REG_BITS_IS_ON(MIBCR_MIBCLR,&((regs)->MIBCR)));\
1204 BYTE_REG_BITS_OFF(MIBCR_MIBFRZ,&((regs)->MIBCR));\
1205 }
1206
1207 #define mac_read_isr(regs) readl(&((regs)->ISR))
1208 #define mac_write_isr(regs, x) writel((x),&((regs)->ISR))
1209 #define mac_clear_isr(regs) writel(0xffffffffL,&((regs)->ISR))
1210
1211 #define mac_write_int_mask(mask, regs) writel((mask),&((regs)->IMR));
1212 #define mac_disable_int(regs) writel(CR0_GINTMSK1,&((regs)->CR0Clr))
1213 #define mac_enable_int(regs) writel(CR0_GINTMSK1,&((regs)->CR0Set))
1214
1215 #define mac_hw_mibs_read(regs, MIBs) {\
1216 int i;\
1217 BYTE_REG_BITS_ON(MIBCR_MPTRINI,&((regs)->MIBCR));\
1218 for (i=0;i<HW_MIB_SIZE;i++) {\
1219 (MIBs)[i]=readl(&((regs)->MIBData));\
1220 }\
1221 }
1222
1223 #define mac_set_dma_length(regs, n) {\
1224 BYTE_REG_BITS_SET((n),0x07,&((regs)->DCFG));\
1225 }
1226
1227 #define mac_set_rx_thresh(regs, n) {\
1228 BYTE_REG_BITS_SET((n),(MCFG_RFT0|MCFG_RFT1),&((regs)->MCFG));\
1229 }
1230
1231 #define mac_rx_queue_run(regs) {\
1232 writeb(TRDCSR_RUN, &((regs)->RDCSRSet));\
1233 }
1234
1235 #define mac_rx_queue_wake(regs) {\
1236 writeb(TRDCSR_WAK, &((regs)->RDCSRSet));\
1237 }
1238
1239 #define mac_tx_queue_run(regs, n) {\
1240 writew(TRDCSR_RUN<<((n)*4),&((regs)->TDCSRSet));\
1241 }
1242
1243 #define mac_tx_queue_wake(regs, n) {\
1244 writew(TRDCSR_WAK<<(n*4),&((regs)->TDCSRSet));\
1245 }
1246
1247 #define mac_eeprom_reload(regs) {\
1248 int i=0;\
1249 BYTE_REG_BITS_ON(EECSR_RELOAD,&((regs)->EECSR));\
1250 do {\
1251 udelay(10);\
1252 if (i++>0x1000) {\
1253 break;\
1254 }\
1255 }while (BYTE_REG_BITS_IS_ON(EECSR_RELOAD,&((regs)->EECSR)));\
1256 }
1257
1258 enum velocity_cam_type {
1259 VELOCITY_VLAN_ID_CAM = 0,
1260 VELOCITY_MULTICAST_CAM
1261 };
1262
1263 /**
1264 * mac_get_cam_mask - Read a CAM mask
1265 * @regs: register block for this velocity
1266 * @mask: buffer to store mask
1267 * @cam_type: CAM to fetch
1268 *
1269 * Fetch the mask bits of the selected CAM and store them into the
1270 * provided mask buffer.
1271 */
1272
1273 static inline void mac_get_cam_mask(struct mac_regs __iomem * regs, u8 * mask, enum velocity_cam_type cam_type)
1274 {
1275 int i;
1276 /* Select CAM mask */
1277 BYTE_REG_BITS_SET(CAMCR_PS_CAM_MASK, CAMCR_PS1 | CAMCR_PS0, &regs->CAMCR);
1278
1279 if (cam_type == VELOCITY_VLAN_ID_CAM)
1280 writeb(CAMADDR_VCAMSL, &regs->CAMADDR);
1281 else
1282 writeb(0, &regs->CAMADDR);
1283
1284 /* read mask */
1285 for (i = 0; i < 8; i++)
1286 *mask++ = readb(&(regs->MARCAM[i]));
1287
1288 /* disable CAMEN */
1289 writeb(0, &regs->CAMADDR);
1290
1291 /* Select mar */
1292 BYTE_REG_BITS_SET(CAMCR_PS_MAR, CAMCR_PS1 | CAMCR_PS0, &regs->CAMCR);
1293
1294 }
1295
1296 /**
1297 * mac_set_cam_mask - Set a CAM mask
1298 * @regs: register block for this velocity
1299 * @mask: CAM mask to load
1300 * @cam_type: CAM to store
1301 *
1302 * Store a new mask into a CAM
1303 */
1304
1305 static inline void mac_set_cam_mask(struct mac_regs __iomem * regs, u8 * mask, enum velocity_cam_type cam_type)
1306 {
1307 int i;
1308 /* Select CAM mask */
1309 BYTE_REG_BITS_SET(CAMCR_PS_CAM_MASK, CAMCR_PS1 | CAMCR_PS0, &regs->CAMCR);
1310
1311 if (cam_type == VELOCITY_VLAN_ID_CAM)
1312 writeb(CAMADDR_CAMEN | CAMADDR_VCAMSL, &regs->CAMADDR);
1313 else
1314 writeb(CAMADDR_CAMEN, &regs->CAMADDR);
1315
1316 for (i = 0; i < 8; i++) {
1317 writeb(*mask++, &(regs->MARCAM[i]));
1318 }
1319 /* disable CAMEN */
1320 writeb(0, &regs->CAMADDR);
1321
1322 /* Select mar */
1323 BYTE_REG_BITS_SET(CAMCR_PS_MAR, CAMCR_PS1 | CAMCR_PS0, &regs->CAMCR);
1324 }
1325
1326 /**
1327 * mac_set_cam - set CAM data
1328 * @regs: register block of this velocity
1329 * @idx: Cam index
1330 * @addr: 2 or 6 bytes of CAM data
1331 * @cam_type: CAM to load
1332 *
1333 * Load an address or vlan tag into a CAM
1334 */
1335
1336 static inline void mac_set_cam(struct mac_regs __iomem * regs, int idx, u8 *addr, enum velocity_cam_type cam_type)
1337 {
1338 int i;
1339
1340 /* Select CAM mask */
1341 BYTE_REG_BITS_SET(CAMCR_PS_CAM_DATA, CAMCR_PS1 | CAMCR_PS0, &regs->CAMCR);
1342
1343 idx &= (64 - 1);
1344
1345 if (cam_type == VELOCITY_VLAN_ID_CAM)
1346 writeb(CAMADDR_CAMEN | CAMADDR_VCAMSL | idx, &regs->CAMADDR);
1347 else
1348 writeb(CAMADDR_CAMEN | idx, &regs->CAMADDR);
1349
1350 if (cam_type == VELOCITY_VLAN_ID_CAM)
1351 writew(*((u16 *) addr), &regs->MARCAM[0]);
1352 else {
1353 for (i = 0; i < 6; i++) {
1354 writeb(*addr++, &(regs->MARCAM[i]));
1355 }
1356 }
1357 BYTE_REG_BITS_ON(CAMCR_CAMWR, &regs->CAMCR);
1358
1359 udelay(10);
1360
1361 writeb(0, &regs->CAMADDR);
1362
1363 /* Select mar */
1364 BYTE_REG_BITS_SET(CAMCR_PS_MAR, CAMCR_PS1 | CAMCR_PS0, &regs->CAMCR);
1365 }
1366
1367 /**
1368 * mac_get_cam - fetch CAM data
1369 * @regs: register block of this velocity
1370 * @idx: Cam index
1371 * @addr: buffer to hold up to 6 bytes of CAM data
1372 * @cam_type: CAM to load
1373 *
1374 * Load an address or vlan tag from a CAM into the buffer provided by
1375 * the caller. VLAN tags are 2 bytes the address cam entries are 6.
1376 */
1377
1378 static inline void mac_get_cam(struct mac_regs __iomem * regs, int idx, u8 *addr, enum velocity_cam_type cam_type)
1379 {
1380 int i;
1381
1382 /* Select CAM mask */
1383 BYTE_REG_BITS_SET(CAMCR_PS_CAM_DATA, CAMCR_PS1 | CAMCR_PS0, &regs->CAMCR);
1384
1385 idx &= (64 - 1);
1386
1387 if (cam_type == VELOCITY_VLAN_ID_CAM)
1388 writeb(CAMADDR_CAMEN | CAMADDR_VCAMSL | idx, &regs->CAMADDR);
1389 else
1390 writeb(CAMADDR_CAMEN | idx, &regs->CAMADDR);
1391
1392 BYTE_REG_BITS_ON(CAMCR_CAMRD, &regs->CAMCR);
1393
1394 udelay(10);
1395
1396 if (cam_type == VELOCITY_VLAN_ID_CAM)
1397 *((u16 *) addr) = readw(&(regs->MARCAM[0]));
1398 else
1399 for (i = 0; i < 6; i++, addr++)
1400 *((u8 *) addr) = readb(&(regs->MARCAM[i]));
1401
1402 writeb(0, &regs->CAMADDR);
1403
1404 /* Select mar */
1405 BYTE_REG_BITS_SET(CAMCR_PS_MAR, CAMCR_PS1 | CAMCR_PS0, &regs->CAMCR);
1406 }
1407
1408 /**
1409 * mac_wol_reset - reset WOL after exiting low power
1410 * @regs: register block of this velocity
1411 *
1412 * Called after we drop out of wake on lan mode in order to
1413 * reset the Wake on lan features. This function doesn't restore
1414 * the rest of the logic from the result of sleep/wakeup
1415 */
1416
1417 inline static void mac_wol_reset(struct mac_regs __iomem * regs)
1418 {
1419
1420 /* Turn off SWPTAG right after leaving power mode */
1421 BYTE_REG_BITS_OFF(STICKHW_SWPTAG, &regs->STICKHW);
1422 /* clear sticky bits */
1423 BYTE_REG_BITS_OFF((STICKHW_DS1 | STICKHW_DS0), &regs->STICKHW);
1424
1425 BYTE_REG_BITS_OFF(CHIPGCR_FCGMII, &regs->CHIPGCR);
1426 BYTE_REG_BITS_OFF(CHIPGCR_FCMODE, &regs->CHIPGCR);
1427 /* disable force PME-enable */
1428 writeb(WOLCFG_PMEOVR, &regs->WOLCFGClr);
1429 /* disable power-event config bit */
1430 writew(0xFFFF, &regs->WOLCRClr);
1431 /* clear power status */
1432 writew(0xFFFF, &regs->WOLSRClr);
1433 }
1434
1435
1436 /*
1437 * Header for WOL definitions. Used to compute hashes
1438 */
1439
1440 typedef u8 MCAM_ADDR[ETH_ALEN];
1441
1442 struct arp_packet {
1443 u8 dest_mac[ETH_ALEN];
1444 u8 src_mac[ETH_ALEN];
1445 u16 type;
1446 u16 ar_hrd;
1447 u16 ar_pro;
1448 u8 ar_hln;
1449 u8 ar_pln;
1450 u16 ar_op;
1451 u8 ar_sha[ETH_ALEN];
1452 u8 ar_sip[4];
1453 u8 ar_tha[ETH_ALEN];
1454 u8 ar_tip[4];
1455 } __attribute__ ((__packed__));
1456
1457 struct _magic_packet {
1458 u8 dest_mac[6];
1459 u8 src_mac[6];
1460 u16 type;
1461 u8 MAC[16][6];
1462 u8 password[6];
1463 } __attribute__ ((__packed__));
1464
1465 /*
1466 * Store for chip context when saving and restoring status. Not
1467 * all fields are saved/restored currently.
1468 */
1469
1470 struct velocity_context {
1471 u8 mac_reg[256];
1472 MCAM_ADDR cam_addr[MCAM_SIZE];
1473 u16 vcam[VCAM_SIZE];
1474 u32 cammask[2];
1475 u32 patcrc[2];
1476 u32 pattern[8];
1477 };
1478
1479
1480 /*
1481 * MII registers.
1482 */
1483
1484
1485 /*
1486 * Registers in the MII (offset unit is WORD)
1487 */
1488
1489 #define MII_REG_BMCR 0x00 // physical address
1490 #define MII_REG_BMSR 0x01 //
1491 #define MII_REG_PHYID1 0x02 // OUI
1492 #define MII_REG_PHYID2 0x03 // OUI + Module ID + REV ID
1493 #define MII_REG_ANAR 0x04 //
1494 #define MII_REG_ANLPAR 0x05 //
1495 #define MII_REG_G1000CR 0x09 //
1496 #define MII_REG_G1000SR 0x0A //
1497 #define MII_REG_MODCFG 0x10 //
1498 #define MII_REG_TCSR 0x16 //
1499 #define MII_REG_PLED 0x1B //
1500 // NS, MYSON only
1501 #define MII_REG_PCR 0x17 //
1502 // ESI only
1503 #define MII_REG_PCSR 0x17 //
1504 #define MII_REG_AUXCR 0x1C //
1505
1506 // Marvell 88E1000/88E1000S
1507 #define MII_REG_PSCR 0x10 // PHY specific control register
1508
1509 //
1510 // Bits in the BMCR register
1511 //
1512 #define BMCR_RESET 0x8000 //
1513 #define BMCR_LBK 0x4000 //
1514 #define BMCR_SPEED100 0x2000 //
1515 #define BMCR_AUTO 0x1000 //
1516 #define BMCR_PD 0x0800 //
1517 #define BMCR_ISO 0x0400 //
1518 #define BMCR_REAUTO 0x0200 //
1519 #define BMCR_FDX 0x0100 //
1520 #define BMCR_SPEED1G 0x0040 //
1521 //
1522 // Bits in the BMSR register
1523 //
1524 #define BMSR_AUTOCM 0x0020 //
1525 #define BMSR_LNK 0x0004 //
1526
1527 //
1528 // Bits in the ANAR register
1529 //
1530 #define ANAR_ASMDIR 0x0800 // Asymmetric PAUSE support
1531 #define ANAR_PAUSE 0x0400 // Symmetric PAUSE Support
1532 #define ANAR_T4 0x0200 //
1533 #define ANAR_TXFD 0x0100 //
1534 #define ANAR_TX 0x0080 //
1535 #define ANAR_10FD 0x0040 //
1536 #define ANAR_10 0x0020 //
1537 //
1538 // Bits in the ANLPAR register
1539 //
1540 #define ANLPAR_ASMDIR 0x0800 // Asymmetric PAUSE support
1541 #define ANLPAR_PAUSE 0x0400 // Symmetric PAUSE Support
1542 #define ANLPAR_T4 0x0200 //
1543 #define ANLPAR_TXFD 0x0100 //
1544 #define ANLPAR_TX 0x0080 //
1545 #define ANLPAR_10FD 0x0040 //
1546 #define ANLPAR_10 0x0020 //
1547
1548 //
1549 // Bits in the G1000CR register
1550 //
1551 #define G1000CR_1000FD 0x0200 // PHY is 1000-T Full-duplex capable
1552 #define G1000CR_1000 0x0100 // PHY is 1000-T Half-duplex capable
1553
1554 //
1555 // Bits in the G1000SR register
1556 //
1557 #define G1000SR_1000FD 0x0800 // LP PHY is 1000-T Full-duplex capable
1558 #define G1000SR_1000 0x0400 // LP PHY is 1000-T Half-duplex capable
1559
1560 #define TCSR_ECHODIS 0x2000 //
1561 #define AUXCR_MDPPS 0x0004 //
1562
1563 // Bits in the PLED register
1564 #define PLED_LALBE 0x0004 //
1565
1566 // Marvell 88E1000/88E1000S Bits in the PHY specific control register (10h)
1567 #define PSCR_ACRSTX 0x0800 // Assert CRS on Transmit
1568
1569 #define PHYID_CICADA_CS8201 0x000FC410UL
1570 #define PHYID_VT3216_32BIT 0x000FC610UL
1571 #define PHYID_VT3216_64BIT 0x000FC600UL
1572 #define PHYID_MARVELL_1000 0x01410C50UL
1573 #define PHYID_MARVELL_1000S 0x01410C40UL
1574
1575 #define PHYID_REV_ID_MASK 0x0000000FUL
1576
1577 #define PHYID_GET_PHY_REV_ID(i) ((i) & PHYID_REV_ID_MASK)
1578 #define PHYID_GET_PHY_ID(i) ((i) & ~PHYID_REV_ID_MASK)
1579
1580 #define MII_REG_BITS_ON(x,i,p) do {\
1581 u16 w;\
1582 velocity_mii_read((p),(i),&(w));\
1583 (w)|=(x);\
1584 velocity_mii_write((p),(i),(w));\
1585 } while (0)
1586
1587 #define MII_REG_BITS_OFF(x,i,p) do {\
1588 u16 w;\
1589 velocity_mii_read((p),(i),&(w));\
1590 (w)&=(~(x));\
1591 velocity_mii_write((p),(i),(w));\
1592 } while (0)
1593
1594 #define MII_REG_BITS_IS_ON(x,i,p) ({\
1595 u16 w;\
1596 velocity_mii_read((p),(i),&(w));\
1597 ((int) ((w) & (x)));})
1598
1599 #define MII_GET_PHY_ID(p) ({\
1600 u32 id;\
1601 velocity_mii_read((p),MII_REG_PHYID2,(u16 *) &id);\
1602 velocity_mii_read((p),MII_REG_PHYID1,((u16 *) &id)+1);\
1603 (id);})
1604
1605 /*
1606 * Inline debug routine
1607 */
1608
1609
1610 enum velocity_msg_level {
1611 MSG_LEVEL_ERR = 0, //Errors that will cause abnormal operation.
1612 MSG_LEVEL_NOTICE = 1, //Some errors need users to be notified.
1613 MSG_LEVEL_INFO = 2, //Normal message.
1614 MSG_LEVEL_VERBOSE = 3, //Will report all trival errors.
1615 MSG_LEVEL_DEBUG = 4 //Only for debug purpose.
1616 };
1617
1618 #ifdef VELOCITY_DEBUG
1619 #define ASSERT(x) { \
1620 if (!(x)) { \
1621 printk(KERN_ERR "assertion %s failed: file %s line %d\n", #x,\
1622 __FUNCTION__, __LINE__);\
1623 BUG(); \
1624 }\
1625 }
1626 #define VELOCITY_DBG(p,args...) printk(p, ##args)
1627 #else
1628 #define ASSERT(x)
1629 #define VELOCITY_DBG(x)
1630 #endif
1631
1632 #define VELOCITY_PRT(l, p, args...) do {if (l<=msglevel) printk( p ,##args);} while (0)
1633
1634 #define VELOCITY_PRT_CAMMASK(p,t) {\
1635 int i;\
1636 if ((t)==VELOCITY_MULTICAST_CAM) {\
1637 for (i=0;i<(MCAM_SIZE/8);i++)\
1638 printk("%02X",(p)->mCAMmask[i]);\
1639 }\
1640 else {\
1641 for (i=0;i<(VCAM_SIZE/8);i++)\
1642 printk("%02X",(p)->vCAMmask[i]);\
1643 }\
1644 printk("\n");\
1645 }
1646
1647
1648
1649 #define VELOCITY_WOL_MAGIC 0x00000000UL
1650 #define VELOCITY_WOL_PHY 0x00000001UL
1651 #define VELOCITY_WOL_ARP 0x00000002UL
1652 #define VELOCITY_WOL_UCAST 0x00000004UL
1653 #define VELOCITY_WOL_BCAST 0x00000010UL
1654 #define VELOCITY_WOL_MCAST 0x00000020UL
1655 #define VELOCITY_WOL_MAGIC_SEC 0x00000040UL
1656
1657 /*
1658 * Flags for options
1659 */
1660
1661 #define VELOCITY_FLAGS_TAGGING 0x00000001UL
1662 #define VELOCITY_FLAGS_TX_CSUM 0x00000002UL
1663 #define VELOCITY_FLAGS_RX_CSUM 0x00000004UL
1664 #define VELOCITY_FLAGS_IP_ALIGN 0x00000008UL
1665 #define VELOCITY_FLAGS_VAL_PKT_LEN 0x00000010UL
1666
1667 #define VELOCITY_FLAGS_FLOW_CTRL 0x01000000UL
1668
1669 /*
1670 * Flags for driver status
1671 */
1672
1673 #define VELOCITY_FLAGS_OPENED 0x00010000UL
1674 #define VELOCITY_FLAGS_VMNS_CONNECTED 0x00020000UL
1675 #define VELOCITY_FLAGS_VMNS_COMMITTED 0x00040000UL
1676 #define VELOCITY_FLAGS_WOL_ENABLED 0x00080000UL
1677
1678 /*
1679 * Flags for MII status
1680 */
1681
1682 #define VELOCITY_LINK_FAIL 0x00000001UL
1683 #define VELOCITY_SPEED_10 0x00000002UL
1684 #define VELOCITY_SPEED_100 0x00000004UL
1685 #define VELOCITY_SPEED_1000 0x00000008UL
1686 #define VELOCITY_DUPLEX_FULL 0x00000010UL
1687 #define VELOCITY_AUTONEG_ENABLE 0x00000020UL
1688 #define VELOCITY_FORCED_BY_EEPROM 0x00000040UL
1689
1690 /*
1691 * For velocity_set_media_duplex
1692 */
1693
1694 #define VELOCITY_LINK_CHANGE 0x00000001UL
1695
1696 enum speed_opt {
1697 SPD_DPX_AUTO = 0,
1698 SPD_DPX_100_HALF = 1,
1699 SPD_DPX_100_FULL = 2,
1700 SPD_DPX_10_HALF = 3,
1701 SPD_DPX_10_FULL = 4
1702 };
1703
1704 enum velocity_init_type {
1705 VELOCITY_INIT_COLD = 0,
1706 VELOCITY_INIT_RESET,
1707 VELOCITY_INIT_WOL
1708 };
1709
1710 enum velocity_flow_cntl_type {
1711 FLOW_CNTL_DEFAULT = 1,
1712 FLOW_CNTL_TX,
1713 FLOW_CNTL_RX,
1714 FLOW_CNTL_TX_RX,
1715 FLOW_CNTL_DISABLE,
1716 };
1717
1718 struct velocity_opt {
1719 int numrx; /* Number of RX descriptors */
1720 int numtx; /* Number of TX descriptors */
1721 enum speed_opt spd_dpx; /* Media link mode */
1722 int vid; /* vlan id */
1723 int DMA_length; /* DMA length */
1724 int rx_thresh; /* RX_THRESH */
1725 int flow_cntl;
1726 int wol_opts; /* Wake on lan options */
1727 int td_int_count;
1728 int int_works;
1729 int rx_bandwidth_hi;
1730 int rx_bandwidth_lo;
1731 int rx_bandwidth_en;
1732 u32 flags;
1733 };
1734
1735 struct velocity_info {
1736 struct list_head list;
1737
1738 struct pci_dev *pdev;
1739 struct net_device *dev;
1740 struct net_device_stats stats;
1741
1742 dma_addr_t rd_pool_dma;
1743 dma_addr_t td_pool_dma[TX_QUEUE_NO];
1744
1745 dma_addr_t tx_bufs_dma;
1746 u8 *tx_bufs;
1747
1748 u8 ip_addr[4];
1749 enum chip_type chip_id;
1750
1751 struct mac_regs __iomem * mac_regs;
1752 unsigned long memaddr;
1753 unsigned long ioaddr;
1754 u32 io_size;
1755
1756 u8 rev_id;
1757
1758 #define AVAIL_TD(p,q) ((p)->options.numtx-((p)->td_used[(q)]))
1759
1760 int num_txq;
1761
1762 volatile int td_used[TX_QUEUE_NO];
1763 int td_curr[TX_QUEUE_NO];
1764 int td_tail[TX_QUEUE_NO];
1765 struct tx_desc *td_rings[TX_QUEUE_NO];
1766 struct velocity_td_info *td_infos[TX_QUEUE_NO];
1767
1768 int rd_curr;
1769 int rd_dirty;
1770 u32 rd_filled;
1771 struct rx_desc *rd_ring;
1772 struct velocity_rd_info *rd_info; /* It's an array */
1773
1774 #define GET_RD_BY_IDX(vptr, idx) (vptr->rd_ring[idx])
1775 u32 mib_counter[MAX_HW_MIB_COUNTER];
1776 struct velocity_opt options;
1777
1778 u32 int_mask;
1779
1780 u32 flags;
1781
1782 int rx_buf_sz;
1783 u32 mii_status;
1784 u32 phy_id;
1785 int multicast_limit;
1786
1787 u8 vCAMmask[(VCAM_SIZE / 8)];
1788 u8 mCAMmask[(MCAM_SIZE / 8)];
1789
1790 spinlock_t lock;
1791
1792 int wol_opts;
1793 u8 wol_passwd[6];
1794
1795 struct velocity_context context;
1796
1797 u32 ticks;
1798 u32 rx_bytes;
1799
1800 };
1801
1802 /**
1803 * velocity_get_ip - find an IP address for the device
1804 * @vptr: Velocity to query
1805 *
1806 * Dig out an IP address for this interface so that we can
1807 * configure wakeup with WOL for ARP. If there are multiple IP
1808 * addresses on this chain then we use the first - multi-IP WOL is not
1809 * supported.
1810 *
1811 * CHECK ME: locking
1812 */
1813
1814 inline static int velocity_get_ip(struct velocity_info *vptr)
1815 {
1816 struct in_device *in_dev = (struct in_device *) vptr->dev->ip_ptr;
1817 struct in_ifaddr *ifa;
1818
1819 if (in_dev != NULL) {
1820 ifa = (struct in_ifaddr *) in_dev->ifa_list;
1821 if (ifa != NULL) {
1822 memcpy(vptr->ip_addr, &ifa->ifa_address, 4);
1823 return 0;
1824 }
1825 }
1826 return -ENOENT;
1827 }
1828
1829 /**
1830 * velocity_update_hw_mibs - fetch MIB counters from chip
1831 * @vptr: velocity to update
1832 *
1833 * The velocity hardware keeps certain counters in the hardware
1834 * side. We need to read these when the user asks for statistics
1835 * or when they overflow (causing an interrupt). The read of the
1836 * statistic clears it, so we keep running master counters in user
1837 * space.
1838 */
1839
1840 static inline void velocity_update_hw_mibs(struct velocity_info *vptr)
1841 {
1842 u32 tmp;
1843 int i;
1844 BYTE_REG_BITS_ON(MIBCR_MIBFLSH, &(vptr->mac_regs->MIBCR));
1845
1846 while (BYTE_REG_BITS_IS_ON(MIBCR_MIBFLSH, &(vptr->mac_regs->MIBCR)));
1847
1848 BYTE_REG_BITS_ON(MIBCR_MPTRINI, &(vptr->mac_regs->MIBCR));
1849 for (i = 0; i < HW_MIB_SIZE; i++) {
1850 tmp = readl(&(vptr->mac_regs->MIBData)) & 0x00FFFFFFUL;
1851 vptr->mib_counter[i] += tmp;
1852 }
1853 }
1854
1855 /**
1856 * init_flow_control_register - set up flow control
1857 * @vptr: velocity to configure
1858 *
1859 * Configure the flow control registers for this velocity device.
1860 */
1861
1862 static inline void init_flow_control_register(struct velocity_info *vptr)
1863 {
1864 struct mac_regs __iomem * regs = vptr->mac_regs;
1865
1866 /* Set {XHITH1, XHITH0, XLTH1, XLTH0} in FlowCR1 to {1, 0, 1, 1}
1867 depend on RD=64, and Turn on XNOEN in FlowCR1 */
1868 writel((CR0_XONEN | CR0_XHITH1 | CR0_XLTH1 | CR0_XLTH0), &regs->CR0Set);
1869 writel((CR0_FDXTFCEN | CR0_FDXRFCEN | CR0_HDXFCEN | CR0_XHITH0), &regs->CR0Clr);
1870
1871 /* Set TxPauseTimer to 0xFFFF */
1872 writew(0xFFFF, &regs->tx_pause_timer);
1873
1874 /* Initialize RBRDU to Rx buffer count. */
1875 writew(vptr->options.numrx, &regs->RBRDU);
1876 }
1877
1878
1879 #endif
Verdex Pro support