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[TG3]: Set minimal hw interrupt mitigation.
[linux-2.6/verdex.git] / drivers / net / wan / wanxl.c
blob1e7b47704ad9e15a3c64e47e7374c449bf9b7e79
1 /*
2 * wanXL serial card driver for Linux
3 * host part
4 *
5 * Copyright (C) 2003 Krzysztof Halasa <khc@pm.waw.pl>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of version 2 of the GNU General Public License
9 * as published by the Free Software Foundation.
10 *
11 * Status:
12 * - Only DTE (external clock) support with NRZ and NRZI encodings
13 * - wanXL100 will require minor driver modifications, no access to hw
14 */
15
16 #include <linux/module.h>
17 #include <linux/kernel.h>
18 #include <linux/slab.h>
19 #include <linux/sched.h>
20 #include <linux/types.h>
21 #include <linux/fcntl.h>
22 #include <linux/string.h>
23 #include <linux/errno.h>
24 #include <linux/init.h>
25 #include <linux/ioport.h>
26 #include <linux/netdevice.h>
27 #include <linux/hdlc.h>
28 #include <linux/pci.h>
29 #include <asm/io.h>
30 #include <asm/delay.h>
31
32 #include "wanxl.h"
33
34 static const char* version = "wanXL serial card driver version: 0.48";
35
36 #define PLX_CTL_RESET 0x40000000 /* adapter reset */
37
38 #undef DEBUG_PKT
39 #undef DEBUG_PCI
40
41 /* MAILBOX #1 - PUTS COMMANDS */
42 #define MBX1_CMD_ABORTJ 0x85000000 /* Abort and Jump */
43 #ifdef __LITTLE_ENDIAN
44 #define MBX1_CMD_BSWAP 0x8C000001 /* little-endian Byte Swap Mode */
45 #else
46 #define MBX1_CMD_BSWAP 0x8C000000 /* big-endian Byte Swap Mode */
47 #endif
48
49 /* MAILBOX #2 - DRAM SIZE */
50 #define MBX2_MEMSZ_MASK 0xFFFF0000 /* PUTS Memory Size Register mask */
51
52
53 typedef struct {
54 struct net_device *dev;
55 struct card_t *card;
56 spinlock_t lock; /* for wanxl_xmit */
57 int node; /* physical port #0 - 3 */
58 unsigned int clock_type;
59 int tx_in, tx_out;
60 struct sk_buff *tx_skbs[TX_BUFFERS];
61 }port_t;
62
63
64 typedef struct {
65 desc_t rx_descs[RX_QUEUE_LENGTH];
66 port_status_t port_status[4];
67 }card_status_t;
68
69
70 typedef struct card_t {
71 int n_ports; /* 1, 2 or 4 ports */
72 u8 irq;
73
74 u8 __iomem *plx; /* PLX PCI9060 virtual base address */
75 struct pci_dev *pdev; /* for pci_name(pdev) */
76 int rx_in;
77 struct sk_buff *rx_skbs[RX_QUEUE_LENGTH];
78 card_status_t *status; /* shared between host and card */
79 dma_addr_t status_address;
80 port_t ports[0]; /* 1 - 4 port_t structures follow */
81 }card_t;
82
83
84
85 static inline port_t* dev_to_port(struct net_device *dev)
86 {
87 return (port_t *)dev_to_hdlc(dev)->priv;
88 }
89
90
91 static inline port_status_t* get_status(port_t *port)
92 {
93 return &port->card->status->port_status[port->node];
94 }
95
96
97 #ifdef DEBUG_PCI
98 static inline dma_addr_t pci_map_single_debug(struct pci_dev *pdev, void *ptr,
99 size_t size, int direction)
100 {
101 dma_addr_t addr = pci_map_single(pdev, ptr, size, direction);
102 if (addr + size > 0x100000000LL)
103 printk(KERN_CRIT "wanXL %s: pci_map_single() returned memory"
104 " at 0x%LX!\n", pci_name(pdev),
105 (unsigned long long)addr);
106 return addr;
107 }
108
109 #undef pci_map_single
110 #define pci_map_single pci_map_single_debug
111 #endif
112
113
114 /* Cable and/or personality module change interrupt service */
115 static inline void wanxl_cable_intr(port_t *port)
116 {
117 u32 value = get_status(port)->cable;
118 int valid = 1;
119 const char *cable, *pm, *dte = "", *dsr = "", *dcd = "";
120
121 switch(value & 0x7) {
122 case STATUS_CABLE_V35: cable = "V.35"; break;
123 case STATUS_CABLE_X21: cable = "X.21"; break;
124 case STATUS_CABLE_V24: cable = "V.24"; break;
125 case STATUS_CABLE_EIA530: cable = "EIA530"; break;
126 case STATUS_CABLE_NONE: cable = "no"; break;
127 default: cable = "invalid";
128 }
129
130 switch((value >> STATUS_CABLE_PM_SHIFT) & 0x7) {
131 case STATUS_CABLE_V35: pm = "V.35"; break;
132 case STATUS_CABLE_X21: pm = "X.21"; break;
133 case STATUS_CABLE_V24: pm = "V.24"; break;
134 case STATUS_CABLE_EIA530: pm = "EIA530"; break;
135 case STATUS_CABLE_NONE: pm = "no personality"; valid = 0; break;
136 default: pm = "invalid personality"; valid = 0;
137 }
138
139 if (valid) {
140 if ((value & 7) == ((value >> STATUS_CABLE_PM_SHIFT) & 7)) {
141 dsr = (value & STATUS_CABLE_DSR) ? ", DSR ON" :
142 ", DSR off";
143 dcd = (value & STATUS_CABLE_DCD) ? ", carrier ON" :
144 ", carrier off";
145 }
146 dte = (value & STATUS_CABLE_DCE) ? " DCE" : " DTE";
147 }
148 printk(KERN_INFO "%s: %s%s module, %s cable%s%s\n",
149 port->dev->name, pm, dte, cable, dsr, dcd);
150
151 hdlc_set_carrier(value & STATUS_CABLE_DCD, port->dev);
152 }
153
154
155
156 /* Transmit complete interrupt service */
157 static inline void wanxl_tx_intr(port_t *port)
158 {
159 struct net_device *dev = port->dev;
160 struct net_device_stats *stats = hdlc_stats(dev);
161 while (1) {
162 desc_t *desc = &get_status(port)->tx_descs[port->tx_in];
163 struct sk_buff *skb = port->tx_skbs[port->tx_in];
164
165 switch (desc->stat) {
166 case PACKET_FULL:
167 case PACKET_EMPTY:
168 netif_wake_queue(dev);
169 return;
170
171 case PACKET_UNDERRUN:
172 stats->tx_errors++;
173 stats->tx_fifo_errors++;
174 break;
175
176 default:
177 stats->tx_packets++;
178 stats->tx_bytes += skb->len;
179 }
180 desc->stat = PACKET_EMPTY; /* Free descriptor */
181 pci_unmap_single(port->card->pdev, desc->address, skb->len,
182 PCI_DMA_TODEVICE);
183 dev_kfree_skb_irq(skb);
184 port->tx_in = (port->tx_in + 1) % TX_BUFFERS;
185 }
186 }
187
188
189
190 /* Receive complete interrupt service */
191 static inline void wanxl_rx_intr(card_t *card)
192 {
193 desc_t *desc;
194 while (desc = &card->status->rx_descs[card->rx_in],
195 desc->stat != PACKET_EMPTY) {
196 if ((desc->stat & PACKET_PORT_MASK) > card->n_ports)
197 printk(KERN_CRIT "wanXL %s: received packet for"
198 " nonexistent port\n", pci_name(card->pdev));
199 else {
200 struct sk_buff *skb = card->rx_skbs[card->rx_in];
201 port_t *port = &card->ports[desc->stat &
202 PACKET_PORT_MASK];
203 struct net_device *dev = port->dev;
204 struct net_device_stats *stats = hdlc_stats(dev);
205
206 if (!skb)
207 stats->rx_dropped++;
208 else {
209 pci_unmap_single(card->pdev, desc->address,
210 BUFFER_LENGTH,
211 PCI_DMA_FROMDEVICE);
212 skb_put(skb, desc->length);
213
214 #ifdef DEBUG_PKT
215 printk(KERN_DEBUG "%s RX(%i):", dev->name,
216 skb->len);
217 debug_frame(skb);
218 #endif
219 stats->rx_packets++;
220 stats->rx_bytes += skb->len;
221 dev->last_rx = jiffies;
222 skb->protocol = hdlc_type_trans(skb, dev);
223 netif_rx(skb);
224 skb = NULL;
225 }
226
227 if (!skb) {
228 skb = dev_alloc_skb(BUFFER_LENGTH);
229 desc->address = skb ?
230 pci_map_single(card->pdev, skb->data,
231 BUFFER_LENGTH,
232 PCI_DMA_FROMDEVICE) : 0;
233 card->rx_skbs[card->rx_in] = skb;
234 }
235 }
236 desc->stat = PACKET_EMPTY; /* Free descriptor */
237 card->rx_in = (card->rx_in + 1) % RX_QUEUE_LENGTH;
238 }
239 }
240
241
242
243 static irqreturn_t wanxl_intr(int irq, void* dev_id, struct pt_regs *regs)
244 {
245 card_t *card = dev_id;
246 int i;
247 u32 stat;
248 int handled = 0;
249
250
251 while((stat = readl(card->plx + PLX_DOORBELL_FROM_CARD)) != 0) {
252 handled = 1;
253 writel(stat, card->plx + PLX_DOORBELL_FROM_CARD);
254
255 for (i = 0; i < card->n_ports; i++) {
256 if (stat & (1 << (DOORBELL_FROM_CARD_TX_0 + i)))
257 wanxl_tx_intr(&card->ports[i]);
258 if (stat & (1 << (DOORBELL_FROM_CARD_CABLE_0 + i)))
259 wanxl_cable_intr(&card->ports[i]);
260 }
261 if (stat & (1 << DOORBELL_FROM_CARD_RX))
262 wanxl_rx_intr(card);
263 }
264
265 return IRQ_RETVAL(handled);
266 }
267
268
269
270 static int wanxl_xmit(struct sk_buff *skb, struct net_device *dev)
271 {
272 port_t *port = dev_to_port(dev);
273 desc_t *desc;
274
275 spin_lock(&port->lock);
276
277 desc = &get_status(port)->tx_descs[port->tx_out];
278 if (desc->stat != PACKET_EMPTY) {
279 /* should never happen - previous xmit should stop queue */
280 #ifdef DEBUG_PKT
281 printk(KERN_DEBUG "%s: transmitter buffer full\n", dev->name);
282 #endif
283 netif_stop_queue(dev);
284 spin_unlock_irq(&port->lock);
285 return 1; /* request packet to be queued */
286 }
287
288 #ifdef DEBUG_PKT
289 printk(KERN_DEBUG "%s TX(%i):", dev->name, skb->len);
290 debug_frame(skb);
291 #endif
292
293 port->tx_skbs[port->tx_out] = skb;
294 desc->address = pci_map_single(port->card->pdev, skb->data, skb->len,
295 PCI_DMA_TODEVICE);
296 desc->length = skb->len;
297 desc->stat = PACKET_FULL;
298 writel(1 << (DOORBELL_TO_CARD_TX_0 + port->node),
299 port->card->plx + PLX_DOORBELL_TO_CARD);
300 dev->trans_start = jiffies;
301
302 port->tx_out = (port->tx_out + 1) % TX_BUFFERS;
303
304 if (get_status(port)->tx_descs[port->tx_out].stat != PACKET_EMPTY) {
305 netif_stop_queue(dev);
306 #ifdef DEBUG_PKT
307 printk(KERN_DEBUG "%s: transmitter buffer full\n", dev->name);
308 #endif
309 }
310
311 spin_unlock(&port->lock);
312 return 0;
313 }
314
315
316
317 static int wanxl_attach(struct net_device *dev, unsigned short encoding,
318 unsigned short parity)
319 {
320 port_t *port = dev_to_port(dev);
321
322 if (encoding != ENCODING_NRZ &&
323 encoding != ENCODING_NRZI)
324 return -EINVAL;
325
326 if (parity != PARITY_NONE &&
327 parity != PARITY_CRC32_PR1_CCITT &&
328 parity != PARITY_CRC16_PR1_CCITT &&
329 parity != PARITY_CRC32_PR0_CCITT &&
330 parity != PARITY_CRC16_PR0_CCITT)
331 return -EINVAL;
332
333 get_status(port)->encoding = encoding;
334 get_status(port)->parity = parity;
335 return 0;
336 }
337
338
339
340 static int wanxl_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
341 {
342 const size_t size = sizeof(sync_serial_settings);
343 sync_serial_settings line;
344 port_t *port = dev_to_port(dev);
345
346 if (cmd != SIOCWANDEV)
347 return hdlc_ioctl(dev, ifr, cmd);
348
349 switch (ifr->ifr_settings.type) {
350 case IF_GET_IFACE:
351 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
352 if (ifr->ifr_settings.size < size) {
353 ifr->ifr_settings.size = size; /* data size wanted */
354 return -ENOBUFS;
355 }
356 line.clock_type = get_status(port)->clocking;
357 line.clock_rate = 0;
358 line.loopback = 0;
359
360 if (copy_to_user(ifr->ifr_settings.ifs_ifsu.sync, &line, size))
361 return -EFAULT;
362 return 0;
363
364 case IF_IFACE_SYNC_SERIAL:
365 if (!capable(CAP_NET_ADMIN))
366 return -EPERM;
367 if (dev->flags & IFF_UP)
368 return -EBUSY;
369
370 if (copy_from_user(&line, ifr->ifr_settings.ifs_ifsu.sync,
371 size))
372 return -EFAULT;
373
374 if (line.clock_type != CLOCK_EXT &&
375 line.clock_type != CLOCK_TXFROMRX)
376 return -EINVAL; /* No such clock setting */
377
378 if (line.loopback != 0)
379 return -EINVAL;
380
381 get_status(port)->clocking = line.clock_type;
382 return 0;
383
384 default:
385 return hdlc_ioctl(dev, ifr, cmd);
386 }
387 }
388
389
390
391 static int wanxl_open(struct net_device *dev)
392 {
393 port_t *port = dev_to_port(dev);
394 u8 __iomem *dbr = port->card->plx + PLX_DOORBELL_TO_CARD;
395 unsigned long timeout;
396 int i;
397
398 if (get_status(port)->open) {
399 printk(KERN_ERR "%s: port already open\n", dev->name);
400 return -EIO;
401 }
402 if ((i = hdlc_open(dev)) != 0)
403 return i;
404
405 port->tx_in = port->tx_out = 0;
406 for (i = 0; i < TX_BUFFERS; i++)
407 get_status(port)->tx_descs[i].stat = PACKET_EMPTY;
408 /* signal the card */
409 writel(1 << (DOORBELL_TO_CARD_OPEN_0 + port->node), dbr);
410
411 timeout = jiffies + HZ;
412 do
413 if (get_status(port)->open) {
414 netif_start_queue(dev);
415 return 0;
416 }
417 while (time_after(timeout, jiffies));
418
419 printk(KERN_ERR "%s: unable to open port\n", dev->name);
420 /* ask the card to close the port, should it be still alive */
421 writel(1 << (DOORBELL_TO_CARD_CLOSE_0 + port->node), dbr);
422 return -EFAULT;
423 }
424
425
426
427 static int wanxl_close(struct net_device *dev)
428 {
429 port_t *port = dev_to_port(dev);
430 unsigned long timeout;
431 int i;
432
433 hdlc_close(dev);
434 /* signal the card */
435 writel(1 << (DOORBELL_TO_CARD_CLOSE_0 + port->node),
436 port->card->plx + PLX_DOORBELL_TO_CARD);
437
438 timeout = jiffies + HZ;
439 do
440 if (!get_status(port)->open)
441 break;
442 while (time_after(timeout, jiffies));
443
444 if (get_status(port)->open)
445 printk(KERN_ERR "%s: unable to close port\n", dev->name);
446
447 netif_stop_queue(dev);
448
449 for (i = 0; i < TX_BUFFERS; i++) {
450 desc_t *desc = &get_status(port)->tx_descs[i];
451
452 if (desc->stat != PACKET_EMPTY) {
453 desc->stat = PACKET_EMPTY;
454 pci_unmap_single(port->card->pdev, desc->address,
455 port->tx_skbs[i]->len,
456 PCI_DMA_TODEVICE);
457 dev_kfree_skb(port->tx_skbs[i]);
458 }
459 }
460 return 0;
461 }
462
463
464
465 static struct net_device_stats *wanxl_get_stats(struct net_device *dev)
466 {
467 struct net_device_stats *stats = hdlc_stats(dev);
468 port_t *port = dev_to_port(dev);
469
470 stats->rx_over_errors = get_status(port)->rx_overruns;
471 stats->rx_frame_errors = get_status(port)->rx_frame_errors;
472 stats->rx_errors = stats->rx_over_errors + stats->rx_frame_errors;
473 return stats;
474 }
475
476
477
478 static int wanxl_puts_command(card_t *card, u32 cmd)
479 {
480 unsigned long timeout = jiffies + 5 * HZ;
481
482 writel(cmd, card->plx + PLX_MAILBOX_1);
483 do {
484 if (readl(card->plx + PLX_MAILBOX_1) == 0)
485 return 0;
486
487 schedule();
488 }while (time_after(timeout, jiffies));
489
490 return -1;
491 }
492
493
494
495 static void wanxl_reset(card_t *card)
496 {
497 u32 old_value = readl(card->plx + PLX_CONTROL) & ~PLX_CTL_RESET;
498
499 writel(0x80, card->plx + PLX_MAILBOX_0);
500 writel(old_value | PLX_CTL_RESET, card->plx + PLX_CONTROL);
501 readl(card->plx + PLX_CONTROL); /* wait for posted write */
502 udelay(1);
503 writel(old_value, card->plx + PLX_CONTROL);
504 readl(card->plx + PLX_CONTROL); /* wait for posted write */
505 }
506
507
508
509 static void wanxl_pci_remove_one(struct pci_dev *pdev)
510 {
511 card_t *card = pci_get_drvdata(pdev);
512 int i;
513
514 for (i = 0; i < card->n_ports; i++) {
515 unregister_hdlc_device(card->ports[i].dev);
516 free_netdev(card->ports[i].dev);
517 }
518
519 /* unregister and free all host resources */
520 if (card->irq)
521 free_irq(card->irq, card);
522
523 wanxl_reset(card);
524
525 for (i = 0; i < RX_QUEUE_LENGTH; i++)
526 if (card->rx_skbs[i]) {
527 pci_unmap_single(card->pdev,
528 card->status->rx_descs[i].address,
529 BUFFER_LENGTH, PCI_DMA_FROMDEVICE);
530 dev_kfree_skb(card->rx_skbs[i]);
531 }
532
533 if (card->plx)
534 iounmap(card->plx);
535
536 if (card->status)
537 pci_free_consistent(pdev, sizeof(card_status_t),
538 card->status, card->status_address);
539
540 pci_release_regions(pdev);
541 pci_disable_device(pdev);
542 pci_set_drvdata(pdev, NULL);
543 kfree(card);
544 }
545
546
547 #include "wanxlfw.inc"
548
549 static int __devinit wanxl_pci_init_one(struct pci_dev *pdev,
550 const struct pci_device_id *ent)
551 {
552 card_t *card;
553 u32 ramsize, stat;
554 unsigned long timeout;
555 u32 plx_phy; /* PLX PCI base address */
556 u32 mem_phy; /* memory PCI base addr */
557 u8 __iomem *mem; /* memory virtual base addr */
558 int i, ports, alloc_size;
559
560 #ifndef MODULE
561 static int printed_version;
562 if (!printed_version) {
563 printed_version++;
564 printk(KERN_INFO "%s\n", version);
565 }
566 #endif
567
568 i = pci_enable_device(pdev);
569 if (i)
570 return i;
571
572 /* QUICC can only access first 256 MB of host RAM directly,
573 but PLX9060 DMA does 32-bits for actual packet data transfers */
574
575 /* FIXME when PCI/DMA subsystems are fixed.
576 We set both dma_mask and consistent_dma_mask to 28 bits
577 and pray pci_alloc_consistent() will use this info. It should
578 work on most platforms */
579 if (pci_set_consistent_dma_mask(pdev, 0x0FFFFFFF) ||
580 pci_set_dma_mask(pdev, 0x0FFFFFFF)) {
581 printk(KERN_ERR "wanXL: No usable DMA configuration\n");
582 return -EIO;
583 }
584
585 i = pci_request_regions(pdev, "wanXL");
586 if (i) {
587 pci_disable_device(pdev);
588 return i;
589 }
590
591 switch (pdev->device) {
592 case PCI_DEVICE_ID_SBE_WANXL100: ports = 1; break;
593 case PCI_DEVICE_ID_SBE_WANXL200: ports = 2; break;
594 default: ports = 4;
595 }
596
597 alloc_size = sizeof(card_t) + ports * sizeof(port_t);
598 card = kmalloc(alloc_size, GFP_KERNEL);
599 if (card == NULL) {
600 printk(KERN_ERR "wanXL %s: unable to allocate memory\n",
601 pci_name(pdev));
602 pci_release_regions(pdev);
603 pci_disable_device(pdev);
604 return -ENOBUFS;
605 }
606 memset(card, 0, alloc_size);
607
608 pci_set_drvdata(pdev, card);
609 card->pdev = pdev;
610
611 card->status = pci_alloc_consistent(pdev, sizeof(card_status_t),
612 &card->status_address);
613 if (card->status == NULL) {
614 wanxl_pci_remove_one(pdev);
615 return -ENOBUFS;
616 }
617
618 #ifdef DEBUG_PCI
619 printk(KERN_DEBUG "wanXL %s: pci_alloc_consistent() returned memory"
620 " at 0x%LX\n", pci_name(pdev),
621 (unsigned long long)card->status_address);
622 #endif
623
624 /* FIXME when PCI/DMA subsystems are fixed.
625 We set both dma_mask and consistent_dma_mask back to 32 bits
626 to indicate the card can do 32-bit DMA addressing */
627 if (pci_set_consistent_dma_mask(pdev, 0xFFFFFFFF) ||
628 pci_set_dma_mask(pdev, 0xFFFFFFFF)) {
629 printk(KERN_ERR "wanXL: No usable DMA configuration\n");
630 wanxl_pci_remove_one(pdev);
631 return -EIO;
632 }
633
634 /* set up PLX mapping */
635 plx_phy = pci_resource_start(pdev, 0);
636 card->plx = ioremap_nocache(plx_phy, 0x70);
637
638 #if RESET_WHILE_LOADING
639 wanxl_reset(card);
640 #endif
641
642 timeout = jiffies + 20 * HZ;
643 while ((stat = readl(card->plx + PLX_MAILBOX_0)) != 0) {
644 if (time_before(timeout, jiffies)) {
645 printk(KERN_WARNING "wanXL %s: timeout waiting for"
646 " PUTS to complete\n", pci_name(pdev));
647 wanxl_pci_remove_one(pdev);
648 return -ENODEV;
649 }
650
651 switch(stat & 0xC0) {
652 case 0x00: /* hmm - PUTS completed with non-zero code? */
653 case 0x80: /* PUTS still testing the hardware */
654 break;
655
656 default:
657 printk(KERN_WARNING "wanXL %s: PUTS test 0x%X"
658 " failed\n", pci_name(pdev), stat & 0x30);
659 wanxl_pci_remove_one(pdev);
660 return -ENODEV;
661 }
662
663 schedule();
664 }
665
666 /* get on-board memory size (PUTS detects no more than 4 MB) */
667 ramsize = readl(card->plx + PLX_MAILBOX_2) & MBX2_MEMSZ_MASK;
668
669 /* set up on-board RAM mapping */
670 mem_phy = pci_resource_start(pdev, 2);
671
672
673 /* sanity check the board's reported memory size */
674 if (ramsize < BUFFERS_ADDR +
675 (TX_BUFFERS + RX_BUFFERS) * BUFFER_LENGTH * ports) {
676 printk(KERN_WARNING "wanXL %s: no enough on-board RAM"
677 " (%u bytes detected, %u bytes required)\n",
678 pci_name(pdev), ramsize, BUFFERS_ADDR +
679 (TX_BUFFERS + RX_BUFFERS) * BUFFER_LENGTH * ports);
680 wanxl_pci_remove_one(pdev);
681 return -ENODEV;
682 }
683
684 if (wanxl_puts_command(card, MBX1_CMD_BSWAP)) {
685 printk(KERN_WARNING "wanXL %s: unable to Set Byte Swap"
686 " Mode\n", pci_name(pdev));
687 wanxl_pci_remove_one(pdev);
688 return -ENODEV;
689 }
690
691 for (i = 0; i < RX_QUEUE_LENGTH; i++) {
692 struct sk_buff *skb = dev_alloc_skb(BUFFER_LENGTH);
693 card->rx_skbs[i] = skb;
694 if (skb)
695 card->status->rx_descs[i].address =
696 pci_map_single(card->pdev, skb->data,
697 BUFFER_LENGTH,
698 PCI_DMA_FROMDEVICE);
699 }
700
701 mem = ioremap_nocache(mem_phy, PDM_OFFSET + sizeof(firmware));
702 for (i = 0; i < sizeof(firmware); i += 4)
703 writel(htonl(*(u32*)(firmware + i)), mem + PDM_OFFSET + i);
704
705 for (i = 0; i < ports; i++)
706 writel(card->status_address +
707 (void *)&card->status->port_status[i] -
708 (void *)card->status, mem + PDM_OFFSET + 4 + i * 4);
709 writel(card->status_address, mem + PDM_OFFSET + 20);
710 writel(PDM_OFFSET, mem);
711 iounmap(mem);
712
713 writel(0, card->plx + PLX_MAILBOX_5);
714
715 if (wanxl_puts_command(card, MBX1_CMD_ABORTJ)) {
716 printk(KERN_WARNING "wanXL %s: unable to Abort and Jump\n",
717 pci_name(pdev));
718 wanxl_pci_remove_one(pdev);
719 return -ENODEV;
720 }
721
722 stat = 0;
723 timeout = jiffies + 5 * HZ;
724 do {
725 if ((stat = readl(card->plx + PLX_MAILBOX_5)) != 0)
726 break;
727 schedule();
728 }while (time_after(timeout, jiffies));
729
730 if (!stat) {
731 printk(KERN_WARNING "wanXL %s: timeout while initializing card"
732 "firmware\n", pci_name(pdev));
733 wanxl_pci_remove_one(pdev);
734 return -ENODEV;
735 }
736
737 #if DETECT_RAM
738 ramsize = stat;
739 #endif
740
741 printk(KERN_INFO "wanXL %s: at 0x%X, %u KB of RAM at 0x%X, irq %u\n",
742 pci_name(pdev), plx_phy, ramsize / 1024, mem_phy, pdev->irq);
743
744 /* Allocate IRQ */
745 if (request_irq(pdev->irq, wanxl_intr, SA_SHIRQ, "wanXL", card)) {
746 printk(KERN_WARNING "wanXL %s: could not allocate IRQ%i.\n",
747 pci_name(pdev), pdev->irq);
748 wanxl_pci_remove_one(pdev);
749 return -EBUSY;
750 }
751 card->irq = pdev->irq;
752
753 for (i = 0; i < ports; i++) {
754 hdlc_device *hdlc;
755 port_t *port = &card->ports[i];
756 struct net_device *dev = alloc_hdlcdev(port);
757 if (!dev) {
758 printk(KERN_ERR "wanXL %s: unable to allocate"
759 " memory\n", pci_name(pdev));
760 wanxl_pci_remove_one(pdev);
761 return -ENOMEM;
762 }
763
764 port->dev = dev;
765 hdlc = dev_to_hdlc(dev);
766 spin_lock_init(&port->lock);
767 SET_MODULE_OWNER(dev);
768 dev->tx_queue_len = 50;
769 dev->do_ioctl = wanxl_ioctl;
770 dev->open = wanxl_open;
771 dev->stop = wanxl_close;
772 hdlc->attach = wanxl_attach;
773 hdlc->xmit = wanxl_xmit;
774 dev->get_stats = wanxl_get_stats;
775 port->card = card;
776 port->node = i;
777 get_status(port)->clocking = CLOCK_EXT;
778 if (register_hdlc_device(dev)) {
779 printk(KERN_ERR "wanXL %s: unable to register hdlc"
780 " device\n", pci_name(pdev));
781 free_netdev(dev);
782 wanxl_pci_remove_one(pdev);
783 return -ENOBUFS;
784 }
785 card->n_ports++;
786 }
787
788 printk(KERN_INFO "wanXL %s: port", pci_name(pdev));
789 for (i = 0; i < ports; i++)
790 printk("%s #%i: %s", i ? "," : "", i,
791 card->ports[i].dev->name);
792 printk("\n");
793
794 for (i = 0; i < ports; i++)
795 wanxl_cable_intr(&card->ports[i]); /* get carrier status etc.*/
796
797 return 0;
798 }
799
800 static struct pci_device_id wanxl_pci_tbl[] __devinitdata = {
801 { PCI_VENDOR_ID_SBE, PCI_DEVICE_ID_SBE_WANXL100, PCI_ANY_ID,
802 PCI_ANY_ID, 0, 0, 0 },
803 { PCI_VENDOR_ID_SBE, PCI_DEVICE_ID_SBE_WANXL200, PCI_ANY_ID,
804 PCI_ANY_ID, 0, 0, 0 },
805 { PCI_VENDOR_ID_SBE, PCI_DEVICE_ID_SBE_WANXL400, PCI_ANY_ID,
806 PCI_ANY_ID, 0, 0, 0 },
807 { 0, }
808 };
809
810
811 static struct pci_driver wanxl_pci_driver = {
812 .name = "wanXL",
813 .id_table = wanxl_pci_tbl,
814 .probe = wanxl_pci_init_one,
815 .remove = wanxl_pci_remove_one,
816 };
817
818
819 static int __init wanxl_init_module(void)
820 {
821 #ifdef MODULE
822 printk(KERN_INFO "%s\n", version);
823 #endif
824 return pci_module_init(&wanxl_pci_driver);
825 }
826
827 static void __exit wanxl_cleanup_module(void)
828 {
829 pci_unregister_driver(&wanxl_pci_driver);
830 }
831
832
833 MODULE_AUTHOR("Krzysztof Halasa <khc@pm.waw.pl>");
834 MODULE_DESCRIPTION("SBE Inc. wanXL serial port driver");
835 MODULE_LICENSE("GPL v2");
836 MODULE_DEVICE_TABLE(pci, wanxl_pci_tbl);
837
838 module_init(wanxl_init_module);
839 module_exit(wanxl_cleanup_module);
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