drivers/pci/probe.c

   1 /*
   2  * probe.c - PCI detection and setup code
   3  */
   4
   5 #include <linux/kernel.h>
   6 #include <linux/delay.h>
   7 #include <linux/init.h>
   8 #include <linux/pci.h>
   9 #include <linux/slab.h>
  10 #include <linux/module.h>
  11 #include <linux/cpumask.h>
  12 #include "pci.h"
  13
  14 #define CARDBUS_LATENCY_TIMER   176     /* secondary latency timer */
  15 #define CARDBUS_RESERVE_BUSNR   3
  16 #define PCI_CFG_SPACE_SIZE      256
  17 #define PCI_CFG_SPACE_EXP_SIZE  4096
  18
  19 /* Ugh.  Need to stop exporting this to modules. */
  20 LIST_HEAD(pci_root_buses);
  21 EXPORT_SYMBOL(pci_root_buses);
  22
  23 LIST_HEAD(pci_devices);
  24
  25 #ifdef HAVE_PCI_LEGACY
  26 /**
  27  * pci_create_legacy_files - create legacy I/O port and memory files
  28  * @b: bus to create files under
  29  *
  30  * Some platforms allow access to legacy I/O port and ISA memory space on
  31  * a per-bus basis.  This routine creates the files and ties them into
  32  * their associated read, write and mmap files from pci-sysfs.c
  33  */
  34 static void pci_create_legacy_files(struct pci_bus *b)
  35 {
  36         b->legacy_io = kmalloc(sizeof(struct bin_attribute) * 2,
  37                                GFP_ATOMIC);
  38         if (b->legacy_io) {
  39                 memset(b->legacy_io, 0, sizeof(struct bin_attribute) * 2);
  40                 b->legacy_io->attr.name = "legacy_io";
  41                 b->legacy_io->size = 0xffff;
  42                 b->legacy_io->attr.mode = S_IRUSR | S_IWUSR;
  43                 b->legacy_io->attr.owner = THIS_MODULE;
  44                 b->legacy_io->read = pci_read_legacy_io;
  45                 b->legacy_io->write = pci_write_legacy_io;
  46                 class_device_create_bin_file(&b->class_dev, b->legacy_io);
  47
  48                 /* Allocated above after the legacy_io struct */
  49                 b->legacy_mem = b->legacy_io + 1;
  50                 b->legacy_mem->attr.name = "legacy_mem";
  51                 b->legacy_mem->size = 1024*1024;
  52                 b->legacy_mem->attr.mode = S_IRUSR | S_IWUSR;
  53                 b->legacy_mem->attr.owner = THIS_MODULE;
  54                 b->legacy_mem->mmap = pci_mmap_legacy_mem;
  55                 class_device_create_bin_file(&b->class_dev, b->legacy_mem);
  56         }
  57 }
  58
  59 void pci_remove_legacy_files(struct pci_bus *b)
  60 {
  61         if (b->legacy_io) {
  62                 class_device_remove_bin_file(&b->class_dev, b->legacy_io);
  63                 class_device_remove_bin_file(&b->class_dev, b->legacy_mem);
  64                 kfree(b->legacy_io); /* both are allocated here */
  65         }
  66 }
  67 #else /* !HAVE_PCI_LEGACY */
  68 static inline void pci_create_legacy_files(struct pci_bus *bus) { return; }
  69 void pci_remove_legacy_files(struct pci_bus *bus) { return; }
  70 #endif /* HAVE_PCI_LEGACY */
  71
  72 /*
  73  * PCI Bus Class Devices
  74  */
  75 static ssize_t pci_bus_show_cpuaffinity(struct class_device *class_dev, char *buf)
  76 {
  77         cpumask_t cpumask = pcibus_to_cpumask(to_pci_bus(class_dev));
  78         int ret;
  79
  80         ret = cpumask_scnprintf(buf, PAGE_SIZE, cpumask);
  81         if (ret < PAGE_SIZE)
  82                 buf[ret++] = '\n';
  83         return ret;
  84 }
  85 CLASS_DEVICE_ATTR(cpuaffinity, S_IRUGO, pci_bus_show_cpuaffinity, NULL);
  86
  87 /*
  88  * PCI Bus Class
  89  */
  90 static void release_pcibus_dev(struct class_device *class_dev)
  91 {
  92         struct pci_bus *pci_bus = to_pci_bus(class_dev);
  93
  94         if (pci_bus->bridge)
  95                 put_device(pci_bus->bridge);
  96         kfree(pci_bus);
  97 }
  98
  99 static struct class pcibus_class = {
 100         .name           = "pci_bus",
 101         .release        = &release_pcibus_dev,
 102 };
 103
 104 static int __init pcibus_class_init(void)
 105 {
 106         return class_register(&pcibus_class);
 107 }
 108 postcore_initcall(pcibus_class_init);
 109
 110 /*
 111  * Translate the low bits of the PCI base
 112  * to the resource type
 113  */
 114 static inline unsigned int pci_calc_resource_flags(unsigned int flags)
 115 {
 116         if (flags & PCI_BASE_ADDRESS_SPACE_IO)
 117                 return IORESOURCE_IO;
 118
 119         if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
 120                 return IORESOURCE_MEM | IORESOURCE_PREFETCH;
 121
 122         return IORESOURCE_MEM;
 123 }
 124
 125 /*
 126  * Find the extent of a PCI decode..
 127  */
 128 static u32 pci_size(u32 base, u32 maxbase, unsigned long mask)
 129 {
 130         u32 size = mask & maxbase;      /* Find the significant bits */
 131         if (!size)
 132                 return 0;
 133
 134         /* Get the lowest of them to find the decode size, and
 135            from that the extent.  */
 136         size = (size & ~(size-1)) - 1;
 137
 138         /* base == maxbase can be valid only if the BAR has
 139            already been programmed with all 1s.  */
 140         if (base == maxbase && ((base | size) & mask) != mask)
 141                 return 0;
 142
 143         return size;
 144 }
 145
 146 static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
 147 {
 148         unsigned int pos, reg, next;
 149         u32 l, sz;
 150         struct resource *res;
 151
 152         for(pos=0; pos<howmany; pos = next) {
 153                 next = pos+1;
 154                 res = &dev->resource[pos];
 155                 res->name = pci_name(dev);
 156                 reg = PCI_BASE_ADDRESS_0 + (pos << 2);
 157                 pci_read_config_dword(dev, reg, &l);
 158                 pci_write_config_dword(dev, reg, ~0);
 159                 pci_read_config_dword(dev, reg, &sz);
 160                 pci_write_config_dword(dev, reg, l);
 161                 if (!sz || sz == 0xffffffff)
 162                         continue;
 163                 if (l == 0xffffffff)
 164                         l = 0;
 165                 if ((l & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_MEMORY) {
 166                         sz = pci_size(l, sz, PCI_BASE_ADDRESS_MEM_MASK);
 167                         if (!sz)
 168                                 continue;
 169                         res->start = l & PCI_BASE_ADDRESS_MEM_MASK;
 170                         res->flags |= l & ~PCI_BASE_ADDRESS_MEM_MASK;
 171                 } else {
 172                         sz = pci_size(l, sz, PCI_BASE_ADDRESS_IO_MASK & 0xffff);
 173                         if (!sz)
 174                                 continue;
 175                         res->start = l & PCI_BASE_ADDRESS_IO_MASK;
 176                         res->flags |= l & ~PCI_BASE_ADDRESS_IO_MASK;
 177                 }
 178                 res->end = res->start + (unsigned long) sz;
 179                 res->flags |= pci_calc_resource_flags(l);
 180                 if ((l & (PCI_BASE_ADDRESS_SPACE | PCI_BASE_ADDRESS_MEM_TYPE_MASK))
 181                     == (PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_64)) {
 182                         pci_read_config_dword(dev, reg+4, &l);
 183                         next++;
 184 #if BITS_PER_LONG == 64
 185                         res->start |= ((unsigned long) l) << 32;
 186                         res->end = res->start + sz;
 187                         pci_write_config_dword(dev, reg+4, ~0);
 188                         pci_read_config_dword(dev, reg+4, &sz);
 189                         pci_write_config_dword(dev, reg+4, l);
 190                         sz = pci_size(l, sz, 0xffffffff);
 191                         if (sz) {
 192                                 /* This BAR needs > 4GB?  Wow. */
 193                                 res->end |= (unsigned long)sz<<32;
 194                         }
 195 #else
 196                         if (l) {
 197                                 printk(KERN_ERR "PCI: Unable to handle 64-bit address for device %s\n", pci_name(dev));
 198                                 res->start = 0;
 199                                 res->flags = 0;
 200                                 continue;
 201                         }
 202 #endif
 203                 }
 204         }
 205         if (rom) {
 206                 dev->rom_base_reg = rom;
 207                 res = &dev->resource[PCI_ROM_RESOURCE];
 208                 res->name = pci_name(dev);
 209                 pci_read_config_dword(dev, rom, &l);
 210                 pci_write_config_dword(dev, rom, ~PCI_ROM_ADDRESS_ENABLE);
 211                 pci_read_config_dword(dev, rom, &sz);
 212                 pci_write_config_dword(dev, rom, l);
 213                 if (l == 0xffffffff)
 214                         l = 0;
 215                 if (sz && sz != 0xffffffff) {
 216                         sz = pci_size(l, sz, PCI_ROM_ADDRESS_MASK);
 217                         if (sz) {
 218                                 res->flags = (l & IORESOURCE_ROM_ENABLE) |
 219                                   IORESOURCE_MEM | IORESOURCE_PREFETCH |
 220                                   IORESOURCE_READONLY | IORESOURCE_CACHEABLE;
 221                                 res->start = l & PCI_ROM_ADDRESS_MASK;
 222                                 res->end = res->start + (unsigned long) sz;
 223                         }
 224                 }
 225         }
 226 }
 227
 228 void __devinit pci_read_bridge_bases(struct pci_bus *child)
 229 {
 230         struct pci_dev *dev = child->self;
 231         u8 io_base_lo, io_limit_lo;
 232         u16 mem_base_lo, mem_limit_lo;
 233         unsigned long base, limit;
 234         struct resource *res;
 235         int i;
 236
 237         if (!dev)               /* It's a host bus, nothing to read */
 238                 return;
 239
 240         if (dev->transparent) {
 241                 printk(KERN_INFO "PCI: Transparent bridge - %s\n", pci_name(dev));
 242                 for(i = 0; i < PCI_BUS_NUM_RESOURCES; i++)
 243                         child->resource[i] = child->parent->resource[i];
 244                 return;
 245         }
 246
 247         for(i=0; i<3; i++)
 248                 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i];
 249
 250         res = child->resource[0];
 251         pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
 252         pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
 253         base = (io_base_lo & PCI_IO_RANGE_MASK) << 8;
 254         limit = (io_limit_lo & PCI_IO_RANGE_MASK) << 8;
 255
 256         if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
 257                 u16 io_base_hi, io_limit_hi;
 258                 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
 259                 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
 260                 base |= (io_base_hi << 16);
 261                 limit |= (io_limit_hi << 16);
 262         }
 263
 264         if (base <= limit) {
 265                 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
 266                 res->start = base;
 267                 res->end = limit + 0xfff;
 268         }
 269
 270         res = child->resource[1];
 271         pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
 272         pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
 273         base = (mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
 274         limit = (mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
 275         if (base <= limit) {
 276                 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM;
 277                 res->start = base;
 278                 res->end = limit + 0xfffff;
 279         }
 280
 281         res = child->resource[2];
 282         pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
 283         pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
 284         base = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
 285         limit = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
 286
 287         if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
 288                 u32 mem_base_hi, mem_limit_hi;
 289                 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
 290                 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
 291
 292                 /*
 293                  * Some bridges set the base > limit by default, and some
 294                  * (broken) BIOSes do not initialize them.  If we find
 295                  * this, just assume they are not being used.
 296                  */
 297                 if (mem_base_hi <= mem_limit_hi) {
 298 #if BITS_PER_LONG == 64
 299                         base |= ((long) mem_base_hi) << 32;
 300                         limit |= ((long) mem_limit_hi) << 32;
 301 #else
 302                         if (mem_base_hi || mem_limit_hi) {
 303                                 printk(KERN_ERR "PCI: Unable to handle 64-bit address space for bridge %s\n", pci_name(dev));
 304                                 return;
 305                         }
 306 #endif
 307                 }
 308         }
 309         if (base <= limit) {
 310                 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM | IORESOURCE_PREFETCH;
 311                 res->start = base;
 312                 res->end = limit + 0xfffff;
 313         }
 314 }
 315
 316 static struct pci_bus * __devinit pci_alloc_bus(void)
 317 {
 318         struct pci_bus *b;
 319
 320         b = kmalloc(sizeof(*b), GFP_KERNEL);
 321         if (b) {
 322                 memset(b, 0, sizeof(*b));
 323                 INIT_LIST_HEAD(&b->node);
 324                 INIT_LIST_HEAD(&b->children);
 325                 INIT_LIST_HEAD(&b->devices);
 326         }
 327         return b;
 328 }
 329
 330 static struct pci_bus * __devinit
 331 pci_alloc_child_bus(struct pci_bus *parent, struct pci_dev *bridge, int busnr)
 332 {
 333         struct pci_bus *child;
 334         int i;
 335
 336         /*
 337          * Allocate a new bus, and inherit stuff from the parent..
 338          */
 339         child = pci_alloc_bus();
 340         if (!child)
 341                 return NULL;
 342
 343         child->self = bridge;
 344         child->parent = parent;
 345         child->ops = parent->ops;
 346         child->sysdata = parent->sysdata;
 347         child->bridge = get_device(&bridge->dev);
 348
 349         child->class_dev.class = &pcibus_class;
 350         sprintf(child->class_dev.class_id, "%04x:%02x", pci_domain_nr(child), busnr);
 351         class_device_register(&child->class_dev);
 352         class_device_create_file(&child->class_dev, &class_device_attr_cpuaffinity);
 353
 354         /*
 355          * Set up the primary, secondary and subordinate
 356          * bus numbers.
 357          */
 358         child->number = child->secondary = busnr;
 359         child->primary = parent->secondary;
 360         child->subordinate = 0xff;
 361
 362         /* Set up default resource pointers and names.. */
 363         for (i = 0; i < 4; i++) {
 364                 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];
 365                 child->resource[i]->name = child->name;
 366         }
 367         bridge->subordinate = child;
 368
 369         return child;
 370 }
 371
 372 struct pci_bus * __devinit pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, int busnr)
 373 {
 374         struct pci_bus *child;
 375
 376         child = pci_alloc_child_bus(parent, dev, busnr);
 377         if (child)
 378                 list_add_tail(&child->node, &parent->children);
 379         return child;
 380 }
 381
 382 static void pci_enable_crs(struct pci_dev *dev)
 383 {
 384         u16 cap, rpctl;
 385         int rpcap = pci_find_capability(dev, PCI_CAP_ID_EXP);
 386         if (!rpcap)
 387                 return;
 388
 389         pci_read_config_word(dev, rpcap + PCI_CAP_FLAGS, &cap);
 390         if (((cap & PCI_EXP_FLAGS_TYPE) >> 4) != PCI_EXP_TYPE_ROOT_PORT)
 391                 return;
 392
 393         pci_read_config_word(dev, rpcap + PCI_EXP_RTCTL, &rpctl);
 394         rpctl |= PCI_EXP_RTCTL_CRSSVE;
 395         pci_write_config_word(dev, rpcap + PCI_EXP_RTCTL, rpctl);
 396 }
 397
 398 unsigned int __devinit pci_scan_child_bus(struct pci_bus *bus);
 399
 400 /*
 401  * If it's a bridge, configure it and scan the bus behind it.
 402  * For CardBus bridges, we don't scan behind as the devices will
 403  * be handled by the bridge driver itself.
 404  *
 405  * We need to process bridges in two passes -- first we scan those
 406  * already configured by the BIOS and after we are done with all of
 407  * them, we proceed to assigning numbers to the remaining buses in
 408  * order to avoid overlaps between old and new bus numbers.
 409  */
 410 int __devinit pci_scan_bridge(struct pci_bus *bus, struct pci_dev * dev, int max, int pass)
 411 {
 412         struct pci_bus *child;
 413         int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS);
 414         u32 buses;
 415         u16 bctl;
 416
 417         pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses);
 418
 419         pr_debug("PCI: Scanning behind PCI bridge %s, config %06x, pass %d\n",
 420                  pci_name(dev), buses & 0xffffff, pass);
 421
 422         /* Disable MasterAbortMode during probing to avoid reporting
 423            of bus errors (in some architectures) */
 424         pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl);
 425         pci_write_config_word(dev, PCI_BRIDGE_CONTROL,
 426                               bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);
 427
 428         pci_enable_crs(dev);
 429
 430         if ((buses & 0xffff00) && !pcibios_assign_all_busses() && !is_cardbus) {
 431                 unsigned int cmax, busnr;
 432                 /*
 433                  * Bus already configured by firmware, process it in the first
 434                  * pass and just note the configuration.
 435                  */
 436                 if (pass)
 437                         return max;
 438                 busnr = (buses >> 8) & 0xFF;
 439
 440                 /*
 441                  * If we already got to this bus through a different bridge,
 442                  * ignore it.  This can happen with the i450NX chipset.
 443                  */
 444                 if (pci_find_bus(pci_domain_nr(bus), busnr)) {
 445                         printk(KERN_INFO "PCI: Bus %04x:%02x already known\n",
 446                                         pci_domain_nr(bus), busnr);
 447                         return max;
 448                 }
 449
 450                 child = pci_alloc_child_bus(bus, dev, busnr);
 451                 if (!child)
 452                         return max;
 453                 child->primary = buses & 0xFF;
 454                 child->subordinate = (buses >> 16) & 0xFF;
 455                 child->bridge_ctl = bctl;
 456
 457                 cmax = pci_scan_child_bus(child);
 458                 if (cmax > max)
 459                         max = cmax;
 460                 if (child->subordinate > max)
 461                         max = child->subordinate;
 462         } else {
 463                 /*
 464                  * We need to assign a number to this bus which we always
 465                  * do in the second pass.
 466                  */
 467                 if (!pass)
 468                         return max;
 469
 470                 /* Clear errors */
 471                 pci_write_config_word(dev, PCI_STATUS, 0xffff);
 472
 473                 child = pci_alloc_child_bus(bus, dev, ++max);
 474                 buses = (buses & 0xff000000)
 475                       | ((unsigned int)(child->primary)     <<  0)
 476                       | ((unsigned int)(child->secondary)   <<  8)
 477                       | ((unsigned int)(child->subordinate) << 16);
 478
 479                 /*
 480                  * yenta.c forces a secondary latency timer of 176.
 481                  * Copy that behaviour here.
 482                  */
 483                 if (is_cardbus) {
 484                         buses &= ~0xff000000;
 485                         buses |= CARDBUS_LATENCY_TIMER << 24;
 486                 }
 487
 488                 /*
 489                  * We need to blast all three values with a single write.
 490                  */
 491                 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
 492
 493                 if (!is_cardbus) {
 494                         child->bridge_ctl = PCI_BRIDGE_CTL_NO_ISA;
 495
 496                         /* Now we can scan all subordinate buses... */
 497                         max = pci_scan_child_bus(child);
 498                 } else {
 499                         /*
 500                          * For CardBus bridges, we leave 4 bus numbers
 501                          * as cards with a PCI-to-PCI bridge can be
 502                          * inserted later.
 503                          */
 504                         max += CARDBUS_RESERVE_BUSNR;
 505                 }
 506                 /*
 507                  * Set the subordinate bus number to its real value.
 508                  */
 509                 child->subordinate = max;
 510                 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
 511         }
 512
 513         pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl);
 514
 515         sprintf(child->name, (is_cardbus ? "PCI CardBus #%02x" : "PCI Bus #%02x"), child->number);
 516
 517         return max;
 518 }
 519
 520 /*
 521  * Read interrupt line and base address registers.
 522  * The architecture-dependent code can tweak these, of course.
 523  */
 524 static void pci_read_irq(struct pci_dev *dev)
 525 {
 526         unsigned char irq;
 527
 528         pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq);
 529         if (irq)
 530                 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
 531         dev->irq = irq;
 532 }
 533
 534 /**
 535  * pci_setup_device - fill in class and map information of a device
 536  * @dev: the device structure to fill
 537  *
 538  * Initialize the device structure with information about the device's
 539  * vendor,class,memory and IO-space addresses,IRQ lines etc.
 540  * Called at initialisation of the PCI subsystem and by CardBus services.
 541  * Returns 0 on success and -1 if unknown type of device (not normal, bridge
 542  * or CardBus).
 543  */
 544 static int pci_setup_device(struct pci_dev * dev)
 545 {
 546         u32 class;
 547
 548         sprintf(pci_name(dev), "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus),
 549                 dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
 550
 551         pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
 552         class >>= 8;                                /* upper 3 bytes */
 553         dev->class = class;
 554         class >>= 8;
 555
 556         pr_debug("PCI: Found %s [%04x/%04x] %06x %02x\n", pci_name(dev),
 557                  dev->vendor, dev->device, class, dev->hdr_type);
 558
 559         /* "Unknown power state" */
 560         dev->current_state = 4;
 561
 562         /* Early fixups, before probing the BARs */
 563         pci_fixup_device(pci_fixup_early, dev);
 564         class = dev->class >> 8;
 565
 566         switch (dev->hdr_type) {                    /* header type */
 567         case PCI_HEADER_TYPE_NORMAL:                /* standard header */
 568                 if (class == PCI_CLASS_BRIDGE_PCI)
 569                         goto bad;
 570                 pci_read_irq(dev);
 571                 pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
 572                 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
 573                 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device);
 574                 break;
 575
 576         case PCI_HEADER_TYPE_BRIDGE:                /* bridge header */
 577                 if (class != PCI_CLASS_BRIDGE_PCI)
 578                         goto bad;
 579                 /* The PCI-to-PCI bridge spec requires that subtractive
 580                    decoding (i.e. transparent) bridge must have programming
 581                    interface code of 0x01. */
 582                 dev->transparent = ((dev->class & 0xff) == 1);
 583                 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
 584                 break;
 585
 586         case PCI_HEADER_TYPE_CARDBUS:               /* CardBus bridge header */
 587                 if (class != PCI_CLASS_BRIDGE_CARDBUS)
 588                         goto bad;
 589                 pci_read_irq(dev);
 590                 pci_read_bases(dev, 1, 0);
 591                 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
 592                 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device);
 593                 break;
 594
 595         default:                                    /* unknown header */
 596                 printk(KERN_ERR "PCI: device %s has unknown header type %02x, ignoring.\n",
 597                         pci_name(dev), dev->hdr_type);
 598                 return -1;
 599
 600         bad:
 601                 printk(KERN_ERR "PCI: %s: class %x doesn't match header type %02x. Ignoring class.\n",
 602                        pci_name(dev), class, dev->hdr_type);
 603                 dev->class = PCI_CLASS_NOT_DEFINED;
 604         }
 605
 606         /* We found a fine healthy device, go go go... */
 607         return 0;
 608 }
 609
 610 /**
 611  * pci_release_dev - free a pci device structure when all users of it are finished.
 612  * @dev: device that's been disconnected
 613  *
 614  * Will be called only by the device core when all users of this pci device are
 615  * done.
 616  */
 617 static void pci_release_dev(struct device *dev)
 618 {
 619         struct pci_dev *pci_dev;
 620
 621         pci_dev = to_pci_dev(dev);
 622         kfree(pci_dev);
 623 }
 624
 625 /**
 626  * pci_cfg_space_size - get the configuration space size of the PCI device.
 627  *
 628  * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
 629  * have 4096 bytes.  Even if the device is capable, that doesn't mean we can
 630  * access it.  Maybe we don't have a way to generate extended config space
 631  * accesses, or the device is behind a reverse Express bridge.  So we try
 632  * reading the dword at 0x100 which must either be 0 or a valid extended
 633  * capability header.
 634  */
 635 static int pci_cfg_space_size(struct pci_dev *dev)
 636 {
 637         int pos;
 638         u32 status;
 639
 640         pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
 641         if (!pos) {
 642                 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
 643                 if (!pos)
 644                         goto fail;
 645
 646                 pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
 647                 if (!(status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ)))
 648                         goto fail;
 649         }
 650
 651         if (pci_read_config_dword(dev, 256, &status) != PCIBIOS_SUCCESSFUL)
 652                 goto fail;
 653         if (status == 0xffffffff)
 654                 goto fail;
 655
 656         return PCI_CFG_SPACE_EXP_SIZE;
 657
 658  fail:
 659         return PCI_CFG_SPACE_SIZE;
 660 }
 661
 662 static void pci_release_bus_bridge_dev(struct device *dev)
 663 {
 664         kfree(dev);
 665 }
 666
 667 /*
 668  * Read the config data for a PCI device, sanity-check it
 669  * and fill in the dev structure...
 670  */
 671 static struct pci_dev * __devinit
 672 pci_scan_device(struct pci_bus *bus, int devfn)
 673 {
 674         struct pci_dev *dev;
 675         u32 l;
 676         u8 hdr_type;
 677         int delay = 1;
 678
 679         if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l))
 680                 return NULL;
 681
 682         /* some broken boards return 0 or ~0 if a slot is empty: */
 683         if (l == 0xffffffff || l == 0x00000000 ||
 684             l == 0x0000ffff || l == 0xffff0000)
 685                 return NULL;
 686
 687         /* Configuration request Retry Status */
 688         while (l == 0xffff0001) {
 689                 msleep(delay);
 690                 delay *= 2;
 691                 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l))
 692                         return NULL;
 693                 /* Card hasn't responded in 60 seconds?  Must be stuck. */
 694                 if (delay > 60 * 1000) {
 695                         printk(KERN_WARNING "Device %04x:%02x:%02x.%d not "
 696                                         "responding\n", pci_domain_nr(bus),
 697                                         bus->number, PCI_SLOT(devfn),
 698                                         PCI_FUNC(devfn));
 699                         return NULL;
 700                 }
 701         }
 702
 703         if (pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type))
 704                 return NULL;
 705
 706         dev = kmalloc(sizeof(struct pci_dev), GFP_KERNEL);
 707         if (!dev)
 708                 return NULL;
 709
 710         memset(dev, 0, sizeof(struct pci_dev));
 711         dev->bus = bus;
 712         dev->sysdata = bus->sysdata;
 713         dev->dev.parent = bus->bridge;
 714         dev->dev.bus = &pci_bus_type;
 715         dev->devfn = devfn;
 716         dev->hdr_type = hdr_type & 0x7f;
 717         dev->multifunction = !!(hdr_type & 0x80);
 718         dev->vendor = l & 0xffff;
 719         dev->device = (l >> 16) & 0xffff;
 720         dev->cfg_size = pci_cfg_space_size(dev);
 721
 722         /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
 723            set this higher, assuming the system even supports it.  */
 724         dev->dma_mask = 0xffffffff;
 725         if (pci_setup_device(dev) < 0) {
 726                 kfree(dev);
 727                 return NULL;
 728         }
 729         device_initialize(&dev->dev);
 730         dev->dev.release = pci_release_dev;
 731         pci_dev_get(dev);
 732
 733         pci_name_device(dev);
 734
 735         dev->dev.dma_mask = &dev->dma_mask;
 736         dev->dev.coherent_dma_mask = 0xffffffffull;
 737
 738         return dev;
 739 }
 740
 741 struct pci_dev * __devinit
 742 pci_scan_single_device(struct pci_bus *bus, int devfn)
 743 {
 744         struct pci_dev *dev;
 745
 746         dev = pci_scan_device(bus, devfn);
 747         pci_scan_msi_device(dev);
 748
 749         if (!dev)
 750                 return NULL;
 751
 752         /* Fix up broken headers */
 753         pci_fixup_device(pci_fixup_header, dev);
 754
 755         /*
 756          * Add the device to our list of discovered devices
 757          * and the bus list for fixup functions, etc.
 758          */
 759         INIT_LIST_HEAD(&dev->global_list);
 760         list_add_tail(&dev->bus_list, &bus->devices);
 761
 762         return dev;
 763 }
 764
 765 /**
 766  * pci_scan_slot - scan a PCI slot on a bus for devices.
 767  * @bus: PCI bus to scan
 768  * @devfn: slot number to scan (must have zero function.)
 769  *
 770  * Scan a PCI slot on the specified PCI bus for devices, adding
 771  * discovered devices to the @bus->devices list.  New devices
 772  * will have an empty dev->global_list head.
 773  */
 774 int __devinit pci_scan_slot(struct pci_bus *bus, int devfn)
 775 {
 776         int func, nr = 0;
 777         int scan_all_fns;
 778
 779         scan_all_fns = pcibios_scan_all_fns(bus, devfn);
 780
 781         for (func = 0; func < 8; func++, devfn++) {
 782                 struct pci_dev *dev;
 783
 784                 dev = pci_scan_single_device(bus, devfn);
 785                 if (dev) {
 786                         nr++;
 787
 788                         /*
 789                          * If this is a single function device,
 790                          * don't scan past the first function.
 791                          */
 792                         if (!dev->multifunction) {
 793                                 if (func > 0) {
 794                                         dev->multifunction = 1;
 795                                 } else {
 796                                         break;
 797                                 }
 798                         }
 799                 } else {
 800                         if (func == 0 && !scan_all_fns)
 801                                 break;
 802                 }
 803         }
 804         return nr;
 805 }
 806
 807 unsigned int __devinit pci_scan_child_bus(struct pci_bus *bus)
 808 {
 809         unsigned int devfn, pass, max = bus->secondary;
 810         struct pci_dev *dev;
 811
 812         pr_debug("PCI: Scanning bus %04x:%02x\n", pci_domain_nr(bus), bus->number);
 813
 814         /* Go find them, Rover! */
 815         for (devfn = 0; devfn < 0x100; devfn += 8)
 816                 pci_scan_slot(bus, devfn);
 817
 818         /*
 819          * After performing arch-dependent fixup of the bus, look behind
 820          * all PCI-to-PCI bridges on this bus.
 821          */
 822         pr_debug("PCI: Fixups for bus %04x:%02x\n", pci_domain_nr(bus), bus->number);
 823         pcibios_fixup_bus(bus);
 824         for (pass=0; pass < 2; pass++)
 825                 list_for_each_entry(dev, &bus->devices, bus_list) {
 826                         if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
 827                             dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
 828                                 max = pci_scan_bridge(bus, dev, max, pass);
 829                 }
 830
 831         /*
 832          * We've scanned the bus and so we know all about what's on
 833          * the other side of any bridges that may be on this bus plus
 834          * any devices.
 835          *
 836          * Return how far we've got finding sub-buses.
 837          */
 838         pr_debug("PCI: Bus scan for %04x:%02x returning with max=%02x\n",
 839                 pci_domain_nr(bus), bus->number, max);
 840         return max;
 841 }
 842
 843 unsigned int __devinit pci_do_scan_bus(struct pci_bus *bus)
 844 {
 845         unsigned int max;
 846
 847         max = pci_scan_child_bus(bus);
 848
 849         /*
 850          * Make the discovered devices available.
 851          */
 852         pci_bus_add_devices(bus);
 853
 854         return max;
 855 }
 856
 857 struct pci_bus * __devinit pci_scan_bus_parented(struct device *parent, int bus, struct pci_ops *ops, void *sysdata)
 858 {
 859         int error;
 860         struct pci_bus *b;
 861         struct device *dev;
 862
 863         b = pci_alloc_bus();
 864         if (!b)
 865                 return NULL;
 866
 867         dev = kmalloc(sizeof(*dev), GFP_KERNEL);
 868         if (!dev){
 869                 kfree(b);
 870                 return NULL;
 871         }
 872
 873         b->sysdata = sysdata;
 874         b->ops = ops;
 875
 876         if (pci_find_bus(pci_domain_nr(b), bus)) {
 877                 /* If we already got to this bus through a different bridge, ignore it */
 878                 pr_debug("PCI: Bus %04x:%02x already known\n", pci_domain_nr(b), bus);
 879                 goto err_out;
 880         }
 881         list_add_tail(&b->node, &pci_root_buses);
 882
 883         memset(dev, 0, sizeof(*dev));
 884         dev->parent = parent;
 885         dev->release = pci_release_bus_bridge_dev;
 886         sprintf(dev->bus_id, "pci%04x:%02x", pci_domain_nr(b), bus);
 887         error = device_register(dev);
 888         if (error)
 889                 goto dev_reg_err;
 890         b->bridge = get_device(dev);
 891
 892         b->class_dev.class = &pcibus_class;
 893         sprintf(b->class_dev.class_id, "%04x:%02x", pci_domain_nr(b), bus);
 894         error = class_device_register(&b->class_dev);
 895         if (error)
 896                 goto class_dev_reg_err;
 897         error = class_device_create_file(&b->class_dev, &class_device_attr_cpuaffinity);
 898         if (error)
 899                 goto class_dev_create_file_err;
 900
 901         /* Create legacy_io and legacy_mem files for this bus */
 902         pci_create_legacy_files(b);
 903
 904         error = sysfs_create_link(&b->class_dev.kobj, &b->bridge->kobj, "bridge");
 905         if (error)
 906                 goto sys_create_link_err;
 907
 908         b->number = b->secondary = bus;
 909         b->resource[0] = &ioport_resource;
 910         b->resource[1] = &iomem_resource;
 911
 912         b->subordinate = pci_scan_child_bus(b);
 913
 914         pci_bus_add_devices(b);
 915
 916         return b;
 917
 918 sys_create_link_err:
 919         class_device_remove_file(&b->class_dev, &class_device_attr_cpuaffinity);
 920 class_dev_create_file_err:
 921         class_device_unregister(&b->class_dev);
 922 class_dev_reg_err:
 923         device_unregister(dev);
 924 dev_reg_err:
 925         list_del(&b->node);
 926 err_out:
 927         kfree(dev);
 928         kfree(b);
 929         return NULL;
 930 }
 931 EXPORT_SYMBOL(pci_scan_bus_parented);
 932
 933 #ifdef CONFIG_HOTPLUG
 934 EXPORT_SYMBOL(pci_add_new_bus);
 935 EXPORT_SYMBOL(pci_do_scan_bus);
 936 EXPORT_SYMBOL(pci_scan_slot);
 937 EXPORT_SYMBOL(pci_scan_bridge);
 938 EXPORT_SYMBOL(pci_scan_single_device);
 939 EXPORT_SYMBOL_GPL(pci_scan_child_bus);
 940 #endif