[TG3]: Set minimal hw interrupt mitigation.
[linux-2.6/verdex.git] / drivers / s390 / net / qeth_mpc.c
blobf685ecc7da99dc8dbca4ac61a5ab63cfb6c7683a
1 /*
2 * linux/drivers/s390/net/qeth_mpc.c
4 * Linux on zSeries OSA Express and HiperSockets support
6 * Copyright 2000,2003 IBM Corporation
7 * Author(s): Frank Pavlic <pavlic@de.ibm.com>
8 * Thomas Spatzier <tspat@de.ibm.com>
11 #include <asm/cio.h>
12 #include "qeth_mpc.h"
14 const char *VERSION_QETH_MPC_C = "$Revision: 1.11 $";
16 unsigned char IDX_ACTIVATE_READ[]={
17 0x00,0x00,0x80,0x00, 0x00,0x00,0x00,0x00,
18 0x19,0x01,0x01,0x80, 0x00,0x00,0x00,0x00,
19 0x00,0x00,0x00,0x00, 0x00,0x00,0xc8,0xc1,
20 0xd3,0xd3,0xd6,0xd3, 0xc5,0x40,0x00,0x00,
21 0x00,0x00
24 unsigned char IDX_ACTIVATE_WRITE[]={
25 0x00,0x00,0x80,0x00, 0x00,0x00,0x00,0x00,
26 0x15,0x01,0x01,0x80, 0x00,0x00,0x00,0x00,
27 0xff,0xff,0x00,0x00, 0x00,0x00,0xc8,0xc1,
28 0xd3,0xd3,0xd6,0xd3, 0xc5,0x40,0x00,0x00,
29 0x00,0x00
32 unsigned char CM_ENABLE[]={
33 0x00,0xe0,0x00,0x00, 0x00,0x00,0x00,0x01,
34 0x00,0x00,0x00,0x14, 0x00,0x00,0x00,0x63,
35 0x10,0x00,0x00,0x01,
36 0x00,0x00,0x00,0x00,
37 0x81,0x7e,0x00,0x01, 0x00,0x00,0x00,0x00,
38 0x00,0x00,0x00,0x00, 0x00,0x24,0x00,0x23,
39 0x00,0x00,0x23,0x05, 0x00,0x00,0x00,0x00,
40 0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,
41 0x01,0x00,0x00,0x23, 0x00,0x00,0x00,0x40,
42 0x00,0x0c,0x41,0x02, 0x00,0x17,0x00,0x00,
43 0x00,0x00,0x00,0x00,
44 0x00,0x0b,0x04,0x01,
45 0x7e,0x04,0x05,0x00, 0x01,0x01,0x0f,
46 0x00,
47 0x0c,0x04,0x02,0xff, 0xff,0xff,0xff,0xff,
48 0xff,0xff,0xff
51 unsigned char CM_SETUP[]={
52 0x00,0xe0,0x00,0x00, 0x00,0x00,0x00,0x02,
53 0x00,0x00,0x00,0x14, 0x00,0x00,0x00,0x64,
54 0x10,0x00,0x00,0x01,
55 0x00,0x00,0x00,0x00,
56 0x81,0x7e,0x00,0x01, 0x00,0x00,0x00,0x00,
57 0x00,0x00,0x00,0x00, 0x00,0x24,0x00,0x24,
58 0x00,0x00,0x24,0x05, 0x00,0x00,0x00,0x00,
59 0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,
60 0x01,0x00,0x00,0x24, 0x00,0x00,0x00,0x40,
61 0x00,0x0c,0x41,0x04, 0x00,0x18,0x00,0x00,
62 0x00,0x00,0x00,0x00,
63 0x00,0x09,0x04,0x04,
64 0x05,0x00,0x01,0x01, 0x11,
65 0x00,0x09,0x04,
66 0x05,0x05,0x00,0x00, 0x00,0x00,
67 0x00,0x06,
68 0x04,0x06,0xc8,0x00
71 unsigned char ULP_ENABLE[]={
72 0x00,0xe0,0x00,0x00, 0x00,0x00,0x00,0x03,
73 0x00,0x00,0x00,0x14, 0x00,0x00,0x00,0x6b,
74 0x10,0x00,0x00,0x01,
75 0x00,0x00,0x00,0x00,
76 0x41,0x7e,0x00,0x01, 0x00,0x00,0x00,0x01,
77 0x00,0x00,0x00,0x00, 0x00,0x24,0x00,0x2b,
78 0x00,0x00,0x2b,0x05, 0x20,0x01,0x00,0x00,
79 0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,
80 0x01,0x00,0x00,0x2b, 0x00,0x00,0x00,0x40,
81 0x00,0x0c,0x41,0x02, 0x00,0x1f,0x00,0x00,
82 0x00,0x00,0x00,0x00,
83 0x00,0x0b,0x04,0x01,
84 0x03,0x04,0x05,0x00, 0x01,0x01,0x12,
85 0x00,
86 0x14,0x04,0x0a,0x00, 0x20,0x00,0x00,0xff,
87 0xff,0x00,0x08,0xc8, 0xe8,0xc4,0xf1,0xc7,
88 0xf1,0x00,0x00
91 unsigned char ULP_SETUP[]={
92 0x00,0xe0,0x00,0x00, 0x00,0x00,0x00,0x04,
93 0x00,0x00,0x00,0x14, 0x00,0x00,0x00,0x6c,
94 0x10,0x00,0x00,0x01,
95 0x00,0x00,0x00,0x00,
96 0x41,0x7e,0x00,0x01, 0x00,0x00,0x00,0x02,
97 0x00,0x00,0x00,0x01, 0x00,0x24,0x00,0x2c,
98 0x00,0x00,0x2c,0x05, 0x20,0x01,0x00,0x00,
99 0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,
100 0x01,0x00,0x00,0x2c, 0x00,0x00,0x00,0x40,
101 0x00,0x0c,0x41,0x04, 0x00,0x20,0x00,0x00,
102 0x00,0x00,0x00,0x00,
103 0x00,0x09,0x04,0x04,
104 0x05,0x00,0x01,0x01, 0x14,
105 0x00,0x09,0x04,
106 0x05,0x05,0x30,0x01, 0x00,0x00,
107 0x00,0x06,
108 0x04,0x06,0x40,0x00,
109 0x00,0x08,0x04,0x0b,
110 0x00,0x00,0x00,0x00
113 unsigned char DM_ACT[]={
114 0x00,0xe0,0x00,0x00, 0x00,0x00,0x00,0x05,
115 0x00,0x00,0x00,0x14, 0x00,0x00,0x00,0x55,
116 0x10,0x00,0x00,0x01,
117 0x00,0x00,0x00,0x00,
118 0x41,0x7e,0x00,0x01, 0x00,0x00,0x00,0x03,
119 0x00,0x00,0x00,0x02, 0x00,0x24,0x00,0x15,
120 0x00,0x00,0x2c,0x05, 0x20,0x01,0x00,0x00,
121 0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,
122 0x01,0x00,0x00,0x15, 0x00,0x00,0x00,0x40,
123 0x00,0x0c,0x43,0x60, 0x00,0x09,0x00,0x00,
124 0x00,0x00,0x00,0x00,
125 0x00,0x09,0x04,0x04,
126 0x05,0x40,0x01,0x01, 0x00
129 unsigned char IPA_PDU_HEADER[]={
130 0x00,0xe0,0x00,0x00, 0x77,0x77,0x77,0x77,
131 0x00,0x00,0x00,0x14, 0x00,0x00,
132 (IPA_PDU_HEADER_SIZE+sizeof(struct qeth_ipa_cmd))/256,
133 (IPA_PDU_HEADER_SIZE+sizeof(struct qeth_ipa_cmd))%256,
134 0x10,0x00,0x00,0x01, 0x00,0x00,0x00,0x00,
135 0xc1,0x03,0x00,0x01, 0x00,0x00,0x00,0x00,
136 0x00,0x00,0x00,0x00, 0x00,0x24,
137 sizeof(struct qeth_ipa_cmd)/256,
138 sizeof(struct qeth_ipa_cmd)%256,
139 0x00,
140 sizeof(struct qeth_ipa_cmd)/256,
141 sizeof(struct qeth_ipa_cmd),0x05, 0x77,0x77,0x77,0x77,
142 0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,
143 0x01,0x00,
144 sizeof(struct qeth_ipa_cmd)/256,
145 sizeof(struct qeth_ipa_cmd)%256,
146 0x00,0x00,0x00,0x40,
149 unsigned char WRITE_CCW[]={
150 0x01,CCW_FLAG_SLI,0,0,
151 0,0,0,0
154 unsigned char READ_CCW[]={
155 0x02,CCW_FLAG_SLI,0,0,
156 0,0,0,0