drivers/scsi/NCR53C9x.h

   1 /* NCR53C9x.c:  Defines and structures for the NCR53C9x generic driver.
   2  *
   3  * Originaly esp.h:  Defines and structures for the Sparc ESP
   4  *                   (Enhanced SCSI Processor) driver under Linux.
   5  *
   6  * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
   7  *
   8  * Generalization by Jesper Skov (jskov@cygnus.co.uk)
   9  *
  10  * More generalization (for i386 stuff) by Tymm Twillman (tymm@computer.org)
  11  */
  12
  13 #ifndef NCR53C9X_H
  14 #define NCR53C9X_H
  15
  16 #include <linux/config.h>
  17 #include <linux/interrupt.h>
  18
  19 /* djweis for mac driver */
  20 #if defined(CONFIG_MAC)
  21 #define PAD_SIZE 15
  22 #else
  23 #define PAD_SIZE 3
  24 #endif
  25
  26 /* Handle multiple hostadapters on Amiga
  27  * generally PAD_SIZE = 3
  28  * but there is one exception: Oktagon (PAD_SIZE = 1) */
  29 #if defined(CONFIG_OKTAGON_SCSI) || defined(CONFIG_OKTAGON_SCSI_MODULE)
  30 #undef PAD_SIZE
  31 #if defined(CONFIG_BLZ1230_SCSI) || defined(CONFIG_BLZ1230_SCSI_MODULE) || \
  32     defined(CONFIG_BLZ2060_SCSI) || defined(CONFIG_BLZ2060_SCSI_MODULE) || \
  33     defined(CONFIG_CYBERSTORM_SCSI) || defined(CONFIG_CYBERSTORM_SCSI_MODULE) || \
  34     defined(CONFIG_CYBERSTORMII_SCSI) || defined(CONFIG_CYBERSTORMII_SCSI_MODULE) || \
  35     defined(CONFIG_FASTLANE_SCSI) || defined(CONFIG_FASTLANE_SCSI_MODULE)
  36 #define MULTIPLE_PAD_SIZES
  37 #else
  38 #define PAD_SIZE 1
  39 #endif
  40 #endif
  41
  42 /* Macros for debugging messages */
  43
  44 #define DEBUG_ESP
  45 /* #define DEBUG_ESP_DATA */
  46 /* #define DEBUG_ESP_QUEUE */
  47 /* #define DEBUG_ESP_DISCONNECT */
  48 /* #define DEBUG_ESP_STATUS */
  49 /* #define DEBUG_ESP_PHASES */
  50 /* #define DEBUG_ESP_WORKBUS */
  51 /* #define DEBUG_STATE_MACHINE */
  52 /* #define DEBUG_ESP_CMDS */
  53 /* #define DEBUG_ESP_IRQS */
  54 /* #define DEBUG_SDTR */
  55 /* #define DEBUG_ESP_SG */
  56
  57 /* Use the following to sprinkle debugging messages in a way which
  58  * suits you if combinations of the above become too verbose when
  59  * trying to track down a specific problem.
  60  */
  61 /* #define DEBUG_ESP_MISC */
  62
  63 #if defined(DEBUG_ESP)
  64 #define ESPLOG(foo)  printk foo
  65 #else
  66 #define ESPLOG(foo)
  67 #endif /* (DEBUG_ESP) */
  68
  69 #if defined(DEBUG_ESP_DATA)
  70 #define ESPDATA(foo)  printk foo
  71 #else
  72 #define ESPDATA(foo)
  73 #endif
  74
  75 #if defined(DEBUG_ESP_QUEUE)
  76 #define ESPQUEUE(foo)  printk foo
  77 #else
  78 #define ESPQUEUE(foo)
  79 #endif
  80
  81 #if defined(DEBUG_ESP_DISCONNECT)
  82 #define ESPDISC(foo)  printk foo
  83 #else
  84 #define ESPDISC(foo)
  85 #endif
  86
  87 #if defined(DEBUG_ESP_STATUS)
  88 #define ESPSTAT(foo)  printk foo
  89 #else
  90 #define ESPSTAT(foo)
  91 #endif
  92
  93 #if defined(DEBUG_ESP_PHASES)
  94 #define ESPPHASE(foo)  printk foo
  95 #else
  96 #define ESPPHASE(foo)
  97 #endif
  98
  99 #if defined(DEBUG_ESP_WORKBUS)
 100 #define ESPBUS(foo)  printk foo
 101 #else
 102 #define ESPBUS(foo)
 103 #endif
 104
 105 #if defined(DEBUG_ESP_IRQS)
 106 #define ESPIRQ(foo)  printk foo
 107 #else
 108 #define ESPIRQ(foo)
 109 #endif
 110
 111 #if defined(DEBUG_SDTR)
 112 #define ESPSDTR(foo)  printk foo
 113 #else
 114 #define ESPSDTR(foo)
 115 #endif
 116
 117 #if defined(DEBUG_ESP_MISC)
 118 #define ESPMISC(foo)  printk foo
 119 #else
 120 #define ESPMISC(foo)
 121 #endif
 122
 123 /*
 124  * padding for register structure
 125  */
 126 #ifdef CONFIG_JAZZ_ESP
 127 #define EREGS_PAD(n)
 128 #else
 129 #ifndef MULTIPLE_PAD_SIZES
 130 #define EREGS_PAD(n)    unchar n[PAD_SIZE];
 131 #endif
 132 #endif
 133
 134 /* The ESP SCSI controllers have their register sets in three
 135  * "classes":
 136  *
 137  * 1) Registers which are both read and write.
 138  * 2) Registers which are read only.
 139  * 3) Registers which are write only.
 140  *
 141  * Yet, they all live within the same IO space.
 142  */
 143
 144 #if !defined(__i386__) && !defined(__x86_64__)
 145
 146 #ifndef MULTIPLE_PAD_SIZES
 147
 148 #ifdef CONFIG_CPU_HAS_WB
 149 #include <asm/wbflush.h>
 150 #define esp_write(__reg, __val) do{(__reg) = (__val); wbflush();} while(0)
 151 #else
 152 #define esp_write(__reg, __val) ((__reg) = (__val))
 153 #endif
 154 #define esp_read(__reg) (__reg)
 155
 156 struct ESP_regs {
 157                                 /* Access    Description              Offset */
 158     volatile unchar esp_tclow;  /* rw  Low bits of the transfer count 0x00   */
 159                                 EREGS_PAD(tlpad1);
 160     volatile unchar esp_tcmed;  /* rw  Mid bits of the transfer count 0x04   */
 161                                 EREGS_PAD(fdpad);
 162     volatile unchar esp_fdata;  /* rw  FIFO data bits                 0x08   */
 163                                 EREGS_PAD(cbpad);
 164     volatile unchar esp_cmnd;   /* rw  SCSI command bits              0x0c   */
 165                                 EREGS_PAD(stpad);
 166     volatile unchar esp_status; /* ro  ESP status register            0x10   */
 167 #define esp_busid   esp_status  /* wo  Bus ID for select/reselect     0x10   */
 168                                 EREGS_PAD(irqpd);
 169     volatile unchar esp_intrpt; /* ro  Kind of interrupt              0x14   */
 170 #define esp_timeo   esp_intrpt  /* wo  Timeout value for select/resel 0x14   */
 171                                 EREGS_PAD(sspad);
 172     volatile unchar esp_sstep;  /* ro  Sequence step register         0x18   */
 173 #define esp_stp     esp_sstep   /* wo  Transfer period per sync       0x18   */
 174                                 EREGS_PAD(ffpad);
 175     volatile unchar esp_fflags; /* ro  Bits of current FIFO info      0x1c   */
 176 #define esp_soff    esp_fflags  /* wo  Sync offset                    0x1c   */
 177                                 EREGS_PAD(cf1pd);
 178     volatile unchar esp_cfg1;   /* rw  First configuration register   0x20   */
 179                                 EREGS_PAD(cfpad);
 180     volatile unchar esp_cfact;  /* wo  Clock conversion factor        0x24   */
 181                                 EREGS_PAD(ctpad);
 182     volatile unchar esp_ctest;  /* wo  Chip test register             0x28   */
 183                                 EREGS_PAD(cf2pd);
 184     volatile unchar esp_cfg2;   /* rw  Second configuration register  0x2c   */
 185                                 EREGS_PAD(cf3pd);
 186
 187     /* The following is only found on the 53C9X series SCSI chips */
 188     volatile unchar esp_cfg3;   /* rw  Third configuration register   0x30  */
 189                                 EREGS_PAD(cf4pd);
 190     volatile unchar esp_cfg4;   /* rw  Fourth configuration register  0x34  */
 191                                 EREGS_PAD(thpd);
 192     /* The following is found on all chips except the NCR53C90 (ESP100) */
 193     volatile unchar esp_tchi;   /* rw  High bits of transfer count    0x38  */
 194 #define esp_uid     esp_tchi    /* ro  Unique ID code                 0x38  */
 195                                 EREGS_PAD(fgpad);
 196     volatile unchar esp_fgrnd;  /* rw  Data base for fifo             0x3c  */
 197 };
 198
 199 #else /* MULTIPLE_PAD_SIZES */
 200
 201 #define esp_write(__reg, __val) (*(__reg) = (__val))
 202 #define esp_read(__reg) (*(__reg))
 203
 204 struct ESP_regs {
 205     unsigned char io_addr[64]; /* dummy */
 206                                                  /* Access    Description              Offset */
 207 #define esp_tclow   io_addr                      /* rw  Low bits of the transfer count 0x00   */
 208 #define esp_tcmed   io_addr + (1<<(esp->shift))  /* rw  Mid bits of the transfer count 0x04   */
 209 #define esp_fdata   io_addr + (2<<(esp->shift))  /* rw  FIFO data bits                 0x08   */
 210 #define esp_cmnd    io_addr + (3<<(esp->shift))  /* rw  SCSI command bits              0x0c   */
 211 #define esp_status  io_addr + (4<<(esp->shift))  /* ro  ESP status register            0x10   */
 212 #define esp_busid   esp_status                   /* wo  Bus ID for select/reselect     0x10   */
 213 #define esp_intrpt  io_addr + (5<<(esp->shift))  /* ro  Kind of interrupt              0x14   */
 214 #define esp_timeo   esp_intrpt                   /* wo  Timeout value for select/resel 0x14   */
 215 #define esp_sstep   io_addr + (6<<(esp->shift))  /* ro  Sequence step register         0x18   */
 216 #define esp_stp     esp_sstep                    /* wo  Transfer period per sync       0x18   */
 217 #define esp_fflags  io_addr + (7<<(esp->shift))  /* ro  Bits of current FIFO info      0x1c   */
 218 #define esp_soff    esp_fflags                   /* wo  Sync offset                    0x1c   */
 219 #define esp_cfg1    io_addr + (8<<(esp->shift))  /* rw  First configuration register   0x20   */
 220 #define esp_cfact   io_addr + (9<<(esp->shift))  /* wo  Clock conversion factor        0x24   */
 221 #define esp_ctest   io_addr + (10<<(esp->shift)) /* wo  Chip test register             0x28   */
 222 #define esp_cfg2    io_addr + (11<<(esp->shift)) /* rw  Second configuration register  0x2c   */
 223
 224     /* The following is only found on the 53C9X series SCSI chips */
 225 #define esp_cfg3    io_addr + (12<<(esp->shift)) /* rw  Third configuration register   0x30  */
 226 #define esp_cfg4    io_addr + (13<<(esp->shift)) /* rw  Fourth configuration register  0x34  */
 227
 228     /* The following is found on all chips except the NCR53C90 (ESP100) */
 229 #define esp_tchi    io_addr + (14<<(esp->shift)) /* rw  High bits of transfer count    0x38  */
 230 #define esp_uid     esp_tchi                     /* ro  Unique ID code                 0x38  */
 231 #define esp_fgrnd   io_addr + (15<<(esp->shift)) /* rw  Data base for fifo             0x3c  */
 232 };
 233
 234 #endif
 235
 236 #else /* !defined(__i386__) && !defined(__x86_64__) */
 237
 238 #define esp_write(__reg, __val) outb((__val), (__reg))
 239 #define esp_read(__reg) inb((__reg))
 240
 241 struct ESP_regs {
 242     unsigned int io_addr;
 243                                  /* Access    Description              Offset */
 244 #define esp_tclow   io_addr      /* rw  Low bits of the transfer count 0x00   */
 245 #define esp_tcmed   io_addr + 1  /* rw  Mid bits of the transfer count 0x04   */
 246 #define esp_fdata   io_addr + 2  /* rw  FIFO data bits                 0x08   */
 247 #define esp_cmnd    io_addr + 3  /* rw  SCSI command bits              0x0c   */
 248 #define esp_status  io_addr + 4  /* ro  ESP status register            0x10   */
 249 #define esp_busid   esp_status   /* wo  Bus ID for select/reselect     0x10   */
 250 #define esp_intrpt  io_addr + 5  /* ro  Kind of interrupt              0x14   */
 251 #define esp_timeo   esp_intrpt   /* wo  Timeout value for select/resel 0x14   */
 252 #define esp_sstep   io_addr + 6  /* ro  Sequence step register         0x18   */
 253 #define esp_stp     esp_sstep    /* wo  Transfer period per sync       0x18   */
 254 #define esp_fflags  io_addr + 7  /* ro  Bits of current FIFO info      0x1c   */
 255 #define esp_soff    esp_fflags   /* wo  Sync offset                    0x1c   */
 256 #define esp_cfg1    io_addr + 8  /* rw  First configuration register   0x20   */
 257 #define esp_cfact   io_addr + 9  /* wo  Clock conversion factor        0x24   */
 258 #define esp_ctest   io_addr + 10 /* wo  Chip test register             0x28   */
 259 #define esp_cfg2    io_addr + 11 /* rw  Second configuration register  0x2c   */
 260
 261     /* The following is only found on the 53C9X series SCSI chips */
 262 #define esp_cfg3    io_addr + 12 /* rw  Third configuration register   0x30  */
 263 #define esp_cfg4    io_addr + 13 /* rw  Fourth configuration register  0x34  */
 264
 265     /* The following is found on all chips except the NCR53C90 (ESP100) */
 266 #define esp_tchi    io_addr + 14 /* rw  High bits of transfer count    0x38  */
 267 #define esp_uid     esp_tchi     /* ro  Unique ID code                 0x38  */
 268 #define esp_fgrnd   io_addr + 15 /* rw  Data base for fifo             0x3c  */
 269 };
 270
 271 #endif /* !defined(__i386__) && !defined(__x86_64__) */
 272
 273 /* Various revisions of the ESP board. */
 274 enum esp_rev {
 275   esp100     = 0x00,  /* NCR53C90 - very broken */
 276   esp100a    = 0x01,  /* NCR53C90A */
 277   esp236     = 0x02,
 278   fas236     = 0x03,
 279   fas100a    = 0x04,
 280   fast       = 0x05,
 281   fas366     = 0x06,
 282   fas216     = 0x07,
 283   fsc        = 0x08,  /* SYM53C94-2 */
 284   espunknown = 0x09
 285 };
 286
 287 /* We allocate one of these for each scsi device and attach it to
 288  * SDptr->hostdata for use in the driver
 289  */
 290 struct esp_device {
 291   unsigned char sync_min_period;
 292   unsigned char sync_max_offset;
 293   unsigned sync:1;
 294   unsigned wide:1;
 295   unsigned disconnect:1;
 296 };
 297
 298 /* We get one of these for each ESP probed. */
 299 struct NCR_ESP {
 300   struct NCR_ESP *next;                   /* Next ESP on probed or NULL */
 301   struct ESP_regs *eregs;                 /* All esp registers */
 302   int dma;                                /* Who I do transfers with. */
 303   void *dregs;                            /* And his registers. */
 304   struct Scsi_Host *ehost;                /* Backpointer to SCSI Host */
 305
 306   void *edev;                             /* Pointer to controller base/SBus */
 307   int esp_id;                             /* Unique per-ESP ID number */
 308
 309   /* ESP Configuration Registers */
 310   unsigned char config1;                  /* Copy of the 1st config register */
 311   unsigned char config2;                  /* Copy of the 2nd config register */
 312   unsigned char config3[16];              /* Copy of the 3rd config register */
 313
 314   /* The current command we are sending to the ESP chip.  This esp_command
 315    * ptr needs to be mapped in DVMA area so we can send commands and read
 316    * from the ESP fifo without burning precious CPU cycles.  Programmed I/O
 317    * sucks when we have the DVMA to do it for us.  The ESP is stupid and will
 318    * only send out 6, 10, and 12 byte SCSI commands, others we need to send
 319    * one byte at a time.  esp_slowcmd being set says that we are doing one
 320    * of the command types ESP doesn't understand, esp_scmdp keeps track of
 321    * which byte we are sending, esp_scmdleft says how many bytes to go.
 322    */
 323   volatile unchar *esp_command;           /* Location of command (CPU view)  */
 324   __u32            esp_command_dvma;      /* Location of command (DVMA view) */
 325   unsigned char esp_clen;                 /* Length of this command */
 326   unsigned char esp_slowcmd;
 327   unsigned char *esp_scmdp;
 328   unsigned char esp_scmdleft;
 329
 330   /* The following are used to determine the cause of an IRQ. Upon every
 331    * IRQ entry we synchronize these with the hardware registers.
 332    */
 333   unchar ireg;                            /* Copy of ESP interrupt register */
 334   unchar sreg;                            /* Same for ESP status register */
 335   unchar seqreg;                          /* The ESP sequence register */
 336
 337   /* The following is set when a premature interrupt condition is detected
 338    * in some FAS revisions.
 339    */
 340   unchar fas_premature_intr_workaround;
 341
 342   /* To save register writes to the ESP, which can be expensive, we
 343    * keep track of the previous value that various registers had for
 344    * the last target we connected to.  If they are the same for the
 345    * current target, we skip the register writes as they are not needed.
 346    */
 347   unchar prev_soff, prev_stp, prev_cfg3;
 348
 349   /* For each target we keep track of save/restore data
 350    * pointer information.  This needs to be updated majorly
 351    * when we add support for tagged queueing.  -DaveM
 352    */
 353   struct esp_pointers {
 354           char *saved_ptr;
 355           struct scatterlist *saved_buffer;
 356           int saved_this_residual;
 357           int saved_buffers_residual;
 358   } data_pointers[16] /*XXX [MAX_TAGS_PER_TARGET]*/;
 359
 360   /* Clock periods, frequencies, synchronization, etc. */
 361   unsigned int cfreq;                    /* Clock frequency in HZ */
 362   unsigned int cfact;                    /* Clock conversion factor */
 363   unsigned int ccycle;                   /* One ESP clock cycle */
 364   unsigned int ctick;                    /* One ESP clock time */
 365   unsigned int radelay;                  /* FAST chip req/ack delay */
 366   unsigned int neg_defp;                 /* Default negotiation period */
 367   unsigned int sync_defp;                /* Default sync transfer period */
 368   unsigned int max_period;               /* longest our period can be */
 369   unsigned int min_period;               /* shortest period we can withstand */
 370   /* For slow to medium speed input clock rates we shoot for 5mb/s,
 371    * but for high input clock rates we try to do 10mb/s although I
 372    * don't think a transfer can even run that fast with an ESP even
 373    * with DMA2 scatter gather pipelining.
 374    */
 375 #define SYNC_DEFP_SLOW            0x32   /* 5mb/s  */
 376 #define SYNC_DEFP_FAST            0x19   /* 10mb/s */
 377
 378   unsigned int snip;                      /* Sync. negotiation in progress */
 379   unsigned int wnip;                      /* WIDE negotiation in progress */
 380   unsigned int targets_present;           /* targets spoken to before */
 381
 382   int current_transfer_size;              /* Set at beginning of data dma */
 383
 384   unchar espcmdlog[32];                   /* Log of current esp cmds sent. */
 385   unchar espcmdent;                       /* Current entry in esp cmd log. */
 386
 387   /* Misc. info about this ESP */
 388   enum esp_rev erev;                      /* ESP revision */
 389   int irq;                                /* IRQ for this ESP */
 390   int scsi_id;                            /* Who am I as initiator? */
 391   int scsi_id_mask;                       /* Bitmask of 'me'. */
 392   int diff;                               /* Differential SCSI bus? */
 393   int slot;                               /* Slot the adapter occupies */
 394
 395   /* Our command queues, only one cmd lives in the current_SC queue. */
 396   Scsi_Cmnd *issue_SC;           /* Commands to be issued */
 397   Scsi_Cmnd *current_SC;         /* Who is currently working the bus */
 398   Scsi_Cmnd *disconnected_SC;    /* Commands disconnected from the bus */
 399
 400   /* Message goo */
 401   unchar cur_msgout[16];
 402   unchar cur_msgin[16];
 403   unchar prevmsgout, prevmsgin;
 404   unchar msgout_len, msgin_len;
 405   unchar msgout_ctr, msgin_ctr;
 406
 407   /* States that we cannot keep in the per cmd structure because they
 408    * cannot be assosciated with any specific command.
 409    */
 410   unchar resetting_bus;
 411   wait_queue_head_t reset_queue;
 412
 413   unchar do_pio_cmds;           /* Do command transfer with pio */
 414
 415   /* How much bits do we have to shift the registers */
 416   unsigned char shift;
 417
 418   /* Functions handling DMA
 419    */
 420   /* Required functions */
 421   int  (*dma_bytes_sent)(struct NCR_ESP *, int);
 422   int  (*dma_can_transfer)(struct NCR_ESP *, Scsi_Cmnd *);
 423   void (*dma_dump_state)(struct NCR_ESP *);
 424   void (*dma_init_read)(struct NCR_ESP *, __u32, int);
 425   void (*dma_init_write)(struct NCR_ESP *, __u32, int);
 426   void (*dma_ints_off)(struct NCR_ESP *);
 427   void (*dma_ints_on)(struct NCR_ESP *);
 428   int  (*dma_irq_p)(struct NCR_ESP *);
 429   int  (*dma_ports_p)(struct NCR_ESP *);
 430   void (*dma_setup)(struct NCR_ESP *, __u32, int, int);
 431
 432   /* Optional functions (i.e. may be initialized to 0) */
 433   void (*dma_barrier)(struct NCR_ESP *);
 434   void (*dma_drain)(struct NCR_ESP *);
 435   void (*dma_invalidate)(struct NCR_ESP *);
 436   void (*dma_irq_entry)(struct NCR_ESP *);
 437   void (*dma_irq_exit)(struct NCR_ESP *);
 438   void (*dma_led_off)(struct NCR_ESP *);
 439   void (*dma_led_on)(struct NCR_ESP *);
 440   void (*dma_poll)(struct NCR_ESP *, unsigned char *);
 441   void (*dma_reset)(struct NCR_ESP *);
 442
 443   /* Optional virtual DMA functions */
 444   void (*dma_mmu_get_scsi_one)(struct NCR_ESP *, Scsi_Cmnd *);
 445   void (*dma_mmu_get_scsi_sgl)(struct NCR_ESP *, Scsi_Cmnd *);
 446   void (*dma_mmu_release_scsi_one)(struct NCR_ESP *, Scsi_Cmnd *);
 447   void (*dma_mmu_release_scsi_sgl)(struct NCR_ESP *, Scsi_Cmnd *);
 448   void (*dma_advance_sg)(Scsi_Cmnd *);
 449 };
 450
 451 /* Bitfield meanings for the above registers. */
 452
 453 /* ESP config reg 1, read-write, found on all ESP chips */
 454 #define ESP_CONFIG1_ID        0x07             /* My BUS ID bits */
 455 #define ESP_CONFIG1_CHTEST    0x08             /* Enable ESP chip tests */
 456 #define ESP_CONFIG1_PENABLE   0x10             /* Enable parity checks */
 457 #define ESP_CONFIG1_PARTEST   0x20             /* Parity test mode enabled? */
 458 #define ESP_CONFIG1_SRRDISAB  0x40             /* Disable SCSI reset reports */
 459 #define ESP_CONFIG1_SLCABLE   0x80             /* Enable slow cable mode */
 460
 461 /* ESP config reg 2, read-write, found only on esp100a+esp200+esp236+fsc chips */
 462 #define ESP_CONFIG2_DMAPARITY 0x01             /* enable DMA Parity (200,236,fsc) */
 463 #define ESP_CONFIG2_REGPARITY 0x02             /* enable reg Parity (200,236,fsc) */
 464 #define ESP_CONFIG2_BADPARITY 0x04             /* Bad parity target abort  */
 465 #define ESP_CONFIG2_SCSI2ENAB 0x08             /* Enable SCSI-2 features (tmode only) */
 466 #define ESP_CONFIG2_HI        0x10             /* High Impedance DREQ ???  */
 467 #define ESP_CONFIG2_HMEFENAB  0x10             /* HME features enable */
 468 #define ESP_CONFIG2_BCM       0x20             /* Enable byte-ctrl (236,fsc)   */
 469 #define ESP_CONFIG2_FENAB     0x40             /* Enable features (fas100,esp216,fsc)      */
 470 #define ESP_CONFIG2_SPL       0x40             /* Enable status-phase latch (esp236)   */
 471 #define ESP_CONFIG2_RFB       0x80             /* Reserve FIFO byte (fsc) */
 472 #define ESP_CONFIG2_MAGIC     0xe0             /* Invalid bits... */
 473
 474 /* ESP config register 3 read-write, found only esp236+fas236+fas100a+fsc chips */
 475 #define ESP_CONFIG3_FCLOCK    0x01             /* FAST SCSI clock rate (esp100a/fas366) */
 476 #define ESP_CONFIG3_TEM       0x01             /* Enable thresh-8 mode (esp/fas236/fsc)  */
 477 #define ESP_CONFIG3_FAST      0x02             /* Enable FAST SCSI     (esp100a) */
 478 #define ESP_CONFIG3_ADMA      0x02             /* Enable alternate-dma (esp/fas236/fsc)  */
 479 #define ESP_CONFIG3_TENB      0x04             /* group2 SCSI2 support (esp100a) */
 480 #define ESP_CONFIG3_SRB       0x04             /* Save residual byte   (esp/fas236/fsc)  */
 481 #define ESP_CONFIG3_TMS       0x08             /* Three-byte msg's ok  (esp100a) */
 482 #define ESP_CONFIG3_FCLK      0x08             /* Fast SCSI clock rate (esp/fas236/fsc)  */
 483 #define ESP_CONFIG3_IDMSG     0x10             /* ID message checking  (esp100a) */
 484 #define ESP_CONFIG3_FSCSI     0x10             /* Enable FAST SCSI     (esp/fas236/fsc)  */
 485 #define ESP_CONFIG3_GTM       0x20             /* group2 SCSI2 support (esp/fas236/fsc)  */
 486 #define ESP_CONFIG3_TBMS      0x40             /* Three-byte msg's ok  (esp/fas236/fsc)  */
 487 #define ESP_CONFIG3_IMS       0x80             /* ID msg chk'ng        (esp/fas236/fsc)  */
 488
 489 /* ESP config register 4 read-write, found only on fsc chips */
 490 #define ESP_CONFIG4_BBTE      0x01             /* Back-to-Back transfer enable */
 491 #define ESP_CONFIG4_TEST      0x02             /* Transfer counter test mode */
 492 #define ESP_CONFIG4_EAN       0x04             /* Enable Active Negotiation */
 493
 494 /* ESP command register read-write */
 495 /* Group 1 commands:  These may be sent at any point in time to the ESP
 496  *                    chip.  None of them can generate interrupts 'cept
 497  *                    the "SCSI bus reset" command if you have not disabled
 498  *                    SCSI reset interrupts in the config1 ESP register.
 499  */
 500 #define ESP_CMD_NULL          0x00             /* Null command, ie. a nop */
 501 #define ESP_CMD_FLUSH         0x01             /* FIFO Flush */
 502 #define ESP_CMD_RC            0x02             /* Chip reset */
 503 #define ESP_CMD_RS            0x03             /* SCSI bus reset */
 504
 505 /* Group 2 commands:  ESP must be an initiator and connected to a target
 506  *                    for these commands to work.
 507  */
 508 #define ESP_CMD_TI            0x10             /* Transfer Information */
 509 #define ESP_CMD_ICCSEQ        0x11             /* Initiator cmd complete sequence */
 510 #define ESP_CMD_MOK           0x12             /* Message okie-dokie */
 511 #define ESP_CMD_TPAD          0x18             /* Transfer Pad */
 512 #define ESP_CMD_SATN          0x1a             /* Set ATN */
 513 #define ESP_CMD_RATN          0x1b             /* De-assert ATN */
 514
 515 /* Group 3 commands:  ESP must be in the MSGOUT or MSGIN state and be connected
 516  *                    to a target as the initiator for these commands to work.
 517  */
 518 #define ESP_CMD_SMSG          0x20             /* Send message */
 519 #define ESP_CMD_SSTAT         0x21             /* Send status */
 520 #define ESP_CMD_SDATA         0x22             /* Send data */
 521 #define ESP_CMD_DSEQ          0x23             /* Discontinue Sequence */
 522 #define ESP_CMD_TSEQ          0x24             /* Terminate Sequence */
 523 #define ESP_CMD_TCCSEQ        0x25             /* Target cmd cmplt sequence */
 524 #define ESP_CMD_DCNCT         0x27             /* Disconnect */
 525 #define ESP_CMD_RMSG          0x28             /* Receive Message */
 526 #define ESP_CMD_RCMD          0x29             /* Receive Command */
 527 #define ESP_CMD_RDATA         0x2a             /* Receive Data */
 528 #define ESP_CMD_RCSEQ         0x2b             /* Receive cmd sequence */
 529
 530 /* Group 4 commands:  The ESP must be in the disconnected state and must
 531  *                    not be connected to any targets as initiator for
 532  *                    these commands to work.
 533  */
 534 #define ESP_CMD_RSEL          0x40             /* Reselect */
 535 #define ESP_CMD_SEL           0x41             /* Select w/o ATN */
 536 #define ESP_CMD_SELA          0x42             /* Select w/ATN */
 537 #define ESP_CMD_SELAS         0x43             /* Select w/ATN & STOP */
 538 #define ESP_CMD_ESEL          0x44             /* Enable selection */
 539 #define ESP_CMD_DSEL          0x45             /* Disable selections */
 540 #define ESP_CMD_SA3           0x46             /* Select w/ATN3 */
 541 #define ESP_CMD_RSEL3         0x47             /* Reselect3 */
 542
 543 /* This bit enables the ESP's DMA */
 544 #define ESP_CMD_DMA           0x80             /* Do DMA? */
 545
 546 /* ESP status register read-only */
 547 #define ESP_STAT_PIO          0x01             /* IO phase bit */
 548 #define ESP_STAT_PCD          0x02             /* CD phase bit */
 549 #define ESP_STAT_PMSG         0x04             /* MSG phase bit */
 550 #define ESP_STAT_PMASK        0x07             /* Mask of phase bits */
 551 #define ESP_STAT_TDONE        0x08             /* Transfer Completed */
 552 #define ESP_STAT_TCNT         0x10             /* Transfer Counter Is Zero */
 553 #define ESP_STAT_PERR         0x20             /* Parity error */
 554 #define ESP_STAT_SPAM         0x40             /* Real bad error */
 555 /* This indicates the 'interrupt pending' condition, it is a reserved
 556  * bit on old revs of the ESP (ESP100, ESP100A, FAS100A).
 557  */
 558 #define ESP_STAT_INTR         0x80             /* Interrupt */
 559
 560 /* The status register can be masked with ESP_STAT_PMASK and compared
 561  * with the following values to determine the current phase the ESP
 562  * (at least thinks it) is in.  For our purposes we also add our own
 563  * software 'done' bit for our phase management engine.
 564  */
 565 #define ESP_DOP   (0)                                       /* Data Out  */
 566 #define ESP_DIP   (ESP_STAT_PIO)                            /* Data In   */
 567 #define ESP_CMDP  (ESP_STAT_PCD)                            /* Command   */
 568 #define ESP_STATP (ESP_STAT_PCD|ESP_STAT_PIO)               /* Status    */
 569 #define ESP_MOP   (ESP_STAT_PMSG|ESP_STAT_PCD)              /* Message Out */
 570 #define ESP_MIP   (ESP_STAT_PMSG|ESP_STAT_PCD|ESP_STAT_PIO) /* Message In */
 571
 572 /* ESP interrupt register read-only */
 573 #define ESP_INTR_S            0x01             /* Select w/o ATN */
 574 #define ESP_INTR_SATN         0x02             /* Select w/ATN */
 575 #define ESP_INTR_RSEL         0x04             /* Reselected */
 576 #define ESP_INTR_FDONE        0x08             /* Function done */
 577 #define ESP_INTR_BSERV        0x10             /* Bus service */
 578 #define ESP_INTR_DC           0x20             /* Disconnect */
 579 #define ESP_INTR_IC           0x40             /* Illegal command given */
 580 #define ESP_INTR_SR           0x80             /* SCSI bus reset detected */
 581
 582 /* Interrupt status macros */
 583 #define ESP_SRESET_IRQ(esp)  ((esp)->intreg & (ESP_INTR_SR))
 584 #define ESP_ILLCMD_IRQ(esp)  ((esp)->intreg & (ESP_INTR_IC))
 585 #define ESP_SELECT_WITH_ATN_IRQ(esp)     ((esp)->intreg & (ESP_INTR_SATN))
 586 #define ESP_SELECT_WITHOUT_ATN_IRQ(esp)  ((esp)->intreg & (ESP_INTR_S))
 587 #define ESP_SELECTION_IRQ(esp)  ((ESP_SELECT_WITH_ATN_IRQ(esp)) ||         \
 588                                  (ESP_SELECT_WITHOUT_ATN_IRQ(esp)))
 589 #define ESP_RESELECTION_IRQ(esp)         ((esp)->intreg & (ESP_INTR_RSEL))
 590
 591 /* ESP sequence step register read-only */
 592 #define ESP_STEP_VBITS        0x07             /* Valid bits */
 593 #define ESP_STEP_ASEL         0x00             /* Selection&Arbitrate cmplt */
 594 #define ESP_STEP_SID          0x01             /* One msg byte sent */
 595 #define ESP_STEP_NCMD         0x02             /* Was not in command phase */
 596 #define ESP_STEP_PPC          0x03             /* Early phase chg caused cmnd
 597                                                 * bytes to be lost
 598                                                 */
 599 #define ESP_STEP_FINI4        0x04             /* Command was sent ok */
 600
 601 /* Ho hum, some ESP's set the step register to this as well... */
 602 #define ESP_STEP_FINI5        0x05
 603 #define ESP_STEP_FINI6        0x06
 604 #define ESP_STEP_FINI7        0x07
 605 #define ESP_STEP_SOM          0x08             /* Synchronous Offset Max */
 606
 607 /* ESP chip-test register read-write */
 608 #define ESP_TEST_TARG         0x01             /* Target test mode */
 609 #define ESP_TEST_INI          0x02             /* Initiator test mode */
 610 #define ESP_TEST_TS           0x04             /* Tristate test mode */
 611
 612 /* ESP unique ID register read-only, found on fas236+fas100a+fsc only */
 613 #define ESP_UID_F100A         0x00             /* FAS100A  */
 614 #define ESP_UID_F236          0x02             /* FAS236   */
 615 #define ESP_UID_FSC           0xa2             /* NCR53CF9x-2  */
 616 #define ESP_UID_REV           0x07             /* ESP revision */
 617 #define ESP_UID_FAM           0xf8             /* ESP family   */
 618
 619 /* ESP fifo flags register read-only */
 620 /* Note that the following implies a 16 byte FIFO on the ESP. */
 621 #define ESP_FF_FBYTES         0x1f             /* Num bytes in FIFO */
 622 #define ESP_FF_ONOTZERO       0x20             /* offset ctr not zero (esp100,fsc) */
 623 #define ESP_FF_SSTEP          0xe0             /* Sequence step */
 624
 625 /* ESP clock conversion factor register write-only */
 626 #define ESP_CCF_F0            0x00             /* 35.01MHz - 40MHz */
 627 #define ESP_CCF_NEVER         0x01             /* Set it to this and die */
 628 #define ESP_CCF_F2            0x02             /* 10MHz */
 629 #define ESP_CCF_F3            0x03             /* 10.01MHz - 15MHz */
 630 #define ESP_CCF_F4            0x04             /* 15.01MHz - 20MHz */
 631 #define ESP_CCF_F5            0x05             /* 20.01MHz - 25MHz */
 632 #define ESP_CCF_F6            0x06             /* 25.01MHz - 30MHz */
 633 #define ESP_CCF_F7            0x07             /* 30.01MHz - 35MHz */
 634
 635 #define ESP_BUS_TIMEOUT        275             /* In milli-seconds */
 636 #define ESP_TIMEO_CONST       8192
 637 #define FSC_TIMEO_CONST       7668
 638 #define ESP_NEG_DEFP(mhz, cfact) \
 639         ((ESP_BUS_TIMEOUT * ((mhz) / 1000)) / (8192 * (cfact)))
 640 #define FSC_NEG_DEFP(mhz, cfact) \
 641         ((ESP_BUS_TIMEOUT * ((mhz) / 1000)) / (7668 * (cfact)))
 642 #define ESP_MHZ_TO_CYCLE(mhertz)  ((1000000000) / ((mhertz) / 1000))
 643 #define ESP_TICK(ccf, cycle)  ((7682 * (ccf) * (cycle) / 1000))
 644
 645
 646 /* UGLY, UGLY, UGLY! */
 647 extern int nesps, esps_in_use, esps_running;
 648
 649 /* For our interrupt engine. */
 650 #define for_each_esp(esp) \
 651         for((esp) = espchain; (esp); (esp) = (esp)->next)
 652
 653
 654 /* External functions */
 655 extern void esp_bootup_reset(struct NCR_ESP *esp, struct ESP_regs *eregs);
 656 extern struct NCR_ESP *esp_allocate(Scsi_Host_Template *, void *);
 657 extern void esp_deallocate(struct NCR_ESP *);
 658 extern void esp_release(void);
 659 extern void esp_initialize(struct NCR_ESP *);
 660 extern irqreturn_t esp_intr(int, void *, struct pt_regs *);
 661 extern const char *esp_info(struct Scsi_Host *);
 662 extern int esp_queue(Scsi_Cmnd *, void (*done)(Scsi_Cmnd *));
 663 extern int esp_abort(Scsi_Cmnd *);
 664 extern int esp_reset(Scsi_Cmnd *);
 665 extern int esp_proc_info(struct Scsi_Host *shost, char *buffer, char **start, off_t offset, int length,
 666                          int inout);
 667 extern int esp_slave_alloc(Scsi_Device *);
 668 extern void esp_slave_destroy(Scsi_Device *);
 669 #endif /* !(NCR53C9X_H) */