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[TG3]: Set minimal hw interrupt mitigation.
[linux-2.6/verdex.git] / drivers / scsi / qla1280.h
blobd245ae07518e9b4d8e163c1b05b0b573729c3303
1 /******************************************************************************
2 * QLOGIC LINUX SOFTWARE
3 *
4 * QLogic ISP1280 (Ultra2) /12160 (Ultra3) SCSI driver
5 * Copyright (C) 2000 Qlogic Corporation
6 * (www.qlogic.com)
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2, or (at your option) any
11 * later version.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 ******************************************************************************/
19
20 #ifndef _QLA1280_H
21 #define _QLA1280_H
22
23 /*
24 * Data bit definitions.
25 */
26 #define BIT_0 0x1
27 #define BIT_1 0x2
28 #define BIT_2 0x4
29 #define BIT_3 0x8
30 #define BIT_4 0x10
31 #define BIT_5 0x20
32 #define BIT_6 0x40
33 #define BIT_7 0x80
34 #define BIT_8 0x100
35 #define BIT_9 0x200
36 #define BIT_10 0x400
37 #define BIT_11 0x800
38 #define BIT_12 0x1000
39 #define BIT_13 0x2000
40 #define BIT_14 0x4000
41 #define BIT_15 0x8000
42 #define BIT_16 0x10000
43 #define BIT_17 0x20000
44 #define BIT_18 0x40000
45 #define BIT_19 0x80000
46 #define BIT_20 0x100000
47 #define BIT_21 0x200000
48 #define BIT_22 0x400000
49 #define BIT_23 0x800000
50 #define BIT_24 0x1000000
51 #define BIT_25 0x2000000
52 #define BIT_26 0x4000000
53 #define BIT_27 0x8000000
54 #define BIT_28 0x10000000
55 #define BIT_29 0x20000000
56 #define BIT_30 0x40000000
57 #define BIT_31 0x80000000
58
59 #if MEMORY_MAPPED_IO
60 #define RD_REG_WORD(addr) readw_relaxed(addr)
61 #define RD_REG_WORD_dmasync(addr) readw(addr)
62 #define WRT_REG_WORD(addr, data) writew(data, addr)
63 #else /* MEMORY_MAPPED_IO */
64 #define RD_REG_WORD(addr) inw((unsigned long)addr)
65 #define RD_REG_WORD_dmasync(addr) RD_REG_WORD(addr)
66 #define WRT_REG_WORD(addr, data) outw(data, (unsigned long)addr)
67 #endif /* MEMORY_MAPPED_IO */
68
69 /*
70 * Host adapter default definitions.
71 */
72 #define MAX_BUSES 2 /* 2 */
73 #define MAX_B_BITS 1
74
75 #define MAX_TARGETS 16 /* 16 */
76 #define MAX_T_BITS 4 /* 4 */
77
78 #define MAX_LUNS 8 /* 32 */
79 #define MAX_L_BITS 3 /* 5 */
80
81 /*
82 * Watchdog time quantum
83 */
84 #define QLA1280_WDG_TIME_QUANTUM 5 /* In seconds */
85
86 /* Command retry count (0-65535) */
87 #define COMMAND_RETRY_COUNT 255
88
89 /* Maximum outstanding commands in ISP queues */
90 #define MAX_OUTSTANDING_COMMANDS 512
91 #define INVALID_HANDLE (MAX_OUTSTANDING_COMMANDS + 2)
92
93 /* ISP request and response entry counts (37-65535) */
94 #define REQUEST_ENTRY_CNT 256 /* Number of request entries. */
95 #define RESPONSE_ENTRY_CNT 16 /* Number of response entries. */
96
97 /* Number of segments 1 - 65535 */
98 #define SG_SEGMENTS 32 /* Cmd entry + 6 continuations */
99
100 /*
101 * SCSI Request Block structure (sp) that is placed
102 * on cmd->SCp location of every I/O
103 */
104 struct srb {
105 struct list_head list; /* (8/16) LU queue */
106 struct scsi_cmnd *cmd; /* (4/8) SCSI command block */
107 /* NOTE: the sp->cmd will be NULL when this completion is
108 * called, so you should know the scsi_cmnd when using this */
109 struct completion *wait;
110 dma_addr_t saved_dma_handle; /* for unmap of single transfers */
111 uint8_t flags; /* (1) Status flags. */
112 uint8_t dir; /* direction of transfer */
113 };
114
115 /*
116 * SRB flag definitions
117 */
118 #define SRB_TIMEOUT (1 << 0) /* Command timed out */
119 #define SRB_SENT (1 << 1) /* Command sent to ISP */
120 #define SRB_ABORT_PENDING (1 << 2) /* Command abort sent to device */
121 #define SRB_ABORTED (1 << 3) /* Command aborted command already */
122
123 /*
124 * ISP I/O Register Set structure definitions.
125 */
126 struct device_reg {
127 uint16_t id_l; /* ID low */
128 uint16_t id_h; /* ID high */
129 uint16_t cfg_0; /* Configuration 0 */
130 #define ISP_CFG0_HWMSK 0x000f /* Hardware revision mask */
131 #define ISP_CFG0_1020 BIT_0 /* ISP1020 */
132 #define ISP_CFG0_1020A BIT_1 /* ISP1020A */
133 #define ISP_CFG0_1040 BIT_2 /* ISP1040 */
134 #define ISP_CFG0_1040A BIT_3 /* ISP1040A */
135 #define ISP_CFG0_1040B BIT_4 /* ISP1040B */
136 #define ISP_CFG0_1040C BIT_5 /* ISP1040C */
137 uint16_t cfg_1; /* Configuration 1 */
138 #define ISP_CFG1_F128 BIT_6 /* 128-byte FIFO threshold */
139 #define ISP_CFG1_F64 BIT_4|BIT_5 /* 128-byte FIFO threshold */
140 #define ISP_CFG1_F32 BIT_5 /* 128-byte FIFO threshold */
141 #define ISP_CFG1_F16 BIT_4 /* 128-byte FIFO threshold */
142 #define ISP_CFG1_BENAB BIT_2 /* Global Bus burst enable */
143 #define ISP_CFG1_SXP BIT_0 /* SXP register select */
144 uint16_t ictrl; /* Interface control */
145 #define ISP_RESET BIT_0 /* ISP soft reset */
146 #define ISP_EN_INT BIT_1 /* ISP enable interrupts. */
147 #define ISP_EN_RISC BIT_2 /* ISP enable RISC interrupts. */
148 #define ISP_FLASH_ENABLE BIT_8 /* Flash BIOS Read/Write enable */
149 #define ISP_FLASH_UPPER BIT_9 /* Flash upper bank select */
150 uint16_t istatus; /* Interface status */
151 #define PCI_64BIT_SLOT BIT_14 /* PCI 64-bit slot indicator. */
152 #define RISC_INT BIT_2 /* RISC interrupt */
153 #define PCI_INT BIT_1 /* PCI interrupt */
154 uint16_t semaphore; /* Semaphore */
155 uint16_t nvram; /* NVRAM register. */
156 #define NV_DESELECT 0
157 #define NV_CLOCK BIT_0
158 #define NV_SELECT BIT_1
159 #define NV_DATA_OUT BIT_2
160 #define NV_DATA_IN BIT_3
161 uint16_t flash_data; /* Flash BIOS data */
162 uint16_t flash_address; /* Flash BIOS address */
163
164 uint16_t unused_1[0x06];
165
166 /* cdma_* and ddma_* are 1040 only */
167 uint16_t cdma_cfg;
168 #define CDMA_CONF_SENAB BIT_3 /* SXP to DMA Data enable */
169 #define CDMA_CONF_RIRQ BIT_2 /* RISC interrupt enable */
170 #define CDMA_CONF_BENAB BIT_1 /* Bus burst enable */
171 #define CDMA_CONF_DIR BIT_0 /* DMA direction (0=fifo->host 1=host->fifo) */
172 uint16_t cdma_ctrl;
173 uint16_t cdma_status;
174 uint16_t cdma_fifo_status;
175 uint16_t cdma_count;
176 uint16_t cdma_reserved;
177 uint16_t cdma_address_count_0;
178 uint16_t cdma_address_count_1;
179 uint16_t cdma_address_count_2;
180 uint16_t cdma_address_count_3;
181
182 uint16_t unused_2[0x06];
183
184 uint16_t ddma_cfg;
185 #define DDMA_CONF_SENAB BIT_3 /* SXP to DMA Data enable */
186 #define DDMA_CONF_RIRQ BIT_2 /* RISC interrupt enable */
187 #define DDMA_CONF_BENAB BIT_1 /* Bus burst enable */
188 #define DDMA_CONF_DIR BIT_0 /* DMA direction (0=fifo->host 1=host->fifo) */
189 uint16_t ddma_ctrl;
190 uint16_t ddma_status;
191 uint16_t ddma_fifo_status;
192 uint16_t ddma_xfer_count_low;
193 uint16_t ddma_xfer_count_high;
194 uint16_t ddma_addr_count_0;
195 uint16_t ddma_addr_count_1;
196 uint16_t ddma_addr_count_2;
197 uint16_t ddma_addr_count_3;
198
199 uint16_t unused_3[0x0e];
200
201 uint16_t mailbox0; /* Mailbox 0 */
202 uint16_t mailbox1; /* Mailbox 1 */
203 uint16_t mailbox2; /* Mailbox 2 */
204 uint16_t mailbox3; /* Mailbox 3 */
205 uint16_t mailbox4; /* Mailbox 4 */
206 uint16_t mailbox5; /* Mailbox 5 */
207 uint16_t mailbox6; /* Mailbox 6 */
208 uint16_t mailbox7; /* Mailbox 7 */
209
210 uint16_t unused_4[0x20];/* 0x80-0xbf Gap */
211
212 uint16_t host_cmd; /* Host command and control */
213 #define HOST_INT BIT_7 /* host interrupt bit */
214 #define BIOS_ENABLE BIT_0
215
216 uint16_t unused_5[0x5]; /* 0xc2-0xcb Gap */
217
218 uint16_t gpio_data;
219 uint16_t gpio_enable;
220
221 uint16_t unused_6[0x11]; /* d0-f0 */
222 uint16_t scsiControlPins; /* f2 */
223 };
224
225 #define MAILBOX_REGISTER_COUNT 8
226
227 /*
228 * ISP product identification definitions in mailboxes after reset.
229 */
230 #define PROD_ID_1 0x4953
231 #define PROD_ID_2 0x0000
232 #define PROD_ID_2a 0x5020
233 #define PROD_ID_3 0x2020
234 #define PROD_ID_4 0x1
235
236 /*
237 * ISP host command and control register command definitions
238 */
239 #define HC_RESET_RISC 0x1000 /* Reset RISC */
240 #define HC_PAUSE_RISC 0x2000 /* Pause RISC */
241 #define HC_RELEASE_RISC 0x3000 /* Release RISC from reset. */
242 #define HC_SET_HOST_INT 0x5000 /* Set host interrupt */
243 #define HC_CLR_HOST_INT 0x6000 /* Clear HOST interrupt */
244 #define HC_CLR_RISC_INT 0x7000 /* Clear RISC interrupt */
245 #define HC_DISABLE_BIOS 0x9000 /* Disable BIOS. */
246
247 /*
248 * ISP mailbox Self-Test status codes
249 */
250 #define MBS_FRM_ALIVE 0 /* Firmware Alive. */
251 #define MBS_CHKSUM_ERR 1 /* Checksum Error. */
252 #define MBS_SHADOW_LD_ERR 2 /* Shadow Load Error. */
253 #define MBS_BUSY 4 /* Busy. */
254
255 /*
256 * ISP mailbox command complete status codes
257 */
258 #define MBS_CMD_CMP 0x4000 /* Command Complete. */
259 #define MBS_INV_CMD 0x4001 /* Invalid Command. */
260 #define MBS_HOST_INF_ERR 0x4002 /* Host Interface Error. */
261 #define MBS_TEST_FAILED 0x4003 /* Test Failed. */
262 #define MBS_CMD_ERR 0x4005 /* Command Error. */
263 #define MBS_CMD_PARAM_ERR 0x4006 /* Command Parameter Error. */
264
265 /*
266 * ISP mailbox asynchronous event status codes
267 */
268 #define MBA_ASYNC_EVENT 0x8000 /* Asynchronous event. */
269 #define MBA_BUS_RESET 0x8001 /* SCSI Bus Reset. */
270 #define MBA_SYSTEM_ERR 0x8002 /* System Error. */
271 #define MBA_REQ_TRANSFER_ERR 0x8003 /* Request Transfer Error. */
272 #define MBA_RSP_TRANSFER_ERR 0x8004 /* Response Transfer Error. */
273 #define MBA_WAKEUP_THRES 0x8005 /* Request Queue Wake-up. */
274 #define MBA_TIMEOUT_RESET 0x8006 /* Execution Timeout Reset. */
275 #define MBA_DEVICE_RESET 0x8007 /* Bus Device Reset. */
276 #define MBA_BUS_MODE_CHANGE 0x800E /* SCSI bus mode transition. */
277 #define MBA_SCSI_COMPLETION 0x8020 /* Completion response. */
278
279 /*
280 * ISP mailbox commands
281 */
282 #define MBC_NOP 0 /* No Operation */
283 #define MBC_LOAD_RAM 1 /* Load RAM */
284 #define MBC_EXECUTE_FIRMWARE 2 /* Execute firmware */
285 #define MBC_DUMP_RAM 3 /* Dump RAM contents */
286 #define MBC_WRITE_RAM_WORD 4 /* Write ram word */
287 #define MBC_READ_RAM_WORD 5 /* Read ram word */
288 #define MBC_MAILBOX_REGISTER_TEST 6 /* Wrap incoming mailboxes */
289 #define MBC_VERIFY_CHECKSUM 7 /* Verify checksum */
290 #define MBC_ABOUT_FIRMWARE 8 /* Get firmware revision */
291 #define MBC_INIT_REQUEST_QUEUE 0x10 /* Initialize request queue */
292 #define MBC_INIT_RESPONSE_QUEUE 0x11 /* Initialize response queue */
293 #define MBC_EXECUTE_IOCB 0x12 /* Execute IOCB command */
294 #define MBC_ABORT_COMMAND 0x15 /* Abort IOCB command */
295 #define MBC_ABORT_DEVICE 0x16 /* Abort device (ID/LUN) */
296 #define MBC_ABORT_TARGET 0x17 /* Abort target (ID) */
297 #define MBC_BUS_RESET 0x18 /* SCSI bus reset */
298 #define MBC_GET_RETRY_COUNT 0x22 /* Get retry count and delay */
299 #define MBC_GET_TARGET_PARAMETERS 0x28 /* Get target parameters */
300 #define MBC_SET_INITIATOR_ID 0x30 /* Set initiator SCSI ID */
301 #define MBC_SET_SELECTION_TIMEOUT 0x31 /* Set selection timeout */
302 #define MBC_SET_RETRY_COUNT 0x32 /* Set retry count and delay */
303 #define MBC_SET_TAG_AGE_LIMIT 0x33 /* Set tag age limit */
304 #define MBC_SET_CLOCK_RATE 0x34 /* Set clock rate */
305 #define MBC_SET_ACTIVE_NEGATION 0x35 /* Set active negation state */
306 #define MBC_SET_ASYNC_DATA_SETUP 0x36 /* Set async data setup time */
307 #define MBC_SET_PCI_CONTROL 0x37 /* Set BUS control parameters */
308 #define MBC_SET_TARGET_PARAMETERS 0x38 /* Set target parameters */
309 #define MBC_SET_DEVICE_QUEUE 0x39 /* Set device queue parameters */
310 #define MBC_SET_RESET_DELAY_PARAMETERS 0x3A /* Set reset delay parameters */
311 #define MBC_SET_SYSTEM_PARAMETER 0x45 /* Set system parameter word */
312 #define MBC_SET_FIRMWARE_FEATURES 0x4A /* Set firmware feature word */
313 #define MBC_INIT_REQUEST_QUEUE_A64 0x52 /* Initialize request queue A64 */
314 #define MBC_INIT_RESPONSE_QUEUE_A64 0x53 /* Initialize response q A64 */
315 #define MBC_ENABLE_TARGET_MODE 0x55 /* Enable target mode */
316 #define MBC_SET_DATA_OVERRUN_RECOVERY 0x5A /* Set data overrun recovery mode */
317
318 /*
319 * ISP Get/Set Target Parameters mailbox command control flags.
320 */
321 #define TP_PPR BIT_5 /* PPR */
322 #define TP_RENEGOTIATE BIT_8 /* Renegotiate on error. */
323 #define TP_STOP_QUEUE BIT_9 /* Stop que on check condition */
324 #define TP_AUTO_REQUEST_SENSE BIT_10 /* Automatic request sense. */
325 #define TP_TAGGED_QUEUE BIT_11 /* Tagged queuing. */
326 #define TP_SYNC BIT_12 /* Synchronous data transfers. */
327 #define TP_WIDE BIT_13 /* Wide data transfers. */
328 #define TP_PARITY BIT_14 /* Parity checking. */
329 #define TP_DISCONNECT BIT_15 /* Disconnect privilege. */
330
331 /*
332 * NVRAM Command values.
333 */
334 #define NV_START_BIT BIT_2
335 #define NV_WRITE_OP (BIT_26 | BIT_24)
336 #define NV_READ_OP (BIT_26 | BIT_25)
337 #define NV_ERASE_OP (BIT_26 | BIT_25 | BIT_24)
338 #define NV_MASK_OP (BIT_26 | BIT_25 | BIT_24)
339 #define NV_DELAY_COUNT 10
340
341 /*
342 * QLogic ISP1280/ISP12160 NVRAM structure definition.
343 */
344 struct nvram {
345 uint8_t id0; /* 0 */
346 uint8_t id1; /* 1 */
347 uint8_t id2; /* 2 */
348 uint8_t id3; /* 3 */
349 uint8_t version; /* 4 */
350
351 struct {
352 uint8_t bios_configuration_mode:2;
353 uint8_t bios_disable:1;
354 uint8_t selectable_scsi_boot_enable:1;
355 uint8_t cd_rom_boot_enable:1;
356 uint8_t disable_loading_risc_code:1;
357 uint8_t enable_64bit_addressing:1;
358 uint8_t unused_7:1;
359 } cntr_flags_1; /* 5 */
360
361 struct {
362 uint8_t boot_lun_number:5;
363 uint8_t scsi_bus_number:1;
364 uint8_t unused_6:1;
365 uint8_t unused_7:1;
366 } cntr_flags_2l; /* 7 */
367
368 struct {
369 uint8_t boot_target_number:4;
370 uint8_t unused_12:1;
371 uint8_t unused_13:1;
372 uint8_t unused_14:1;
373 uint8_t unused_15:1;
374 } cntr_flags_2h; /* 8 */
375
376 uint16_t unused_8; /* 8, 9 */
377 uint16_t unused_10; /* 10, 11 */
378 uint16_t unused_12; /* 12, 13 */
379 uint16_t unused_14; /* 14, 15 */
380
381 union {
382 uint8_t c;
383 struct {
384 uint8_t reserved:2;
385 uint8_t burst_enable:1;
386 uint8_t reserved_1:1;
387 uint8_t fifo_threshold:4;
388 } f;
389 } isp_config; /* 16 */
390
391 /* Termination
392 * 0 = Disable, 1 = high only, 3 = Auto term
393 */
394 union {
395 uint8_t c;
396 struct {
397 uint8_t scsi_bus_1_control:2;
398 uint8_t scsi_bus_0_control:2;
399 uint8_t unused_0:1;
400 uint8_t unused_1:1;
401 uint8_t unused_2:1;
402 uint8_t auto_term_support:1;
403 } f;
404 } termination; /* 17 */
405
406 uint16_t isp_parameter; /* 18, 19 */
407
408 union {
409 uint16_t w;
410 struct {
411 uint16_t enable_fast_posting:1;
412 uint16_t report_lvd_bus_transition:1;
413 uint16_t unused_2:1;
414 uint16_t unused_3:1;
415 uint16_t disable_iosbs_with_bus_reset_status:1;
416 uint16_t disable_synchronous_backoff:1;
417 uint16_t unused_6:1;
418 uint16_t synchronous_backoff_reporting:1;
419 uint16_t disable_reselection_fairness:1;
420 uint16_t unused_9:1;
421 uint16_t unused_10:1;
422 uint16_t unused_11:1;
423 uint16_t unused_12:1;
424 uint16_t unused_13:1;
425 uint16_t unused_14:1;
426 uint16_t unused_15:1;
427 } f;
428 } firmware_feature; /* 20, 21 */
429
430 uint16_t unused_22; /* 22, 23 */
431
432 struct {
433 struct {
434 uint8_t initiator_id:4;
435 uint8_t scsi_reset_disable:1;
436 uint8_t scsi_bus_size:1;
437 uint8_t scsi_bus_type:1;
438 uint8_t unused_7:1;
439 } config_1; /* 24 */
440
441 uint8_t bus_reset_delay; /* 25 */
442 uint8_t retry_count; /* 26 */
443 uint8_t retry_delay; /* 27 */
444
445 struct {
446 uint8_t async_data_setup_time:4;
447 uint8_t req_ack_active_negation:1;
448 uint8_t data_line_active_negation:1;
449 uint8_t unused_6:1;
450 uint8_t unused_7:1;
451 } config_2; /* 28 */
452
453 uint8_t unused_29; /* 29 */
454
455 uint16_t selection_timeout; /* 30, 31 */
456 uint16_t max_queue_depth; /* 32, 33 */
457
458 uint16_t unused_34; /* 34, 35 */
459 uint16_t unused_36; /* 36, 37 */
460 uint16_t unused_38; /* 38, 39 */
461
462 struct {
463 union {
464 uint8_t c;
465 struct {
466 uint8_t renegotiate_on_error:1;
467 uint8_t stop_queue_on_check:1;
468 uint8_t auto_request_sense:1;
469 uint8_t tag_queuing:1;
470 uint8_t enable_sync:1;
471 uint8_t enable_wide:1;
472 uint8_t parity_checking:1;
473 uint8_t disconnect_allowed:1;
474 } f;
475 } parameter; /* 40 */
476
477 uint8_t execution_throttle; /* 41 */
478 uint8_t sync_period; /* 42 */
479
480 union { /* 43 */
481 uint8_t flags_43;
482 struct {
483 uint8_t sync_offset:4;
484 uint8_t device_enable:1;
485 uint8_t lun_disable:1;
486 uint8_t unused_6:1;
487 uint8_t unused_7:1;
488 } flags1x80;
489 struct {
490 uint8_t sync_offset:5;
491 uint8_t device_enable:1;
492 uint8_t unused_6:1;
493 uint8_t unused_7:1;
494 } flags1x160;
495 } flags;
496 union { /* PPR flags for the 1x160 controllers */
497 uint8_t unused_44;
498 struct {
499 uint8_t ppr_options:4;
500 uint8_t ppr_bus_width:2;
501 uint8_t unused_8:1;
502 uint8_t enable_ppr:1;
503 } flags; /* 44 */
504 } ppr_1x160;
505 uint8_t unused_45; /* 45 */
506 } target[MAX_TARGETS];
507 } bus[MAX_BUSES];
508
509 uint16_t unused_248; /* 248, 249 */
510
511 uint16_t subsystem_id[2]; /* 250, 251, 252, 253 */
512
513 union { /* 254 */
514 uint8_t unused_254;
515 uint8_t system_id_pointer;
516 } sysid_1x160;
517
518 uint8_t chksum; /* 255 */
519 };
520
521 /*
522 * ISP queue - command entry structure definition.
523 */
524 #define MAX_CMDSZ 12 /* SCSI maximum CDB size. */
525 struct cmd_entry {
526 uint8_t entry_type; /* Entry type. */
527 #define COMMAND_TYPE 1 /* Command entry */
528 uint8_t entry_count; /* Entry count. */
529 uint8_t sys_define; /* System defined. */
530 uint8_t entry_status; /* Entry Status. */
531 uint32_t handle; /* System handle. */
532 uint8_t lun; /* SCSI LUN */
533 uint8_t target; /* SCSI ID */
534 uint16_t cdb_len; /* SCSI command length. */
535 uint16_t control_flags; /* Control flags. */
536 uint16_t reserved;
537 uint16_t timeout; /* Command timeout. */
538 uint16_t dseg_count; /* Data segment count. */
539 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */
540 uint32_t dseg_0_address; /* Data segment 0 address. */
541 uint32_t dseg_0_length; /* Data segment 0 length. */
542 uint32_t dseg_1_address; /* Data segment 1 address. */
543 uint32_t dseg_1_length; /* Data segment 1 length. */
544 uint32_t dseg_2_address; /* Data segment 2 address. */
545 uint32_t dseg_2_length; /* Data segment 2 length. */
546 uint32_t dseg_3_address; /* Data segment 3 address. */
547 uint32_t dseg_3_length; /* Data segment 3 length. */
548 };
549
550 /*
551 * ISP queue - continuation entry structure definition.
552 */
553 struct cont_entry {
554 uint8_t entry_type; /* Entry type. */
555 #define CONTINUE_TYPE 2 /* Continuation entry. */
556 uint8_t entry_count; /* Entry count. */
557 uint8_t sys_define; /* System defined. */
558 uint8_t entry_status; /* Entry Status. */
559 uint32_t reserved; /* Reserved */
560 uint32_t dseg_0_address; /* Data segment 0 address. */
561 uint32_t dseg_0_length; /* Data segment 0 length. */
562 uint32_t dseg_1_address; /* Data segment 1 address. */
563 uint32_t dseg_1_length; /* Data segment 1 length. */
564 uint32_t dseg_2_address; /* Data segment 2 address. */
565 uint32_t dseg_2_length; /* Data segment 2 length. */
566 uint32_t dseg_3_address; /* Data segment 3 address. */
567 uint32_t dseg_3_length; /* Data segment 3 length. */
568 uint32_t dseg_4_address; /* Data segment 4 address. */
569 uint32_t dseg_4_length; /* Data segment 4 length. */
570 uint32_t dseg_5_address; /* Data segment 5 address. */
571 uint32_t dseg_5_length; /* Data segment 5 length. */
572 uint32_t dseg_6_address; /* Data segment 6 address. */
573 uint32_t dseg_6_length; /* Data segment 6 length. */
574 };
575
576 /*
577 * ISP queue - status entry structure definition.
578 */
579 struct response {
580 uint8_t entry_type; /* Entry type. */
581 #define STATUS_TYPE 3 /* Status entry. */
582 uint8_t entry_count; /* Entry count. */
583 uint8_t sys_define; /* System defined. */
584 uint8_t entry_status; /* Entry Status. */
585 #define RF_CONT BIT_0 /* Continuation. */
586 #define RF_FULL BIT_1 /* Full */
587 #define RF_BAD_HEADER BIT_2 /* Bad header. */
588 #define RF_BAD_PAYLOAD BIT_3 /* Bad payload. */
589 uint32_t handle; /* System handle. */
590 uint16_t scsi_status; /* SCSI status. */
591 uint16_t comp_status; /* Completion status. */
592 uint16_t state_flags; /* State flags. */
593 #define SF_TRANSFER_CMPL BIT_14 /* Transfer Complete. */
594 #define SF_GOT_SENSE BIT_13 /* Got Sense */
595 #define SF_GOT_STATUS BIT_12 /* Got Status */
596 #define SF_TRANSFERRED_DATA BIT_11 /* Transferred data */
597 #define SF_SENT_CDB BIT_10 /* Send CDB */
598 #define SF_GOT_TARGET BIT_9 /* */
599 #define SF_GOT_BUS BIT_8 /* */
600 uint16_t status_flags; /* Status flags. */
601 uint16_t time; /* Time. */
602 uint16_t req_sense_length; /* Request sense data length. */
603 uint32_t residual_length; /* Residual transfer length. */
604 uint16_t reserved[4];
605 uint8_t req_sense_data[32]; /* Request sense data. */
606 };
607
608 /*
609 * ISP queue - marker entry structure definition.
610 */
611 struct mrk_entry {
612 uint8_t entry_type; /* Entry type. */
613 #define MARKER_TYPE 4 /* Marker entry. */
614 uint8_t entry_count; /* Entry count. */
615 uint8_t sys_define; /* System defined. */
616 uint8_t entry_status; /* Entry Status. */
617 uint32_t reserved;
618 uint8_t lun; /* SCSI LUN */
619 uint8_t target; /* SCSI ID */
620 uint8_t modifier; /* Modifier (7-0). */
621 #define MK_SYNC_ID_LUN 0 /* Synchronize ID/LUN */
622 #define MK_SYNC_ID 1 /* Synchronize ID */
623 #define MK_SYNC_ALL 2 /* Synchronize all ID/LUN */
624 uint8_t reserved_1[53];
625 };
626
627 /*
628 * ISP queue - extended command entry structure definition.
629 *
630 * Unused by the driver!
631 */
632 struct ecmd_entry {
633 uint8_t entry_type; /* Entry type. */
634 #define EXTENDED_CMD_TYPE 5 /* Extended command entry. */
635 uint8_t entry_count; /* Entry count. */
636 uint8_t sys_define; /* System defined. */
637 uint8_t entry_status; /* Entry Status. */
638 uint32_t handle; /* System handle. */
639 uint8_t lun; /* SCSI LUN */
640 uint8_t target; /* SCSI ID */
641 uint16_t cdb_len; /* SCSI command length. */
642 uint16_t control_flags; /* Control flags. */
643 uint16_t reserved;
644 uint16_t timeout; /* Command timeout. */
645 uint16_t dseg_count; /* Data segment count. */
646 uint8_t scsi_cdb[88]; /* SCSI command words. */
647 };
648
649 /*
650 * ISP queue - 64-Bit addressing, command entry structure definition.
651 */
652 typedef struct {
653 uint8_t entry_type; /* Entry type. */
654 #define COMMAND_A64_TYPE 9 /* Command A64 entry */
655 uint8_t entry_count; /* Entry count. */
656 uint8_t sys_define; /* System defined. */
657 uint8_t entry_status; /* Entry Status. */
658 uint32_t handle; /* System handle. */
659 uint8_t lun; /* SCSI LUN */
660 uint8_t target; /* SCSI ID */
661 uint16_t cdb_len; /* SCSI command length. */
662 uint16_t control_flags; /* Control flags. */
663 uint16_t reserved;
664 uint16_t timeout; /* Command timeout. */
665 uint16_t dseg_count; /* Data segment count. */
666 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */
667 uint32_t reserved_1[2]; /* unused */
668 uint32_t dseg_0_address[2]; /* Data segment 0 address. */
669 uint32_t dseg_0_length; /* Data segment 0 length. */
670 uint32_t dseg_1_address[2]; /* Data segment 1 address. */
671 uint32_t dseg_1_length; /* Data segment 1 length. */
672 } cmd_a64_entry_t, request_t;
673
674 /*
675 * ISP queue - 64-Bit addressing, continuation entry structure definition.
676 */
677 struct cont_a64_entry {
678 uint8_t entry_type; /* Entry type. */
679 #define CONTINUE_A64_TYPE 0xA /* Continuation A64 entry. */
680 uint8_t entry_count; /* Entry count. */
681 uint8_t sys_define; /* System defined. */
682 uint8_t entry_status; /* Entry Status. */
683 uint32_t dseg_0_address[2]; /* Data segment 0 address. */
684 uint32_t dseg_0_length; /* Data segment 0 length. */
685 uint32_t dseg_1_address[2]; /* Data segment 1 address. */
686 uint32_t dseg_1_length; /* Data segment 1 length. */
687 uint32_t dseg_2_address[2]; /* Data segment 2 address. */
688 uint32_t dseg_2_length; /* Data segment 2 length. */
689 uint32_t dseg_3_address[2]; /* Data segment 3 address. */
690 uint32_t dseg_3_length; /* Data segment 3 length. */
691 uint32_t dseg_4_address[2]; /* Data segment 4 address. */
692 uint32_t dseg_4_length; /* Data segment 4 length. */
693 };
694
695 /*
696 * ISP queue - enable LUN entry structure definition.
697 */
698 struct elun_entry {
699 uint8_t entry_type; /* Entry type. */
700 #define ENABLE_LUN_TYPE 0xB /* Enable LUN entry. */
701 uint8_t entry_count; /* Entry count. */
702 uint8_t reserved_1;
703 uint8_t entry_status; /* Entry Status not used. */
704 uint32_t reserved_2;
705 uint16_t lun; /* Bit 15 is bus number. */
706 uint16_t reserved_4;
707 uint32_t option_flags;
708 uint8_t status;
709 uint8_t reserved_5;
710 uint8_t command_count; /* Number of ATIOs allocated. */
711 uint8_t immed_notify_count; /* Number of Immediate Notify */
712 /* entries allocated. */
713 uint8_t group_6_length; /* SCSI CDB length for group 6 */
714 /* commands (2-26). */
715 uint8_t group_7_length; /* SCSI CDB length for group 7 */
716 /* commands (2-26). */
717 uint16_t timeout; /* 0 = 30 seconds, 0xFFFF = disable */
718 uint16_t reserved_6[20];
719 };
720
721 /*
722 * ISP queue - modify LUN entry structure definition.
723 *
724 * Unused by the driver!
725 */
726 struct modify_lun_entry {
727 uint8_t entry_type; /* Entry type. */
728 #define MODIFY_LUN_TYPE 0xC /* Modify LUN entry. */
729 uint8_t entry_count; /* Entry count. */
730 uint8_t reserved_1;
731 uint8_t entry_status; /* Entry Status. */
732 uint32_t reserved_2;
733 uint8_t lun; /* SCSI LUN */
734 uint8_t reserved_3;
735 uint8_t operators;
736 uint8_t reserved_4;
737 uint32_t option_flags;
738 uint8_t status;
739 uint8_t reserved_5;
740 uint8_t command_count; /* Number of ATIOs allocated. */
741 uint8_t immed_notify_count; /* Number of Immediate Notify */
742 /* entries allocated. */
743 uint16_t reserved_6;
744 uint16_t timeout; /* 0 = 30 seconds, 0xFFFF = disable */
745 uint16_t reserved_7[20];
746 };
747
748 /*
749 * ISP queue - immediate notify entry structure definition.
750 */
751 struct notify_entry {
752 uint8_t entry_type; /* Entry type. */
753 #define IMMED_NOTIFY_TYPE 0xD /* Immediate notify entry. */
754 uint8_t entry_count; /* Entry count. */
755 uint8_t reserved_1;
756 uint8_t entry_status; /* Entry Status. */
757 uint32_t reserved_2;
758 uint8_t lun;
759 uint8_t initiator_id;
760 uint8_t reserved_3;
761 uint8_t target_id;
762 uint32_t option_flags;
763 uint8_t status;
764 uint8_t reserved_4;
765 uint8_t tag_value; /* Received queue tag message value */
766 uint8_t tag_type; /* Received queue tag message type */
767 /* entries allocated. */
768 uint16_t seq_id;
769 uint8_t scsi_msg[8]; /* SCSI message not handled by ISP */
770 uint16_t reserved_5[8];
771 uint8_t sense_data[18];
772 };
773
774 /*
775 * ISP queue - notify acknowledge entry structure definition.
776 */
777 struct nack_entry {
778 uint8_t entry_type; /* Entry type. */
779 #define NOTIFY_ACK_TYPE 0xE /* Notify acknowledge entry. */
780 uint8_t entry_count; /* Entry count. */
781 uint8_t reserved_1;
782 uint8_t entry_status; /* Entry Status. */
783 uint32_t reserved_2;
784 uint8_t lun;
785 uint8_t initiator_id;
786 uint8_t reserved_3;
787 uint8_t target_id;
788 uint32_t option_flags;
789 uint8_t status;
790 uint8_t event;
791 uint16_t seq_id;
792 uint16_t reserved_4[22];
793 };
794
795 /*
796 * ISP queue - Accept Target I/O (ATIO) entry structure definition.
797 */
798 struct atio_entry {
799 uint8_t entry_type; /* Entry type. */
800 #define ACCEPT_TGT_IO_TYPE 6 /* Accept target I/O entry. */
801 uint8_t entry_count; /* Entry count. */
802 uint8_t reserved_1;
803 uint8_t entry_status; /* Entry Status. */
804 uint32_t reserved_2;
805 uint8_t lun;
806 uint8_t initiator_id;
807 uint8_t cdb_len;
808 uint8_t target_id;
809 uint32_t option_flags;
810 uint8_t status;
811 uint8_t scsi_status;
812 uint8_t tag_value; /* Received queue tag message value */
813 uint8_t tag_type; /* Received queue tag message type */
814 uint8_t cdb[26];
815 uint8_t sense_data[18];
816 };
817
818 /*
819 * ISP queue - Continue Target I/O (CTIO) entry structure definition.
820 */
821 struct ctio_entry {
822 uint8_t entry_type; /* Entry type. */
823 #define CONTINUE_TGT_IO_TYPE 7 /* CTIO entry */
824 uint8_t entry_count; /* Entry count. */
825 uint8_t reserved_1;
826 uint8_t entry_status; /* Entry Status. */
827 uint32_t reserved_2;
828 uint8_t lun; /* SCSI LUN */
829 uint8_t initiator_id;
830 uint8_t reserved_3;
831 uint8_t target_id;
832 uint32_t option_flags;
833 uint8_t status;
834 uint8_t scsi_status;
835 uint8_t tag_value; /* Received queue tag message value */
836 uint8_t tag_type; /* Received queue tag message type */
837 uint32_t transfer_length;
838 uint32_t residual;
839 uint16_t timeout; /* 0 = 30 seconds, 0xFFFF = disable */
840 uint16_t dseg_count; /* Data segment count. */
841 uint32_t dseg_0_address; /* Data segment 0 address. */
842 uint32_t dseg_0_length; /* Data segment 0 length. */
843 uint32_t dseg_1_address; /* Data segment 1 address. */
844 uint32_t dseg_1_length; /* Data segment 1 length. */
845 uint32_t dseg_2_address; /* Data segment 2 address. */
846 uint32_t dseg_2_length; /* Data segment 2 length. */
847 uint32_t dseg_3_address; /* Data segment 3 address. */
848 uint32_t dseg_3_length; /* Data segment 3 length. */
849 };
850
851 /*
852 * ISP queue - CTIO returned entry structure definition.
853 */
854 struct ctio_ret_entry {
855 uint8_t entry_type; /* Entry type. */
856 #define CTIO_RET_TYPE 7 /* CTIO return entry */
857 uint8_t entry_count; /* Entry count. */
858 uint8_t reserved_1;
859 uint8_t entry_status; /* Entry Status. */
860 uint32_t reserved_2;
861 uint8_t lun; /* SCSI LUN */
862 uint8_t initiator_id;
863 uint8_t reserved_3;
864 uint8_t target_id;
865 uint32_t option_flags;
866 uint8_t status;
867 uint8_t scsi_status;
868 uint8_t tag_value; /* Received queue tag message value */
869 uint8_t tag_type; /* Received queue tag message type */
870 uint32_t transfer_length;
871 uint32_t residual;
872 uint16_t timeout; /* 0 = 30 seconds, 0xFFFF = disable */
873 uint16_t dseg_count; /* Data segment count. */
874 uint32_t dseg_0_address; /* Data segment 0 address. */
875 uint32_t dseg_0_length; /* Data segment 0 length. */
876 uint32_t dseg_1_address; /* Data segment 1 address. */
877 uint16_t dseg_1_length; /* Data segment 1 length. */
878 uint8_t sense_data[18];
879 };
880
881 /*
882 * ISP queue - CTIO A64 entry structure definition.
883 */
884 struct ctio_a64_entry {
885 uint8_t entry_type; /* Entry type. */
886 #define CTIO_A64_TYPE 0xF /* CTIO A64 entry */
887 uint8_t entry_count; /* Entry count. */
888 uint8_t reserved_1;
889 uint8_t entry_status; /* Entry Status. */
890 uint32_t reserved_2;
891 uint8_t lun; /* SCSI LUN */
892 uint8_t initiator_id;
893 uint8_t reserved_3;
894 uint8_t target_id;
895 uint32_t option_flags;
896 uint8_t status;
897 uint8_t scsi_status;
898 uint8_t tag_value; /* Received queue tag message value */
899 uint8_t tag_type; /* Received queue tag message type */
900 uint32_t transfer_length;
901 uint32_t residual;
902 uint16_t timeout; /* 0 = 30 seconds, 0xFFFF = disable */
903 uint16_t dseg_count; /* Data segment count. */
904 uint32_t reserved_4[2];
905 uint32_t dseg_0_address[2]; /* Data segment 0 address. */
906 uint32_t dseg_0_length; /* Data segment 0 length. */
907 uint32_t dseg_1_address[2]; /* Data segment 1 address. */
908 uint32_t dseg_1_length; /* Data segment 1 length. */
909 };
910
911 /*
912 * ISP queue - CTIO returned entry structure definition.
913 */
914 struct ctio_a64_ret_entry {
915 uint8_t entry_type; /* Entry type. */
916 #define CTIO_A64_RET_TYPE 0xF /* CTIO A64 returned entry */
917 uint8_t entry_count; /* Entry count. */
918 uint8_t reserved_1;
919 uint8_t entry_status; /* Entry Status. */
920 uint32_t reserved_2;
921 uint8_t lun; /* SCSI LUN */
922 uint8_t initiator_id;
923 uint8_t reserved_3;
924 uint8_t target_id;
925 uint32_t option_flags;
926 uint8_t status;
927 uint8_t scsi_status;
928 uint8_t tag_value; /* Received queue tag message value */
929 uint8_t tag_type; /* Received queue tag message type */
930 uint32_t transfer_length;
931 uint32_t residual;
932 uint16_t timeout; /* 0 = 30 seconds, 0xFFFF = disable */
933 uint16_t dseg_count; /* Data segment count. */
934 uint16_t reserved_4[7];
935 uint8_t sense_data[18];
936 };
937
938 /*
939 * ISP request and response queue entry sizes
940 */
941 #define RESPONSE_ENTRY_SIZE (sizeof(struct response))
942 #define REQUEST_ENTRY_SIZE (sizeof(request_t))
943
944 /*
945 * ISP status entry - completion status definitions.
946 */
947 #define CS_COMPLETE 0x0 /* No errors */
948 #define CS_INCOMPLETE 0x1 /* Incomplete transfer of cmd. */
949 #define CS_DMA 0x2 /* A DMA direction error. */
950 #define CS_TRANSPORT 0x3 /* Transport error. */
951 #define CS_RESET 0x4 /* SCSI bus reset occurred */
952 #define CS_ABORTED 0x5 /* System aborted command. */
953 #define CS_TIMEOUT 0x6 /* Timeout error. */
954 #define CS_DATA_OVERRUN 0x7 /* Data overrun. */
955 #define CS_COMMAND_OVERRUN 0x8 /* Command Overrun. */
956 #define CS_STATUS_OVERRUN 0x9 /* Status Overrun. */
957 #define CS_BAD_MSG 0xA /* Bad msg after status phase. */
958 #define CS_NO_MSG_OUT 0xB /* No msg out after selection. */
959 #define CS_EXTENDED_ID 0xC /* Extended ID failed. */
960 #define CS_IDE_MSG 0xD /* Target rejected IDE msg. */
961 #define CS_ABORT_MSG 0xE /* Target rejected abort msg. */
962 #define CS_REJECT_MSG 0xF /* Target rejected reject msg. */
963 #define CS_NOP_MSG 0x10 /* Target rejected NOP msg. */
964 #define CS_PARITY_MSG 0x11 /* Target rejected parity msg. */
965 #define CS_DEV_RESET_MSG 0x12 /* Target rejected dev rst msg. */
966 #define CS_ID_MSG 0x13 /* Target rejected ID msg. */
967 #define CS_FREE 0x14 /* Unexpected bus free. */
968 #define CS_DATA_UNDERRUN 0x15 /* Data Underrun. */
969 #define CS_TRANACTION_1 0x18 /* Transaction error 1 */
970 #define CS_TRANACTION_2 0x19 /* Transaction error 2 */
971 #define CS_TRANACTION_3 0x1a /* Transaction error 3 */
972 #define CS_INV_ENTRY_TYPE 0x1b /* Invalid entry type */
973 #define CS_DEV_QUEUE_FULL 0x1c /* Device queue full */
974 #define CS_PHASED_SKIPPED 0x1d /* SCSI phase skipped */
975 #define CS_ARS_FAILED 0x1e /* ARS failed */
976 #define CS_LVD_BUS_ERROR 0x21 /* LVD bus error */
977 #define CS_BAD_PAYLOAD 0x80 /* Driver defined */
978 #define CS_UNKNOWN 0x81 /* Driver defined */
979 #define CS_RETRY 0x82 /* Driver defined */
980
981 /*
982 * ISP status entry - SCSI status byte bit definitions.
983 */
984 #define SS_CHECK_CONDITION BIT_1
985 #define SS_CONDITION_MET BIT_2
986 #define SS_BUSY_CONDITION BIT_3
987 #define SS_RESERVE_CONFLICT (BIT_4 | BIT_3)
988
989 /*
990 * ISP target entries - Option flags bit definitions.
991 */
992 #define OF_ENABLE_TAG BIT_1 /* Tagged queue action enable */
993 #define OF_DATA_IN BIT_6 /* Data in to initiator */
994 /* (data from target to initiator) */
995 #define OF_DATA_OUT BIT_7 /* Data out from initiator */
996 /* (data from initiator to target) */
997 #define OF_NO_DATA (BIT_7 | BIT_6)
998 #define OF_DISC_DISABLED BIT_15 /* Disconnects disabled */
999 #define OF_DISABLE_SDP BIT_24 /* Disable sending save data ptr */
1000 #define OF_SEND_RDP BIT_26 /* Send restore data pointers msg */
1001 #define OF_FORCE_DISC BIT_30 /* Disconnects mandatory */
1002 #define OF_SSTS BIT_31 /* Send SCSI status */
1003
1004
1005 /*
1006 * BUS parameters/settings structure - UNUSED
1007 */
1008 struct bus_param {
1009 uint8_t id; /* Host adapter SCSI id */
1010 uint8_t bus_reset_delay; /* SCSI bus reset delay. */
1011 uint8_t failed_reset_count; /* number of time reset failed */
1012 uint8_t unused;
1013 uint16_t device_enables; /* Device enable bits. */
1014 uint16_t lun_disables; /* LUN disable bits. */
1015 uint16_t qtag_enables; /* Tag queue enables. */
1016 uint16_t hiwat; /* High water mark per device. */
1017 uint8_t reset_marker:1;
1018 uint8_t disable_scsi_reset:1;
1019 uint8_t scsi_bus_dead:1; /* SCSI Bus is Dead, when 5 back to back resets failed */
1020 };
1021
1022
1023 struct qla_driver_setup {
1024 uint32_t no_sync:1;
1025 uint32_t no_wide:1;
1026 uint32_t no_ppr:1;
1027 uint32_t no_nvram:1;
1028 uint16_t sync_mask;
1029 uint16_t wide_mask;
1030 uint16_t ppr_mask;
1031 };
1032
1033
1034 /*
1035 * Linux Host Adapter structure
1036 */
1037 struct scsi_qla_host {
1038 /* Linux adapter configuration data */
1039 struct Scsi_Host *host; /* pointer to host data */
1040 struct scsi_qla_host *next;
1041 struct device_reg __iomem *iobase; /* Base Memory-mapped I/O address */
1042
1043 unsigned char __iomem *mmpbase; /* memory mapped address */
1044 unsigned long host_no;
1045 struct pci_dev *pdev;
1046 uint8_t devnum;
1047 uint8_t revision;
1048 uint8_t ports;
1049
1050 unsigned long actthreads;
1051 unsigned long isr_count; /* Interrupt count */
1052 unsigned long spurious_int;
1053
1054 /* Outstandings ISP commands. */
1055 struct srb *outstanding_cmds[MAX_OUTSTANDING_COMMANDS];
1056
1057 /* BUS configuration data */
1058 struct bus_param bus_settings[MAX_BUSES];
1059
1060 /* Received ISP mailbox data. */
1061 volatile uint16_t mailbox_out[MAILBOX_REGISTER_COUNT];
1062
1063 dma_addr_t request_dma; /* Physical Address */
1064 request_t *request_ring; /* Base virtual address */
1065 request_t *request_ring_ptr; /* Current address. */
1066 uint16_t req_ring_index; /* Current index. */
1067 uint16_t req_q_cnt; /* Number of available entries. */
1068
1069 dma_addr_t response_dma; /* Physical address. */
1070 struct response *response_ring; /* Base virtual address */
1071 struct response *response_ring_ptr; /* Current address. */
1072 uint16_t rsp_ring_index; /* Current index. */
1073
1074 struct list_head done_q; /* Done queue */
1075
1076 struct completion *mailbox_wait;
1077
1078 volatile struct {
1079 uint32_t online:1; /* 0 */
1080 uint32_t reset_marker:1; /* 1 */
1081 uint32_t disable_host_adapter:1; /* 2 */
1082 uint32_t reset_active:1; /* 3 */
1083 uint32_t abort_isp_active:1; /* 4 */
1084 uint32_t disable_risc_code_load:1; /* 5 */
1085 uint32_t enable_64bit_addressing:1; /* 6 */
1086 uint32_t in_reset:1; /* 7 */
1087 uint32_t ints_enabled:1;
1088 uint32_t ignore_nvram:1;
1089 #ifdef __ia64__
1090 uint32_t use_pci_vchannel:1;
1091 #endif
1092 } flags;
1093
1094 struct nvram nvram;
1095 int nvram_valid;
1096 };
1097
1098 #endif /* _QLA1280_H */
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