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[TG3]: Set minimal hw interrupt mitigation.
[linux-2.6/verdex.git] / drivers / scsi / qlogicisp.c
blob6d29e1b864e2361ec067280be8d586bf04e17d38
1 /*
2 * QLogic ISP1020 Intelligent SCSI Processor Driver (PCI)
3 * Written by Erik H. Moe, ehm@cris.com
4 * Copyright 1995, Erik H. Moe
5 * Copyright 1996, 1997 Michael A. Griffith <grif@acm.org>
6 * Copyright 2000, Jayson C. Vantuyl <vantuyl@csc.smsu.edu>
7 * and Bryon W. Roche <bryon@csc.smsu.edu>
8 *
9 * 64-bit addressing added by Kanoj Sarcar <kanoj@sgi.com>
10 * and Leo Dagum <dagum@sgi.com>
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2, or (at your option) any
15 * later version.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 */
22
23 #include <linux/blkdev.h>
24 #include <linux/config.h>
25 #include <linux/kernel.h>
26 #include <linux/string.h>
27 #include <linux/ioport.h>
28 #include <linux/sched.h>
29 #include <linux/types.h>
30 #include <linux/pci.h>
31 #include <linux/delay.h>
32 #include <linux/unistd.h>
33 #include <linux/spinlock.h>
34 #include <linux/interrupt.h>
35 #include <asm/io.h>
36 #include <asm/irq.h>
37 #include <asm/byteorder.h>
38 #include "scsi.h"
39 #include <scsi/scsi_host.h>
40
41 /*
42 * With the qlogic interface, every queue slot can hold a SCSI
43 * command with up to 4 scatter/gather entries. If we need more
44 * than 4 entries, continuation entries can be used that hold
45 * another 7 entries each. Unlike for other drivers, this means
46 * that the maximum number of scatter/gather entries we can
47 * support at any given time is a function of the number of queue
48 * slots available. That is, host->can_queue and host->sg_tablesize
49 * are dynamic and _not_ independent. This all works fine because
50 * requests are queued serially and the scatter/gather limit is
51 * determined for each queue request anew.
52 */
53 #define QLOGICISP_REQ_QUEUE_LEN 63 /* must be power of two - 1 */
54 #define QLOGICISP_MAX_SG(ql) (4 + ((ql) > 0) ? 7*((ql) - 1) : 0)
55
56 /* Configuration section *****************************************************/
57
58 /* Set the following macro to 1 to reload the ISP1020's firmware. This is
59 the latest firmware provided by QLogic. This may be an earlier/later
60 revision than supplied by your board. */
61
62 #define RELOAD_FIRMWARE 1
63
64 /* Set the following macro to 1 to reload the ISP1020's defaults from nvram.
65 If you are not sure of your settings, leave this alone, the driver will
66 use a set of 'safe' defaults */
67
68 #define USE_NVRAM_DEFAULTS 0
69
70 /* Macros used for debugging */
71
72 #define DEBUG_ISP1020 0
73 #define DEBUG_ISP1020_INTR 0
74 #define DEBUG_ISP1020_SETUP 0
75 #define TRACE_ISP 0
76
77 #define DEFAULT_LOOP_COUNT 1000000
78
79 /* End Configuration section *************************************************/
80
81 #include <linux/module.h>
82
83 #if TRACE_ISP
84
85 # define TRACE_BUF_LEN (32*1024)
86
87 struct {
88 u_long next;
89 struct {
90 u_long time;
91 u_int index;
92 u_int addr;
93 u_char * name;
94 } buf[TRACE_BUF_LEN];
95 } trace;
96
97 #define TRACE(w, i, a) \
98 { \
99 unsigned long flags; \
100 \
101 trace.buf[trace.next].name = (w); \
102 trace.buf[trace.next].time = jiffies; \
103 trace.buf[trace.next].index = (i); \
104 trace.buf[trace.next].addr = (long) (a); \
105 trace.next = (trace.next + 1) & (TRACE_BUF_LEN - 1); \
106 }
107
108 #else
109 # define TRACE(w, i, a)
110 #endif
111
112 #if DEBUG_ISP1020
113 #define ENTER(x) printk("isp1020 : entering %s()\n", x);
114 #define LEAVE(x) printk("isp1020 : leaving %s()\n", x);
115 #define DEBUG(x) x
116 #else
117 #define ENTER(x)
118 #define LEAVE(x)
119 #define DEBUG(x)
120 #endif /* DEBUG_ISP1020 */
121
122 #if DEBUG_ISP1020_INTR
123 #define ENTER_INTR(x) printk("isp1020 : entering %s()\n", x);
124 #define LEAVE_INTR(x) printk("isp1020 : leaving %s()\n", x);
125 #define DEBUG_INTR(x) x
126 #else
127 #define ENTER_INTR(x)
128 #define LEAVE_INTR(x)
129 #define DEBUG_INTR(x)
130 #endif /* DEBUG ISP1020_INTR */
131
132 #define ISP1020_REV_ID 1
133
134 #define MAX_TARGETS 16
135 #define MAX_LUNS 8
136
137 /* host configuration and control registers */
138 #define HOST_HCCR 0xc0 /* host command and control */
139
140 /* pci bus interface registers */
141 #define PCI_ID_LOW 0x00 /* vendor id */
142 #define PCI_ID_HIGH 0x02 /* device id */
143 #define ISP_CFG0 0x04 /* configuration register #0 */
144 #define ISP_CFG0_HWMSK 0x000f /* Hardware revision mask */
145 #define ISP_CFG0_1020 0x0001 /* ISP1020 */
146 #define ISP_CFG0_1020A 0x0002 /* ISP1020A */
147 #define ISP_CFG0_1040 0x0003 /* ISP1040 */
148 #define ISP_CFG0_1040A 0x0004 /* ISP1040A */
149 #define ISP_CFG0_1040B 0x0005 /* ISP1040B */
150 #define ISP_CFG0_1040C 0x0006 /* ISP1040C */
151 #define ISP_CFG1 0x06 /* configuration register #1 */
152 #define ISP_CFG1_F128 0x0040 /* 128-byte FIFO threshold */
153 #define ISP_CFG1_F64 0x0030 /* 128-byte FIFO threshold */
154 #define ISP_CFG1_F32 0x0020 /* 128-byte FIFO threshold */
155 #define ISP_CFG1_F16 0x0010 /* 128-byte FIFO threshold */
156 #define ISP_CFG1_BENAB 0x0004 /* Global Bus burst enable */
157 #define ISP_CFG1_SXP 0x0001 /* SXP register select */
158 #define PCI_INTF_CTL 0x08 /* pci interface control */
159 #define PCI_INTF_STS 0x0a /* pci interface status */
160 #define PCI_SEMAPHORE 0x0c /* pci semaphore */
161 #define PCI_NVRAM 0x0e /* pci nvram interface */
162 #define CDMA_CONF 0x20 /* Command DMA Config */
163 #define DDMA_CONF 0x40 /* Data DMA Config */
164 #define DMA_CONF_SENAB 0x0008 /* SXP to DMA Data enable */
165 #define DMA_CONF_RIRQ 0x0004 /* RISC interrupt enable */
166 #define DMA_CONF_BENAB 0x0002 /* Bus burst enable */
167 #define DMA_CONF_DIR 0x0001 /* DMA direction (0=fifo->host 1=host->fifo) */
168
169 /* mailbox registers */
170 #define MBOX0 0x70 /* mailbox 0 */
171 #define MBOX1 0x72 /* mailbox 1 */
172 #define MBOX2 0x74 /* mailbox 2 */
173 #define MBOX3 0x76 /* mailbox 3 */
174 #define MBOX4 0x78 /* mailbox 4 */
175 #define MBOX5 0x7a /* mailbox 5 */
176 #define MBOX6 0x7c /* mailbox 6 */
177 #define MBOX7 0x7e /* mailbox 7 */
178
179 /* mailbox command complete status codes */
180 #define MBOX_COMMAND_COMPLETE 0x4000
181 #define INVALID_COMMAND 0x4001
182 #define HOST_INTERFACE_ERROR 0x4002
183 #define TEST_FAILED 0x4003
184 #define COMMAND_ERROR 0x4005
185 #define COMMAND_PARAM_ERROR 0x4006
186
187 /* async event status codes */
188 #define ASYNC_SCSI_BUS_RESET 0x8001
189 #define SYSTEM_ERROR 0x8002
190 #define REQUEST_TRANSFER_ERROR 0x8003
191 #define RESPONSE_TRANSFER_ERROR 0x8004
192 #define REQUEST_QUEUE_WAKEUP 0x8005
193 #define EXECUTION_TIMEOUT_RESET 0x8006
194
195 #ifdef CONFIG_QL_ISP_A64
196 #define IOCB_SEGS 2
197 #define CONTINUATION_SEGS 5
198 #define MAX_CONTINUATION_ENTRIES 254
199 #else
200 #define IOCB_SEGS 4
201 #define CONTINUATION_SEGS 7
202 #endif /* CONFIG_QL_ISP_A64 */
203
204 struct Entry_header {
205 u_char entry_type;
206 u_char entry_cnt;
207 u_char sys_def_1;
208 u_char flags;
209 };
210
211 /* entry header type commands */
212 #ifdef CONFIG_QL_ISP_A64
213 #define ENTRY_COMMAND 9
214 #define ENTRY_CONTINUATION 0xa
215 #else
216 #define ENTRY_COMMAND 1
217 #define ENTRY_CONTINUATION 2
218 #endif /* CONFIG_QL_ISP_A64 */
219
220 #define ENTRY_STATUS 3
221 #define ENTRY_MARKER 4
222 #define ENTRY_EXTENDED_COMMAND 5
223
224 /* entry header flag definitions */
225 #define EFLAG_CONTINUATION 1
226 #define EFLAG_BUSY 2
227 #define EFLAG_BAD_HEADER 4
228 #define EFLAG_BAD_PAYLOAD 8
229
230 struct dataseg {
231 u_int d_base;
232 #ifdef CONFIG_QL_ISP_A64
233 u_int d_base_hi;
234 #endif
235 u_int d_count;
236 };
237
238 struct Command_Entry {
239 struct Entry_header hdr;
240 u_int handle;
241 u_char target_lun;
242 u_char target_id;
243 u_short cdb_length;
244 u_short control_flags;
245 u_short rsvd;
246 u_short time_out;
247 u_short segment_cnt;
248 u_char cdb[12];
249 #ifdef CONFIG_QL_ISP_A64
250 u_int rsvd1;
251 u_int rsvd2;
252 #endif
253 struct dataseg dataseg[IOCB_SEGS];
254 };
255
256 /* command entry control flag definitions */
257 #define CFLAG_NODISC 0x01
258 #define CFLAG_HEAD_TAG 0x02
259 #define CFLAG_ORDERED_TAG 0x04
260 #define CFLAG_SIMPLE_TAG 0x08
261 #define CFLAG_TAR_RTN 0x10
262 #define CFLAG_READ 0x20
263 #define CFLAG_WRITE 0x40
264
265 struct Ext_Command_Entry {
266 struct Entry_header hdr;
267 u_int handle;
268 u_char target_lun;
269 u_char target_id;
270 u_short cdb_length;
271 u_short control_flags;
272 u_short rsvd;
273 u_short time_out;
274 u_short segment_cnt;
275 u_char cdb[44];
276 };
277
278 struct Continuation_Entry {
279 struct Entry_header hdr;
280 #ifndef CONFIG_QL_ISP_A64
281 u_int reserved;
282 #endif
283 struct dataseg dataseg[CONTINUATION_SEGS];
284 };
285
286 struct Marker_Entry {
287 struct Entry_header hdr;
288 u_int reserved;
289 u_char target_lun;
290 u_char target_id;
291 u_char modifier;
292 u_char rsvd;
293 u_char rsvds[52];
294 };
295
296 /* marker entry modifier definitions */
297 #define SYNC_DEVICE 0
298 #define SYNC_TARGET 1
299 #define SYNC_ALL 2
300
301 struct Status_Entry {
302 struct Entry_header hdr;
303 u_int handle;
304 u_short scsi_status;
305 u_short completion_status;
306 u_short state_flags;
307 u_short status_flags;
308 u_short time;
309 u_short req_sense_len;
310 u_int residual;
311 u_char rsvd[8];
312 u_char req_sense_data[32];
313 };
314
315 /* status entry completion status definitions */
316 #define CS_COMPLETE 0x0000
317 #define CS_INCOMPLETE 0x0001
318 #define CS_DMA_ERROR 0x0002
319 #define CS_TRANSPORT_ERROR 0x0003
320 #define CS_RESET_OCCURRED 0x0004
321 #define CS_ABORTED 0x0005
322 #define CS_TIMEOUT 0x0006
323 #define CS_DATA_OVERRUN 0x0007
324 #define CS_COMMAND_OVERRUN 0x0008
325 #define CS_STATUS_OVERRUN 0x0009
326 #define CS_BAD_MESSAGE 0x000a
327 #define CS_NO_MESSAGE_OUT 0x000b
328 #define CS_EXT_ID_FAILED 0x000c
329 #define CS_IDE_MSG_FAILED 0x000d
330 #define CS_ABORT_MSG_FAILED 0x000e
331 #define CS_REJECT_MSG_FAILED 0x000f
332 #define CS_NOP_MSG_FAILED 0x0010
333 #define CS_PARITY_ERROR_MSG_FAILED 0x0011
334 #define CS_DEVICE_RESET_MSG_FAILED 0x0012
335 #define CS_ID_MSG_FAILED 0x0013
336 #define CS_UNEXP_BUS_FREE 0x0014
337 #define CS_DATA_UNDERRUN 0x0015
338
339 /* status entry state flag definitions */
340 #define SF_GOT_BUS 0x0100
341 #define SF_GOT_TARGET 0x0200
342 #define SF_SENT_CDB 0x0400
343 #define SF_TRANSFERRED_DATA 0x0800
344 #define SF_GOT_STATUS 0x1000
345 #define SF_GOT_SENSE 0x2000
346
347 /* status entry status flag definitions */
348 #define STF_DISCONNECT 0x0001
349 #define STF_SYNCHRONOUS 0x0002
350 #define STF_PARITY_ERROR 0x0004
351 #define STF_BUS_RESET 0x0008
352 #define STF_DEVICE_RESET 0x0010
353 #define STF_ABORTED 0x0020
354 #define STF_TIMEOUT 0x0040
355 #define STF_NEGOTIATION 0x0080
356
357 /* interface control commands */
358 #define ISP_RESET 0x0001
359 #define ISP_EN_INT 0x0002
360 #define ISP_EN_RISC 0x0004
361
362 /* host control commands */
363 #define HCCR_NOP 0x0000
364 #define HCCR_RESET 0x1000
365 #define HCCR_PAUSE 0x2000
366 #define HCCR_RELEASE 0x3000
367 #define HCCR_SINGLE_STEP 0x4000
368 #define HCCR_SET_HOST_INTR 0x5000
369 #define HCCR_CLEAR_HOST_INTR 0x6000
370 #define HCCR_CLEAR_RISC_INTR 0x7000
371 #define HCCR_BP_ENABLE 0x8000
372 #define HCCR_BIOS_DISABLE 0x9000
373 #define HCCR_TEST_MODE 0xf000
374
375 #define RISC_BUSY 0x0004
376
377 /* mailbox commands */
378 #define MBOX_NO_OP 0x0000
379 #define MBOX_LOAD_RAM 0x0001
380 #define MBOX_EXEC_FIRMWARE 0x0002
381 #define MBOX_DUMP_RAM 0x0003
382 #define MBOX_WRITE_RAM_WORD 0x0004
383 #define MBOX_READ_RAM_WORD 0x0005
384 #define MBOX_MAILBOX_REG_TEST 0x0006
385 #define MBOX_VERIFY_CHECKSUM 0x0007
386 #define MBOX_ABOUT_FIRMWARE 0x0008
387 #define MBOX_CHECK_FIRMWARE 0x000e
388 #define MBOX_INIT_REQ_QUEUE 0x0010
389 #define MBOX_INIT_RES_QUEUE 0x0011
390 #define MBOX_EXECUTE_IOCB 0x0012
391 #define MBOX_WAKE_UP 0x0013
392 #define MBOX_STOP_FIRMWARE 0x0014
393 #define MBOX_ABORT 0x0015
394 #define MBOX_ABORT_DEVICE 0x0016
395 #define MBOX_ABORT_TARGET 0x0017
396 #define MBOX_BUS_RESET 0x0018
397 #define MBOX_STOP_QUEUE 0x0019
398 #define MBOX_START_QUEUE 0x001a
399 #define MBOX_SINGLE_STEP_QUEUE 0x001b
400 #define MBOX_ABORT_QUEUE 0x001c
401 #define MBOX_GET_DEV_QUEUE_STATUS 0x001d
402 #define MBOX_GET_FIRMWARE_STATUS 0x001f
403 #define MBOX_GET_INIT_SCSI_ID 0x0020
404 #define MBOX_GET_SELECT_TIMEOUT 0x0021
405 #define MBOX_GET_RETRY_COUNT 0x0022
406 #define MBOX_GET_TAG_AGE_LIMIT 0x0023
407 #define MBOX_GET_CLOCK_RATE 0x0024
408 #define MBOX_GET_ACT_NEG_STATE 0x0025
409 #define MBOX_GET_ASYNC_DATA_SETUP_TIME 0x0026
410 #define MBOX_GET_PCI_PARAMS 0x0027
411 #define MBOX_GET_TARGET_PARAMS 0x0028
412 #define MBOX_GET_DEV_QUEUE_PARAMS 0x0029
413 #define MBOX_SET_INIT_SCSI_ID 0x0030
414 #define MBOX_SET_SELECT_TIMEOUT 0x0031
415 #define MBOX_SET_RETRY_COUNT 0x0032
416 #define MBOX_SET_TAG_AGE_LIMIT 0x0033
417 #define MBOX_SET_CLOCK_RATE 0x0034
418 #define MBOX_SET_ACTIVE_NEG_STATE 0x0035
419 #define MBOX_SET_ASYNC_DATA_SETUP_TIME 0x0036
420 #define MBOX_SET_PCI_CONTROL_PARAMS 0x0037
421 #define MBOX_SET_TARGET_PARAMS 0x0038
422 #define MBOX_SET_DEV_QUEUE_PARAMS 0x0039
423 #define MBOX_RETURN_BIOS_BLOCK_ADDR 0x0040
424 #define MBOX_WRITE_FOUR_RAM_WORDS 0x0041
425 #define MBOX_EXEC_BIOS_IOCB 0x0042
426
427 #ifdef CONFIG_QL_ISP_A64
428 #define MBOX_CMD_INIT_REQUEST_QUEUE_64 0x0052
429 #define MBOX_CMD_INIT_RESPONSE_QUEUE_64 0x0053
430 #endif /* CONFIG_QL_ISP_A64 */
431
432 #include "qlogicisp_asm.c"
433
434 #define PACKB(a, b) (((a)<<4)|(b))
435
436 static const u_char mbox_param[] = {
437 PACKB(1, 1), /* MBOX_NO_OP */
438 PACKB(5, 5), /* MBOX_LOAD_RAM */
439 PACKB(2, 0), /* MBOX_EXEC_FIRMWARE */
440 PACKB(5, 5), /* MBOX_DUMP_RAM */
441 PACKB(3, 3), /* MBOX_WRITE_RAM_WORD */
442 PACKB(2, 3), /* MBOX_READ_RAM_WORD */
443 PACKB(6, 6), /* MBOX_MAILBOX_REG_TEST */
444 PACKB(2, 3), /* MBOX_VERIFY_CHECKSUM */
445 PACKB(1, 3), /* MBOX_ABOUT_FIRMWARE */
446 PACKB(0, 0), /* 0x0009 */
447 PACKB(0, 0), /* 0x000a */
448 PACKB(0, 0), /* 0x000b */
449 PACKB(0, 0), /* 0x000c */
450 PACKB(0, 0), /* 0x000d */
451 PACKB(1, 2), /* MBOX_CHECK_FIRMWARE */
452 PACKB(0, 0), /* 0x000f */
453 PACKB(5, 5), /* MBOX_INIT_REQ_QUEUE */
454 PACKB(6, 6), /* MBOX_INIT_RES_QUEUE */
455 PACKB(4, 4), /* MBOX_EXECUTE_IOCB */
456 PACKB(2, 2), /* MBOX_WAKE_UP */
457 PACKB(1, 6), /* MBOX_STOP_FIRMWARE */
458 PACKB(4, 4), /* MBOX_ABORT */
459 PACKB(2, 2), /* MBOX_ABORT_DEVICE */
460 PACKB(3, 3), /* MBOX_ABORT_TARGET */
461 PACKB(2, 2), /* MBOX_BUS_RESET */
462 PACKB(2, 3), /* MBOX_STOP_QUEUE */
463 PACKB(2, 3), /* MBOX_START_QUEUE */
464 PACKB(2, 3), /* MBOX_SINGLE_STEP_QUEUE */
465 PACKB(2, 3), /* MBOX_ABORT_QUEUE */
466 PACKB(2, 4), /* MBOX_GET_DEV_QUEUE_STATUS */
467 PACKB(0, 0), /* 0x001e */
468 PACKB(1, 3), /* MBOX_GET_FIRMWARE_STATUS */
469 PACKB(1, 2), /* MBOX_GET_INIT_SCSI_ID */
470 PACKB(1, 2), /* MBOX_GET_SELECT_TIMEOUT */
471 PACKB(1, 3), /* MBOX_GET_RETRY_COUNT */
472 PACKB(1, 2), /* MBOX_GET_TAG_AGE_LIMIT */
473 PACKB(1, 2), /* MBOX_GET_CLOCK_RATE */
474 PACKB(1, 2), /* MBOX_GET_ACT_NEG_STATE */
475 PACKB(1, 2), /* MBOX_GET_ASYNC_DATA_SETUP_TIME */
476 PACKB(1, 3), /* MBOX_GET_PCI_PARAMS */
477 PACKB(2, 4), /* MBOX_GET_TARGET_PARAMS */
478 PACKB(2, 4), /* MBOX_GET_DEV_QUEUE_PARAMS */
479 PACKB(0, 0), /* 0x002a */
480 PACKB(0, 0), /* 0x002b */
481 PACKB(0, 0), /* 0x002c */
482 PACKB(0, 0), /* 0x002d */
483 PACKB(0, 0), /* 0x002e */
484 PACKB(0, 0), /* 0x002f */
485 PACKB(2, 2), /* MBOX_SET_INIT_SCSI_ID */
486 PACKB(2, 2), /* MBOX_SET_SELECT_TIMEOUT */
487 PACKB(3, 3), /* MBOX_SET_RETRY_COUNT */
488 PACKB(2, 2), /* MBOX_SET_TAG_AGE_LIMIT */
489 PACKB(2, 2), /* MBOX_SET_CLOCK_RATE */
490 PACKB(2, 2), /* MBOX_SET_ACTIVE_NEG_STATE */
491 PACKB(2, 2), /* MBOX_SET_ASYNC_DATA_SETUP_TIME */
492 PACKB(3, 3), /* MBOX_SET_PCI_CONTROL_PARAMS */
493 PACKB(4, 4), /* MBOX_SET_TARGET_PARAMS */
494 PACKB(4, 4), /* MBOX_SET_DEV_QUEUE_PARAMS */
495 PACKB(0, 0), /* 0x003a */
496 PACKB(0, 0), /* 0x003b */
497 PACKB(0, 0), /* 0x003c */
498 PACKB(0, 0), /* 0x003d */
499 PACKB(0, 0), /* 0x003e */
500 PACKB(0, 0), /* 0x003f */
501 PACKB(1, 2), /* MBOX_RETURN_BIOS_BLOCK_ADDR */
502 PACKB(6, 1), /* MBOX_WRITE_FOUR_RAM_WORDS */
503 PACKB(2, 3) /* MBOX_EXEC_BIOS_IOCB */
504 #ifdef CONFIG_QL_ISP_A64
505 ,PACKB(0, 0), /* 0x0043 */
506 PACKB(0, 0), /* 0x0044 */
507 PACKB(0, 0), /* 0x0045 */
508 PACKB(0, 0), /* 0x0046 */
509 PACKB(0, 0), /* 0x0047 */
510 PACKB(0, 0), /* 0x0048 */
511 PACKB(0, 0), /* 0x0049 */
512 PACKB(0, 0), /* 0x004a */
513 PACKB(0, 0), /* 0x004b */
514 PACKB(0, 0), /* 0x004c */
515 PACKB(0, 0), /* 0x004d */
516 PACKB(0, 0), /* 0x004e */
517 PACKB(0, 0), /* 0x004f */
518 PACKB(0, 0), /* 0x0050 */
519 PACKB(0, 0), /* 0x0051 */
520 PACKB(8, 8), /* MBOX_CMD_INIT_REQUEST_QUEUE_64 (0x0052) */
521 PACKB(8, 8) /* MBOX_CMD_INIT_RESPONSE_QUEUE_64 (0x0053) */
522 #endif /* CONFIG_QL_ISP_A64 */
523 };
524
525 #define MAX_MBOX_COMMAND (sizeof(mbox_param)/sizeof(u_short))
526
527 struct host_param {
528 u_short fifo_threshold;
529 u_short host_adapter_enable;
530 u_short initiator_scsi_id;
531 u_short bus_reset_delay;
532 u_short retry_count;
533 u_short retry_delay;
534 u_short async_data_setup_time;
535 u_short req_ack_active_negation;
536 u_short data_line_active_negation;
537 u_short data_dma_burst_enable;
538 u_short command_dma_burst_enable;
539 u_short tag_aging;
540 u_short selection_timeout;
541 u_short max_queue_depth;
542 };
543
544 /*
545 * Device Flags:
546 *
547 * Bit Name
548 * ---------
549 * 7 Disconnect Privilege
550 * 6 Parity Checking
551 * 5 Wide Data Transfers
552 * 4 Synchronous Data Transfers
553 * 3 Tagged Queuing
554 * 2 Automatic Request Sense
555 * 1 Stop Queue on Check Condition
556 * 0 Renegotiate on Error
557 */
558
559 struct dev_param {
560 u_short device_flags;
561 u_short execution_throttle;
562 u_short synchronous_period;
563 u_short synchronous_offset;
564 u_short device_enable;
565 u_short reserved; /* pad */
566 };
567
568 /*
569 * The result queue can be quite a bit smaller since continuation entries
570 * do not show up there:
571 */
572 #define RES_QUEUE_LEN ((QLOGICISP_REQ_QUEUE_LEN + 1) / 8 - 1)
573 #define QUEUE_ENTRY_LEN 64
574 #define QSIZE(entries) (((entries) + 1) * QUEUE_ENTRY_LEN)
575
576 struct isp_queue_entry {
577 char __opaque[QUEUE_ENTRY_LEN];
578 };
579
580 struct isp1020_hostdata {
581 void __iomem *memaddr;
582 u_char revision;
583 struct host_param host_param;
584 struct dev_param dev_param[MAX_TARGETS];
585 struct pci_dev *pci_dev;
586
587 struct isp_queue_entry *res_cpu; /* CPU-side address of response queue. */
588 struct isp_queue_entry *req_cpu; /* CPU-size address of request queue. */
589
590 /* result and request queues (shared with isp1020): */
591 u_int req_in_ptr; /* index of next request slot */
592 u_int res_out_ptr; /* index of next result slot */
593
594 /* this is here so the queues are nicely aligned */
595 long send_marker; /* do we need to send a marker? */
596
597 /* The cmd->handle has a fixed size, and is only 32-bits. We
598 * need to take care to handle 64-bit systems correctly thus what
599 * we actually place in cmd->handle is an index to the following
600 * table. Kudos to Matt Jacob for the technique. -DaveM
601 */
602 Scsi_Cmnd *cmd_slots[QLOGICISP_REQ_QUEUE_LEN + 1];
603
604 dma_addr_t res_dma; /* PCI side view of response queue */
605 dma_addr_t req_dma; /* PCI side view of request queue */
606 };
607
608 /* queue length's _must_ be power of two: */
609 #define QUEUE_DEPTH(in, out, ql) ((in - out) & (ql))
610 #define REQ_QUEUE_DEPTH(in, out) QUEUE_DEPTH(in, out, \
611 QLOGICISP_REQ_QUEUE_LEN)
612 #define RES_QUEUE_DEPTH(in, out) QUEUE_DEPTH(in, out, RES_QUEUE_LEN)
613
614 static void isp1020_enable_irqs(struct Scsi_Host *);
615 static void isp1020_disable_irqs(struct Scsi_Host *);
616 static int isp1020_init(struct Scsi_Host *);
617 static int isp1020_reset_hardware(struct Scsi_Host *);
618 static int isp1020_set_defaults(struct Scsi_Host *);
619 static int isp1020_load_parameters(struct Scsi_Host *);
620 static int isp1020_mbox_command(struct Scsi_Host *, u_short []);
621 static int isp1020_return_status(struct Status_Entry *);
622 static void isp1020_intr_handler(int, void *, struct pt_regs *);
623 static irqreturn_t do_isp1020_intr_handler(int, void *, struct pt_regs *);
624
625 #if USE_NVRAM_DEFAULTS
626 static int isp1020_get_defaults(struct Scsi_Host *);
627 static int isp1020_verify_nvram(struct Scsi_Host *);
628 static u_short isp1020_read_nvram_word(struct Scsi_Host *, u_short);
629 #endif
630
631 #if DEBUG_ISP1020
632 static void isp1020_print_scsi_cmd(Scsi_Cmnd *);
633 #endif
634 #if DEBUG_ISP1020_INTR
635 static void isp1020_print_status_entry(struct Status_Entry *);
636 #endif
637
638 /* memaddr should be used to determine if memmapped port i/o is being used
639 * non-null memaddr == mmap'd
640 * JV 7-Jan-2000
641 */
642 static inline u_short isp_inw(struct Scsi_Host *host, long offset)
643 {
644 struct isp1020_hostdata *h = (struct isp1020_hostdata *)host->hostdata;
645 if (h->memaddr)
646 return readw(h->memaddr + offset);
647 else
648 return inw(host->io_port + offset);
649 }
650
651 static inline void isp_outw(u_short val, struct Scsi_Host *host, long offset)
652 {
653 struct isp1020_hostdata *h = (struct isp1020_hostdata *)host->hostdata;
654 if (h->memaddr)
655 writew(val, h->memaddr + offset);
656 else
657 outw(val, host->io_port + offset);
658 }
659
660 static inline void isp1020_enable_irqs(struct Scsi_Host *host)
661 {
662 isp_outw(ISP_EN_INT|ISP_EN_RISC, host, PCI_INTF_CTL);
663 }
664
665
666 static inline void isp1020_disable_irqs(struct Scsi_Host *host)
667 {
668 isp_outw(0x0, host, PCI_INTF_CTL);
669 }
670
671
672 static int isp1020_detect(Scsi_Host_Template *tmpt)
673 {
674 int hosts = 0;
675 struct Scsi_Host *host;
676 struct isp1020_hostdata *hostdata;
677 struct pci_dev *pdev = NULL;
678
679 ENTER("isp1020_detect");
680
681 tmpt->proc_name = "isp1020";
682
683 while ((pdev = pci_find_device(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP1020, pdev)))
684 {
685 if (pci_enable_device(pdev))
686 continue;
687
688 host = scsi_register(tmpt, sizeof(struct isp1020_hostdata));
689 if (!host)
690 continue;
691
692 hostdata = (struct isp1020_hostdata *) host->hostdata;
693
694 memset(hostdata, 0, sizeof(struct isp1020_hostdata));
695
696 hostdata->pci_dev = pdev;
697 scsi_set_device(host, &pdev->dev);
698
699 if (isp1020_init(host))
700 goto fail_and_unregister;
701
702 if (isp1020_reset_hardware(host)
703 #if USE_NVRAM_DEFAULTS
704 || isp1020_get_defaults(host)
705 #else
706 || isp1020_set_defaults(host)
707 #endif /* USE_NVRAM_DEFAULTS */
708 || isp1020_load_parameters(host)) {
709 goto fail_uninit;
710 }
711
712 host->this_id = hostdata->host_param.initiator_scsi_id;
713 host->max_sectors = 64;
714
715 if (request_irq(host->irq, do_isp1020_intr_handler, SA_INTERRUPT | SA_SHIRQ,
716 "qlogicisp", host))
717 {
718 printk("qlogicisp : interrupt %d already in use\n",
719 host->irq);
720 goto fail_uninit;
721 }
722
723 isp_outw(0x0, host, PCI_SEMAPHORE);
724 isp_outw(HCCR_CLEAR_RISC_INTR, host, HOST_HCCR);
725 isp1020_enable_irqs(host);
726
727 hosts++;
728 continue;
729
730 fail_uninit:
731 iounmap(hostdata->memaddr);
732 release_region(host->io_port, 0xff);
733 fail_and_unregister:
734 if (hostdata->res_cpu)
735 pci_free_consistent(hostdata->pci_dev,
736 QSIZE(RES_QUEUE_LEN),
737 hostdata->res_cpu,
738 hostdata->res_dma);
739 if (hostdata->req_cpu)
740 pci_free_consistent(hostdata->pci_dev,
741 QSIZE(QLOGICISP_REQ_QUEUE_LEN),
742 hostdata->req_cpu,
743 hostdata->req_dma);
744 scsi_unregister(host);
745 }
746
747 LEAVE("isp1020_detect");
748
749 return hosts;
750 }
751
752
753 static int isp1020_release(struct Scsi_Host *host)
754 {
755 struct isp1020_hostdata *hostdata;
756
757 ENTER("isp1020_release");
758
759 hostdata = (struct isp1020_hostdata *) host->hostdata;
760
761 isp_outw(0x0, host, PCI_INTF_CTL);
762 free_irq(host->irq, host);
763
764 iounmap(hostdata->memaddr);
765
766 release_region(host->io_port, 0xff);
767
768 LEAVE("isp1020_release");
769
770 return 0;
771 }
772
773
774 static const char *isp1020_info(struct Scsi_Host *host)
775 {
776 static char buf[80];
777 struct isp1020_hostdata *hostdata;
778
779 ENTER("isp1020_info");
780
781 hostdata = (struct isp1020_hostdata *) host->hostdata;
782 sprintf(buf,
783 "QLogic ISP1020 SCSI on PCI bus %02x device %02x irq %d %s base 0x%lx",
784 hostdata->pci_dev->bus->number, hostdata->pci_dev->devfn, host->irq,
785 (hostdata->memaddr ? "MEM" : "I/O"),
786 (hostdata->memaddr ? (unsigned long)hostdata->memaddr : host->io_port));
787
788 LEAVE("isp1020_info");
789
790 return buf;
791 }
792
793
794 /*
795 * The middle SCSI layer ensures that queuecommand never gets invoked
796 * concurrently with itself or the interrupt handler (though the
797 * interrupt handler may call this routine as part of
798 * request-completion handling).
799 */
800 static int isp1020_queuecommand(Scsi_Cmnd *Cmnd, void (*done)(Scsi_Cmnd *))
801 {
802 int i, n, num_free;
803 u_int in_ptr, out_ptr;
804 struct dataseg * ds;
805 struct scatterlist *sg;
806 struct Command_Entry *cmd;
807 struct Continuation_Entry *cont;
808 struct Scsi_Host *host;
809 struct isp1020_hostdata *hostdata;
810 dma_addr_t dma_addr;
811
812 ENTER("isp1020_queuecommand");
813
814 host = Cmnd->device->host;
815 hostdata = (struct isp1020_hostdata *) host->hostdata;
816 Cmnd->scsi_done = done;
817
818 DEBUG(isp1020_print_scsi_cmd(Cmnd));
819
820 out_ptr = isp_inw(host, + MBOX4);
821 in_ptr = hostdata->req_in_ptr;
822
823 DEBUG(printk("qlogicisp : request queue depth %d\n",
824 REQ_QUEUE_DEPTH(in_ptr, out_ptr)));
825
826 cmd = (struct Command_Entry *) &hostdata->req_cpu[in_ptr];
827 in_ptr = (in_ptr + 1) & QLOGICISP_REQ_QUEUE_LEN;
828 if (in_ptr == out_ptr) {
829 printk("qlogicisp : request queue overflow\n");
830 return 1;
831 }
832
833 if (hostdata->send_marker) {
834 struct Marker_Entry *marker;
835
836 TRACE("queue marker", in_ptr, 0);
837
838 DEBUG(printk("qlogicisp : adding marker entry\n"));
839 marker = (struct Marker_Entry *) cmd;
840 memset(marker, 0, sizeof(struct Marker_Entry));
841
842 marker->hdr.entry_type = ENTRY_MARKER;
843 marker->hdr.entry_cnt = 1;
844 marker->modifier = SYNC_ALL;
845
846 hostdata->send_marker = 0;
847
848 if (((in_ptr + 1) & QLOGICISP_REQ_QUEUE_LEN) == out_ptr) {
849 isp_outw(in_ptr, host, MBOX4);
850 hostdata->req_in_ptr = in_ptr;
851 printk("qlogicisp : request queue overflow\n");
852 return 1;
853 }
854 cmd = (struct Command_Entry *) &hostdata->req_cpu[in_ptr];
855 in_ptr = (in_ptr + 1) & QLOGICISP_REQ_QUEUE_LEN;
856 }
857
858 TRACE("queue command", in_ptr, Cmnd);
859
860 memset(cmd, 0, sizeof(struct Command_Entry));
861
862 cmd->hdr.entry_type = ENTRY_COMMAND;
863 cmd->hdr.entry_cnt = 1;
864
865 cmd->target_lun = Cmnd->device->lun;
866 cmd->target_id = Cmnd->device->id;
867 cmd->cdb_length = cpu_to_le16(Cmnd->cmd_len);
868 cmd->control_flags = cpu_to_le16(CFLAG_READ | CFLAG_WRITE);
869 cmd->time_out = cpu_to_le16(30);
870
871 memcpy(cmd->cdb, Cmnd->cmnd, Cmnd->cmd_len);
872
873 if (Cmnd->use_sg) {
874 int sg_count;
875
876 sg = (struct scatterlist *) Cmnd->request_buffer;
877 ds = cmd->dataseg;
878
879 sg_count = pci_map_sg(hostdata->pci_dev, sg, Cmnd->use_sg,
880 Cmnd->sc_data_direction);
881
882 cmd->segment_cnt = cpu_to_le16(sg_count);
883
884 /* fill in first four sg entries: */
885 n = sg_count;
886 if (n > IOCB_SEGS)
887 n = IOCB_SEGS;
888 for (i = 0; i < n; i++) {
889 dma_addr = sg_dma_address(sg);
890 ds[i].d_base = cpu_to_le32((u32) dma_addr);
891 #ifdef CONFIG_QL_ISP_A64
892 ds[i].d_base_hi = cpu_to_le32((u32) (dma_addr>>32));
893 #endif /* CONFIG_QL_ISP_A64 */
894 ds[i].d_count = cpu_to_le32(sg_dma_len(sg));
895 ++sg;
896 }
897 sg_count -= IOCB_SEGS;
898
899 while (sg_count > 0) {
900 ++cmd->hdr.entry_cnt;
901 cont = (struct Continuation_Entry *)
902 &hostdata->req_cpu[in_ptr];
903 in_ptr = (in_ptr + 1) & QLOGICISP_REQ_QUEUE_LEN;
904 if (in_ptr == out_ptr) {
905 printk("isp1020: unexpected request queue "
906 "overflow\n");
907 return 1;
908 }
909 TRACE("queue continuation", in_ptr, 0);
910 cont->hdr.entry_type = ENTRY_CONTINUATION;
911 cont->hdr.entry_cnt = 0;
912 cont->hdr.sys_def_1 = 0;
913 cont->hdr.flags = 0;
914 #ifndef CONFIG_QL_ISP_A64
915 cont->reserved = 0;
916 #endif
917 ds = cont->dataseg;
918 n = sg_count;
919 if (n > CONTINUATION_SEGS)
920 n = CONTINUATION_SEGS;
921 for (i = 0; i < n; ++i) {
922 dma_addr = sg_dma_address(sg);
923 ds[i].d_base = cpu_to_le32((u32) dma_addr);
924 #ifdef CONFIG_QL_ISP_A64
925 ds[i].d_base_hi = cpu_to_le32((u32)(dma_addr>>32));
926 #endif /* CONFIG_QL_ISP_A64 */
927 ds[i].d_count = cpu_to_le32(sg_dma_len(sg));
928 ++sg;
929 }
930 sg_count -= n;
931 }
932 } else if (Cmnd->request_bufflen) {
933 /*Cmnd->SCp.ptr = (char *)(unsigned long)*/
934 dma_addr = pci_map_single(hostdata->pci_dev,
935 Cmnd->request_buffer,
936 Cmnd->request_bufflen,
937 Cmnd->sc_data_direction);
938 Cmnd->SCp.ptr = (char *)(unsigned long) dma_addr;
939
940 cmd->dataseg[0].d_base =
941 cpu_to_le32((u32) dma_addr);
942 #ifdef CONFIG_QL_ISP_A64
943 cmd->dataseg[0].d_base_hi =
944 cpu_to_le32((u32) (dma_addr>>32));
945 #endif /* CONFIG_QL_ISP_A64 */
946 cmd->dataseg[0].d_count =
947 cpu_to_le32((u32)Cmnd->request_bufflen);
948 cmd->segment_cnt = cpu_to_le16(1);
949 } else {
950 cmd->dataseg[0].d_base = 0;
951 #ifdef CONFIG_QL_ISP_A64
952 cmd->dataseg[0].d_base_hi = 0;
953 #endif /* CONFIG_QL_ISP_A64 */
954 cmd->dataseg[0].d_count = 0;
955 cmd->segment_cnt = cpu_to_le16(1); /* Shouldn't this be 0? */
956 }
957
958 /* Committed, record Scsi_Cmd so we can find it later. */
959 cmd->handle = in_ptr;
960 hostdata->cmd_slots[in_ptr] = Cmnd;
961
962 isp_outw(in_ptr, host, MBOX4);
963 hostdata->req_in_ptr = in_ptr;
964
965 num_free = QLOGICISP_REQ_QUEUE_LEN - REQ_QUEUE_DEPTH(in_ptr, out_ptr);
966 host->can_queue = host->host_busy + num_free;
967 host->sg_tablesize = QLOGICISP_MAX_SG(num_free);
968
969 LEAVE("isp1020_queuecommand");
970
971 return 0;
972 }
973
974
975 #define ASYNC_EVENT_INTERRUPT 0x01
976
977 irqreturn_t do_isp1020_intr_handler(int irq, void *dev_id, struct pt_regs *regs)
978 {
979 struct Scsi_Host *host = dev_id;
980 unsigned long flags;
981
982 spin_lock_irqsave(host->host_lock, flags);
983 isp1020_intr_handler(irq, dev_id, regs);
984 spin_unlock_irqrestore(host->host_lock, flags);
985
986 return IRQ_HANDLED;
987 }
988
989 void isp1020_intr_handler(int irq, void *dev_id, struct pt_regs *regs)
990 {
991 Scsi_Cmnd *Cmnd;
992 struct Status_Entry *sts;
993 struct Scsi_Host *host = dev_id;
994 struct isp1020_hostdata *hostdata;
995 u_int in_ptr, out_ptr;
996 u_short status;
997
998 ENTER_INTR("isp1020_intr_handler");
999
1000 hostdata = (struct isp1020_hostdata *) host->hostdata;
1001
1002 DEBUG_INTR(printk("qlogicisp : interrupt on line %d\n", irq));
1003
1004 if (!(isp_inw(host, PCI_INTF_STS) & 0x04)) {
1005 /* spurious interrupts can happen legally */
1006 DEBUG_INTR(printk("qlogicisp: got spurious interrupt\n"));
1007 return;
1008 }
1009 in_ptr = isp_inw(host, MBOX5);
1010 isp_outw(HCCR_CLEAR_RISC_INTR, host, HOST_HCCR);
1011
1012 if ((isp_inw(host, PCI_SEMAPHORE) & ASYNC_EVENT_INTERRUPT)) {
1013 status = isp_inw(host, MBOX0);
1014
1015 DEBUG_INTR(printk("qlogicisp : mbox completion status: %x\n",
1016 status));
1017
1018 switch (status) {
1019 case ASYNC_SCSI_BUS_RESET:
1020 case EXECUTION_TIMEOUT_RESET:
1021 hostdata->send_marker = 1;
1022 break;
1023 case INVALID_COMMAND:
1024 case HOST_INTERFACE_ERROR:
1025 case COMMAND_ERROR:
1026 case COMMAND_PARAM_ERROR:
1027 printk("qlogicisp : bad mailbox return status\n");
1028 break;
1029 }
1030 isp_outw(0x0, host, PCI_SEMAPHORE);
1031 }
1032 out_ptr = hostdata->res_out_ptr;
1033
1034 DEBUG_INTR(printk("qlogicisp : response queue update\n"));
1035 DEBUG_INTR(printk("qlogicisp : response queue depth %d\n",
1036 QUEUE_DEPTH(in_ptr, out_ptr, RES_QUEUE_LEN)));
1037
1038 while (out_ptr != in_ptr) {
1039 u_int cmd_slot;
1040
1041 sts = (struct Status_Entry *) &hostdata->res_cpu[out_ptr];
1042 out_ptr = (out_ptr + 1) & RES_QUEUE_LEN;
1043
1044 cmd_slot = sts->handle;
1045 Cmnd = hostdata->cmd_slots[cmd_slot];
1046 hostdata->cmd_slots[cmd_slot] = NULL;
1047
1048 TRACE("done", out_ptr, Cmnd);
1049
1050 if (le16_to_cpu(sts->completion_status) == CS_RESET_OCCURRED
1051 || le16_to_cpu(sts->completion_status) == CS_ABORTED
1052 || (le16_to_cpu(sts->status_flags) & STF_BUS_RESET))
1053 hostdata->send_marker = 1;
1054
1055 if (le16_to_cpu(sts->state_flags) & SF_GOT_SENSE)
1056 memcpy(Cmnd->sense_buffer, sts->req_sense_data,
1057 sizeof(Cmnd->sense_buffer));
1058
1059 DEBUG_INTR(isp1020_print_status_entry(sts));
1060
1061 if (sts->hdr.entry_type == ENTRY_STATUS)
1062 Cmnd->result = isp1020_return_status(sts);
1063 else
1064 Cmnd->result = DID_ERROR << 16;
1065
1066 if (Cmnd->use_sg)
1067 pci_unmap_sg(hostdata->pci_dev,
1068 (struct scatterlist *)Cmnd->buffer,
1069 Cmnd->use_sg,
1070 Cmnd->sc_data_direction);
1071 else if (Cmnd->request_bufflen)
1072 pci_unmap_single(hostdata->pci_dev,
1073 #ifdef CONFIG_QL_ISP_A64
1074 (dma_addr_t)((long)Cmnd->SCp.ptr),
1075 #else
1076 (u32)((long)Cmnd->SCp.ptr),
1077 #endif
1078 Cmnd->request_bufflen,
1079 Cmnd->sc_data_direction);
1080
1081 isp_outw(out_ptr, host, MBOX5);
1082 (*Cmnd->scsi_done)(Cmnd);
1083 }
1084 hostdata->res_out_ptr = out_ptr;
1085
1086 LEAVE_INTR("isp1020_intr_handler");
1087 }
1088
1089
1090 static int isp1020_return_status(struct Status_Entry *sts)
1091 {
1092 int host_status = DID_ERROR;
1093 #if DEBUG_ISP1020_INTR
1094 static char *reason[] = {
1095 "DID_OK",
1096 "DID_NO_CONNECT",
1097 "DID_BUS_BUSY",
1098 "DID_TIME_OUT",
1099 "DID_BAD_TARGET",
1100 "DID_ABORT",
1101 "DID_PARITY",
1102 "DID_ERROR",
1103 "DID_RESET",
1104 "DID_BAD_INTR"
1105 };
1106 #endif /* DEBUG_ISP1020_INTR */
1107
1108 ENTER("isp1020_return_status");
1109
1110 DEBUG(printk("qlogicisp : completion status = 0x%04x\n",
1111 le16_to_cpu(sts->completion_status)));
1112
1113 switch(le16_to_cpu(sts->completion_status)) {
1114 case CS_COMPLETE:
1115 host_status = DID_OK;
1116 break;
1117 case CS_INCOMPLETE:
1118 if (!(le16_to_cpu(sts->state_flags) & SF_GOT_BUS))
1119 host_status = DID_NO_CONNECT;
1120 else if (!(le16_to_cpu(sts->state_flags) & SF_GOT_TARGET))
1121 host_status = DID_BAD_TARGET;
1122 else if (!(le16_to_cpu(sts->state_flags) & SF_SENT_CDB))
1123 host_status = DID_ERROR;
1124 else if (!(le16_to_cpu(sts->state_flags) & SF_TRANSFERRED_DATA))
1125 host_status = DID_ERROR;
1126 else if (!(le16_to_cpu(sts->state_flags) & SF_GOT_STATUS))
1127 host_status = DID_ERROR;
1128 else if (!(le16_to_cpu(sts->state_flags) & SF_GOT_SENSE))
1129 host_status = DID_ERROR;
1130 break;
1131 case CS_DMA_ERROR:
1132 case CS_TRANSPORT_ERROR:
1133 host_status = DID_ERROR;
1134 break;
1135 case CS_RESET_OCCURRED:
1136 host_status = DID_RESET;
1137 break;
1138 case CS_ABORTED:
1139 host_status = DID_ABORT;
1140 break;
1141 case CS_TIMEOUT:
1142 host_status = DID_TIME_OUT;
1143 break;
1144 case CS_DATA_OVERRUN:
1145 case CS_COMMAND_OVERRUN:
1146 case CS_STATUS_OVERRUN:
1147 case CS_BAD_MESSAGE:
1148 case CS_NO_MESSAGE_OUT:
1149 case CS_EXT_ID_FAILED:
1150 case CS_IDE_MSG_FAILED:
1151 case CS_ABORT_MSG_FAILED:
1152 case CS_NOP_MSG_FAILED:
1153 case CS_PARITY_ERROR_MSG_FAILED:
1154 case CS_DEVICE_RESET_MSG_FAILED:
1155 case CS_ID_MSG_FAILED:
1156 case CS_UNEXP_BUS_FREE:
1157 host_status = DID_ERROR;
1158 break;
1159 case CS_DATA_UNDERRUN:
1160 host_status = DID_OK;
1161 break;
1162 default:
1163 printk("qlogicisp : unknown completion status 0x%04x\n",
1164 le16_to_cpu(sts->completion_status));
1165 host_status = DID_ERROR;
1166 break;
1167 }
1168
1169 DEBUG_INTR(printk("qlogicisp : host status (%s) scsi status %x\n",
1170 reason[host_status], le16_to_cpu(sts->scsi_status)));
1171
1172 LEAVE("isp1020_return_status");
1173
1174 return (le16_to_cpu(sts->scsi_status) & STATUS_MASK) | (host_status << 16);
1175 }
1176
1177
1178 static int isp1020_biosparam(struct scsi_device *sdev, struct block_device *n,
1179 sector_t capacity, int ip[])
1180 {
1181 int size = capacity;
1182
1183 ENTER("isp1020_biosparam");
1184
1185 ip[0] = 64;
1186 ip[1] = 32;
1187 ip[2] = size >> 11;
1188 if (ip[2] > 1024) {
1189 ip[0] = 255;
1190 ip[1] = 63;
1191 ip[2] = size / (ip[0] * ip[1]);
1192 #if 0
1193 if (ip[2] > 1023)
1194 ip[2] = 1023;
1195 #endif
1196 }
1197
1198 LEAVE("isp1020_biosparam");
1199
1200 return 0;
1201 }
1202
1203
1204 static int isp1020_reset_hardware(struct Scsi_Host *host)
1205 {
1206 u_short param[6];
1207 int loop_count;
1208
1209 ENTER("isp1020_reset_hardware");
1210
1211 isp_outw(ISP_RESET, host, PCI_INTF_CTL);
1212 udelay(100);
1213 isp_outw(HCCR_RESET, host, HOST_HCCR);
1214 udelay(100);
1215 isp_outw(HCCR_RELEASE, host, HOST_HCCR);
1216 isp_outw(HCCR_BIOS_DISABLE, host, HOST_HCCR);
1217
1218 loop_count = DEFAULT_LOOP_COUNT;
1219 while (--loop_count && isp_inw(host, HOST_HCCR) == RISC_BUSY) {
1220 barrier();
1221 cpu_relax();
1222 }
1223 if (!loop_count)
1224 printk("qlogicisp: reset_hardware loop timeout\n");
1225
1226 isp_outw(0, host, ISP_CFG1);
1227
1228 #if DEBUG_ISP1020
1229 printk("qlogicisp : mbox 0 0x%04x \n", isp_inw(host, MBOX0));
1230 printk("qlogicisp : mbox 1 0x%04x \n", isp_inw(host, MBOX1));
1231 printk("qlogicisp : mbox 2 0x%04x \n", isp_inw(host, MBOX2));
1232 printk("qlogicisp : mbox 3 0x%04x \n", isp_inw(host, MBOX3));
1233 printk("qlogicisp : mbox 4 0x%04x \n", isp_inw(host, MBOX4));
1234 printk("qlogicisp : mbox 5 0x%04x \n", isp_inw(host, MBOX5));
1235 #endif /* DEBUG_ISP1020 */
1236
1237 param[0] = MBOX_NO_OP;
1238 isp1020_mbox_command(host, param);
1239 if (param[0] != MBOX_COMMAND_COMPLETE) {
1240 printk("qlogicisp : NOP test failed\n");
1241 return 1;
1242 }
1243
1244 DEBUG(printk("qlogicisp : loading risc ram\n"));
1245
1246 #if RELOAD_FIRMWARE
1247 for (loop_count = 0; loop_count < risc_code_length01; loop_count++) {
1248 param[0] = MBOX_WRITE_RAM_WORD;
1249 param[1] = risc_code_addr01 + loop_count;
1250 param[2] = risc_code01[loop_count];
1251 isp1020_mbox_command(host, param);
1252 if (param[0] != MBOX_COMMAND_COMPLETE) {
1253 printk("qlogicisp : firmware load failure at %d\n",
1254 loop_count);
1255 return 1;
1256 }
1257 }
1258 #endif /* RELOAD_FIRMWARE */
1259
1260 DEBUG(printk("qlogicisp : verifying checksum\n"));
1261
1262 param[0] = MBOX_VERIFY_CHECKSUM;
1263 param[1] = risc_code_addr01;
1264
1265 isp1020_mbox_command(host, param);
1266
1267 if (param[0] != MBOX_COMMAND_COMPLETE) {
1268 printk("qlogicisp : ram checksum failure\n");
1269 return 1;
1270 }
1271
1272 DEBUG(printk("qlogicisp : executing firmware\n"));
1273
1274 param[0] = MBOX_EXEC_FIRMWARE;
1275 param[1] = risc_code_addr01;
1276
1277 isp1020_mbox_command(host, param);
1278
1279 param[0] = MBOX_ABOUT_FIRMWARE;
1280
1281 isp1020_mbox_command(host, param);
1282
1283 if (param[0] != MBOX_COMMAND_COMPLETE) {
1284 printk("qlogicisp : about firmware failure\n");
1285 return 1;
1286 }
1287
1288 DEBUG(printk("qlogicisp : firmware major revision %d\n", param[1]));
1289 DEBUG(printk("qlogicisp : firmware minor revision %d\n", param[2]));
1290
1291 LEAVE("isp1020_reset_hardware");
1292
1293 return 0;
1294 }
1295
1296
1297 static int isp1020_init(struct Scsi_Host *sh)
1298 {
1299 u_long io_base, mem_base, io_flags, mem_flags;
1300 struct isp1020_hostdata *hostdata;
1301 u_char revision;
1302 u_int irq;
1303 u_short command;
1304 struct pci_dev *pdev;
1305
1306 ENTER("isp1020_init");
1307
1308 hostdata = (struct isp1020_hostdata *) sh->hostdata;
1309 pdev = hostdata->pci_dev;
1310
1311 if (pci_read_config_word(pdev, PCI_COMMAND, &command)
1312 || pci_read_config_byte(pdev, PCI_CLASS_REVISION, &revision))
1313 {
1314 printk("qlogicisp : error reading PCI configuration\n");
1315 return 1;
1316 }
1317
1318 io_base = pci_resource_start(pdev, 0);
1319 mem_base = pci_resource_start(pdev, 1);
1320 io_flags = pci_resource_flags(pdev, 0);
1321 mem_flags = pci_resource_flags(pdev, 1);
1322 irq = pdev->irq;
1323
1324 if (pdev->vendor != PCI_VENDOR_ID_QLOGIC) {
1325 printk("qlogicisp : 0x%04x is not QLogic vendor ID\n",
1326 pdev->vendor);
1327 return 1;
1328 }
1329
1330 if (pdev->device != PCI_DEVICE_ID_QLOGIC_ISP1020) {
1331 printk("qlogicisp : 0x%04x does not match ISP1020 device id\n",
1332 pdev->device);
1333 return 1;
1334 }
1335
1336 #ifdef __alpha__
1337 /* Force ALPHA to use bus I/O and not bus MEM.
1338 This is to avoid having to use HAE_MEM registers,
1339 which is broken on some platforms and with SMP. */
1340 command &= ~PCI_COMMAND_MEMORY;
1341 #endif
1342
1343 sh->io_port = io_base;
1344
1345 if (!request_region(sh->io_port, 0xff, "qlogicisp")) {
1346 printk("qlogicisp : i/o region 0x%lx-0x%lx already "
1347 "in use\n",
1348 sh->io_port, sh->io_port + 0xff);
1349 return 1;
1350 }
1351
1352 if ((command & PCI_COMMAND_MEMORY) &&
1353 ((mem_flags & 1) == 0)) {
1354 hostdata->memaddr = ioremap(mem_base, PAGE_SIZE);
1355 if (!hostdata->memaddr) {
1356 printk("qlogicisp : i/o remapping failed.\n");
1357 goto out_release;
1358 }
1359 } else {
1360 if (command & PCI_COMMAND_IO && (io_flags & 3) != 1) {
1361 printk("qlogicisp : i/o mapping is disabled\n");
1362 goto out_release;
1363 }
1364 hostdata->memaddr = NULL; /* zero to signify no i/o mapping */
1365 mem_base = 0;
1366 }
1367
1368 if (revision != ISP1020_REV_ID)
1369 printk("qlogicisp : new isp1020 revision ID (%d)\n", revision);
1370
1371 if (isp_inw(sh, PCI_ID_LOW) != PCI_VENDOR_ID_QLOGIC
1372 || isp_inw(sh, PCI_ID_HIGH) != PCI_DEVICE_ID_QLOGIC_ISP1020)
1373 {
1374 printk("qlogicisp : can't decode %s address space 0x%lx\n",
1375 (io_base ? "I/O" : "MEM"),
1376 (io_base ? io_base : mem_base));
1377 goto out_unmap;
1378 }
1379
1380 hostdata->revision = revision;
1381
1382 sh->irq = irq;
1383 sh->max_id = MAX_TARGETS;
1384 sh->max_lun = MAX_LUNS;
1385
1386 hostdata->res_cpu = pci_alloc_consistent(hostdata->pci_dev,
1387 QSIZE(RES_QUEUE_LEN),
1388 &hostdata->res_dma);
1389 if (hostdata->res_cpu == NULL) {
1390 printk("qlogicisp : can't allocate response queue\n");
1391 goto out_unmap;
1392 }
1393
1394 hostdata->req_cpu = pci_alloc_consistent(hostdata->pci_dev,
1395 QSIZE(QLOGICISP_REQ_QUEUE_LEN),
1396 &hostdata->req_dma);
1397 if (hostdata->req_cpu == NULL) {
1398 pci_free_consistent(hostdata->pci_dev,
1399 QSIZE(RES_QUEUE_LEN),
1400 hostdata->res_cpu,
1401 hostdata->res_dma);
1402 printk("qlogicisp : can't allocate request queue\n");
1403 goto out_unmap;
1404 }
1405
1406 pci_set_master(pdev);
1407
1408 LEAVE("isp1020_init");
1409
1410 return 0;
1411
1412 out_unmap:
1413 iounmap(hostdata->memaddr);
1414 out_release:
1415 release_region(sh->io_port, 0xff);
1416 return 1;
1417 }
1418
1419
1420 #if USE_NVRAM_DEFAULTS
1421
1422 static int isp1020_get_defaults(struct Scsi_Host *host)
1423 {
1424 int i;
1425 u_short value;
1426 struct isp1020_hostdata *hostdata =
1427 (struct isp1020_hostdata *) host->hostdata;
1428
1429 ENTER("isp1020_get_defaults");
1430
1431 if (!isp1020_verify_nvram(host)) {
1432 printk("qlogicisp : nvram checksum failure\n");
1433 printk("qlogicisp : attempting to use default parameters\n");
1434 return isp1020_set_defaults(host);
1435 }
1436
1437 value = isp1020_read_nvram_word(host, 2);
1438 hostdata->host_param.fifo_threshold = (value >> 8) & 0x03;
1439 hostdata->host_param.host_adapter_enable = (value >> 11) & 0x01;
1440 hostdata->host_param.initiator_scsi_id = (value >> 12) & 0x0f;
1441
1442 value = isp1020_read_nvram_word(host, 3);
1443 hostdata->host_param.bus_reset_delay = value & 0xff;
1444 hostdata->host_param.retry_count = value >> 8;
1445
1446 value = isp1020_read_nvram_word(host, 4);
1447 hostdata->host_param.retry_delay = value & 0xff;
1448 hostdata->host_param.async_data_setup_time = (value >> 8) & 0x0f;
1449 hostdata->host_param.req_ack_active_negation = (value >> 12) & 0x01;
1450 hostdata->host_param.data_line_active_negation = (value >> 13) & 0x01;
1451 hostdata->host_param.data_dma_burst_enable = (value >> 14) & 0x01;
1452 hostdata->host_param.command_dma_burst_enable = (value >> 15);
1453
1454 value = isp1020_read_nvram_word(host, 5);
1455 hostdata->host_param.tag_aging = value & 0xff;
1456
1457 value = isp1020_read_nvram_word(host, 6);
1458 hostdata->host_param.selection_timeout = value & 0xffff;
1459
1460 value = isp1020_read_nvram_word(host, 7);
1461 hostdata->host_param.max_queue_depth = value & 0xffff;
1462
1463 #if DEBUG_ISP1020_SETUP
1464 printk("qlogicisp : fifo threshold=%d\n",
1465 hostdata->host_param.fifo_threshold);
1466 printk("qlogicisp : initiator scsi id=%d\n",
1467 hostdata->host_param.initiator_scsi_id);
1468 printk("qlogicisp : bus reset delay=%d\n",
1469 hostdata->host_param.bus_reset_delay);
1470 printk("qlogicisp : retry count=%d\n",
1471 hostdata->host_param.retry_count);
1472 printk("qlogicisp : retry delay=%d\n",
1473 hostdata->host_param.retry_delay);
1474 printk("qlogicisp : async data setup time=%d\n",
1475 hostdata->host_param.async_data_setup_time);
1476 printk("qlogicisp : req/ack active negation=%d\n",
1477 hostdata->host_param.req_ack_active_negation);
1478 printk("qlogicisp : data line active negation=%d\n",
1479 hostdata->host_param.data_line_active_negation);
1480 printk("qlogicisp : data DMA burst enable=%d\n",
1481 hostdata->host_param.data_dma_burst_enable);
1482 printk("qlogicisp : command DMA burst enable=%d\n",
1483 hostdata->host_param.command_dma_burst_enable);
1484 printk("qlogicisp : tag age limit=%d\n",
1485 hostdata->host_param.tag_aging);
1486 printk("qlogicisp : selection timeout limit=%d\n",
1487 hostdata->host_param.selection_timeout);
1488 printk("qlogicisp : max queue depth=%d\n",
1489 hostdata->host_param.max_queue_depth);
1490 #endif /* DEBUG_ISP1020_SETUP */
1491
1492 for (i = 0; i < MAX_TARGETS; i++) {
1493
1494 value = isp1020_read_nvram_word(host, 14 + i * 3);
1495 hostdata->dev_param[i].device_flags = value & 0xff;
1496 hostdata->dev_param[i].execution_throttle = value >> 8;
1497
1498 value = isp1020_read_nvram_word(host, 15 + i * 3);
1499 hostdata->dev_param[i].synchronous_period = value & 0xff;
1500 hostdata->dev_param[i].synchronous_offset = (value >> 8) & 0x0f;
1501 hostdata->dev_param[i].device_enable = (value >> 12) & 0x01;
1502
1503 #if DEBUG_ISP1020_SETUP
1504 printk("qlogicisp : target 0x%02x\n", i);
1505 printk("qlogicisp : device flags=0x%02x\n",
1506 hostdata->dev_param[i].device_flags);
1507 printk("qlogicisp : execution throttle=%d\n",
1508 hostdata->dev_param[i].execution_throttle);
1509 printk("qlogicisp : synchronous period=%d\n",
1510 hostdata->dev_param[i].synchronous_period);
1511 printk("qlogicisp : synchronous offset=%d\n",
1512 hostdata->dev_param[i].synchronous_offset);
1513 printk("qlogicisp : device enable=%d\n",
1514 hostdata->dev_param[i].device_enable);
1515 #endif /* DEBUG_ISP1020_SETUP */
1516 }
1517
1518 LEAVE("isp1020_get_defaults");
1519
1520 return 0;
1521 }
1522
1523
1524 #define ISP1020_NVRAM_LEN 0x40
1525 #define ISP1020_NVRAM_SIG1 0x5349
1526 #define ISP1020_NVRAM_SIG2 0x2050
1527
1528 static int isp1020_verify_nvram(struct Scsi_Host *host)
1529 {
1530 int i;
1531 u_short value;
1532 u_char checksum = 0;
1533
1534 for (i = 0; i < ISP1020_NVRAM_LEN; i++) {
1535 value = isp1020_read_nvram_word(host, i);
1536
1537 switch (i) {
1538 case 0:
1539 if (value != ISP1020_NVRAM_SIG1) return 0;
1540 break;
1541 case 1:
1542 if (value != ISP1020_NVRAM_SIG2) return 0;
1543 break;
1544 case 2:
1545 if ((value & 0xff) != 0x02) return 0;
1546 break;
1547 }
1548 checksum += value & 0xff;
1549 checksum += value >> 8;
1550 }
1551
1552 return (checksum == 0);
1553 }
1554
1555 #define NVRAM_DELAY() udelay(2) /* 2 microsecond delay */
1556
1557
1558 u_short isp1020_read_nvram_word(struct Scsi_Host *host, u_short byte)
1559 {
1560 int i;
1561 u_short value, output, input;
1562
1563 byte &= 0x3f; byte |= 0x0180;
1564
1565 for (i = 8; i >= 0; i--) {
1566 output = ((byte >> i) & 0x1) ? 0x4 : 0x0;
1567 isp_outw(output | 0x2, host, PCI_NVRAM); NVRAM_DELAY();
1568 isp_outw(output | 0x3, host, PCI_NVRAM); NVRAM_DELAY();
1569 isp_outw(output | 0x2, host, PCI_NVRAM); NVRAM_DELAY();
1570 }
1571
1572 for (i = 0xf, value = 0; i >= 0; i--) {
1573 value <<= 1;
1574 isp_outw(0x3, host, PCI_NVRAM); NVRAM_DELAY();
1575 input = isp_inw(host, PCI_NVRAM); NVRAM_DELAY();
1576 isp_outw(0x2, host, PCI_NVRAM); NVRAM_DELAY();
1577 if (input & 0x8) value |= 1;
1578 }
1579
1580 isp_outw(0x0, host, PCI_NVRAM); NVRAM_DELAY();
1581
1582 return value;
1583 }
1584
1585 #endif /* USE_NVRAM_DEFAULTS */
1586
1587
1588 static int isp1020_set_defaults(struct Scsi_Host *host)
1589 {
1590 struct isp1020_hostdata *hostdata =
1591 (struct isp1020_hostdata *) host->hostdata;
1592 int i;
1593
1594 ENTER("isp1020_set_defaults");
1595
1596 hostdata->host_param.fifo_threshold = 2;
1597 hostdata->host_param.host_adapter_enable = 1;
1598 hostdata->host_param.initiator_scsi_id = 7;
1599 hostdata->host_param.bus_reset_delay = 3;
1600 hostdata->host_param.retry_count = 0;
1601 hostdata->host_param.retry_delay = 1;
1602 hostdata->host_param.async_data_setup_time = 6;
1603 hostdata->host_param.req_ack_active_negation = 1;
1604 hostdata->host_param.data_line_active_negation = 1;
1605 hostdata->host_param.data_dma_burst_enable = 1;
1606 hostdata->host_param.command_dma_burst_enable = 1;
1607 hostdata->host_param.tag_aging = 8;
1608 hostdata->host_param.selection_timeout = 250;
1609 hostdata->host_param.max_queue_depth = 256;
1610
1611 for (i = 0; i < MAX_TARGETS; i++) {
1612 hostdata->dev_param[i].device_flags = 0xfd;
1613 hostdata->dev_param[i].execution_throttle = 16;
1614 hostdata->dev_param[i].synchronous_period = 25;
1615 hostdata->dev_param[i].synchronous_offset = 12;
1616 hostdata->dev_param[i].device_enable = 1;
1617 }
1618
1619 LEAVE("isp1020_set_defaults");
1620
1621 return 0;
1622 }
1623
1624
1625 static int isp1020_load_parameters(struct Scsi_Host *host)
1626 {
1627 int i, k;
1628 #ifdef CONFIG_QL_ISP_A64
1629 u_long queue_addr;
1630 u_short param[8];
1631 #else
1632 u_int queue_addr;
1633 u_short param[6];
1634 #endif
1635 u_short isp_cfg1, hwrev;
1636 struct isp1020_hostdata *hostdata =
1637 (struct isp1020_hostdata *) host->hostdata;
1638
1639 ENTER("isp1020_load_parameters");
1640
1641 hwrev = isp_inw(host, ISP_CFG0) & ISP_CFG0_HWMSK;
1642 isp_cfg1 = ISP_CFG1_F64 | ISP_CFG1_BENAB;
1643 if (hwrev == ISP_CFG0_1040A) {
1644 /* Busted fifo, says mjacob. */
1645 isp_cfg1 &= ISP_CFG1_BENAB;
1646 }
1647
1648 isp_outw(isp_inw(host, ISP_CFG1) | isp_cfg1, host, ISP_CFG1);
1649 isp_outw(isp_inw(host, CDMA_CONF) | DMA_CONF_BENAB, host, CDMA_CONF);
1650 isp_outw(isp_inw(host, DDMA_CONF) | DMA_CONF_BENAB, host, DDMA_CONF);
1651
1652 param[0] = MBOX_SET_INIT_SCSI_ID;
1653 param[1] = hostdata->host_param.initiator_scsi_id;
1654
1655 isp1020_mbox_command(host, param);
1656
1657 if (param[0] != MBOX_COMMAND_COMPLETE) {
1658 printk("qlogicisp : set initiator id failure\n");
1659 return 1;
1660 }
1661
1662 param[0] = MBOX_SET_RETRY_COUNT;
1663 param[1] = hostdata->host_param.retry_count;
1664 param[2] = hostdata->host_param.retry_delay;
1665
1666 isp1020_mbox_command(host, param);
1667
1668 if (param[0] != MBOX_COMMAND_COMPLETE) {
1669 printk("qlogicisp : set retry count failure\n");
1670 return 1;
1671 }
1672
1673 param[0] = MBOX_SET_ASYNC_DATA_SETUP_TIME;
1674 param[1] = hostdata->host_param.async_data_setup_time;
1675
1676 isp1020_mbox_command(host, param);
1677
1678 if (param[0] != MBOX_COMMAND_COMPLETE) {
1679 printk("qlogicisp : async data setup time failure\n");
1680 return 1;
1681 }
1682
1683 param[0] = MBOX_SET_ACTIVE_NEG_STATE;
1684 param[1] = (hostdata->host_param.req_ack_active_negation << 4)
1685 | (hostdata->host_param.data_line_active_negation << 5);
1686
1687 isp1020_mbox_command(host, param);
1688
1689 if (param[0] != MBOX_COMMAND_COMPLETE) {
1690 printk("qlogicisp : set active negation state failure\n");
1691 return 1;
1692 }
1693
1694 param[0] = MBOX_SET_PCI_CONTROL_PARAMS;
1695 param[1] = hostdata->host_param.data_dma_burst_enable << 1;
1696 param[2] = hostdata->host_param.command_dma_burst_enable << 1;
1697
1698 isp1020_mbox_command(host, param);
1699
1700 if (param[0] != MBOX_COMMAND_COMPLETE) {
1701 printk("qlogicisp : set pci control parameter failure\n");
1702 return 1;
1703 }
1704
1705 param[0] = MBOX_SET_TAG_AGE_LIMIT;
1706 param[1] = hostdata->host_param.tag_aging;
1707
1708 isp1020_mbox_command(host, param);
1709
1710 if (param[0] != MBOX_COMMAND_COMPLETE) {
1711 printk("qlogicisp : set tag age limit failure\n");
1712 return 1;
1713 }
1714
1715 param[0] = MBOX_SET_SELECT_TIMEOUT;
1716 param[1] = hostdata->host_param.selection_timeout;
1717
1718 isp1020_mbox_command(host, param);
1719
1720 if (param[0] != MBOX_COMMAND_COMPLETE) {
1721 printk("qlogicisp : set selection timeout failure\n");
1722 return 1;
1723 }
1724
1725 for (i = 0; i < MAX_TARGETS; i++) {
1726
1727 if (!hostdata->dev_param[i].device_enable)
1728 continue;
1729
1730 param[0] = MBOX_SET_TARGET_PARAMS;
1731 param[1] = i << 8;
1732 param[2] = hostdata->dev_param[i].device_flags << 8;
1733 param[3] = (hostdata->dev_param[i].synchronous_offset << 8)
1734 | hostdata->dev_param[i].synchronous_period;
1735
1736 isp1020_mbox_command(host, param);
1737
1738 if (param[0] != MBOX_COMMAND_COMPLETE) {
1739 printk("qlogicisp : set target parameter failure\n");
1740 return 1;
1741 }
1742
1743 for (k = 0; k < MAX_LUNS; k++) {
1744
1745 param[0] = MBOX_SET_DEV_QUEUE_PARAMS;
1746 param[1] = (i << 8) | k;
1747 param[2] = hostdata->host_param.max_queue_depth;
1748 param[3] = hostdata->dev_param[i].execution_throttle;
1749
1750 isp1020_mbox_command(host, param);
1751
1752 if (param[0] != MBOX_COMMAND_COMPLETE) {
1753 printk("qlogicisp : set device queue "
1754 "parameter failure\n");
1755 return 1;
1756 }
1757 }
1758 }
1759
1760 queue_addr = hostdata->res_dma;
1761 #ifdef CONFIG_QL_ISP_A64
1762 param[0] = MBOX_CMD_INIT_RESPONSE_QUEUE_64;
1763 #else
1764 param[0] = MBOX_INIT_RES_QUEUE;
1765 #endif
1766 param[1] = RES_QUEUE_LEN + 1;
1767 param[2] = (u_short) (queue_addr >> 16);
1768 param[3] = (u_short) (queue_addr & 0xffff);
1769 param[4] = 0;
1770 param[5] = 0;
1771 #ifdef CONFIG_QL_ISP_A64
1772 param[6] = (u_short) (queue_addr >> 48);
1773 param[7] = (u_short) (queue_addr >> 32);
1774 #endif
1775
1776 isp1020_mbox_command(host, param);
1777
1778 if (param[0] != MBOX_COMMAND_COMPLETE) {
1779 printk("qlogicisp : set response queue failure\n");
1780 return 1;
1781 }
1782
1783 queue_addr = hostdata->req_dma;
1784 #ifdef CONFIG_QL_ISP_A64
1785 param[0] = MBOX_CMD_INIT_REQUEST_QUEUE_64;
1786 #else
1787 param[0] = MBOX_INIT_REQ_QUEUE;
1788 #endif
1789 param[1] = QLOGICISP_REQ_QUEUE_LEN + 1;
1790 param[2] = (u_short) (queue_addr >> 16);
1791 param[3] = (u_short) (queue_addr & 0xffff);
1792 param[4] = 0;
1793
1794 #ifdef CONFIG_QL_ISP_A64
1795 param[5] = 0;
1796 param[6] = (u_short) (queue_addr >> 48);
1797 param[7] = (u_short) (queue_addr >> 32);
1798 #endif
1799
1800 isp1020_mbox_command(host, param);
1801
1802 if (param[0] != MBOX_COMMAND_COMPLETE) {
1803 printk("qlogicisp : set request queue failure\n");
1804 return 1;
1805 }
1806
1807 LEAVE("isp1020_load_parameters");
1808
1809 return 0;
1810 }
1811
1812
1813 /*
1814 * currently, this is only called during initialization or abort/reset,
1815 * at which times interrupts are disabled, so polling is OK, I guess...
1816 */
1817 static int isp1020_mbox_command(struct Scsi_Host *host, u_short param[])
1818 {
1819 int loop_count;
1820
1821 if (mbox_param[param[0]] == 0)
1822 return 1;
1823
1824 loop_count = DEFAULT_LOOP_COUNT;
1825 while (--loop_count && isp_inw(host, HOST_HCCR) & 0x0080) {
1826 barrier();
1827 cpu_relax();
1828 }
1829 if (!loop_count)
1830 printk("qlogicisp: mbox_command loop timeout #1\n");
1831
1832 switch(mbox_param[param[0]] >> 4) {
1833 case 8: isp_outw(param[7], host, MBOX7);
1834 case 7: isp_outw(param[6], host, MBOX6);
1835 case 6: isp_outw(param[5], host, MBOX5);
1836 case 5: isp_outw(param[4], host, MBOX4);
1837 case 4: isp_outw(param[3], host, MBOX3);
1838 case 3: isp_outw(param[2], host, MBOX2);
1839 case 2: isp_outw(param[1], host, MBOX1);
1840 case 1: isp_outw(param[0], host, MBOX0);
1841 }
1842
1843 isp_outw(0x0, host, PCI_SEMAPHORE);
1844 isp_outw(HCCR_CLEAR_RISC_INTR, host, HOST_HCCR);
1845 isp_outw(HCCR_SET_HOST_INTR, host, HOST_HCCR);
1846
1847 loop_count = DEFAULT_LOOP_COUNT;
1848 while (--loop_count && !(isp_inw(host, PCI_INTF_STS) & 0x04)) {
1849 barrier();
1850 cpu_relax();
1851 }
1852 if (!loop_count)
1853 printk("qlogicisp: mbox_command loop timeout #2\n");
1854
1855 loop_count = DEFAULT_LOOP_COUNT;
1856 while (--loop_count && isp_inw(host, MBOX0) == 0x04) {
1857 barrier();
1858 cpu_relax();
1859 }
1860 if (!loop_count)
1861 printk("qlogicisp: mbox_command loop timeout #3\n");
1862
1863 switch(mbox_param[param[0]] & 0xf) {
1864 case 8: param[7] = isp_inw(host, MBOX7);
1865 case 7: param[6] = isp_inw(host, MBOX6);
1866 case 6: param[5] = isp_inw(host, MBOX5);
1867 case 5: param[4] = isp_inw(host, MBOX4);
1868 case 4: param[3] = isp_inw(host, MBOX3);
1869 case 3: param[2] = isp_inw(host, MBOX2);
1870 case 2: param[1] = isp_inw(host, MBOX1);
1871 case 1: param[0] = isp_inw(host, MBOX0);
1872 }
1873
1874 isp_outw(0x0, host, PCI_SEMAPHORE);
1875 isp_outw(HCCR_CLEAR_RISC_INTR, host, HOST_HCCR);
1876
1877 return 0;
1878 }
1879
1880
1881 #if DEBUG_ISP1020_INTR
1882
1883 void isp1020_print_status_entry(struct Status_Entry *status)
1884 {
1885 int i;
1886
1887 printk("qlogicisp : entry count = 0x%02x, type = 0x%02x, flags = 0x%02x\n",
1888 status->hdr.entry_cnt, status->hdr.entry_type, status->hdr.flags);
1889 printk("qlogicisp : scsi status = 0x%04x, completion status = 0x%04x\n",
1890 le16_to_cpu(status->scsi_status), le16_to_cpu(status->completion_status));
1891 printk("qlogicisp : state flags = 0x%04x, status flags = 0x%04x\n",
1892 le16_to_cpu(status->state_flags), le16_to_cpu(status->status_flags));
1893 printk("qlogicisp : time = 0x%04x, request sense length = 0x%04x\n",
1894 le16_to_cpu(status->time), le16_to_cpu(status->req_sense_len));
1895 printk("qlogicisp : residual transfer length = 0x%08x\n",
1896 le32_to_cpu(status->residual));
1897
1898 for (i = 0; i < le16_to_cpu(status->req_sense_len); i++)
1899 printk("qlogicisp : sense data = 0x%02x\n", status->req_sense_data[i]);
1900 }
1901
1902 #endif /* DEBUG_ISP1020_INTR */
1903
1904
1905 #if DEBUG_ISP1020
1906
1907 void isp1020_print_scsi_cmd(Scsi_Cmnd *cmd)
1908 {
1909 int i;
1910
1911 printk("qlogicisp : target = 0x%02x, lun = 0x%02x, cmd_len = 0x%02x\n",
1912 cmd->target, cmd->lun, cmd->cmd_len);
1913 printk("qlogicisp : command = ");
1914 for (i = 0; i < cmd->cmd_len; i++)
1915 printk("0x%02x ", cmd->cmnd[i]);
1916 printk("\n");
1917 }
1918
1919 #endif /* DEBUG_ISP1020 */
1920
1921 MODULE_LICENSE("GPL");
1922
1923 static Scsi_Host_Template driver_template = {
1924 .detect = isp1020_detect,
1925 .release = isp1020_release,
1926 .info = isp1020_info,
1927 .queuecommand = isp1020_queuecommand,
1928 .bios_param = isp1020_biosparam,
1929 .can_queue = QLOGICISP_REQ_QUEUE_LEN,
1930 .this_id = -1,
1931 .sg_tablesize = QLOGICISP_MAX_SG(QLOGICISP_REQ_QUEUE_LEN),
1932 .cmd_per_lun = 1,
1933 .use_clustering = DISABLE_CLUSTERING,
1934 };
1935 #include "scsi_module.c"
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