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[TG3]: Set minimal hw interrupt mitigation.
[linux-2.6/verdex.git] / drivers / scsi / sata_qstor.c
blobdfd3621047171dc748ba9a11c82a418f89faaed6
1 /*
2 * sata_qstor.c - Pacific Digital Corporation QStor SATA
3 *
4 * Maintained by: Mark Lord <mlord@pobox.com>
5 *
6 * Copyright 2005 Pacific Digital Corporation.
7 * (OSL/GPL code release authorized by Jalil Fadavi).
8 *
9 * The contents of this file are subject to the Open
10 * Software License version 1.1 that can be found at
11 * http://www.opensource.org/licenses/osl-1.1.txt and is included herein
12 * by reference.
13 *
14 * Alternatively, the contents of this file may be used under the terms
15 * of the GNU General Public License version 2 (the "GPL") as distributed
16 * in the kernel source COPYING file, in which case the provisions of
17 * the GPL are applicable instead of the above. If you wish to allow
18 * the use of your version of this file only under the terms of the
19 * GPL and not to allow others to use your version of this file under
20 * the OSL, indicate your decision by deleting the provisions above and
21 * replace them with the notice and other provisions required by the GPL.
22 * If you do not delete the provisions above, a recipient may use your
23 * version of this file under either the OSL or the GPL.
24 *
25 */
26
27 #include <linux/kernel.h>
28 #include <linux/module.h>
29 #include <linux/pci.h>
30 #include <linux/init.h>
31 #include <linux/blkdev.h>
32 #include <linux/delay.h>
33 #include <linux/interrupt.h>
34 #include <linux/sched.h>
35 #include "scsi.h"
36 #include <scsi/scsi_host.h>
37 #include <asm/io.h>
38 #include <linux/libata.h>
39
40 #define DRV_NAME "sata_qstor"
41 #define DRV_VERSION "0.04"
42
43 enum {
44 QS_PORTS = 4,
45 QS_MAX_PRD = LIBATA_MAX_PRD,
46 QS_CPB_ORDER = 6,
47 QS_CPB_BYTES = (1 << QS_CPB_ORDER),
48 QS_PRD_BYTES = QS_MAX_PRD * 16,
49 QS_PKT_BYTES = QS_CPB_BYTES + QS_PRD_BYTES,
50
51 QS_DMA_BOUNDARY = ~0UL,
52
53 /* global register offsets */
54 QS_HCF_CNFG3 = 0x0003, /* host configuration offset */
55 QS_HID_HPHY = 0x0004, /* host physical interface info */
56 QS_HCT_CTRL = 0x00e4, /* global interrupt mask offset */
57 QS_HST_SFF = 0x0100, /* host status fifo offset */
58 QS_HVS_SERD3 = 0x0393, /* PHY enable offset */
59
60 /* global control bits */
61 QS_HPHY_64BIT = (1 << 1), /* 64-bit bus detected */
62 QS_CNFG3_GSRST = 0x01, /* global chip reset */
63 QS_SERD3_PHY_ENA = 0xf0, /* PHY detection ENAble*/
64
65 /* per-channel register offsets */
66 QS_CCF_CPBA = 0x0710, /* chan CPB base address */
67 QS_CCF_CSEP = 0x0718, /* chan CPB separation factor */
68 QS_CFC_HUFT = 0x0800, /* host upstream fifo threshold */
69 QS_CFC_HDFT = 0x0804, /* host downstream fifo threshold */
70 QS_CFC_DUFT = 0x0808, /* dev upstream fifo threshold */
71 QS_CFC_DDFT = 0x080c, /* dev downstream fifo threshold */
72 QS_CCT_CTR0 = 0x0900, /* chan control-0 offset */
73 QS_CCT_CTR1 = 0x0901, /* chan control-1 offset */
74 QS_CCT_CFF = 0x0a00, /* chan command fifo offset */
75
76 /* channel control bits */
77 QS_CTR0_REG = (1 << 1), /* register mode (vs. pkt mode) */
78 QS_CTR0_CLER = (1 << 2), /* clear channel errors */
79 QS_CTR1_RDEV = (1 << 1), /* sata phy/comms reset */
80 QS_CTR1_RCHN = (1 << 4), /* reset channel logic */
81 QS_CCF_RUN_PKT = 0x107, /* RUN a new dma PKT */
82
83 /* pkt sub-field headers */
84 QS_HCB_HDR = 0x01, /* Host Control Block header */
85 QS_DCB_HDR = 0x02, /* Device Control Block header */
86
87 /* pkt HCB flag bits */
88 QS_HF_DIRO = (1 << 0), /* data DIRection Out */
89 QS_HF_DAT = (1 << 3), /* DATa pkt */
90 QS_HF_IEN = (1 << 4), /* Interrupt ENable */
91 QS_HF_VLD = (1 << 5), /* VaLiD pkt */
92
93 /* pkt DCB flag bits */
94 QS_DF_PORD = (1 << 2), /* Pio OR Dma */
95 QS_DF_ELBA = (1 << 3), /* Extended LBA (lba48) */
96
97 /* PCI device IDs */
98 board_2068_idx = 0, /* QStor 4-port SATA/RAID */
99 };
100
101 typedef enum { qs_state_idle, qs_state_pkt, qs_state_mmio } qs_state_t;
102
103 struct qs_port_priv {
104 u8 *pkt;
105 dma_addr_t pkt_dma;
106 qs_state_t state;
107 };
108
109 static u32 qs_scr_read (struct ata_port *ap, unsigned int sc_reg);
110 static void qs_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
111 static int qs_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
112 static irqreturn_t qs_intr (int irq, void *dev_instance, struct pt_regs *regs);
113 static int qs_port_start(struct ata_port *ap);
114 static void qs_host_stop(struct ata_host_set *host_set);
115 static void qs_port_stop(struct ata_port *ap);
116 static void qs_phy_reset(struct ata_port *ap);
117 static void qs_qc_prep(struct ata_queued_cmd *qc);
118 static int qs_qc_issue(struct ata_queued_cmd *qc);
119 static int qs_check_atapi_dma(struct ata_queued_cmd *qc);
120 static void qs_bmdma_stop(struct ata_port *ap);
121 static u8 qs_bmdma_status(struct ata_port *ap);
122 static void qs_irq_clear(struct ata_port *ap);
123 static void qs_eng_timeout(struct ata_port *ap);
124
125 static Scsi_Host_Template qs_ata_sht = {
126 .module = THIS_MODULE,
127 .name = DRV_NAME,
128 .ioctl = ata_scsi_ioctl,
129 .queuecommand = ata_scsi_queuecmd,
130 .eh_strategy_handler = ata_scsi_error,
131 .can_queue = ATA_DEF_QUEUE,
132 .this_id = ATA_SHT_THIS_ID,
133 .sg_tablesize = QS_MAX_PRD,
134 .max_sectors = ATA_MAX_SECTORS,
135 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
136 .emulated = ATA_SHT_EMULATED,
137 //FIXME .use_clustering = ATA_SHT_USE_CLUSTERING,
138 .use_clustering = ENABLE_CLUSTERING,
139 .proc_name = DRV_NAME,
140 .dma_boundary = QS_DMA_BOUNDARY,
141 .slave_configure = ata_scsi_slave_config,
142 .bios_param = ata_std_bios_param,
143 };
144
145 static struct ata_port_operations qs_ata_ops = {
146 .port_disable = ata_port_disable,
147 .tf_load = ata_tf_load,
148 .tf_read = ata_tf_read,
149 .check_status = ata_check_status,
150 .check_atapi_dma = qs_check_atapi_dma,
151 .exec_command = ata_exec_command,
152 .dev_select = ata_std_dev_select,
153 .phy_reset = qs_phy_reset,
154 .qc_prep = qs_qc_prep,
155 .qc_issue = qs_qc_issue,
156 .eng_timeout = qs_eng_timeout,
157 .irq_handler = qs_intr,
158 .irq_clear = qs_irq_clear,
159 .scr_read = qs_scr_read,
160 .scr_write = qs_scr_write,
161 .port_start = qs_port_start,
162 .port_stop = qs_port_stop,
163 .host_stop = qs_host_stop,
164 .bmdma_stop = qs_bmdma_stop,
165 .bmdma_status = qs_bmdma_status,
166 };
167
168 static struct ata_port_info qs_port_info[] = {
169 /* board_2068_idx */
170 {
171 .sht = &qs_ata_sht,
172 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
173 ATA_FLAG_SATA_RESET |
174 //FIXME ATA_FLAG_SRST |
175 ATA_FLAG_MMIO,
176 .pio_mask = 0x10, /* pio4 */
177 .udma_mask = 0x7f, /* udma0-6 */
178 .port_ops = &qs_ata_ops,
179 },
180 };
181
182 static struct pci_device_id qs_ata_pci_tbl[] = {
183 { PCI_VENDOR_ID_PDC, 0x2068, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
184 board_2068_idx },
185
186 { } /* terminate list */
187 };
188
189 static struct pci_driver qs_ata_pci_driver = {
190 .name = DRV_NAME,
191 .id_table = qs_ata_pci_tbl,
192 .probe = qs_ata_init_one,
193 .remove = ata_pci_remove_one,
194 };
195
196 static int qs_check_atapi_dma(struct ata_queued_cmd *qc)
197 {
198 return 1; /* ATAPI DMA not supported */
199 }
200
201 static void qs_bmdma_stop(struct ata_port *ap)
202 {
203 /* nothing */
204 }
205
206 static u8 qs_bmdma_status(struct ata_port *ap)
207 {
208 return 0;
209 }
210
211 static void qs_irq_clear(struct ata_port *ap)
212 {
213 /* nothing */
214 }
215
216 static inline void qs_enter_reg_mode(struct ata_port *ap)
217 {
218 u8 __iomem *chan = ap->host_set->mmio_base + (ap->port_no * 0x4000);
219
220 writeb(QS_CTR0_REG, chan + QS_CCT_CTR0);
221 readb(chan + QS_CCT_CTR0); /* flush */
222 }
223
224 static inline void qs_reset_channel_logic(struct ata_port *ap)
225 {
226 u8 __iomem *chan = ap->host_set->mmio_base + (ap->port_no * 0x4000);
227
228 writeb(QS_CTR1_RCHN, chan + QS_CCT_CTR1);
229 readb(chan + QS_CCT_CTR0); /* flush */
230 qs_enter_reg_mode(ap);
231 }
232
233 static void qs_phy_reset(struct ata_port *ap)
234 {
235 struct qs_port_priv *pp = ap->private_data;
236
237 pp->state = qs_state_idle;
238 qs_reset_channel_logic(ap);
239 sata_phy_reset(ap);
240 }
241
242 static void qs_eng_timeout(struct ata_port *ap)
243 {
244 struct qs_port_priv *pp = ap->private_data;
245
246 if (pp->state != qs_state_idle) /* healthy paranoia */
247 pp->state = qs_state_mmio;
248 qs_reset_channel_logic(ap);
249 ata_eng_timeout(ap);
250 }
251
252 static u32 qs_scr_read (struct ata_port *ap, unsigned int sc_reg)
253 {
254 if (sc_reg > SCR_CONTROL)
255 return ~0U;
256 return readl((void __iomem *)(ap->ioaddr.scr_addr + (sc_reg * 8)));
257 }
258
259 static void qs_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val)
260 {
261 if (sc_reg > SCR_CONTROL)
262 return;
263 writel(val, (void __iomem *)(ap->ioaddr.scr_addr + (sc_reg * 8)));
264 }
265
266 static void qs_fill_sg(struct ata_queued_cmd *qc)
267 {
268 struct scatterlist *sg = qc->sg;
269 struct ata_port *ap = qc->ap;
270 struct qs_port_priv *pp = ap->private_data;
271 unsigned int nelem;
272 u8 *prd = pp->pkt + QS_CPB_BYTES;
273
274 assert(sg != NULL);
275 assert(qc->n_elem > 0);
276
277 for (nelem = 0; nelem < qc->n_elem; nelem++,sg++) {
278 u64 addr;
279 u32 len;
280
281 addr = sg_dma_address(sg);
282 *(__le64 *)prd = cpu_to_le64(addr);
283 prd += sizeof(u64);
284
285 len = sg_dma_len(sg);
286 *(__le32 *)prd = cpu_to_le32(len);
287 prd += sizeof(u64);
288
289 VPRINTK("PRD[%u] = (0x%llX, 0x%X)\n", nelem,
290 (unsigned long long)addr, len);
291 }
292 }
293
294 static void qs_qc_prep(struct ata_queued_cmd *qc)
295 {
296 struct qs_port_priv *pp = qc->ap->private_data;
297 u8 dflags = QS_DF_PORD, *buf = pp->pkt;
298 u8 hflags = QS_HF_DAT | QS_HF_IEN | QS_HF_VLD;
299 u64 addr;
300
301 VPRINTK("ENTER\n");
302
303 qs_enter_reg_mode(qc->ap);
304 if (qc->tf.protocol != ATA_PROT_DMA) {
305 ata_qc_prep(qc);
306 return;
307 }
308
309 qs_fill_sg(qc);
310
311 if ((qc->tf.flags & ATA_TFLAG_WRITE))
312 hflags |= QS_HF_DIRO;
313 if ((qc->tf.flags & ATA_TFLAG_LBA48))
314 dflags |= QS_DF_ELBA;
315
316 /* host control block (HCB) */
317 buf[ 0] = QS_HCB_HDR;
318 buf[ 1] = hflags;
319 *(__le32 *)(&buf[ 4]) = cpu_to_le32(qc->nsect * ATA_SECT_SIZE);
320 *(__le32 *)(&buf[ 8]) = cpu_to_le32(qc->n_elem);
321 addr = ((u64)pp->pkt_dma) + QS_CPB_BYTES;
322 *(__le64 *)(&buf[16]) = cpu_to_le64(addr);
323
324 /* device control block (DCB) */
325 buf[24] = QS_DCB_HDR;
326 buf[28] = dflags;
327
328 /* frame information structure (FIS) */
329 ata_tf_to_fis(&qc->tf, &buf[32], 0);
330 }
331
332 static inline void qs_packet_start(struct ata_queued_cmd *qc)
333 {
334 struct ata_port *ap = qc->ap;
335 u8 __iomem *chan = ap->host_set->mmio_base + (ap->port_no * 0x4000);
336
337 VPRINTK("ENTER, ap %p\n", ap);
338
339 writeb(QS_CTR0_CLER, chan + QS_CCT_CTR0);
340 wmb(); /* flush PRDs and pkt to memory */
341 writel(QS_CCF_RUN_PKT, chan + QS_CCT_CFF);
342 readl(chan + QS_CCT_CFF); /* flush */
343 }
344
345 static int qs_qc_issue(struct ata_queued_cmd *qc)
346 {
347 struct qs_port_priv *pp = qc->ap->private_data;
348
349 switch (qc->tf.protocol) {
350 case ATA_PROT_DMA:
351
352 pp->state = qs_state_pkt;
353 qs_packet_start(qc);
354 return 0;
355
356 case ATA_PROT_ATAPI_DMA:
357 BUG();
358 break;
359
360 default:
361 break;
362 }
363
364 pp->state = qs_state_mmio;
365 return ata_qc_issue_prot(qc);
366 }
367
368 static inline unsigned int qs_intr_pkt(struct ata_host_set *host_set)
369 {
370 unsigned int handled = 0;
371 u8 sFFE;
372 u8 __iomem *mmio_base = host_set->mmio_base;
373
374 do {
375 u32 sff0 = readl(mmio_base + QS_HST_SFF);
376 u32 sff1 = readl(mmio_base + QS_HST_SFF + 4);
377 u8 sEVLD = (sff1 >> 30) & 0x01; /* valid flag */
378 sFFE = sff1 >> 31; /* empty flag */
379
380 if (sEVLD) {
381 u8 sDST = sff0 >> 16; /* dev status */
382 u8 sHST = sff1 & 0x3f; /* host status */
383 unsigned int port_no = (sff1 >> 8) & 0x03;
384 struct ata_port *ap = host_set->ports[port_no];
385
386 DPRINTK("SFF=%08x%08x: sCHAN=%u sHST=%d sDST=%02x\n",
387 sff1, sff0, port_no, sHST, sDST);
388 handled = 1;
389 if (ap && (!(ap->flags & ATA_FLAG_PORT_DISABLED))) {
390 struct ata_queued_cmd *qc;
391 struct qs_port_priv *pp = ap->private_data;
392 if (!pp || pp->state != qs_state_pkt)
393 continue;
394 qc = ata_qc_from_tag(ap, ap->active_tag);
395 if (qc && (!(qc->tf.ctl & ATA_NIEN))) {
396 switch (sHST) {
397 case 0: /* sucessful CPB */
398 case 3: /* device error */
399 pp->state = qs_state_idle;
400 qs_enter_reg_mode(qc->ap);
401 ata_qc_complete(qc, sDST);
402 break;
403 default:
404 break;
405 }
406 }
407 }
408 }
409 } while (!sFFE);
410 return handled;
411 }
412
413 static inline unsigned int qs_intr_mmio(struct ata_host_set *host_set)
414 {
415 unsigned int handled = 0, port_no;
416
417 for (port_no = 0; port_no < host_set->n_ports; ++port_no) {
418 struct ata_port *ap;
419 ap = host_set->ports[port_no];
420 if (ap && (!(ap->flags & ATA_FLAG_PORT_DISABLED))) {
421 struct ata_queued_cmd *qc;
422 struct qs_port_priv *pp = ap->private_data;
423 if (!pp || pp->state != qs_state_mmio)
424 continue;
425 qc = ata_qc_from_tag(ap, ap->active_tag);
426 if (qc && (!(qc->tf.ctl & ATA_NIEN))) {
427
428 /* check main status, clearing INTRQ */
429 u8 status = ata_chk_status(ap);
430 if ((status & ATA_BUSY))
431 continue;
432 DPRINTK("ata%u: protocol %d (dev_stat 0x%X)\n",
433 ap->id, qc->tf.protocol, status);
434
435 /* complete taskfile transaction */
436 pp->state = qs_state_idle;
437 ata_qc_complete(qc, status);
438 handled = 1;
439 }
440 }
441 }
442 return handled;
443 }
444
445 static irqreturn_t qs_intr(int irq, void *dev_instance, struct pt_regs *regs)
446 {
447 struct ata_host_set *host_set = dev_instance;
448 unsigned int handled = 0;
449
450 VPRINTK("ENTER\n");
451
452 spin_lock(&host_set->lock);
453 handled = qs_intr_pkt(host_set) | qs_intr_mmio(host_set);
454 spin_unlock(&host_set->lock);
455
456 VPRINTK("EXIT\n");
457
458 return IRQ_RETVAL(handled);
459 }
460
461 static void qs_ata_setup_port(struct ata_ioports *port, unsigned long base)
462 {
463 port->cmd_addr =
464 port->data_addr = base + 0x400;
465 port->error_addr =
466 port->feature_addr = base + 0x408; /* hob_feature = 0x409 */
467 port->nsect_addr = base + 0x410; /* hob_nsect = 0x411 */
468 port->lbal_addr = base + 0x418; /* hob_lbal = 0x419 */
469 port->lbam_addr = base + 0x420; /* hob_lbam = 0x421 */
470 port->lbah_addr = base + 0x428; /* hob_lbah = 0x429 */
471 port->device_addr = base + 0x430;
472 port->status_addr =
473 port->command_addr = base + 0x438;
474 port->altstatus_addr =
475 port->ctl_addr = base + 0x440;
476 port->scr_addr = base + 0xc00;
477 }
478
479 static int qs_port_start(struct ata_port *ap)
480 {
481 struct device *dev = ap->host_set->dev;
482 struct qs_port_priv *pp;
483 void __iomem *mmio_base = ap->host_set->mmio_base;
484 void __iomem *chan = mmio_base + (ap->port_no * 0x4000);
485 u64 addr;
486 int rc;
487
488 rc = ata_port_start(ap);
489 if (rc)
490 return rc;
491 qs_enter_reg_mode(ap);
492 pp = kcalloc(1, sizeof(*pp), GFP_KERNEL);
493 if (!pp) {
494 rc = -ENOMEM;
495 goto err_out;
496 }
497 pp->pkt = dma_alloc_coherent(dev, QS_PKT_BYTES, &pp->pkt_dma,
498 GFP_KERNEL);
499 if (!pp->pkt) {
500 rc = -ENOMEM;
501 goto err_out_kfree;
502 }
503 memset(pp->pkt, 0, QS_PKT_BYTES);
504 ap->private_data = pp;
505
506 addr = (u64)pp->pkt_dma;
507 writel((u32) addr, chan + QS_CCF_CPBA);
508 writel((u32)(addr >> 32), chan + QS_CCF_CPBA + 4);
509 return 0;
510
511 err_out_kfree:
512 kfree(pp);
513 err_out:
514 ata_port_stop(ap);
515 return rc;
516 }
517
518 static void qs_port_stop(struct ata_port *ap)
519 {
520 struct device *dev = ap->host_set->dev;
521 struct qs_port_priv *pp = ap->private_data;
522
523 if (pp != NULL) {
524 ap->private_data = NULL;
525 if (pp->pkt != NULL)
526 dma_free_coherent(dev, QS_PKT_BYTES, pp->pkt,
527 pp->pkt_dma);
528 kfree(pp);
529 }
530 ata_port_stop(ap);
531 }
532
533 static void qs_host_stop(struct ata_host_set *host_set)
534 {
535 void __iomem *mmio_base = host_set->mmio_base;
536
537 writeb(0, mmio_base + QS_HCT_CTRL); /* disable host interrupts */
538 writeb(QS_CNFG3_GSRST, mmio_base + QS_HCF_CNFG3); /* global reset */
539 }
540
541 static void qs_host_init(unsigned int chip_id, struct ata_probe_ent *pe)
542 {
543 void __iomem *mmio_base = pe->mmio_base;
544 unsigned int port_no;
545
546 writeb(0, mmio_base + QS_HCT_CTRL); /* disable host interrupts */
547 writeb(QS_CNFG3_GSRST, mmio_base + QS_HCF_CNFG3); /* global reset */
548
549 /* reset each channel in turn */
550 for (port_no = 0; port_no < pe->n_ports; ++port_no) {
551 u8 __iomem *chan = mmio_base + (port_no * 0x4000);
552 writeb(QS_CTR1_RDEV|QS_CTR1_RCHN, chan + QS_CCT_CTR1);
553 writeb(QS_CTR0_REG, chan + QS_CCT_CTR0);
554 readb(chan + QS_CCT_CTR0); /* flush */
555 }
556 writeb(QS_SERD3_PHY_ENA, mmio_base + QS_HVS_SERD3); /* enable phy */
557
558 for (port_no = 0; port_no < pe->n_ports; ++port_no) {
559 u8 __iomem *chan = mmio_base + (port_no * 0x4000);
560 /* set FIFO depths to same settings as Windows driver */
561 writew(32, chan + QS_CFC_HUFT);
562 writew(32, chan + QS_CFC_HDFT);
563 writew(10, chan + QS_CFC_DUFT);
564 writew( 8, chan + QS_CFC_DDFT);
565 /* set CPB size in bytes, as a power of two */
566 writeb(QS_CPB_ORDER, chan + QS_CCF_CSEP);
567 }
568 writeb(1, mmio_base + QS_HCT_CTRL); /* enable host interrupts */
569 }
570
571 /*
572 * The QStor understands 64-bit buses, and uses 64-bit fields
573 * for DMA pointers regardless of bus width. We just have to
574 * make sure our DMA masks are set appropriately for whatever
575 * bridge lies between us and the QStor, and then the DMA mapping
576 * code will ensure we only ever "see" appropriate buffer addresses.
577 * If we're 32-bit limited somewhere, then our 64-bit fields will
578 * just end up with zeros in the upper 32-bits, without any special
579 * logic required outside of this routine (below).
580 */
581 static int qs_set_dma_masks(struct pci_dev *pdev, void __iomem *mmio_base)
582 {
583 u32 bus_info = readl(mmio_base + QS_HID_HPHY);
584 int rc, have_64bit_bus = (bus_info & QS_HPHY_64BIT);
585
586 if (have_64bit_bus &&
587 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
588 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
589 if (rc) {
590 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
591 if (rc) {
592 printk(KERN_ERR DRV_NAME
593 "(%s): 64-bit DMA enable failed\n",
594 pci_name(pdev));
595 return rc;
596 }
597 }
598 } else {
599 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
600 if (rc) {
601 printk(KERN_ERR DRV_NAME
602 "(%s): 32-bit DMA enable failed\n",
603 pci_name(pdev));
604 return rc;
605 }
606 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
607 if (rc) {
608 printk(KERN_ERR DRV_NAME
609 "(%s): 32-bit consistent DMA enable failed\n",
610 pci_name(pdev));
611 return rc;
612 }
613 }
614 return 0;
615 }
616
617 static int qs_ata_init_one(struct pci_dev *pdev,
618 const struct pci_device_id *ent)
619 {
620 static int printed_version;
621 struct ata_probe_ent *probe_ent = NULL;
622 void __iomem *mmio_base;
623 unsigned int board_idx = (unsigned int) ent->driver_data;
624 int rc, port_no;
625
626 if (!printed_version++)
627 printk(KERN_DEBUG DRV_NAME " version " DRV_VERSION "\n");
628
629 rc = pci_enable_device(pdev);
630 if (rc)
631 return rc;
632
633 rc = pci_request_regions(pdev, DRV_NAME);
634 if (rc)
635 goto err_out;
636
637 if ((pci_resource_flags(pdev, 4) & IORESOURCE_MEM) == 0) {
638 rc = -ENODEV;
639 goto err_out_regions;
640 }
641
642 mmio_base = ioremap(pci_resource_start(pdev, 4),
643 pci_resource_len(pdev, 4));
644 if (mmio_base == NULL) {
645 rc = -ENOMEM;
646 goto err_out_regions;
647 }
648
649 rc = qs_set_dma_masks(pdev, mmio_base);
650 if (rc)
651 goto err_out_iounmap;
652
653 probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
654 if (probe_ent == NULL) {
655 rc = -ENOMEM;
656 goto err_out_iounmap;
657 }
658
659 memset(probe_ent, 0, sizeof(*probe_ent));
660 probe_ent->dev = pci_dev_to_dev(pdev);
661 INIT_LIST_HEAD(&probe_ent->node);
662
663 probe_ent->sht = qs_port_info[board_idx].sht;
664 probe_ent->host_flags = qs_port_info[board_idx].host_flags;
665 probe_ent->pio_mask = qs_port_info[board_idx].pio_mask;
666 probe_ent->mwdma_mask = qs_port_info[board_idx].mwdma_mask;
667 probe_ent->udma_mask = qs_port_info[board_idx].udma_mask;
668 probe_ent->port_ops = qs_port_info[board_idx].port_ops;
669
670 probe_ent->irq = pdev->irq;
671 probe_ent->irq_flags = SA_SHIRQ;
672 probe_ent->mmio_base = mmio_base;
673 probe_ent->n_ports = QS_PORTS;
674
675 for (port_no = 0; port_no < probe_ent->n_ports; ++port_no) {
676 unsigned long chan = (unsigned long)mmio_base +
677 (port_no * 0x4000);
678 qs_ata_setup_port(&probe_ent->port[port_no], chan);
679 }
680
681 pci_set_master(pdev);
682
683 /* initialize adapter */
684 qs_host_init(board_idx, probe_ent);
685
686 rc = ata_device_add(probe_ent);
687 kfree(probe_ent);
688 if (rc != QS_PORTS)
689 goto err_out_iounmap;
690 return 0;
691
692 err_out_iounmap:
693 iounmap(mmio_base);
694 err_out_regions:
695 pci_release_regions(pdev);
696 err_out:
697 pci_disable_device(pdev);
698 return rc;
699 }
700
701 static int __init qs_ata_init(void)
702 {
703 return pci_module_init(&qs_ata_pci_driver);
704 }
705
706 static void __exit qs_ata_exit(void)
707 {
708 pci_unregister_driver(&qs_ata_pci_driver);
709 }
710
711 MODULE_AUTHOR("Mark Lord");
712 MODULE_DESCRIPTION("Pacific Digital Corporation QStor SATA low-level driver");
713 MODULE_LICENSE("GPL");
714 MODULE_DEVICE_TABLE(pci, qs_ata_pci_tbl);
715 MODULE_VERSION(DRV_VERSION);
716
717 module_init(qs_ata_init);
718 module_exit(qs_ata_exit);
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