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[TG3]: Set minimal hw interrupt mitigation.
[linux-2.6/verdex.git] / drivers / scsi / sym53c8xx_2 / sym_fw1.h
blobcdd92d82f4b26b4810ac315ff26e4b3817cb88fb
1 /*
2 * Device driver for the SYMBIOS/LSILOGIC 53C8XX and 53C1010 family
3 * of PCI-SCSI IO processors.
4 *
5 * Copyright (C) 1999-2001 Gerard Roudier <groudier@free.fr>
6 *
7 * This driver is derived from the Linux sym53c8xx driver.
8 * Copyright (C) 1998-2000 Gerard Roudier
9 *
10 * The sym53c8xx driver is derived from the ncr53c8xx driver that had been
11 * a port of the FreeBSD ncr driver to Linux-1.2.13.
12 *
13 * The original ncr driver has been written for 386bsd and FreeBSD by
14 * Wolfgang Stanglmeier <wolf@cologne.de>
15 * Stefan Esser <se@mi.Uni-Koeln.de>
16 * Copyright (C) 1994 Wolfgang Stanglmeier
17 *
18 * Other major contributions:
19 *
20 * NVRAM detection and reading.
21 * Copyright (C) 1997 Richard Waltham <dormouse@farsrobt.demon.co.uk>
22 *
23 *-----------------------------------------------------------------------------
24 *
25 * This program is free software; you can redistribute it and/or modify
26 * it under the terms of the GNU General Public License as published by
27 * the Free Software Foundation; either version 2 of the License, or
28 * (at your option) any later version.
29 *
30 * This program is distributed in the hope that it will be useful,
31 * but WITHOUT ANY WARRANTY; without even the implied warranty of
32 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
33 * GNU General Public License for more details.
34 *
35 * You should have received a copy of the GNU General Public License
36 * along with this program; if not, write to the Free Software
37 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
38 */
39
40 /*
41 * Scripts for SYMBIOS-Processor
42 *
43 * We have to know the offsets of all labels before we reach
44 * them (for forward jumps). Therefore we declare a struct
45 * here. If you make changes inside the script,
46 *
47 * DONT FORGET TO CHANGE THE LENGTHS HERE!
48 */
49
50 /*
51 * Script fragments which are loaded into the on-chip RAM
52 * of 825A, 875, 876, 895, 895A, 896 and 1010 chips.
53 * Must not exceed 4K bytes.
54 */
55 struct SYM_FWA_SCR {
56 u32 start [ 11];
57 u32 getjob_begin [ 4];
58 u32 _sms_a10 [ 5];
59 u32 getjob_end [ 4];
60 u32 _sms_a20 [ 4];
61 #ifdef SYM_CONF_TARGET_ROLE_SUPPORT
62 u32 select [ 8];
63 #else
64 u32 select [ 6];
65 #endif
66 u32 _sms_a30 [ 5];
67 u32 wf_sel_done [ 2];
68 u32 send_ident [ 2];
69 #ifdef SYM_CONF_IARB_SUPPORT
70 u32 select2 [ 8];
71 #else
72 u32 select2 [ 2];
73 #endif
74 u32 command [ 2];
75 u32 dispatch [ 28];
76 u32 sel_no_cmd [ 10];
77 u32 init [ 6];
78 u32 clrack [ 4];
79 u32 datai_done [ 11];
80 u32 datai_done_wsr [ 20];
81 u32 datao_done [ 11];
82 u32 datao_done_wss [ 6];
83 u32 datai_phase [ 5];
84 u32 datao_phase [ 5];
85 u32 msg_in [ 2];
86 u32 msg_in2 [ 10];
87 #ifdef SYM_CONF_IARB_SUPPORT
88 u32 status [ 14];
89 #else
90 u32 status [ 10];
91 #endif
92 u32 complete [ 6];
93 u32 complete2 [ 8];
94 u32 _sms_a40 [ 12];
95 u32 done [ 5];
96 u32 _sms_a50 [ 5];
97 u32 _sms_a60 [ 2];
98 u32 done_end [ 4];
99 u32 complete_error [ 5];
100 u32 save_dp [ 11];
101 u32 restore_dp [ 7];
102 u32 disconnect [ 11];
103 u32 disconnect2 [ 5];
104 u32 _sms_a65 [ 3];
105 #ifdef SYM_CONF_IARB_SUPPORT
106 u32 idle [ 4];
107 #else
108 u32 idle [ 2];
109 #endif
110 #ifdef SYM_CONF_IARB_SUPPORT
111 u32 ungetjob [ 7];
112 #else
113 u32 ungetjob [ 5];
114 #endif
115 #ifdef SYM_CONF_TARGET_ROLE_SUPPORT
116 u32 reselect [ 4];
117 #else
118 u32 reselect [ 2];
119 #endif
120 u32 reselected [ 19];
121 u32 _sms_a70 [ 6];
122 u32 _sms_a80 [ 4];
123 u32 reselected1 [ 25];
124 u32 _sms_a90 [ 4];
125 u32 resel_lun0 [ 7];
126 u32 _sms_a100 [ 4];
127 u32 resel_tag [ 8];
128 #if SYM_CONF_MAX_TASK*4 > 512
129 u32 _sms_a110 [ 23];
130 #elif SYM_CONF_MAX_TASK*4 > 256
131 u32 _sms_a110 [ 17];
132 #else
133 u32 _sms_a110 [ 13];
134 #endif
135 u32 _sms_a120 [ 2];
136 u32 resel_go [ 4];
137 u32 _sms_a130 [ 7];
138 u32 resel_dsa [ 2];
139 u32 resel_dsa1 [ 4];
140 u32 _sms_a140 [ 7];
141 u32 resel_no_tag [ 4];
142 u32 _sms_a145 [ 7];
143 u32 data_in [SYM_CONF_MAX_SG * 2];
144 u32 data_in2 [ 4];
145 u32 data_out [SYM_CONF_MAX_SG * 2];
146 u32 data_out2 [ 4];
147 u32 pm0_data [ 12];
148 u32 pm0_data_out [ 6];
149 u32 pm0_data_end [ 7];
150 u32 pm_data_end [ 4];
151 u32 _sms_a150 [ 4];
152 u32 pm1_data [ 12];
153 u32 pm1_data_out [ 6];
154 u32 pm1_data_end [ 9];
155 };
156
157 /*
158 * Script fragments which stay in main memory for all chips
159 * except for chips that support 8K on-chip RAM.
160 */
161 struct SYM_FWB_SCR {
162 u32 no_data [ 2];
163 #ifdef SYM_CONF_TARGET_ROLE_SUPPORT
164 u32 sel_for_abort [ 18];
165 #else
166 u32 sel_for_abort [ 16];
167 #endif
168 u32 sel_for_abort_1 [ 2];
169 u32 msg_in_etc [ 12];
170 u32 msg_received [ 5];
171 u32 msg_weird_seen [ 5];
172 u32 msg_extended [ 17];
173 u32 _sms_b10 [ 4];
174 u32 msg_bad [ 6];
175 u32 msg_weird [ 4];
176 u32 msg_weird1 [ 8];
177 u32 wdtr_resp [ 6];
178 u32 send_wdtr [ 4];
179 u32 sdtr_resp [ 6];
180 u32 send_sdtr [ 4];
181 u32 ppr_resp [ 6];
182 u32 send_ppr [ 4];
183 u32 nego_bad_phase [ 4];
184 u32 msg_out [ 4];
185 u32 msg_out_done [ 4];
186 u32 data_ovrun [ 3];
187 u32 data_ovrun1 [ 22];
188 u32 data_ovrun2 [ 8];
189 u32 abort_resel [ 16];
190 u32 resend_ident [ 4];
191 u32 ident_break [ 4];
192 u32 ident_break_atn [ 4];
193 u32 sdata_in [ 6];
194 u32 resel_bad_lun [ 4];
195 u32 bad_i_t_l [ 4];
196 u32 bad_i_t_l_q [ 4];
197 u32 bad_status [ 7];
198 u32 wsr_ma_helper [ 4];
199
200 #ifdef SYM_OPT_HANDLE_DIR_UNKNOWN
201 /* Unknown direction handling */
202 u32 data_io [ 2];
203 u32 data_io_com [ 8];
204 u32 data_io_out [ 7];
205 #endif
206 /* Data area */
207 u32 zero [ 1];
208 u32 scratch [ 1];
209 u32 scratch1 [ 1];
210 u32 prev_done [ 1];
211 u32 done_pos [ 1];
212 u32 nextjob [ 1];
213 u32 startpos [ 1];
214 u32 targtbl [ 1];
215 };
216
217 /*
218 * Script fragments used at initialisations.
219 * Only runs out of main memory.
220 */
221 struct SYM_FWZ_SCR {
222 u32 snooptest [ 9];
223 u32 snoopend [ 2];
224 };
225
226 static struct SYM_FWA_SCR SYM_FWA_SCR = {
227 /*--------------------------< START >----------------------------*/ {
228 /*
229 * Switch the LED on.
230 * Will be patched with a NO_OP if LED
231 * not needed or not desired.
232 */
233 SCR_REG_REG (gpreg, SCR_AND, 0xfe),
234 0,
235 /*
236 * Clear SIGP.
237 */
238 SCR_FROM_REG (ctest2),
239 0,
240 /*
241 * Stop here if the C code wants to perform
242 * some error recovery procedure manually.
243 * (Indicate this by setting SEM in ISTAT)
244 */
245 SCR_FROM_REG (istat),
246 0,
247 /*
248 * Report to the C code the next position in
249 * the start queue the SCRIPTS will schedule.
250 * The C code must not change SCRATCHA.
251 */
252 SCR_COPY (4),
253 PADDR_B (startpos),
254 RADDR_1 (scratcha),
255 SCR_INT ^ IFTRUE (MASK (SEM, SEM)),
256 SIR_SCRIPT_STOPPED,
257 /*
258 * Start the next job.
259 *
260 * @DSA = start point for this job.
261 * SCRATCHA = address of this job in the start queue.
262 *
263 * We will restore startpos with SCRATCHA if we fails the
264 * arbitration or if it is the idle job.
265 *
266 * The below GETJOB_BEGIN to GETJOB_END section of SCRIPTS
267 * is a critical path. If it is partially executed, it then
268 * may happen that the job address is not yet in the DSA
269 * and the next queue position points to the next JOB.
270 */
271 }/*-------------------------< GETJOB_BEGIN >---------------------*/,{
272 /*
273 * Copy to a fixed location both the next STARTPOS
274 * and the current JOB address, using self modifying
275 * SCRIPTS.
276 */
277 SCR_COPY (4),
278 RADDR_1 (scratcha),
279 PADDR_A (_sms_a10),
280 SCR_COPY (8),
281 }/*-------------------------< _SMS_A10 >-------------------------*/,{
282 0,
283 PADDR_B (nextjob),
284 /*
285 * Move the start address to TEMP using self-
286 * modifying SCRIPTS and jump indirectly to
287 * that address.
288 */
289 SCR_COPY (4),
290 PADDR_B (nextjob),
291 RADDR_1 (dsa),
292 }/*-------------------------< GETJOB_END >-----------------------*/,{
293 SCR_COPY (4),
294 RADDR_1 (dsa),
295 PADDR_A (_sms_a20),
296 SCR_COPY (4),
297 }/*-------------------------< _SMS_A20 >-------------------------*/,{
298 0,
299 RADDR_1 (temp),
300 SCR_RETURN,
301 0,
302 }/*-------------------------< SELECT >---------------------------*/,{
303 /*
304 * DSA contains the address of a scheduled
305 * data structure.
306 *
307 * SCRATCHA contains the address of the start queue
308 * entry which points to the next job.
309 *
310 * Set Initiator mode.
311 *
312 * (Target mode is left as an exercise for the reader)
313 */
314 #ifdef SYM_CONF_TARGET_ROLE_SUPPORT
315 SCR_CLR (SCR_TRG),
316 0,
317 #endif
318 /*
319 * And try to select this target.
320 */
321 SCR_SEL_TBL_ATN ^ offsetof (struct sym_dsb, select),
322 PADDR_A (ungetjob),
323 /*
324 * Now there are 4 possibilities:
325 *
326 * (1) The chip loses arbitration.
327 * This is ok, because it will try again,
328 * when the bus becomes idle.
329 * (But beware of the timeout function!)
330 *
331 * (2) The chip is reselected.
332 * Then the script processor takes the jump
333 * to the RESELECT label.
334 *
335 * (3) The chip wins arbitration.
336 * Then it will execute SCRIPTS instruction until
337 * the next instruction that checks SCSI phase.
338 * Then will stop and wait for selection to be
339 * complete or selection time-out to occur.
340 *
341 * After having won arbitration, the SCRIPTS
342 * processor is able to execute instructions while
343 * the SCSI core is performing SCSI selection.
344 */
345
346 /*
347 * Copy the CCB header to a fixed location
348 * in the HCB using self-modifying SCRIPTS.
349 */
350 SCR_COPY (4),
351 RADDR_1 (dsa),
352 PADDR_A (_sms_a30),
353 SCR_COPY (sizeof(struct sym_ccbh)),
354 }/*-------------------------< _SMS_A30 >-------------------------*/,{
355 0,
356 HADDR_1 (ccb_head),
357 /*
358 * Initialize the status register
359 */
360 SCR_COPY (4),
361 HADDR_1 (ccb_head.status),
362 RADDR_1 (scr0),
363 }/*-------------------------< WF_SEL_DONE >----------------------*/,{
364 SCR_INT ^ IFFALSE (WHEN (SCR_MSG_OUT)),
365 SIR_SEL_ATN_NO_MSG_OUT,
366 }/*-------------------------< SEND_IDENT >-----------------------*/,{
367 /*
368 * Selection complete.
369 * Send the IDENTIFY and possibly the TAG message
370 * and negotiation message if present.
371 */
372 SCR_MOVE_TBL ^ SCR_MSG_OUT,
373 offsetof (struct sym_dsb, smsg),
374 }/*-------------------------< SELECT2 >--------------------------*/,{
375 #ifdef SYM_CONF_IARB_SUPPORT
376 /*
377 * Set IMMEDIATE ARBITRATION if we have been given
378 * a hint to do so. (Some job to do after this one).
379 */
380 SCR_FROM_REG (HF_REG),
381 0,
382 SCR_JUMPR ^ IFFALSE (MASK (HF_HINT_IARB, HF_HINT_IARB)),
383 8,
384 SCR_REG_REG (scntl1, SCR_OR, IARB),
385 0,
386 #endif
387 /*
388 * Anticipate the COMMAND phase.
389 * This is the PHASE we expect at this point.
390 */
391 SCR_JUMP ^ IFFALSE (WHEN (SCR_COMMAND)),
392 PADDR_A (sel_no_cmd),
393 }/*-------------------------< COMMAND >--------------------------*/,{
394 /*
395 * ... and send the command
396 */
397 SCR_MOVE_TBL ^ SCR_COMMAND,
398 offsetof (struct sym_dsb, cmd),
399 }/*-------------------------< DISPATCH >-------------------------*/,{
400 /*
401 * MSG_IN is the only phase that shall be
402 * entered at least once for each (re)selection.
403 * So we test it first.
404 */
405 SCR_JUMP ^ IFTRUE (WHEN (SCR_MSG_IN)),
406 PADDR_A (msg_in),
407 SCR_JUMP ^ IFTRUE (IF (SCR_DATA_OUT)),
408 PADDR_A (datao_phase),
409 SCR_JUMP ^ IFTRUE (IF (SCR_DATA_IN)),
410 PADDR_A (datai_phase),
411 SCR_JUMP ^ IFTRUE (IF (SCR_STATUS)),
412 PADDR_A (status),
413 SCR_JUMP ^ IFTRUE (IF (SCR_COMMAND)),
414 PADDR_A (command),
415 SCR_JUMP ^ IFTRUE (IF (SCR_MSG_OUT)),
416 PADDR_B (msg_out),
417 /*
418 * Discard as many illegal phases as
419 * required and tell the C code about.
420 */
421 SCR_JUMPR ^ IFFALSE (WHEN (SCR_ILG_OUT)),
422 16,
423 SCR_MOVE_ABS (1) ^ SCR_ILG_OUT,
424 HADDR_1 (scratch),
425 SCR_JUMPR ^ IFTRUE (WHEN (SCR_ILG_OUT)),
426 -16,
427 SCR_JUMPR ^ IFFALSE (WHEN (SCR_ILG_IN)),
428 16,
429 SCR_MOVE_ABS (1) ^ SCR_ILG_IN,
430 HADDR_1 (scratch),
431 SCR_JUMPR ^ IFTRUE (WHEN (SCR_ILG_IN)),
432 -16,
433 SCR_INT,
434 SIR_BAD_PHASE,
435 SCR_JUMP,
436 PADDR_A (dispatch),
437 }/*-------------------------< SEL_NO_CMD >-----------------------*/,{
438 /*
439 * The target does not switch to command
440 * phase after IDENTIFY has been sent.
441 *
442 * If it stays in MSG OUT phase send it
443 * the IDENTIFY again.
444 */
445 SCR_JUMP ^ IFTRUE (WHEN (SCR_MSG_OUT)),
446 PADDR_B (resend_ident),
447 /*
448 * If target does not switch to MSG IN phase
449 * and we sent a negotiation, assert the
450 * failure immediately.
451 */
452 SCR_JUMP ^ IFTRUE (WHEN (SCR_MSG_IN)),
453 PADDR_A (dispatch),
454 SCR_FROM_REG (HS_REG),
455 0,
456 SCR_INT ^ IFTRUE (DATA (HS_NEGOTIATE)),
457 SIR_NEGO_FAILED,
458 /*
459 * Jump to dispatcher.
460 */
461 SCR_JUMP,
462 PADDR_A (dispatch),
463 }/*-------------------------< INIT >-----------------------------*/,{
464 /*
465 * Wait for the SCSI RESET signal to be
466 * inactive before restarting operations,
467 * since the chip may hang on SEL_ATN
468 * if SCSI RESET is active.
469 */
470 SCR_FROM_REG (sstat0),
471 0,
472 SCR_JUMPR ^ IFTRUE (MASK (IRST, IRST)),
473 -16,
474 SCR_JUMP,
475 PADDR_A (start),
476 }/*-------------------------< CLRACK >---------------------------*/,{
477 /*
478 * Terminate possible pending message phase.
479 */
480 SCR_CLR (SCR_ACK),
481 0,
482 SCR_JUMP,
483 PADDR_A (dispatch),
484 }/*-------------------------< DATAI_DONE >-----------------------*/,{
485 /*
486 * Save current pointer to LASTP.
487 */
488 SCR_COPY (4),
489 RADDR_1 (temp),
490 HADDR_1 (ccb_head.lastp),
491 /*
492 * If the SWIDE is not full, jump to dispatcher.
493 * We anticipate a STATUS phase.
494 */
495 SCR_FROM_REG (scntl2),
496 0,
497 SCR_JUMP ^ IFTRUE (MASK (WSR, WSR)),
498 PADDR_A (datai_done_wsr),
499 SCR_JUMP ^ IFTRUE (WHEN (SCR_STATUS)),
500 PADDR_A (status),
501 SCR_JUMP,
502 PADDR_A (dispatch),
503 }/*-------------------------< DATAI_DONE_WSR >-------------------*/,{
504 /*
505 * The SWIDE is full.
506 * Clear this condition.
507 */
508 SCR_REG_REG (scntl2, SCR_OR, WSR),
509 0,
510 /*
511 * We are expecting an IGNORE RESIDUE message
512 * from the device, otherwise we are in data
513 * overrun condition. Check against MSG_IN phase.
514 */
515 SCR_INT ^ IFFALSE (WHEN (SCR_MSG_IN)),
516 SIR_SWIDE_OVERRUN,
517 SCR_JUMP ^ IFFALSE (WHEN (SCR_MSG_IN)),
518 PADDR_A (dispatch),
519 /*
520 * We are in MSG_IN phase,
521 * Read the first byte of the message.
522 * If it is not an IGNORE RESIDUE message,
523 * signal overrun and jump to message
524 * processing.
525 */
526 SCR_MOVE_ABS (1) ^ SCR_MSG_IN,
527 HADDR_1 (msgin[0]),
528 SCR_INT ^ IFFALSE (DATA (M_IGN_RESIDUE)),
529 SIR_SWIDE_OVERRUN,
530 SCR_JUMP ^ IFFALSE (DATA (M_IGN_RESIDUE)),
531 PADDR_A (msg_in2),
532 /*
533 * We got the message we expected.
534 * Read the 2nd byte, and jump to dispatcher.
535 */
536 SCR_CLR (SCR_ACK),
537 0,
538 SCR_MOVE_ABS (1) ^ SCR_MSG_IN,
539 HADDR_1 (msgin[1]),
540 SCR_CLR (SCR_ACK),
541 0,
542 SCR_JUMP,
543 PADDR_A (dispatch),
544 }/*-------------------------< DATAO_DONE >-----------------------*/,{
545 /*
546 * Save current pointer to LASTP.
547 */
548 SCR_COPY (4),
549 RADDR_1 (temp),
550 HADDR_1 (ccb_head.lastp),
551 /*
552 * If the SODL is not full jump to dispatcher.
553 * We anticipate a STATUS phase.
554 */
555 SCR_FROM_REG (scntl2),
556 0,
557 SCR_JUMP ^ IFTRUE (MASK (WSS, WSS)),
558 PADDR_A (datao_done_wss),
559 SCR_JUMP ^ IFTRUE (WHEN (SCR_STATUS)),
560 PADDR_A (status),
561 SCR_JUMP,
562 PADDR_A (dispatch),
563 }/*-------------------------< DATAO_DONE_WSS >-------------------*/,{
564 /*
565 * The SODL is full, clear this condition.
566 */
567 SCR_REG_REG (scntl2, SCR_OR, WSS),
568 0,
569 /*
570 * And signal a DATA UNDERRUN condition
571 * to the C code.
572 */
573 SCR_INT,
574 SIR_SODL_UNDERRUN,
575 SCR_JUMP,
576 PADDR_A (dispatch),
577 }/*-------------------------< DATAI_PHASE >----------------------*/,{
578 /*
579 * Jump to current pointer.
580 */
581 SCR_COPY (4),
582 HADDR_1 (ccb_head.lastp),
583 RADDR_1 (temp),
584 SCR_RETURN,
585 0,
586 }/*-------------------------< DATAO_PHASE >----------------------*/,{
587 /*
588 * Jump to current pointer.
589 */
590 SCR_COPY (4),
591 HADDR_1 (ccb_head.lastp),
592 RADDR_1 (temp),
593 SCR_RETURN,
594 0,
595 }/*-------------------------< MSG_IN >---------------------------*/,{
596 /*
597 * Get the first byte of the message.
598 *
599 * The script processor doesn't negate the
600 * ACK signal after this transfer.
601 */
602 SCR_MOVE_ABS (1) ^ SCR_MSG_IN,
603 HADDR_1 (msgin[0]),
604 }/*-------------------------< MSG_IN2 >--------------------------*/,{
605 /*
606 * Check first against 1 byte messages
607 * that we handle from SCRIPTS.
608 */
609 SCR_JUMP ^ IFTRUE (DATA (M_COMPLETE)),
610 PADDR_A (complete),
611 SCR_JUMP ^ IFTRUE (DATA (M_DISCONNECT)),
612 PADDR_A (disconnect),
613 SCR_JUMP ^ IFTRUE (DATA (M_SAVE_DP)),
614 PADDR_A (save_dp),
615 SCR_JUMP ^ IFTRUE (DATA (M_RESTORE_DP)),
616 PADDR_A (restore_dp),
617 /*
618 * We handle all other messages from the
619 * C code, so no need to waste on-chip RAM
620 * for those ones.
621 */
622 SCR_JUMP,
623 PADDR_B (msg_in_etc),
624 }/*-------------------------< STATUS >---------------------------*/,{
625 /*
626 * get the status
627 */
628 SCR_MOVE_ABS (1) ^ SCR_STATUS,
629 HADDR_1 (scratch),
630 #ifdef SYM_CONF_IARB_SUPPORT
631 /*
632 * If STATUS is not GOOD, clear IMMEDIATE ARBITRATION,
633 * since we may have to tamper the start queue from
634 * the C code.
635 */
636 SCR_JUMPR ^ IFTRUE (DATA (S_GOOD)),
637 8,
638 SCR_REG_REG (scntl1, SCR_AND, ~IARB),
639 0,
640 #endif
641 /*
642 * save status to scsi_status.
643 * mark as complete.
644 */
645 SCR_TO_REG (SS_REG),
646 0,
647 SCR_LOAD_REG (HS_REG, HS_COMPLETE),
648 0,
649 /*
650 * Anticipate the MESSAGE PHASE for
651 * the TASK COMPLETE message.
652 */
653 SCR_JUMP ^ IFTRUE (WHEN (SCR_MSG_IN)),
654 PADDR_A (msg_in),
655 SCR_JUMP,
656 PADDR_A (dispatch),
657 }/*-------------------------< COMPLETE >-------------------------*/,{
658 /*
659 * Complete message.
660 *
661 * When we terminate the cycle by clearing ACK,
662 * the target may disconnect immediately.
663 *
664 * We don't want to be told of an "unexpected disconnect",
665 * so we disable this feature.
666 */
667 SCR_REG_REG (scntl2, SCR_AND, 0x7f),
668 0,
669 /*
670 * Terminate cycle ...
671 */
672 SCR_CLR (SCR_ACK|SCR_ATN),
673 0,
674 /*
675 * ... and wait for the disconnect.
676 */
677 SCR_WAIT_DISC,
678 0,
679 }/*-------------------------< COMPLETE2 >------------------------*/,{
680 /*
681 * Save host status.
682 */
683 SCR_COPY (4),
684 RADDR_1 (scr0),
685 HADDR_1 (ccb_head.status),
686 /*
687 * Move back the CCB header using self-modifying
688 * SCRIPTS.
689 */
690 SCR_COPY (4),
691 RADDR_1 (dsa),
692 PADDR_A (_sms_a40),
693 SCR_COPY (sizeof(struct sym_ccbh)),
694 HADDR_1 (ccb_head),
695 }/*-------------------------< _SMS_A40 >-------------------------*/,{
696 0,
697 /*
698 * Some bridges may reorder DMA writes to memory.
699 * We donnot want the CPU to deal with completions
700 * without all the posted write having been flushed
701 * to memory. This DUMMY READ should flush posted
702 * buffers prior to the CPU having to deal with
703 * completions.
704 */
705 SCR_COPY (4), /* DUMMY READ */
706 HADDR_1 (ccb_head.status),
707 RADDR_1 (scr0),
708 /*
709 * If command resulted in not GOOD status,
710 * call the C code if needed.
711 */
712 SCR_FROM_REG (SS_REG),
713 0,
714 SCR_CALL ^ IFFALSE (DATA (S_GOOD)),
715 PADDR_B (bad_status),
716 /*
717 * If we performed an auto-sense, call
718 * the C code to synchronyze task aborts
719 * with UNIT ATTENTION conditions.
720 */
721 SCR_FROM_REG (HF_REG),
722 0,
723 SCR_JUMP ^ IFFALSE (MASK (0 ,(HF_SENSE|HF_EXT_ERR))),
724 PADDR_A (complete_error),
725 }/*-------------------------< DONE >-----------------------------*/,{
726 /*
727 * Copy the DSA to the DONE QUEUE and
728 * signal completion to the host.
729 * If we are interrupted between DONE
730 * and DONE_END, we must reset, otherwise
731 * the completed CCB may be lost.
732 */
733 SCR_COPY (4),
734 PADDR_B (done_pos),
735 PADDR_A (_sms_a50),
736 SCR_COPY (4),
737 RADDR_1 (dsa),
738 }/*-------------------------< _SMS_A50 >-------------------------*/,{
739 0,
740 SCR_COPY (4),
741 PADDR_B (done_pos),
742 PADDR_A (_sms_a60),
743 /*
744 * The instruction below reads the DONE QUEUE next
745 * free position from memory.
746 * In addition it ensures that all PCI posted writes
747 * are flushed and so the DSA value of the done
748 * CCB is visible by the CPU before INTFLY is raised.
749 */
750 SCR_COPY (8),
751 }/*-------------------------< _SMS_A60 >-------------------------*/,{
752 0,
753 PADDR_B (prev_done),
754 }/*-------------------------< DONE_END >-------------------------*/,{
755 SCR_INT_FLY,
756 0,
757 SCR_JUMP,
758 PADDR_A (start),
759 }/*-------------------------< COMPLETE_ERROR >-------------------*/,{
760 SCR_COPY (4),
761 PADDR_B (startpos),
762 RADDR_1 (scratcha),
763 SCR_INT,
764 SIR_COMPLETE_ERROR,
765 }/*-------------------------< SAVE_DP >--------------------------*/,{
766 /*
767 * Clear ACK immediately.
768 * No need to delay it.
769 */
770 SCR_CLR (SCR_ACK),
771 0,
772 /*
773 * Keep track we received a SAVE DP, so
774 * we will switch to the other PM context
775 * on the next PM since the DP may point
776 * to the current PM context.
777 */
778 SCR_REG_REG (HF_REG, SCR_OR, HF_DP_SAVED),
779 0,
780 /*
781 * SAVE_DP message:
782 * Copy LASTP to SAVEP.
783 */
784 SCR_COPY (4),
785 HADDR_1 (ccb_head.lastp),
786 HADDR_1 (ccb_head.savep),
787 /*
788 * Anticipate the MESSAGE PHASE for
789 * the DISCONNECT message.
790 */
791 SCR_JUMP ^ IFTRUE (WHEN (SCR_MSG_IN)),
792 PADDR_A (msg_in),
793 SCR_JUMP,
794 PADDR_A (dispatch),
795 }/*-------------------------< RESTORE_DP >-----------------------*/,{
796 /*
797 * Clear ACK immediately.
798 * No need to delay it.
799 */
800 SCR_CLR (SCR_ACK),
801 0,
802 /*
803 * Copy SAVEP to LASTP.
804 */
805 SCR_COPY (4),
806 HADDR_1 (ccb_head.savep),
807 HADDR_1 (ccb_head.lastp),
808 SCR_JUMP,
809 PADDR_A (dispatch),
810 }/*-------------------------< DISCONNECT >-----------------------*/,{
811 /*
812 * DISCONNECTing ...
813 *
814 * disable the "unexpected disconnect" feature,
815 * and remove the ACK signal.
816 */
817 SCR_REG_REG (scntl2, SCR_AND, 0x7f),
818 0,
819 SCR_CLR (SCR_ACK|SCR_ATN),
820 0,
821 /*
822 * Wait for the disconnect.
823 */
824 SCR_WAIT_DISC,
825 0,
826 /*
827 * Status is: DISCONNECTED.
828 */
829 SCR_LOAD_REG (HS_REG, HS_DISCONNECT),
830 0,
831 /*
832 * Save host status.
833 */
834 SCR_COPY (4),
835 RADDR_1 (scr0),
836 HADDR_1 (ccb_head.status),
837 }/*-------------------------< DISCONNECT2 >----------------------*/,{
838 /*
839 * Move back the CCB header using self-modifying
840 * SCRIPTS.
841 */
842 SCR_COPY (4),
843 RADDR_1 (dsa),
844 PADDR_A (_sms_a65),
845 SCR_COPY (sizeof(struct sym_ccbh)),
846 HADDR_1 (ccb_head),
847 }/*-------------------------< _SMS_A65 >-------------------------*/,{
848 0,
849 SCR_JUMP,
850 PADDR_A (start),
851 }/*-------------------------< IDLE >-----------------------------*/,{
852 /*
853 * Nothing to do?
854 * Switch the LED off and wait for reselect.
855 * Will be patched with a NO_OP if LED
856 * not needed or not desired.
857 */
858 SCR_REG_REG (gpreg, SCR_OR, 0x01),
859 0,
860 #ifdef SYM_CONF_IARB_SUPPORT
861 SCR_JUMPR,
862 8,
863 #endif
864 }/*-------------------------< UNGETJOB >-------------------------*/,{
865 #ifdef SYM_CONF_IARB_SUPPORT
866 /*
867 * Set IMMEDIATE ARBITRATION, for the next time.
868 * This will give us better chance to win arbitration
869 * for the job we just wanted to do.
870 */
871 SCR_REG_REG (scntl1, SCR_OR, IARB),
872 0,
873 #endif
874 /*
875 * We are not able to restart the SCRIPTS if we are
876 * interrupted and these instruction haven't been
877 * all executed. BTW, this is very unlikely to
878 * happen, but we check that from the C code.
879 */
880 SCR_LOAD_REG (dsa, 0xff),
881 0,
882 SCR_COPY (4),
883 RADDR_1 (scratcha),
884 PADDR_B (startpos),
885 }/*-------------------------< RESELECT >-------------------------*/,{
886 #ifdef SYM_CONF_TARGET_ROLE_SUPPORT
887 /*
888 * Make sure we are in initiator mode.
889 */
890 SCR_CLR (SCR_TRG),
891 0,
892 #endif
893 /*
894 * Sleep waiting for a reselection.
895 */
896 SCR_WAIT_RESEL,
897 PADDR_A(start),
898 }/*-------------------------< RESELECTED >-----------------------*/,{
899 /*
900 * Switch the LED on.
901 * Will be patched with a NO_OP if LED
902 * not needed or not desired.
903 */
904 SCR_REG_REG (gpreg, SCR_AND, 0xfe),
905 0,
906 /*
907 * load the target id into the sdid
908 */
909 SCR_REG_SFBR (ssid, SCR_AND, 0x8F),
910 0,
911 SCR_TO_REG (sdid),
912 0,
913 /*
914 * Load the target control block address
915 */
916 SCR_COPY (4),
917 PADDR_B (targtbl),
918 RADDR_1 (dsa),
919 SCR_SFBR_REG (dsa, SCR_SHL, 0),
920 0,
921 SCR_REG_REG (dsa, SCR_SHL, 0),
922 0,
923 SCR_REG_REG (dsa, SCR_AND, 0x3c),
924 0,
925 SCR_COPY (4),
926 RADDR_1 (dsa),
927 PADDR_A (_sms_a70),
928 SCR_COPY (4),
929 }/*-------------------------< _SMS_A70 >-------------------------*/,{
930 0,
931 RADDR_1 (dsa),
932 /*
933 * Copy the TCB header to a fixed place in
934 * the HCB.
935 */
936 SCR_COPY (4),
937 RADDR_1 (dsa),
938 PADDR_A (_sms_a80),
939 SCR_COPY (sizeof(struct sym_tcbh)),
940 }/*-------------------------< _SMS_A80 >-------------------------*/,{
941 0,
942 HADDR_1 (tcb_head),
943 /*
944 * We expect MESSAGE IN phase.
945 * If not, get help from the C code.
946 */
947 SCR_INT ^ IFFALSE (WHEN (SCR_MSG_IN)),
948 SIR_RESEL_NO_MSG_IN,
949 }/*-------------------------< RESELECTED1 >----------------------*/,{
950 /*
951 * Load the synchronous transfer registers.
952 */
953 SCR_COPY (1),
954 HADDR_1 (tcb_head.wval),
955 RADDR_1 (scntl3),
956 SCR_COPY (1),
957 HADDR_1 (tcb_head.sval),
958 RADDR_1 (sxfer),
959 /*
960 * Get the IDENTIFY message.
961 */
962 SCR_MOVE_ABS (1) ^ SCR_MSG_IN,
963 HADDR_1 (msgin),
964 /*
965 * If IDENTIFY LUN #0, use a faster path
966 * to find the LCB structure.
967 */
968 SCR_JUMP ^ IFTRUE (MASK (0x80, 0xbf)),
969 PADDR_A (resel_lun0),
970 /*
971 * If message isn't an IDENTIFY,
972 * tell the C code about.
973 */
974 SCR_INT ^ IFFALSE (MASK (0x80, 0x80)),
975 SIR_RESEL_NO_IDENTIFY,
976 /*
977 * It is an IDENTIFY message,
978 * Load the LUN control block address.
979 */
980 SCR_COPY (4),
981 HADDR_1 (tcb_head.luntbl_sa),
982 RADDR_1 (dsa),
983 SCR_SFBR_REG (dsa, SCR_SHL, 0),
984 0,
985 SCR_REG_REG (dsa, SCR_SHL, 0),
986 0,
987 SCR_REG_REG (dsa, SCR_AND, 0xfc),
988 0,
989 SCR_COPY (4),
990 RADDR_1 (dsa),
991 PADDR_A (_sms_a90),
992 SCR_COPY (4),
993 }/*-------------------------< _SMS_A90 >-------------------------*/,{
994 0,
995 RADDR_1 (dsa),
996 SCR_JUMPR,
997 12,
998 }/*-------------------------< RESEL_LUN0 >-----------------------*/,{
999 /*
1000 * LUN 0 special case (but usual one :))
1001 */
1002 SCR_COPY (4),
1003 HADDR_1 (tcb_head.lun0_sa),
1004 RADDR_1 (dsa),
1005 /*
1006 * Jump indirectly to the reselect action for this LUN.
1007 * (lcb.head.resel_sa assumed at offset zero of lcb).
1008 */
1009 SCR_COPY (4),
1010 RADDR_1 (dsa),
1011 PADDR_A (_sms_a100),
1012 SCR_COPY (4),
1013 }/*-------------------------< _SMS_A100 >------------------------*/,{
1014 0,
1015 RADDR_1 (temp),
1016 SCR_RETURN,
1017 0,
1018 /* In normal situations, we jump to RESEL_TAG or RESEL_NO_TAG */
1019 }/*-------------------------< RESEL_TAG >------------------------*/,{
1020 /*
1021 * ACK the IDENTIFY previously received.
1022 */
1023 SCR_CLR (SCR_ACK),
1024 0,
1025 /*
1026 * It shall be a tagged command.
1027 * Read SIMPLE+TAG.
1028 * The C code will deal with errors.
1029 * Agressive optimization, is'nt it? :)
1030 */
1031 SCR_MOVE_ABS (2) ^ SCR_MSG_IN,
1032 HADDR_1 (msgin),
1033 /*
1034 * Copy the LCB header to a fixed place in
1035 * the HCB using self-modifying SCRIPTS.
1036 */
1037 SCR_COPY (4),
1038 RADDR_1 (dsa),
1039 PADDR_A (_sms_a110),
1040 SCR_COPY (sizeof(struct sym_lcbh)),
1041 }/*-------------------------< _SMS_A110 >------------------------*/,{
1042 0,
1043 HADDR_1 (lcb_head),
1044 /*
1045 * Load the pointer to the tagged task
1046 * table for this LUN.
1047 */
1048 SCR_COPY (4),
1049 HADDR_1 (lcb_head.itlq_tbl_sa),
1050 RADDR_1 (dsa),
1051 /*
1052 * The SIDL still contains the TAG value.
1053 * Agressive optimization, isn't it? :):)
1054 */
1055 SCR_REG_SFBR (sidl, SCR_SHL, 0),
1056 0,
1057 #if SYM_CONF_MAX_TASK*4 > 512
1058 SCR_JUMPR ^ IFFALSE (CARRYSET),
1059 8,
1060 SCR_REG_REG (dsa1, SCR_OR, 2),
1061 0,
1062 SCR_REG_REG (sfbr, SCR_SHL, 0),
1063 0,
1064 SCR_JUMPR ^ IFFALSE (CARRYSET),
1065 8,
1066 SCR_REG_REG (dsa1, SCR_OR, 1),
1067 0,
1068 #elif SYM_CONF_MAX_TASK*4 > 256
1069 SCR_JUMPR ^ IFFALSE (CARRYSET),
1070 8,
1071 SCR_REG_REG (dsa1, SCR_OR, 1),
1072 0,
1073 #endif
1074 /*
1075 * Retrieve the DSA of this task.
1076 * JUMP indirectly to the restart point of the CCB.
1077 */
1078 SCR_SFBR_REG (dsa, SCR_AND, 0xfc),
1079 0,
1080 SCR_COPY (4),
1081 RADDR_1 (dsa),
1082 PADDR_A (_sms_a120),
1083 SCR_COPY (4),
1084 }/*-------------------------< _SMS_A120 >------------------------*/,{
1085 0,
1086 RADDR_1 (dsa),
1087 }/*-------------------------< RESEL_GO >-------------------------*/,{
1088 SCR_COPY (4),
1089 RADDR_1 (dsa),
1090 PADDR_A (_sms_a130),
1091 /*
1092 * Move 'ccb.phys.head.go' action to
1093 * scratch/scratch1. So scratch1 will
1094 * contain the 'restart' field of the
1095 * 'go' structure.
1096 */
1097 SCR_COPY (8),
1098 }/*-------------------------< _SMS_A130 >------------------------*/,{
1099 0,
1100 PADDR_B (scratch),
1101 SCR_COPY (4),
1102 PADDR_B (scratch1), /* phys.head.go.restart */
1103 RADDR_1 (temp),
1104 SCR_RETURN,
1105 0,
1106 /* In normal situations we branch to RESEL_DSA */
1107 }/*-------------------------< RESEL_DSA >------------------------*/,{
1108 /*
1109 * ACK the IDENTIFY or TAG previously received.
1110 */
1111 SCR_CLR (SCR_ACK),
1112 0,
1113 }/*-------------------------< RESEL_DSA1 >-----------------------*/,{
1114 /*
1115 * Copy the CCB header to a fixed location
1116 * in the HCB using self-modifying SCRIPTS.
1117 */
1118 SCR_COPY (4),
1119 RADDR_1 (dsa),
1120 PADDR_A (_sms_a140),
1121 SCR_COPY (sizeof(struct sym_ccbh)),
1122 }/*-------------------------< _SMS_A140 >------------------------*/,{
1123 0,
1124 HADDR_1 (ccb_head),
1125 /*
1126 * Initialize the status register
1127 */
1128 SCR_COPY (4),
1129 HADDR_1 (ccb_head.status),
1130 RADDR_1 (scr0),
1131 /*
1132 * Jump to dispatcher.
1133 */
1134 SCR_JUMP,
1135 PADDR_A (dispatch),
1136 }/*-------------------------< RESEL_NO_TAG >---------------------*/,{
1137 /*
1138 * Copy the LCB header to a fixed place in
1139 * the HCB using self-modifying SCRIPTS.
1140 */
1141 SCR_COPY (4),
1142 RADDR_1 (dsa),
1143 PADDR_A (_sms_a145),
1144 SCR_COPY (sizeof(struct sym_lcbh)),
1145 }/*-------------------------< _SMS_A145 >------------------------*/,{
1146 0,
1147 HADDR_1 (lcb_head),
1148 /*
1149 * Load the DSA with the unique ITL task.
1150 */
1151 SCR_COPY (4),
1152 HADDR_1 (lcb_head.itl_task_sa),
1153 RADDR_1 (dsa),
1154 SCR_JUMP,
1155 PADDR_A (resel_go),
1156 }/*-------------------------< DATA_IN >--------------------------*/,{
1157 /*
1158 * Because the size depends on the
1159 * #define SYM_CONF_MAX_SG parameter,
1160 * it is filled in at runtime.
1161 *
1162 * ##===========< i=0; i<SYM_CONF_MAX_SG >=========
1163 * || SCR_CHMOV_TBL ^ SCR_DATA_IN,
1164 * || offsetof (struct sym_dsb, data[ i]),
1165 * ##==========================================
1166 */
1167 0
1168 }/*-------------------------< DATA_IN2 >-------------------------*/,{
1169 SCR_CALL,
1170 PADDR_A (datai_done),
1171 SCR_JUMP,
1172 PADDR_B (data_ovrun),
1173 }/*-------------------------< DATA_OUT >-------------------------*/,{
1174 /*
1175 * Because the size depends on the
1176 * #define SYM_CONF_MAX_SG parameter,
1177 * it is filled in at runtime.
1178 *
1179 * ##===========< i=0; i<SYM_CONF_MAX_SG >=========
1180 * || SCR_CHMOV_TBL ^ SCR_DATA_OUT,
1181 * || offsetof (struct sym_dsb, data[ i]),
1182 * ##==========================================
1183 */
1184 0
1185 }/*-------------------------< DATA_OUT2 >------------------------*/,{
1186 SCR_CALL,
1187 PADDR_A (datao_done),
1188 SCR_JUMP,
1189 PADDR_B (data_ovrun),
1190 }/*-------------------------< PM0_DATA >-------------------------*/,{
1191 /*
1192 * Read our host flags to SFBR, so we will be able
1193 * to check against the data direction we expect.
1194 */
1195 SCR_FROM_REG (HF_REG),
1196 0,
1197 /*
1198 * Check against actual DATA PHASE.
1199 */
1200 SCR_JUMP ^ IFFALSE (WHEN (SCR_DATA_IN)),
1201 PADDR_A (pm0_data_out),
1202 /*
1203 * Actual phase is DATA IN.
1204 * Check against expected direction.
1205 */
1206 SCR_JUMP ^ IFFALSE (MASK (HF_DATA_IN, HF_DATA_IN)),
1207 PADDR_B (data_ovrun),
1208 /*
1209 * Keep track we are moving data from the
1210 * PM0 DATA mini-script.
1211 */
1212 SCR_REG_REG (HF_REG, SCR_OR, HF_IN_PM0),
1213 0,
1214 /*
1215 * Move the data to memory.
1216 */
1217 SCR_CHMOV_TBL ^ SCR_DATA_IN,
1218 offsetof (struct sym_ccb, phys.pm0.sg),
1219 SCR_JUMP,
1220 PADDR_A (pm0_data_end),
1221 }/*-------------------------< PM0_DATA_OUT >---------------------*/,{
1222 /*
1223 * Actual phase is DATA OUT.
1224 * Check against expected direction.
1225 */
1226 SCR_JUMP ^ IFTRUE (MASK (HF_DATA_IN, HF_DATA_IN)),
1227 PADDR_B (data_ovrun),
1228 /*
1229 * Keep track we are moving data from the
1230 * PM0 DATA mini-script.
1231 */
1232 SCR_REG_REG (HF_REG, SCR_OR, HF_IN_PM0),
1233 0,
1234 /*
1235 * Move the data from memory.
1236 */
1237 SCR_CHMOV_TBL ^ SCR_DATA_OUT,
1238 offsetof (struct sym_ccb, phys.pm0.sg),
1239 }/*-------------------------< PM0_DATA_END >---------------------*/,{
1240 /*
1241 * Clear the flag that told we were moving
1242 * data from the PM0 DATA mini-script.
1243 */
1244 SCR_REG_REG (HF_REG, SCR_AND, (~HF_IN_PM0)),
1245 0,
1246 /*
1247 * Return to the previous DATA script which
1248 * is guaranteed by design (if no bug) to be
1249 * the main DATA script for this transfer.
1250 */
1251 SCR_COPY (4),
1252 RADDR_1 (dsa),
1253 RADDR_1 (scratcha),
1254 SCR_REG_REG (scratcha, SCR_ADD, offsetof (struct sym_ccb,phys.pm0.ret)),
1255 0,
1256 }/*-------------------------< PM_DATA_END >----------------------*/,{
1257 SCR_COPY (4),
1258 RADDR_1 (scratcha),
1259 PADDR_A (_sms_a150),
1260 SCR_COPY (4),
1261 }/*-------------------------< _SMS_A150 >------------------------*/,{
1262 0,
1263 RADDR_1 (temp),
1264 SCR_RETURN,
1265 0,
1266 }/*-------------------------< PM1_DATA >-------------------------*/,{
1267 /*
1268 * Read our host flags to SFBR, so we will be able
1269 * to check against the data direction we expect.
1270 */
1271 SCR_FROM_REG (HF_REG),
1272 0,
1273 /*
1274 * Check against actual DATA PHASE.
1275 */
1276 SCR_JUMP ^ IFFALSE (WHEN (SCR_DATA_IN)),
1277 PADDR_A (pm1_data_out),
1278 /*
1279 * Actual phase is DATA IN.
1280 * Check against expected direction.
1281 */
1282 SCR_JUMP ^ IFFALSE (MASK (HF_DATA_IN, HF_DATA_IN)),
1283 PADDR_B (data_ovrun),
1284 /*
1285 * Keep track we are moving data from the
1286 * PM1 DATA mini-script.
1287 */
1288 SCR_REG_REG (HF_REG, SCR_OR, HF_IN_PM1),
1289 0,
1290 /*
1291 * Move the data to memory.
1292 */
1293 SCR_CHMOV_TBL ^ SCR_DATA_IN,
1294 offsetof (struct sym_ccb, phys.pm1.sg),
1295 SCR_JUMP,
1296 PADDR_A (pm1_data_end),
1297 }/*-------------------------< PM1_DATA_OUT >---------------------*/,{
1298 /*
1299 * Actual phase is DATA OUT.
1300 * Check against expected direction.
1301 */
1302 SCR_JUMP ^ IFTRUE (MASK (HF_DATA_IN, HF_DATA_IN)),
1303 PADDR_B (data_ovrun),
1304 /*
1305 * Keep track we are moving data from the
1306 * PM1 DATA mini-script.
1307 */
1308 SCR_REG_REG (HF_REG, SCR_OR, HF_IN_PM1),
1309 0,
1310 /*
1311 * Move the data from memory.
1312 */
1313 SCR_CHMOV_TBL ^ SCR_DATA_OUT,
1314 offsetof (struct sym_ccb, phys.pm1.sg),
1315 }/*-------------------------< PM1_DATA_END >---------------------*/,{
1316 /*
1317 * Clear the flag that told we were moving
1318 * data from the PM1 DATA mini-script.
1319 */
1320 SCR_REG_REG (HF_REG, SCR_AND, (~HF_IN_PM1)),
1321 0,
1322 /*
1323 * Return to the previous DATA script which
1324 * is guaranteed by design (if no bug) to be
1325 * the main DATA script for this transfer.
1326 */
1327 SCR_COPY (4),
1328 RADDR_1 (dsa),
1329 RADDR_1 (scratcha),
1330 SCR_REG_REG (scratcha, SCR_ADD, offsetof (struct sym_ccb,phys.pm1.ret)),
1331 0,
1332 SCR_JUMP,
1333 PADDR_A (pm_data_end),
1334 }/*--------------------------<>----------------------------------*/
1335 };
1336
1337 static struct SYM_FWB_SCR SYM_FWB_SCR = {
1338 /*-------------------------< NO_DATA >--------------------------*/ {
1339 SCR_JUMP,
1340 PADDR_B (data_ovrun),
1341 }/*-------------------------< SEL_FOR_ABORT >--------------------*/,{
1342 /*
1343 * We are jumped here by the C code, if we have
1344 * some target to reset or some disconnected
1345 * job to abort. Since error recovery is a serious
1346 * busyness, we will really reset the SCSI BUS, if
1347 * case of a SCSI interrupt occurring in this path.
1348 */
1349
1350 #ifdef SYM_CONF_TARGET_ROLE_SUPPORT
1351 /*
1352 * Set initiator mode.
1353 */
1354 SCR_CLR (SCR_TRG),
1355 0,
1356 #endif
1357 /*
1358 * And try to select this target.
1359 */
1360 SCR_SEL_TBL_ATN ^ offsetof (struct sym_hcb, abrt_sel),
1361 PADDR_A (reselect),
1362 /*
1363 * Wait for the selection to complete or
1364 * the selection to time out.
1365 */
1366 SCR_JUMPR ^ IFFALSE (WHEN (SCR_MSG_OUT)),
1367 -8,
1368 /*
1369 * Call the C code.
1370 */
1371 SCR_INT,
1372 SIR_TARGET_SELECTED,
1373 /*
1374 * The C code should let us continue here.
1375 * Send the 'kiss of death' message.
1376 * We expect an immediate disconnect once
1377 * the target has eaten the message.
1378 */
1379 SCR_REG_REG (scntl2, SCR_AND, 0x7f),
1380 0,
1381 SCR_MOVE_TBL ^ SCR_MSG_OUT,
1382 offsetof (struct sym_hcb, abrt_tbl),
1383 SCR_CLR (SCR_ACK|SCR_ATN),
1384 0,
1385 SCR_WAIT_DISC,
1386 0,
1387 /*
1388 * Tell the C code that we are done.
1389 */
1390 SCR_INT,
1391 SIR_ABORT_SENT,
1392 }/*-------------------------< SEL_FOR_ABORT_1 >------------------*/,{
1393 /*
1394 * Jump at scheduler.
1395 */
1396 SCR_JUMP,
1397 PADDR_A (start),
1398 }/*-------------------------< MSG_IN_ETC >-----------------------*/,{
1399 /*
1400 * If it is an EXTENDED (variable size message)
1401 * Handle it.
1402 */
1403 SCR_JUMP ^ IFTRUE (DATA (M_EXTENDED)),
1404 PADDR_B (msg_extended),
1405 /*
1406 * Let the C code handle any other
1407 * 1 byte message.
1408 */
1409 SCR_JUMP ^ IFTRUE (MASK (0x00, 0xf0)),
1410 PADDR_B (msg_received),
1411 SCR_JUMP ^ IFTRUE (MASK (0x10, 0xf0)),
1412 PADDR_B (msg_received),
1413 /*
1414 * We donnot handle 2 bytes messages from SCRIPTS.
1415 * So, let the C code deal with these ones too.
1416 */
1417 SCR_JUMP ^ IFFALSE (MASK (0x20, 0xf0)),
1418 PADDR_B (msg_weird_seen),
1419 SCR_CLR (SCR_ACK),
1420 0,
1421 SCR_MOVE_ABS (1) ^ SCR_MSG_IN,
1422 HADDR_1 (msgin[1]),
1423 }/*-------------------------< MSG_RECEIVED >---------------------*/,{
1424 SCR_COPY (4), /* DUMMY READ */
1425 HADDR_1 (scratch),
1426 RADDR_1 (scratcha),
1427 SCR_INT,
1428 SIR_MSG_RECEIVED,
1429 }/*-------------------------< MSG_WEIRD_SEEN >-------------------*/,{
1430 SCR_COPY (4), /* DUMMY READ */
1431 HADDR_1 (scratch),
1432 RADDR_1 (scratcha),
1433 SCR_INT,
1434 SIR_MSG_WEIRD,
1435 }/*-------------------------< MSG_EXTENDED >---------------------*/,{
1436 /*
1437 * Clear ACK and get the next byte
1438 * assumed to be the message length.
1439 */
1440 SCR_CLR (SCR_ACK),
1441 0,
1442 SCR_MOVE_ABS (1) ^ SCR_MSG_IN,
1443 HADDR_1 (msgin[1]),
1444 /*
1445 * Try to catch some unlikely situations as 0 length
1446 * or too large the length.
1447 */
1448 SCR_JUMP ^ IFTRUE (DATA (0)),
1449 PADDR_B (msg_weird_seen),
1450 SCR_TO_REG (scratcha),
1451 0,
1452 SCR_REG_REG (sfbr, SCR_ADD, (256-8)),
1453 0,
1454 SCR_JUMP ^ IFTRUE (CARRYSET),
1455 PADDR_B (msg_weird_seen),
1456 /*
1457 * We donnot handle extended messages from SCRIPTS.
1458 * Read the amount of data correponding to the
1459 * message length and call the C code.
1460 */
1461 SCR_COPY (1),
1462 RADDR_1 (scratcha),
1463 PADDR_B (_sms_b10),
1464 SCR_CLR (SCR_ACK),
1465 0,
1466 }/*-------------------------< _SMS_B10 >-------------------------*/,{
1467 SCR_MOVE_ABS (0) ^ SCR_MSG_IN,
1468 HADDR_1 (msgin[2]),
1469 SCR_JUMP,
1470 PADDR_B (msg_received),
1471 }/*-------------------------< MSG_BAD >--------------------------*/,{
1472 /*
1473 * unimplemented message - reject it.
1474 */
1475 SCR_INT,
1476 SIR_REJECT_TO_SEND,
1477 SCR_SET (SCR_ATN),
1478 0,
1479 SCR_JUMP,
1480 PADDR_A (clrack),
1481 }/*-------------------------< MSG_WEIRD >------------------------*/,{
1482 /*
1483 * weird message received
1484 * ignore all MSG IN phases and reject it.
1485 */
1486 SCR_INT,
1487 SIR_REJECT_TO_SEND,
1488 SCR_SET (SCR_ATN),
1489 0,
1490 }/*-------------------------< MSG_WEIRD1 >-----------------------*/,{
1491 SCR_CLR (SCR_ACK),
1492 0,
1493 SCR_JUMP ^ IFFALSE (WHEN (SCR_MSG_IN)),
1494 PADDR_A (dispatch),
1495 SCR_MOVE_ABS (1) ^ SCR_MSG_IN,
1496 HADDR_1 (scratch),
1497 SCR_JUMP,
1498 PADDR_B (msg_weird1),
1499 }/*-------------------------< WDTR_RESP >------------------------*/,{
1500 /*
1501 * let the target fetch our answer.
1502 */
1503 SCR_SET (SCR_ATN),
1504 0,
1505 SCR_CLR (SCR_ACK),
1506 0,
1507 SCR_JUMP ^ IFFALSE (WHEN (SCR_MSG_OUT)),
1508 PADDR_B (nego_bad_phase),
1509 }/*-------------------------< SEND_WDTR >------------------------*/,{
1510 /*
1511 * Send the M_X_WIDE_REQ
1512 */
1513 SCR_MOVE_ABS (4) ^ SCR_MSG_OUT,
1514 HADDR_1 (msgout),
1515 SCR_JUMP,
1516 PADDR_B (msg_out_done),
1517 }/*-------------------------< SDTR_RESP >------------------------*/,{
1518 /*
1519 * let the target fetch our answer.
1520 */
1521 SCR_SET (SCR_ATN),
1522 0,
1523 SCR_CLR (SCR_ACK),
1524 0,
1525 SCR_JUMP ^ IFFALSE (WHEN (SCR_MSG_OUT)),
1526 PADDR_B (nego_bad_phase),
1527 }/*-------------------------< SEND_SDTR >------------------------*/,{
1528 /*
1529 * Send the M_X_SYNC_REQ
1530 */
1531 SCR_MOVE_ABS (5) ^ SCR_MSG_OUT,
1532 HADDR_1 (msgout),
1533 SCR_JUMP,
1534 PADDR_B (msg_out_done),
1535 }/*-------------------------< PPR_RESP >-------------------------*/,{
1536 /*
1537 * let the target fetch our answer.
1538 */
1539 SCR_SET (SCR_ATN),
1540 0,
1541 SCR_CLR (SCR_ACK),
1542 0,
1543 SCR_JUMP ^ IFFALSE (WHEN (SCR_MSG_OUT)),
1544 PADDR_B (nego_bad_phase),
1545 }/*-------------------------< SEND_PPR >-------------------------*/,{
1546 /*
1547 * Send the M_X_PPR_REQ
1548 */
1549 SCR_MOVE_ABS (8) ^ SCR_MSG_OUT,
1550 HADDR_1 (msgout),
1551 SCR_JUMP,
1552 PADDR_B (msg_out_done),
1553 }/*-------------------------< NEGO_BAD_PHASE >-------------------*/,{
1554 SCR_INT,
1555 SIR_NEGO_PROTO,
1556 SCR_JUMP,
1557 PADDR_A (dispatch),
1558 }/*-------------------------< MSG_OUT >--------------------------*/,{
1559 /*
1560 * The target requests a message.
1561 * We donnot send messages that may
1562 * require the device to go to bus free.
1563 */
1564 SCR_MOVE_ABS (1) ^ SCR_MSG_OUT,
1565 HADDR_1 (msgout),
1566 /*
1567 * ... wait for the next phase
1568 * if it's a message out, send it again, ...
1569 */
1570 SCR_JUMP ^ IFTRUE (WHEN (SCR_MSG_OUT)),
1571 PADDR_B (msg_out),
1572 }/*-------------------------< MSG_OUT_DONE >---------------------*/,{
1573 /*
1574 * Let the C code be aware of the
1575 * sent message and clear the message.
1576 */
1577 SCR_INT,
1578 SIR_MSG_OUT_DONE,
1579 /*
1580 * ... and process the next phase
1581 */
1582 SCR_JUMP,
1583 PADDR_A (dispatch),
1584 }/*-------------------------< DATA_OVRUN >-----------------------*/,{
1585 /*
1586 * Zero scratcha that will count the
1587 * extras bytes.
1588 */
1589 SCR_COPY (4),
1590 PADDR_B (zero),
1591 RADDR_1 (scratcha),
1592 }/*-------------------------< DATA_OVRUN1 >----------------------*/,{
1593 /*
1594 * The target may want to transfer too much data.
1595 *
1596 * If phase is DATA OUT write 1 byte and count it.
1597 */
1598 SCR_JUMPR ^ IFFALSE (WHEN (SCR_DATA_OUT)),
1599 16,
1600 SCR_CHMOV_ABS (1) ^ SCR_DATA_OUT,
1601 HADDR_1 (scratch),
1602 SCR_JUMP,
1603 PADDR_B (data_ovrun2),
1604 /*
1605 * If WSR is set, clear this condition, and
1606 * count this byte.
1607 */
1608 SCR_FROM_REG (scntl2),
1609 0,
1610 SCR_JUMPR ^ IFFALSE (MASK (WSR, WSR)),
1611 16,
1612 SCR_REG_REG (scntl2, SCR_OR, WSR),
1613 0,
1614 SCR_JUMP,
1615 PADDR_B (data_ovrun2),
1616 /*
1617 * Finally check against DATA IN phase.
1618 * Signal data overrun to the C code
1619 * and jump to dispatcher if not so.
1620 * Read 1 byte otherwise and count it.
1621 */
1622 SCR_JUMPR ^ IFTRUE (WHEN (SCR_DATA_IN)),
1623 16,
1624 SCR_INT,
1625 SIR_DATA_OVERRUN,
1626 SCR_JUMP,
1627 PADDR_A (dispatch),
1628 SCR_CHMOV_ABS (1) ^ SCR_DATA_IN,
1629 HADDR_1 (scratch),
1630 }/*-------------------------< DATA_OVRUN2 >----------------------*/,{
1631 /*
1632 * Count this byte.
1633 * This will allow to return a negative
1634 * residual to user.
1635 */
1636 SCR_REG_REG (scratcha, SCR_ADD, 0x01),
1637 0,
1638 SCR_REG_REG (scratcha1, SCR_ADDC, 0),
1639 0,
1640 SCR_REG_REG (scratcha2, SCR_ADDC, 0),
1641 0,
1642 /*
1643 * .. and repeat as required.
1644 */
1645 SCR_JUMP,
1646 PADDR_B (data_ovrun1),
1647 }/*-------------------------< ABORT_RESEL >----------------------*/,{
1648 SCR_SET (SCR_ATN),
1649 0,
1650 SCR_CLR (SCR_ACK),
1651 0,
1652 /*
1653 * send the abort/abortag/reset message
1654 * we expect an immediate disconnect
1655 */
1656 SCR_REG_REG (scntl2, SCR_AND, 0x7f),
1657 0,
1658 SCR_MOVE_ABS (1) ^ SCR_MSG_OUT,
1659 HADDR_1 (msgout),
1660 SCR_CLR (SCR_ACK|SCR_ATN),
1661 0,
1662 SCR_WAIT_DISC,
1663 0,
1664 SCR_INT,
1665 SIR_RESEL_ABORTED,
1666 SCR_JUMP,
1667 PADDR_A (start),
1668 }/*-------------------------< RESEND_IDENT >---------------------*/,{
1669 /*
1670 * The target stays in MSG OUT phase after having acked
1671 * Identify [+ Tag [+ Extended message ]]. Targets shall
1672 * behave this way on parity error.
1673 * We must send it again all the messages.
1674 */
1675 SCR_SET (SCR_ATN), /* Shall be asserted 2 deskew delays before the */
1676 0, /* 1rst ACK = 90 ns. Hope the chip isn't too fast */
1677 SCR_JUMP,
1678 PADDR_A (send_ident),
1679 }/*-------------------------< IDENT_BREAK >----------------------*/,{
1680 SCR_CLR (SCR_ATN),
1681 0,
1682 SCR_JUMP,
1683 PADDR_A (select2),
1684 }/*-------------------------< IDENT_BREAK_ATN >------------------*/,{
1685 SCR_SET (SCR_ATN),
1686 0,
1687 SCR_JUMP,
1688 PADDR_A (select2),
1689 }/*-------------------------< SDATA_IN >-------------------------*/,{
1690 SCR_CHMOV_TBL ^ SCR_DATA_IN,
1691 offsetof (struct sym_dsb, sense),
1692 SCR_CALL,
1693 PADDR_A (datai_done),
1694 SCR_JUMP,
1695 PADDR_B (data_ovrun),
1696 }/*-------------------------< RESEL_BAD_LUN >--------------------*/,{
1697 /*
1698 * Message is an IDENTIFY, but lun is unknown.
1699 * Signal problem to C code for logging the event.
1700 * Send a M_ABORT to clear all pending tasks.
1701 */
1702 SCR_INT,
1703 SIR_RESEL_BAD_LUN,
1704 SCR_JUMP,
1705 PADDR_B (abort_resel),
1706 }/*-------------------------< BAD_I_T_L >------------------------*/,{
1707 /*
1708 * We donnot have a task for that I_T_L.
1709 * Signal problem to C code for logging the event.
1710 * Send a M_ABORT message.
1711 */
1712 SCR_INT,
1713 SIR_RESEL_BAD_I_T_L,
1714 SCR_JUMP,
1715 PADDR_B (abort_resel),
1716 }/*-------------------------< BAD_I_T_L_Q >----------------------*/,{
1717 /*
1718 * We donnot have a task that matches the tag.
1719 * Signal problem to C code for logging the event.
1720 * Send a M_ABORTTAG message.
1721 */
1722 SCR_INT,
1723 SIR_RESEL_BAD_I_T_L_Q,
1724 SCR_JUMP,
1725 PADDR_B (abort_resel),
1726 }/*-------------------------< BAD_STATUS >-----------------------*/,{
1727 /*
1728 * Anything different from INTERMEDIATE
1729 * CONDITION MET should be a bad SCSI status,
1730 * given that GOOD status has already been tested.
1731 * Call the C code.
1732 */
1733 SCR_COPY (4),
1734 PADDR_B (startpos),
1735 RADDR_1 (scratcha),
1736 SCR_INT ^ IFFALSE (DATA (S_COND_MET)),
1737 SIR_BAD_SCSI_STATUS,
1738 SCR_RETURN,
1739 0,
1740 }/*-------------------------< WSR_MA_HELPER >--------------------*/,{
1741 /*
1742 * Helper for the C code when WSR bit is set.
1743 * Perform the move of the residual byte.
1744 */
1745 SCR_CHMOV_TBL ^ SCR_DATA_IN,
1746 offsetof (struct sym_ccb, phys.wresid),
1747 SCR_JUMP,
1748 PADDR_A (dispatch),
1749
1750 #ifdef SYM_OPT_HANDLE_DIR_UNKNOWN
1751 }/*-------------------------< DATA_IO >--------------------------*/,{
1752 /*
1753 * We jump here if the data direction was unknown at the
1754 * time we had to queue the command to the scripts processor.
1755 * Pointers had been set as follow in this situation:
1756 * savep --> DATA_IO
1757 * lastp --> start pointer when DATA_IN
1758 * wlastp --> start pointer when DATA_OUT
1759 * This script sets savep and lastp according to the
1760 * direction chosen by the target.
1761 */
1762 SCR_JUMP ^ IFTRUE (WHEN (SCR_DATA_OUT)),
1763 PADDR_B (data_io_out),
1764 }/*-------------------------< DATA_IO_COM >----------------------*/,{
1765 /*
1766 * Direction is DATA IN.
1767 */
1768 SCR_COPY (4),
1769 HADDR_1 (ccb_head.lastp),
1770 HADDR_1 (ccb_head.savep),
1771 /*
1772 * Jump to the SCRIPTS according to actual direction.
1773 */
1774 SCR_COPY (4),
1775 HADDR_1 (ccb_head.savep),
1776 RADDR_1 (temp),
1777 SCR_RETURN,
1778 0,
1779 }/*-------------------------< DATA_IO_OUT >----------------------*/,{
1780 /*
1781 * Direction is DATA OUT.
1782 */
1783 SCR_REG_REG (HF_REG, SCR_AND, (~HF_DATA_IN)),
1784 0,
1785 SCR_COPY (4),
1786 HADDR_1 (ccb_head.wlastp),
1787 HADDR_1 (ccb_head.lastp),
1788 SCR_JUMP,
1789 PADDR_B(data_io_com),
1790 #endif /* SYM_OPT_HANDLE_DIR_UNKNOWN */
1791
1792 }/*-------------------------< ZERO >-----------------------------*/,{
1793 SCR_DATA_ZERO,
1794 }/*-------------------------< SCRATCH >--------------------------*/,{
1795 SCR_DATA_ZERO, /* MUST BE BEFORE SCRATCH1 */
1796 }/*-------------------------< SCRATCH1 >-------------------------*/,{
1797 SCR_DATA_ZERO,
1798 }/*-------------------------< PREV_DONE >------------------------*/,{
1799 SCR_DATA_ZERO, /* MUST BE BEFORE DONE_POS ! */
1800 }/*-------------------------< DONE_POS >-------------------------*/,{
1801 SCR_DATA_ZERO,
1802 }/*-------------------------< NEXTJOB >--------------------------*/,{
1803 SCR_DATA_ZERO, /* MUST BE BEFORE STARTPOS ! */
1804 }/*-------------------------< STARTPOS >-------------------------*/,{
1805 SCR_DATA_ZERO,
1806 }/*-------------------------< TARGTBL >--------------------------*/,{
1807 SCR_DATA_ZERO,
1808 }/*--------------------------<>----------------------------------*/
1809 };
1810
1811 static struct SYM_FWZ_SCR SYM_FWZ_SCR = {
1812 /*-------------------------< SNOOPTEST >------------------------*/{
1813 /*
1814 * Read the variable.
1815 */
1816 SCR_COPY (4),
1817 HADDR_1 (scratch),
1818 RADDR_1 (scratcha),
1819 /*
1820 * Write the variable.
1821 */
1822 SCR_COPY (4),
1823 RADDR_1 (temp),
1824 HADDR_1 (scratch),
1825 /*
1826 * Read back the variable.
1827 */
1828 SCR_COPY (4),
1829 HADDR_1 (scratch),
1830 RADDR_1 (temp),
1831 }/*-------------------------< SNOOPEND >-------------------------*/,{
1832 /*
1833 * And stop.
1834 */
1835 SCR_INT,
1836 99,
1837 }/*--------------------------<>----------------------------------*/
1838 };
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