drivers/serial/m32r_sio_reg.h

   1 /*
   2  * m32r_sio_reg.h
   3  *
   4  * Copyright (C) 1992, 1994 by Theodore Ts'o.
   5  * Copyright (C) 2004  Hirokazu Takata <takata at linux-m32r.org>
   6  *
   7  * Redistribution of this file is permitted under the terms of the GNU
   8  * Public License (GPL)
   9  *
  10  * These are the UART port assignments, expressed as offsets from the base
  11  * register.  These assignments should hold for any serial port based on
  12  * a 8250, 16450, or 16550(A).
  13  */
  14
  15 #ifndef _M32R_SIO_REG_H
  16 #define _M32R_SIO_REG_H
  17
  18 #include <linux/config.h>
  19
  20 #ifdef CONFIG_SERIAL_M32R_PLDSIO
  21
  22 #define SIOCR           0x000
  23 #define SIOMOD0         0x002
  24 #define SIOMOD1         0x004
  25 #define SIOSTS          0x006
  26 #define SIOTRCR         0x008
  27 #define SIOBAUR         0x00a
  28 // #define SIORBAUR     0x018
  29 #define SIOTXB          0x00c
  30 #define SIORXB          0x00e
  31
  32 #define UART_RX         ((unsigned long) PLD_ESIO0RXB)
  33                                 /* In:  Receive buffer (DLAB=0) */
  34 #define UART_TX         ((unsigned long) PLD_ESIO0TXB)
  35                                 /* Out: Transmit buffer (DLAB=0) */
  36 #define UART_DLL        0       /* Out: Divisor Latch Low (DLAB=1) */
  37 #define UART_TRG        0       /* (LCR=BF) FCTR bit 7 selects Rx or Tx
  38                                  * In: Fifo count
  39                                  * Out: Fifo custom trigger levels
  40                                  * XR16C85x only */
  41
  42 #define UART_DLM        0       /* Out: Divisor Latch High (DLAB=1) */
  43 #define UART_IER        ((unsigned long) PLD_ESIO0INTCR)
  44                                 /* Out: Interrupt Enable Register */
  45 #define UART_FCTR       0       /* (LCR=BF) Feature Control Register
  46                                  * XR16C85x only */
  47
  48 #define UART_IIR        0       /* In:  Interrupt ID Register */
  49 #define UART_FCR        0       /* Out: FIFO Control Register */
  50 #define UART_EFR        0       /* I/O: Extended Features Register */
  51                                 /* (DLAB=1, 16C660 only) */
  52
  53 #define UART_LCR        0       /* Out: Line Control Register */
  54 #define UART_MCR        0       /* Out: Modem Control Register */
  55 #define UART_LSR        ((unsigned long) PLD_ESIO0STS)
  56                                 /* In:  Line Status Register */
  57 #define UART_MSR        0       /* In:  Modem Status Register */
  58 #define UART_SCR        0       /* I/O: Scratch Register */
  59 #define UART_EMSR       0       /* (LCR=BF) Extended Mode Select Register
  60                                  * FCTR bit 6 selects SCR or EMSR
  61                                  * XR16c85x only */
  62
  63 #else /* not CONFIG_SERIAL_M32R_PLDSIO */
  64
  65 #define SIOCR           0x000
  66 #define SIOMOD0         0x004
  67 #define SIOMOD1         0x008
  68 #define SIOSTS          0x00c
  69 #define SIOTRCR         0x010
  70 #define SIOBAUR         0x014
  71 #define SIORBAUR        0x018
  72 #define SIOTXB          0x01c
  73 #define SIORXB          0x020
  74
  75 #define UART_RX         M32R_SIO0_RXB_PORTL     /* In:  Receive buffer (DLAB=0) */
  76 #define UART_TX         M32R_SIO0_TXB_PORTL     /* Out: Transmit buffer (DLAB=0) */
  77 #define UART_DLL        0       /* Out: Divisor Latch Low (DLAB=1) */
  78 #define UART_TRG        0       /* (LCR=BF) FCTR bit 7 selects Rx or Tx
  79                                  * In: Fifo count
  80                                  * Out: Fifo custom trigger levels
  81                                  * XR16C85x only */
  82
  83 #define UART_DLM        0       /* Out: Divisor Latch High (DLAB=1) */
  84 #define UART_IER        M32R_SIO0_TRCR_PORTL    /* Out: Interrupt Enable Register */
  85 #define UART_FCTR       0       /* (LCR=BF) Feature Control Register
  86                                  * XR16C85x only */
  87
  88 #define UART_IIR        0       /* In:  Interrupt ID Register */
  89 #define UART_FCR        0       /* Out: FIFO Control Register */
  90 #define UART_EFR        0       /* I/O: Extended Features Register */
  91                                 /* (DLAB=1, 16C660 only) */
  92
  93 #define UART_LCR        0       /* Out: Line Control Register */
  94 #define UART_MCR        0       /* Out: Modem Control Register */
  95 #define UART_LSR        M32R_SIO0_STS_PORTL     /* In:  Line Status Register */
  96 #define UART_MSR        0       /* In:  Modem Status Register */
  97 #define UART_SCR        0       /* I/O: Scratch Register */
  98 #define UART_EMSR       0       /* (LCR=BF) Extended Mode Select Register
  99                                  * FCTR bit 6 selects SCR or EMSR
 100                                  * XR16c85x only */
 101
 102 #endif /* CONFIG_SERIAL_M32R_PLDSIO */
 103
 104 #define UART_EMPTY      (UART_LSR_TEMT | UART_LSR_THRE)
 105
 106 /*
 107  * These are the definitions for the Line Control Register
 108  *
 109  * Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting
 110  * UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits.
 111  */
 112 #define UART_LCR_DLAB   0x80    /* Divisor latch access bit */
 113 #define UART_LCR_SBC    0x40    /* Set break control */
 114 #define UART_LCR_SPAR   0x20    /* Stick parity (?) */
 115 #define UART_LCR_EPAR   0x10    /* Even parity select */
 116 #define UART_LCR_PARITY 0x08    /* Parity Enable */
 117 #define UART_LCR_STOP   0x04    /* Stop bits: 0=1 stop bit, 1= 2 stop bits */
 118 #define UART_LCR_WLEN5  0x00    /* Wordlength: 5 bits */
 119 #define UART_LCR_WLEN6  0x01    /* Wordlength: 6 bits */
 120 #define UART_LCR_WLEN7  0x02    /* Wordlength: 7 bits */
 121 #define UART_LCR_WLEN8  0x03    /* Wordlength: 8 bits */
 122
 123 /*
 124  * These are the definitions for the Line Status Register
 125  */
 126 #define UART_LSR_TEMT   0x02    /* Transmitter empty */
 127 #define UART_LSR_THRE   0x01    /* Transmit-hold-register empty */
 128 #define UART_LSR_BI     0x00    /* Break interrupt indicator */
 129 #define UART_LSR_FE     0x80    /* Frame error indicator */
 130 #define UART_LSR_PE     0x40    /* Parity error indicator */
 131 #define UART_LSR_OE     0x20    /* Overrun error indicator */
 132 #define UART_LSR_DR     0x04    /* Receiver data ready */
 133
 134 /*
 135  * These are the definitions for the Interrupt Identification Register
 136  */
 137 #define UART_IIR_NO_INT 0x01    /* No interrupts pending */
 138 #define UART_IIR_ID     0x06    /* Mask for the interrupt ID */
 139
 140 #define UART_IIR_MSI    0x00    /* Modem status interrupt */
 141 #define UART_IIR_THRI   0x02    /* Transmitter holding register empty */
 142 #define UART_IIR_RDI    0x04    /* Receiver data interrupt */
 143 #define UART_IIR_RLSI   0x06    /* Receiver line status interrupt */
 144
 145 /*
 146  * These are the definitions for the Interrupt Enable Register
 147  */
 148 #define UART_IER_MSI    0x00    /* Enable Modem status interrupt */
 149 #define UART_IER_RLSI   0x08    /* Enable receiver line status interrupt */
 150 #define UART_IER_THRI   0x03    /* Enable Transmitter holding register int. */
 151 #define UART_IER_RDI    0x04    /* Enable receiver data interrupt */
 152
 153 #endif /* _M32R_SIO_REG_H */