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[TG3]: Set minimal hw interrupt mitigation.
[linux-2.6/verdex.git] / drivers / serial / serial_txx9.c
blob3f1051a4a13f8f51cab2efa2783f287e734c8ecb
1 /*
2 * drivers/serial/serial_txx9.c
3 *
4 * Derived from many drivers using generic_serial interface,
5 * especially serial_tx3912.c by Steven J. Hill and r39xx_serial.c
6 * (was in Linux/VR tree) by Jim Pick.
7 *
8 * Copyright (C) 1999 Harald Koerfgen
9 * Copyright (C) 2000 Jim Pick <jim@jimpick.com>
10 * Copyright (C) 2001 Steven J. Hill (sjhill@realitydiluted.com)
11 * Copyright (C) 2000-2002 Toshiba Corporation
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16 *
17 * Serial driver for TX3927/TX4927/TX4925/TX4938 internal SIO controller
18 *
19 * Revision History:
20 * 0.30 Initial revision. (Renamed from serial_txx927.c)
21 * 0.31 Use save_flags instead of local_irq_save.
22 * 0.32 Support SCLK.
23 * 0.33 Switch TXX9_TTY_NAME by CONFIG_SERIAL_TXX9_STDSERIAL.
24 * Support TIOCSERGETLSR.
25 * 0.34 Support slow baudrate.
26 * 0.40 Merge codes from mainstream kernel (2.4.22).
27 * 0.41 Fix console checking in rs_shutdown_port().
28 * Disable flow-control in serial_console_write().
29 * 0.42 Fix minor compiler warning.
30 * 1.00 Kernel 2.6. Converted to new serial core (based on 8250.c).
31 * 1.01 Set fifosize to make tx_empry called properly.
32 * Use standard uart_get_divisor.
33 * 1.02 Cleanup. (import 8250.c changes)
34 */
35 #include <linux/config.h>
36
37 #if defined(CONFIG_SERIAL_TXX9_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
38 #define SUPPORT_SYSRQ
39 #endif
40
41 #include <linux/module.h>
42 #include <linux/ioport.h>
43 #include <linux/init.h>
44 #include <linux/console.h>
45 #include <linux/sysrq.h>
46 #include <linux/delay.h>
47 #include <linux/device.h>
48 #include <linux/pci.h>
49 #include <linux/tty.h>
50 #include <linux/tty_flip.h>
51 #include <linux/serial_core.h>
52 #include <linux/serial.h>
53
54 #include <asm/io.h>
55 #include <asm/irq.h>
56
57 static char *serial_version = "1.02";
58 static char *serial_name = "TX39/49 Serial driver";
59
60 #define PASS_LIMIT 256
61
62 #if !defined(CONFIG_SERIAL_TXX9_STDSERIAL)
63 /* "ttyS" is used for standard serial driver */
64 #define TXX9_TTY_NAME "ttyTX"
65 #define TXX9_TTY_DEVFS_NAME "tttx/"
66 #define TXX9_TTY_MINOR_START (64 + 64) /* ttyTX0(128), ttyTX1(129) */
67 #else
68 /* acts like standard serial driver */
69 #define TXX9_TTY_NAME "ttyS"
70 #define TXX9_TTY_DEVFS_NAME "tts/"
71 #define TXX9_TTY_MINOR_START 64
72 #endif
73 #define TXX9_TTY_MAJOR TTY_MAJOR
74
75 /* flag aliases */
76 #define UPF_TXX9_HAVE_CTS_LINE UPF_BUGGY_UART
77 #define UPF_TXX9_USE_SCLK UPF_MAGIC_MULTIPLIER
78
79 #ifdef CONFIG_PCI
80 /* support for Toshiba TC86C001 SIO */
81 #define ENABLE_SERIAL_TXX9_PCI
82 #endif
83
84 /*
85 * Number of serial ports
86 */
87 #ifdef ENABLE_SERIAL_TXX9_PCI
88 #define NR_PCI_BOARDS 4
89 #define UART_NR (2 + NR_PCI_BOARDS)
90 #else
91 #define UART_NR 2
92 #endif
93
94 struct uart_txx9_port {
95 struct uart_port port;
96
97 /*
98 * We provide a per-port pm hook.
99 */
100 void (*pm)(struct uart_port *port,
101 unsigned int state, unsigned int old);
102 };
103
104 #define TXX9_REGION_SIZE 0x24
105
106 /* TXX9 Serial Registers */
107 #define TXX9_SILCR 0x00
108 #define TXX9_SIDICR 0x04
109 #define TXX9_SIDISR 0x08
110 #define TXX9_SICISR 0x0c
111 #define TXX9_SIFCR 0x10
112 #define TXX9_SIFLCR 0x14
113 #define TXX9_SIBGR 0x18
114 #define TXX9_SITFIFO 0x1c
115 #define TXX9_SIRFIFO 0x20
116
117 /* SILCR : Line Control */
118 #define TXX9_SILCR_SCS_MASK 0x00000060
119 #define TXX9_SILCR_SCS_IMCLK 0x00000000
120 #define TXX9_SILCR_SCS_IMCLK_BG 0x00000020
121 #define TXX9_SILCR_SCS_SCLK 0x00000040
122 #define TXX9_SILCR_SCS_SCLK_BG 0x00000060
123 #define TXX9_SILCR_UEPS 0x00000010
124 #define TXX9_SILCR_UPEN 0x00000008
125 #define TXX9_SILCR_USBL_MASK 0x00000004
126 #define TXX9_SILCR_USBL_1BIT 0x00000000
127 #define TXX9_SILCR_USBL_2BIT 0x00000004
128 #define TXX9_SILCR_UMODE_MASK 0x00000003
129 #define TXX9_SILCR_UMODE_8BIT 0x00000000
130 #define TXX9_SILCR_UMODE_7BIT 0x00000001
131
132 /* SIDICR : DMA/Int. Control */
133 #define TXX9_SIDICR_TDE 0x00008000
134 #define TXX9_SIDICR_RDE 0x00004000
135 #define TXX9_SIDICR_TIE 0x00002000
136 #define TXX9_SIDICR_RIE 0x00001000
137 #define TXX9_SIDICR_SPIE 0x00000800
138 #define TXX9_SIDICR_CTSAC 0x00000600
139 #define TXX9_SIDICR_STIE_MASK 0x0000003f
140 #define TXX9_SIDICR_STIE_OERS 0x00000020
141 #define TXX9_SIDICR_STIE_CTSS 0x00000010
142 #define TXX9_SIDICR_STIE_RBRKD 0x00000008
143 #define TXX9_SIDICR_STIE_TRDY 0x00000004
144 #define TXX9_SIDICR_STIE_TXALS 0x00000002
145 #define TXX9_SIDICR_STIE_UBRKD 0x00000001
146
147 /* SIDISR : DMA/Int. Status */
148 #define TXX9_SIDISR_UBRK 0x00008000
149 #define TXX9_SIDISR_UVALID 0x00004000
150 #define TXX9_SIDISR_UFER 0x00002000
151 #define TXX9_SIDISR_UPER 0x00001000
152 #define TXX9_SIDISR_UOER 0x00000800
153 #define TXX9_SIDISR_ERI 0x00000400
154 #define TXX9_SIDISR_TOUT 0x00000200
155 #define TXX9_SIDISR_TDIS 0x00000100
156 #define TXX9_SIDISR_RDIS 0x00000080
157 #define TXX9_SIDISR_STIS 0x00000040
158 #define TXX9_SIDISR_RFDN_MASK 0x0000001f
159
160 /* SICISR : Change Int. Status */
161 #define TXX9_SICISR_OERS 0x00000020
162 #define TXX9_SICISR_CTSS 0x00000010
163 #define TXX9_SICISR_RBRKD 0x00000008
164 #define TXX9_SICISR_TRDY 0x00000004
165 #define TXX9_SICISR_TXALS 0x00000002
166 #define TXX9_SICISR_UBRKD 0x00000001
167
168 /* SIFCR : FIFO Control */
169 #define TXX9_SIFCR_SWRST 0x00008000
170 #define TXX9_SIFCR_RDIL_MASK 0x00000180
171 #define TXX9_SIFCR_RDIL_1 0x00000000
172 #define TXX9_SIFCR_RDIL_4 0x00000080
173 #define TXX9_SIFCR_RDIL_8 0x00000100
174 #define TXX9_SIFCR_RDIL_12 0x00000180
175 #define TXX9_SIFCR_RDIL_MAX 0x00000180
176 #define TXX9_SIFCR_TDIL_MASK 0x00000018
177 #define TXX9_SIFCR_TDIL_MASK 0x00000018
178 #define TXX9_SIFCR_TDIL_1 0x00000000
179 #define TXX9_SIFCR_TDIL_4 0x00000001
180 #define TXX9_SIFCR_TDIL_8 0x00000010
181 #define TXX9_SIFCR_TDIL_MAX 0x00000010
182 #define TXX9_SIFCR_TFRST 0x00000004
183 #define TXX9_SIFCR_RFRST 0x00000002
184 #define TXX9_SIFCR_FRSTE 0x00000001
185 #define TXX9_SIO_TX_FIFO 8
186 #define TXX9_SIO_RX_FIFO 16
187
188 /* SIFLCR : Flow Control */
189 #define TXX9_SIFLCR_RCS 0x00001000
190 #define TXX9_SIFLCR_TES 0x00000800
191 #define TXX9_SIFLCR_RTSSC 0x00000200
192 #define TXX9_SIFLCR_RSDE 0x00000100
193 #define TXX9_SIFLCR_TSDE 0x00000080
194 #define TXX9_SIFLCR_RTSTL_MASK 0x0000001e
195 #define TXX9_SIFLCR_RTSTL_MAX 0x0000001e
196 #define TXX9_SIFLCR_TBRK 0x00000001
197
198 /* SIBGR : Baudrate Control */
199 #define TXX9_SIBGR_BCLK_MASK 0x00000300
200 #define TXX9_SIBGR_BCLK_T0 0x00000000
201 #define TXX9_SIBGR_BCLK_T2 0x00000100
202 #define TXX9_SIBGR_BCLK_T4 0x00000200
203 #define TXX9_SIBGR_BCLK_T6 0x00000300
204 #define TXX9_SIBGR_BRD_MASK 0x000000ff
205
206 static inline unsigned int sio_in(struct uart_txx9_port *up, int offset)
207 {
208 switch (up->port.iotype) {
209 default:
210 return *(volatile u32 *)(up->port.membase + offset);
211 case UPIO_PORT:
212 return inl(up->port.iobase + offset);
213 }
214 }
215
216 static inline void
217 sio_out(struct uart_txx9_port *up, int offset, int value)
218 {
219 switch (up->port.iotype) {
220 default:
221 *(volatile u32 *)(up->port.membase + offset) = value;
222 break;
223 case UPIO_PORT:
224 outl(value, up->port.iobase + offset);
225 break;
226 }
227 }
228
229 static inline void
230 sio_mask(struct uart_txx9_port *up, int offset, unsigned int value)
231 {
232 sio_out(up, offset, sio_in(up, offset) & ~value);
233 }
234 static inline void
235 sio_set(struct uart_txx9_port *up, int offset, unsigned int value)
236 {
237 sio_out(up, offset, sio_in(up, offset) | value);
238 }
239
240 static inline void
241 sio_quot_set(struct uart_txx9_port *up, int quot)
242 {
243 quot >>= 1;
244 if (quot < 256)
245 sio_out(up, TXX9_SIBGR, quot | TXX9_SIBGR_BCLK_T0);
246 else if (quot < (256 << 2))
247 sio_out(up, TXX9_SIBGR, (quot >> 2) | TXX9_SIBGR_BCLK_T2);
248 else if (quot < (256 << 4))
249 sio_out(up, TXX9_SIBGR, (quot >> 4) | TXX9_SIBGR_BCLK_T4);
250 else if (quot < (256 << 6))
251 sio_out(up, TXX9_SIBGR, (quot >> 6) | TXX9_SIBGR_BCLK_T6);
252 else
253 sio_out(up, TXX9_SIBGR, 0xff | TXX9_SIBGR_BCLK_T6);
254 }
255
256 static void serial_txx9_stop_tx(struct uart_port *port, unsigned int tty_stop)
257 {
258 struct uart_txx9_port *up = (struct uart_txx9_port *)port;
259 unsigned long flags;
260
261 spin_lock_irqsave(&up->port.lock, flags);
262 sio_mask(up, TXX9_SIDICR, TXX9_SIDICR_TIE);
263 spin_unlock_irqrestore(&up->port.lock, flags);
264 }
265
266 static void serial_txx9_start_tx(struct uart_port *port, unsigned int tty_start)
267 {
268 struct uart_txx9_port *up = (struct uart_txx9_port *)port;
269 unsigned long flags;
270
271 spin_lock_irqsave(&up->port.lock, flags);
272 sio_set(up, TXX9_SIDICR, TXX9_SIDICR_TIE);
273 spin_unlock_irqrestore(&up->port.lock, flags);
274 }
275
276 static void serial_txx9_stop_rx(struct uart_port *port)
277 {
278 struct uart_txx9_port *up = (struct uart_txx9_port *)port;
279 unsigned long flags;
280
281 spin_lock_irqsave(&up->port.lock, flags);
282 up->port.read_status_mask &= ~TXX9_SIDISR_RDIS;
283 #if 0
284 sio_mask(up, TXX9_SIDICR, TXX9_SIDICR_RIE);
285 #endif
286 spin_unlock_irqrestore(&up->port.lock, flags);
287 }
288
289 static void serial_txx9_enable_ms(struct uart_port *port)
290 {
291 /* TXX9-SIO can not control DTR... */
292 }
293
294 static inline void
295 receive_chars(struct uart_txx9_port *up, unsigned int *status, struct pt_regs *regs)
296 {
297 struct tty_struct *tty = up->port.info->tty;
298 unsigned char ch;
299 unsigned int disr = *status;
300 int max_count = 256;
301 char flag;
302
303 do {
304 /* The following is not allowed by the tty layer and
305 unsafe. It should be fixed ASAP */
306 if (unlikely(tty->flip.count >= TTY_FLIPBUF_SIZE)) {
307 if(tty->low_latency)
308 tty_flip_buffer_push(tty);
309 /* If this failed then we will throw away the
310 bytes but must do so to clear interrupts */
311 }
312 ch = sio_in(up, TXX9_SIRFIFO);
313 flag = TTY_NORMAL;
314 up->port.icount.rx++;
315
316 if (unlikely(disr & (TXX9_SIDISR_UBRK | TXX9_SIDISR_UPER |
317 TXX9_SIDISR_UFER | TXX9_SIDISR_UOER))) {
318 /*
319 * For statistics only
320 */
321 if (disr & TXX9_SIDISR_UBRK) {
322 disr &= ~(TXX9_SIDISR_UFER | TXX9_SIDISR_UPER);
323 up->port.icount.brk++;
324 /*
325 * We do the SysRQ and SAK checking
326 * here because otherwise the break
327 * may get masked by ignore_status_mask
328 * or read_status_mask.
329 */
330 if (uart_handle_break(&up->port))
331 goto ignore_char;
332 } else if (disr & TXX9_SIDISR_UPER)
333 up->port.icount.parity++;
334 else if (disr & TXX9_SIDISR_UFER)
335 up->port.icount.frame++;
336 if (disr & TXX9_SIDISR_UOER)
337 up->port.icount.overrun++;
338
339 /*
340 * Mask off conditions which should be ingored.
341 */
342 disr &= up->port.read_status_mask;
343
344 if (disr & TXX9_SIDISR_UBRK) {
345 flag = TTY_BREAK;
346 } else if (disr & TXX9_SIDISR_UPER)
347 flag = TTY_PARITY;
348 else if (disr & TXX9_SIDISR_UFER)
349 flag = TTY_FRAME;
350 }
351 if (uart_handle_sysrq_char(&up->port, ch, regs))
352 goto ignore_char;
353
354 uart_insert_char(&up->port, disr, TXX9_SIDISR_UOER, ch, flag);
355
356 ignore_char:
357 disr = sio_in(up, TXX9_SIDISR);
358 } while (!(disr & TXX9_SIDISR_UVALID) && (max_count-- > 0));
359 tty_flip_buffer_push(tty);
360 *status = disr;
361 }
362
363 static inline void transmit_chars(struct uart_txx9_port *up)
364 {
365 struct circ_buf *xmit = &up->port.info->xmit;
366 int count;
367
368 if (up->port.x_char) {
369 sio_out(up, TXX9_SITFIFO, up->port.x_char);
370 up->port.icount.tx++;
371 up->port.x_char = 0;
372 return;
373 }
374 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
375 serial_txx9_stop_tx(&up->port, 0);
376 return;
377 }
378
379 count = TXX9_SIO_TX_FIFO;
380 do {
381 sio_out(up, TXX9_SITFIFO, xmit->buf[xmit->tail]);
382 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
383 up->port.icount.tx++;
384 if (uart_circ_empty(xmit))
385 break;
386 } while (--count > 0);
387
388 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
389 uart_write_wakeup(&up->port);
390
391 if (uart_circ_empty(xmit))
392 serial_txx9_stop_tx(&up->port, 0);
393 }
394
395 static irqreturn_t serial_txx9_interrupt(int irq, void *dev_id, struct pt_regs *regs)
396 {
397 int pass_counter = 0;
398 struct uart_txx9_port *up = dev_id;
399 unsigned int status;
400
401 while (1) {
402 spin_lock(&up->port.lock);
403 status = sio_in(up, TXX9_SIDISR);
404 if (!(sio_in(up, TXX9_SIDICR) & TXX9_SIDICR_TIE))
405 status &= ~TXX9_SIDISR_TDIS;
406 if (!(status & (TXX9_SIDISR_TDIS | TXX9_SIDISR_RDIS |
407 TXX9_SIDISR_TOUT))) {
408 spin_unlock(&up->port.lock);
409 break;
410 }
411
412 if (status & TXX9_SIDISR_RDIS)
413 receive_chars(up, &status, regs);
414 if (status & TXX9_SIDISR_TDIS)
415 transmit_chars(up);
416 /* Clear TX/RX Int. Status */
417 sio_mask(up, TXX9_SIDISR,
418 TXX9_SIDISR_TDIS | TXX9_SIDISR_RDIS |
419 TXX9_SIDISR_TOUT);
420 spin_unlock(&up->port.lock);
421
422 if (pass_counter++ > PASS_LIMIT)
423 break;
424 }
425
426 return pass_counter ? IRQ_HANDLED : IRQ_NONE;
427 }
428
429 static unsigned int serial_txx9_tx_empty(struct uart_port *port)
430 {
431 struct uart_txx9_port *up = (struct uart_txx9_port *)port;
432 unsigned long flags;
433 unsigned int ret;
434
435 spin_lock_irqsave(&up->port.lock, flags);
436 ret = (sio_in(up, TXX9_SICISR) & TXX9_SICISR_TXALS) ? TIOCSER_TEMT : 0;
437 spin_unlock_irqrestore(&up->port.lock, flags);
438
439 return ret;
440 }
441
442 static unsigned int serial_txx9_get_mctrl(struct uart_port *port)
443 {
444 struct uart_txx9_port *up = (struct uart_txx9_port *)port;
445 unsigned long flags;
446 unsigned int ret;
447
448 spin_lock_irqsave(&up->port.lock, flags);
449 ret = ((sio_in(up, TXX9_SIFLCR) & TXX9_SIFLCR_RTSSC) ? 0 : TIOCM_RTS)
450 | ((sio_in(up, TXX9_SICISR) & TXX9_SICISR_CTSS) ? 0 : TIOCM_CTS);
451 spin_unlock_irqrestore(&up->port.lock, flags);
452
453 return ret;
454 }
455
456 static void serial_txx9_set_mctrl(struct uart_port *port, unsigned int mctrl)
457 {
458 struct uart_txx9_port *up = (struct uart_txx9_port *)port;
459 unsigned long flags;
460
461 spin_lock_irqsave(&up->port.lock, flags);
462 if (mctrl & TIOCM_RTS)
463 sio_mask(up, TXX9_SIFLCR, TXX9_SIFLCR_RTSSC);
464 else
465 sio_set(up, TXX9_SIFLCR, TXX9_SIFLCR_RTSSC);
466 spin_unlock_irqrestore(&up->port.lock, flags);
467 }
468
469 static void serial_txx9_break_ctl(struct uart_port *port, int break_state)
470 {
471 struct uart_txx9_port *up = (struct uart_txx9_port *)port;
472 unsigned long flags;
473
474 spin_lock_irqsave(&up->port.lock, flags);
475 if (break_state == -1)
476 sio_set(up, TXX9_SIFLCR, TXX9_SIFLCR_TBRK);
477 else
478 sio_mask(up, TXX9_SIFLCR, TXX9_SIFLCR_TBRK);
479 spin_unlock_irqrestore(&up->port.lock, flags);
480 }
481
482 static int serial_txx9_startup(struct uart_port *port)
483 {
484 struct uart_txx9_port *up = (struct uart_txx9_port *)port;
485 unsigned long flags;
486 int retval;
487
488 /*
489 * Clear the FIFO buffers and disable them.
490 * (they will be reeanbled in set_termios())
491 */
492 sio_set(up, TXX9_SIFCR,
493 TXX9_SIFCR_TFRST | TXX9_SIFCR_RFRST | TXX9_SIFCR_FRSTE);
494 /* clear reset */
495 sio_mask(up, TXX9_SIFCR,
496 TXX9_SIFCR_TFRST | TXX9_SIFCR_RFRST | TXX9_SIFCR_FRSTE);
497 sio_out(up, TXX9_SIDICR, 0);
498
499 /*
500 * Clear the interrupt registers.
501 */
502 sio_out(up, TXX9_SIDISR, 0);
503
504 retval = request_irq(up->port.irq, serial_txx9_interrupt,
505 SA_SHIRQ, "serial_txx9", up);
506 if (retval)
507 return retval;
508
509 /*
510 * Now, initialize the UART
511 */
512 spin_lock_irqsave(&up->port.lock, flags);
513 serial_txx9_set_mctrl(&up->port, up->port.mctrl);
514 spin_unlock_irqrestore(&up->port.lock, flags);
515
516 /* Enable RX/TX */
517 sio_mask(up, TXX9_SIFLCR, TXX9_SIFLCR_RSDE | TXX9_SIFLCR_TSDE);
518
519 /*
520 * Finally, enable interrupts.
521 */
522 sio_set(up, TXX9_SIDICR, TXX9_SIDICR_RIE);
523
524 return 0;
525 }
526
527 static void serial_txx9_shutdown(struct uart_port *port)
528 {
529 struct uart_txx9_port *up = (struct uart_txx9_port *)port;
530 unsigned long flags;
531
532 /*
533 * Disable interrupts from this port
534 */
535 sio_out(up, TXX9_SIDICR, 0); /* disable all intrs */
536
537 spin_lock_irqsave(&up->port.lock, flags);
538 serial_txx9_set_mctrl(&up->port, up->port.mctrl);
539 spin_unlock_irqrestore(&up->port.lock, flags);
540
541 /*
542 * Disable break condition
543 */
544 sio_mask(up, TXX9_SIFLCR, TXX9_SIFLCR_TBRK);
545
546 #ifdef CONFIG_SERIAL_TXX9_CONSOLE
547 if (up->port.cons && up->port.line == up->port.cons->index) {
548 free_irq(up->port.irq, up);
549 return;
550 }
551 #endif
552 /* reset FIFOs */
553 sio_set(up, TXX9_SIFCR,
554 TXX9_SIFCR_TFRST | TXX9_SIFCR_RFRST | TXX9_SIFCR_FRSTE);
555 /* clear reset */
556 sio_mask(up, TXX9_SIFCR,
557 TXX9_SIFCR_TFRST | TXX9_SIFCR_RFRST | TXX9_SIFCR_FRSTE);
558
559 /* Disable RX/TX */
560 sio_set(up, TXX9_SIFLCR, TXX9_SIFLCR_RSDE | TXX9_SIFLCR_TSDE);
561
562 free_irq(up->port.irq, up);
563 }
564
565 static void
566 serial_txx9_set_termios(struct uart_port *port, struct termios *termios,
567 struct termios *old)
568 {
569 struct uart_txx9_port *up = (struct uart_txx9_port *)port;
570 unsigned int cval, fcr = 0;
571 unsigned long flags;
572 unsigned int baud, quot;
573
574 cval = sio_in(up, TXX9_SILCR);
575 /* byte size and parity */
576 cval &= ~TXX9_SILCR_UMODE_MASK;
577 switch (termios->c_cflag & CSIZE) {
578 case CS7:
579 cval |= TXX9_SILCR_UMODE_7BIT;
580 break;
581 default:
582 case CS5: /* not supported */
583 case CS6: /* not supported */
584 case CS8:
585 cval |= TXX9_SILCR_UMODE_8BIT;
586 break;
587 }
588
589 cval &= ~TXX9_SILCR_USBL_MASK;
590 if (termios->c_cflag & CSTOPB)
591 cval |= TXX9_SILCR_USBL_2BIT;
592 else
593 cval |= TXX9_SILCR_USBL_1BIT;
594 cval &= ~(TXX9_SILCR_UPEN | TXX9_SILCR_UEPS);
595 if (termios->c_cflag & PARENB)
596 cval |= TXX9_SILCR_UPEN;
597 if (!(termios->c_cflag & PARODD))
598 cval |= TXX9_SILCR_UEPS;
599
600 /*
601 * Ask the core to calculate the divisor for us.
602 */
603 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16/2);
604 quot = uart_get_divisor(port, baud);
605
606 /* Set up FIFOs */
607 /* TX Int by FIFO Empty, RX Int by Receiving 1 char. */
608 fcr = TXX9_SIFCR_TDIL_MAX | TXX9_SIFCR_RDIL_1;
609
610 /*
611 * Ok, we're now changing the port state. Do it with
612 * interrupts disabled.
613 */
614 spin_lock_irqsave(&up->port.lock, flags);
615
616 /*
617 * Update the per-port timeout.
618 */
619 uart_update_timeout(port, termios->c_cflag, baud);
620
621 up->port.read_status_mask = TXX9_SIDISR_UOER |
622 TXX9_SIDISR_TDIS | TXX9_SIDISR_RDIS;
623 if (termios->c_iflag & INPCK)
624 up->port.read_status_mask |= TXX9_SIDISR_UFER | TXX9_SIDISR_UPER;
625 if (termios->c_iflag & (BRKINT | PARMRK))
626 up->port.read_status_mask |= TXX9_SIDISR_UBRK;
627
628 /*
629 * Characteres to ignore
630 */
631 up->port.ignore_status_mask = 0;
632 if (termios->c_iflag & IGNPAR)
633 up->port.ignore_status_mask |= TXX9_SIDISR_UPER | TXX9_SIDISR_UFER;
634 if (termios->c_iflag & IGNBRK) {
635 up->port.ignore_status_mask |= TXX9_SIDISR_UBRK;
636 /*
637 * If we're ignoring parity and break indicators,
638 * ignore overruns too (for real raw support).
639 */
640 if (termios->c_iflag & IGNPAR)
641 up->port.ignore_status_mask |= TXX9_SIDISR_UOER;
642 }
643
644 /*
645 * ignore all characters if CREAD is not set
646 */
647 if ((termios->c_cflag & CREAD) == 0)
648 up->port.ignore_status_mask |= TXX9_SIDISR_RDIS;
649
650 /* CTS flow control flag */
651 if ((termios->c_cflag & CRTSCTS) &&
652 (up->port.flags & UPF_TXX9_HAVE_CTS_LINE)) {
653 sio_set(up, TXX9_SIFLCR,
654 TXX9_SIFLCR_RCS | TXX9_SIFLCR_TES);
655 } else {
656 sio_mask(up, TXX9_SIFLCR,
657 TXX9_SIFLCR_RCS | TXX9_SIFLCR_TES);
658 }
659
660 sio_out(up, TXX9_SILCR, cval);
661 sio_quot_set(up, quot);
662 sio_out(up, TXX9_SIFCR, fcr);
663
664 serial_txx9_set_mctrl(&up->port, up->port.mctrl);
665 spin_unlock_irqrestore(&up->port.lock, flags);
666 }
667
668 static void
669 serial_txx9_pm(struct uart_port *port, unsigned int state,
670 unsigned int oldstate)
671 {
672 struct uart_txx9_port *up = (struct uart_txx9_port *)port;
673 if (state) {
674 /* sleep */
675
676 if (up->pm)
677 up->pm(port, state, oldstate);
678 } else {
679 /* wake */
680
681 if (up->pm)
682 up->pm(port, state, oldstate);
683 }
684 }
685
686 static int serial_txx9_request_resource(struct uart_txx9_port *up)
687 {
688 unsigned int size = TXX9_REGION_SIZE;
689 int ret = 0;
690
691 switch (up->port.iotype) {
692 default:
693 if (!up->port.mapbase)
694 break;
695
696 if (!request_mem_region(up->port.mapbase, size, "serial_txx9")) {
697 ret = -EBUSY;
698 break;
699 }
700
701 if (up->port.flags & UPF_IOREMAP) {
702 up->port.membase = ioremap(up->port.mapbase, size);
703 if (!up->port.membase) {
704 release_mem_region(up->port.mapbase, size);
705 ret = -ENOMEM;
706 }
707 }
708 break;
709
710 case UPIO_PORT:
711 if (!request_region(up->port.iobase, size, "serial_txx9"))
712 ret = -EBUSY;
713 break;
714 }
715 return ret;
716 }
717
718 static void serial_txx9_release_resource(struct uart_txx9_port *up)
719 {
720 unsigned int size = TXX9_REGION_SIZE;
721
722 switch (up->port.iotype) {
723 default:
724 if (!up->port.mapbase)
725 break;
726
727 if (up->port.flags & UPF_IOREMAP) {
728 iounmap(up->port.membase);
729 up->port.membase = NULL;
730 }
731
732 release_mem_region(up->port.mapbase, size);
733 break;
734
735 case UPIO_PORT:
736 release_region(up->port.iobase, size);
737 break;
738 }
739 }
740
741 static void serial_txx9_release_port(struct uart_port *port)
742 {
743 struct uart_txx9_port *up = (struct uart_txx9_port *)port;
744 serial_txx9_release_resource(up);
745 }
746
747 static int serial_txx9_request_port(struct uart_port *port)
748 {
749 struct uart_txx9_port *up = (struct uart_txx9_port *)port;
750 return serial_txx9_request_resource(up);
751 }
752
753 static void serial_txx9_config_port(struct uart_port *port, int uflags)
754 {
755 struct uart_txx9_port *up = (struct uart_txx9_port *)port;
756 unsigned long flags;
757 int ret;
758
759 /*
760 * Find the region that we can probe for. This in turn
761 * tells us whether we can probe for the type of port.
762 */
763 ret = serial_txx9_request_resource(up);
764 if (ret < 0)
765 return;
766 port->type = PORT_TXX9;
767 up->port.fifosize = TXX9_SIO_TX_FIFO;
768
769 #ifdef CONFIG_SERIAL_TXX9_CONSOLE
770 if (up->port.line == up->port.cons->index)
771 return;
772 #endif
773 spin_lock_irqsave(&up->port.lock, flags);
774 /*
775 * Reset the UART.
776 */
777 sio_out(up, TXX9_SIFCR, TXX9_SIFCR_SWRST);
778 #ifdef CONFIG_CPU_TX49XX
779 /* TX4925 BUG WORKAROUND. Accessing SIOC register
780 * immediately after soft reset causes bus error. */
781 iob();
782 udelay(1);
783 #endif
784 while (sio_in(up, TXX9_SIFCR) & TXX9_SIFCR_SWRST)
785 ;
786 /* TX Int by FIFO Empty, RX Int by Receiving 1 char. */
787 sio_set(up, TXX9_SIFCR,
788 TXX9_SIFCR_TDIL_MAX | TXX9_SIFCR_RDIL_1);
789 /* initial settings */
790 sio_out(up, TXX9_SILCR,
791 TXX9_SILCR_UMODE_8BIT | TXX9_SILCR_USBL_1BIT |
792 ((up->port.flags & UPF_TXX9_USE_SCLK) ?
793 TXX9_SILCR_SCS_SCLK_BG : TXX9_SILCR_SCS_IMCLK_BG));
794 sio_quot_set(up, uart_get_divisor(port, 9600));
795 sio_out(up, TXX9_SIFLCR, TXX9_SIFLCR_RTSTL_MAX /* 15 */);
796 spin_unlock_irqrestore(&up->port.lock, flags);
797 }
798
799 static int
800 serial_txx9_verify_port(struct uart_port *port, struct serial_struct *ser)
801 {
802 if (ser->irq < 0 ||
803 ser->baud_base < 9600 || ser->type != PORT_TXX9)
804 return -EINVAL;
805 return 0;
806 }
807
808 static const char *
809 serial_txx9_type(struct uart_port *port)
810 {
811 return "txx9";
812 }
813
814 static struct uart_ops serial_txx9_pops = {
815 .tx_empty = serial_txx9_tx_empty,
816 .set_mctrl = serial_txx9_set_mctrl,
817 .get_mctrl = serial_txx9_get_mctrl,
818 .stop_tx = serial_txx9_stop_tx,
819 .start_tx = serial_txx9_start_tx,
820 .stop_rx = serial_txx9_stop_rx,
821 .enable_ms = serial_txx9_enable_ms,
822 .break_ctl = serial_txx9_break_ctl,
823 .startup = serial_txx9_startup,
824 .shutdown = serial_txx9_shutdown,
825 .set_termios = serial_txx9_set_termios,
826 .pm = serial_txx9_pm,
827 .type = serial_txx9_type,
828 .release_port = serial_txx9_release_port,
829 .request_port = serial_txx9_request_port,
830 .config_port = serial_txx9_config_port,
831 .verify_port = serial_txx9_verify_port,
832 };
833
834 static struct uart_txx9_port serial_txx9_ports[UART_NR];
835
836 static void __init serial_txx9_register_ports(struct uart_driver *drv)
837 {
838 int i;
839
840 for (i = 0; i < UART_NR; i++) {
841 struct uart_txx9_port *up = &serial_txx9_ports[i];
842
843 up->port.line = i;
844 up->port.ops = &serial_txx9_pops;
845 uart_add_one_port(drv, &up->port);
846 }
847 }
848
849 #ifdef CONFIG_SERIAL_TXX9_CONSOLE
850
851 /*
852 * Wait for transmitter & holding register to empty
853 */
854 static inline void wait_for_xmitr(struct uart_txx9_port *up)
855 {
856 unsigned int tmout = 10000;
857
858 /* Wait up to 10ms for the character(s) to be sent. */
859 while (--tmout &&
860 !(sio_in(up, TXX9_SICISR) & TXX9_SICISR_TXALS))
861 udelay(1);
862
863 /* Wait up to 1s for flow control if necessary */
864 if (up->port.flags & UPF_CONS_FLOW) {
865 tmout = 1000000;
866 while (--tmout &&
867 (sio_in(up, TXX9_SICISR) & TXX9_SICISR_CTSS))
868 udelay(1);
869 }
870 }
871
872 /*
873 * Print a string to the serial port trying not to disturb
874 * any possible real use of the port...
875 *
876 * The console_lock must be held when we get here.
877 */
878 static void
879 serial_txx9_console_write(struct console *co, const char *s, unsigned int count)
880 {
881 struct uart_txx9_port *up = &serial_txx9_ports[co->index];
882 unsigned int ier, flcr;
883 int i;
884
885 /*
886 * First save the UER then disable the interrupts
887 */
888 ier = sio_in(up, TXX9_SIDICR);
889 sio_out(up, TXX9_SIDICR, 0);
890 /*
891 * Disable flow-control if enabled (and unnecessary)
892 */
893 flcr = sio_in(up, TXX9_SIFLCR);
894 if (!(up->port.flags & UPF_CONS_FLOW) && (flcr & TXX9_SIFLCR_TES))
895 sio_out(up, TXX9_SIFLCR, flcr & ~TXX9_SIFLCR_TES);
896
897 /*
898 * Now, do each character
899 */
900 for (i = 0; i < count; i++, s++) {
901 wait_for_xmitr(up);
902
903 /*
904 * Send the character out.
905 * If a LF, also do CR...
906 */
907 sio_out(up, TXX9_SITFIFO, *s);
908 if (*s == 10) {
909 wait_for_xmitr(up);
910 sio_out(up, TXX9_SITFIFO, 13);
911 }
912 }
913
914 /*
915 * Finally, wait for transmitter to become empty
916 * and restore the IER
917 */
918 wait_for_xmitr(up);
919 sio_out(up, TXX9_SIFLCR, flcr);
920 sio_out(up, TXX9_SIDICR, ier);
921 }
922
923 static int serial_txx9_console_setup(struct console *co, char *options)
924 {
925 struct uart_port *port;
926 struct uart_txx9_port *up;
927 int baud = 9600;
928 int bits = 8;
929 int parity = 'n';
930 int flow = 'n';
931
932 /*
933 * Check whether an invalid uart number has been specified, and
934 * if so, search for the first available port that does have
935 * console support.
936 */
937 if (co->index >= UART_NR)
938 co->index = 0;
939 up = &serial_txx9_ports[co->index];
940 port = &up->port;
941 if (!port->ops)
942 return -ENODEV;
943
944 /*
945 * Temporary fix.
946 */
947 spin_lock_init(&port->lock);
948
949 /*
950 * Disable UART interrupts, set DTR and RTS high
951 * and set speed.
952 */
953 sio_out(up, TXX9_SIDICR, 0);
954 /* initial settings */
955 sio_out(up, TXX9_SILCR,
956 TXX9_SILCR_UMODE_8BIT | TXX9_SILCR_USBL_1BIT |
957 ((port->flags & UPF_TXX9_USE_SCLK) ?
958 TXX9_SILCR_SCS_SCLK_BG : TXX9_SILCR_SCS_IMCLK_BG));
959 sio_out(up, TXX9_SIFLCR, TXX9_SIFLCR_RTSTL_MAX /* 15 */);
960
961 if (options)
962 uart_parse_options(options, &baud, &parity, &bits, &flow);
963
964 return uart_set_options(port, co, baud, parity, bits, flow);
965 }
966
967 static struct uart_driver serial_txx9_reg;
968 static struct console serial_txx9_console = {
969 .name = TXX9_TTY_NAME,
970 .write = serial_txx9_console_write,
971 .device = uart_console_device,
972 .setup = serial_txx9_console_setup,
973 .flags = CON_PRINTBUFFER,
974 .index = -1,
975 .data = &serial_txx9_reg,
976 };
977
978 static int __init serial_txx9_console_init(void)
979 {
980 register_console(&serial_txx9_console);
981 return 0;
982 }
983 console_initcall(serial_txx9_console_init);
984
985 static int __init serial_txx9_late_console_init(void)
986 {
987 if (!(serial_txx9_console.flags & CON_ENABLED))
988 register_console(&serial_txx9_console);
989 return 0;
990 }
991 late_initcall(serial_txx9_late_console_init);
992
993 #define SERIAL_TXX9_CONSOLE &serial_txx9_console
994 #else
995 #define SERIAL_TXX9_CONSOLE NULL
996 #endif
997
998 static struct uart_driver serial_txx9_reg = {
999 .owner = THIS_MODULE,
1000 .driver_name = "serial_txx9",
1001 .devfs_name = TXX9_TTY_DEVFS_NAME,
1002 .dev_name = TXX9_TTY_NAME,
1003 .major = TXX9_TTY_MAJOR,
1004 .minor = TXX9_TTY_MINOR_START,
1005 .nr = UART_NR,
1006 .cons = SERIAL_TXX9_CONSOLE,
1007 };
1008
1009 int __init early_serial_txx9_setup(struct uart_port *port)
1010 {
1011 if (port->line >= ARRAY_SIZE(serial_txx9_ports))
1012 return -ENODEV;
1013
1014 serial_txx9_ports[port->line].port = *port;
1015 serial_txx9_ports[port->line].port.ops = &serial_txx9_pops;
1016 serial_txx9_ports[port->line].port.flags |= UPF_BOOT_AUTOCONF;
1017 return 0;
1018 }
1019
1020 #ifdef ENABLE_SERIAL_TXX9_PCI
1021 /**
1022 * serial_txx9_suspend_port - suspend one serial port
1023 * @line: serial line number
1024 * @level: the level of port suspension, as per uart_suspend_port
1025 *
1026 * Suspend one serial port.
1027 */
1028 static void serial_txx9_suspend_port(int line)
1029 {
1030 uart_suspend_port(&serial_txx9_reg, &serial_txx9_ports[line].port);
1031 }
1032
1033 /**
1034 * serial_txx9_resume_port - resume one serial port
1035 * @line: serial line number
1036 * @level: the level of port resumption, as per uart_resume_port
1037 *
1038 * Resume one serial port.
1039 */
1040 static void serial_txx9_resume_port(int line)
1041 {
1042 uart_resume_port(&serial_txx9_reg, &serial_txx9_ports[line].port);
1043 }
1044
1045 /*
1046 * Probe one serial board. Unfortunately, there is no rhyme nor reason
1047 * to the arrangement of serial ports on a PCI card.
1048 */
1049 static int __devinit
1050 pciserial_txx9_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
1051 {
1052 struct uart_port port;
1053 int line;
1054 int rc;
1055
1056 rc = pci_enable_device(dev);
1057 if (rc)
1058 return rc;
1059
1060 memset(&port, 0, sizeof(port));
1061 port.ops = &serial_txx9_pops;
1062 port.flags |= UPF_BOOT_AUTOCONF; /* uart_ops.config_port will be called */
1063 port.flags |= UPF_TXX9_HAVE_CTS_LINE;
1064 port.uartclk = 66670000;
1065 port.irq = dev->irq;
1066 port.iotype = UPIO_PORT;
1067 port.iobase = pci_resource_start(dev, 1);
1068 line = uart_register_port(&serial_txx9_reg, &port);
1069 if (line < 0) {
1070 printk(KERN_WARNING "Couldn't register serial port %s: %d\n", pci_name(dev), line);
1071 }
1072 pci_set_drvdata(dev, (void *)(long)line);
1073
1074 return 0;
1075 }
1076
1077 static void __devexit pciserial_txx9_remove_one(struct pci_dev *dev)
1078 {
1079 int line = (int)(long)pci_get_drvdata(dev);
1080
1081 pci_set_drvdata(dev, NULL);
1082
1083 if (line) {
1084 uart_unregister_port(&serial_txx9_reg, line);
1085 pci_disable_device(dev);
1086 }
1087 }
1088
1089 static int pciserial_txx9_suspend_one(struct pci_dev *dev, pm_message_t state)
1090 {
1091 int line = (int)(long)pci_get_drvdata(dev);
1092
1093 if (line)
1094 serial_txx9_suspend_port(line);
1095 return 0;
1096 }
1097
1098 static int pciserial_txx9_resume_one(struct pci_dev *dev)
1099 {
1100 int line = (int)(long)pci_get_drvdata(dev);
1101
1102 if (line)
1103 serial_txx9_resume_port(line);
1104 return 0;
1105 }
1106
1107 static struct pci_device_id serial_txx9_pci_tbl[] = {
1108 { PCI_VENDOR_ID_TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_TC86C001_MISC,
1109 PCI_ANY_ID, PCI_ANY_ID,
1110 0, 0, 0 },
1111 { 0, }
1112 };
1113
1114 static struct pci_driver serial_txx9_pci_driver = {
1115 .name = "serial_txx9",
1116 .probe = pciserial_txx9_init_one,
1117 .remove = __devexit_p(pciserial_txx9_remove_one),
1118 .suspend = pciserial_txx9_suspend_one,
1119 .resume = pciserial_txx9_resume_one,
1120 .id_table = serial_txx9_pci_tbl,
1121 };
1122
1123 MODULE_DEVICE_TABLE(pci, serial_txx9_pci_tbl);
1124 #endif /* ENABLE_SERIAL_TXX9_PCI */
1125
1126 static int __init serial_txx9_init(void)
1127 {
1128 int ret;
1129
1130 printk(KERN_INFO "%s version %s\n", serial_name, serial_version);
1131
1132 ret = uart_register_driver(&serial_txx9_reg);
1133 if (ret >= 0) {
1134 serial_txx9_register_ports(&serial_txx9_reg);
1135
1136 #ifdef ENABLE_SERIAL_TXX9_PCI
1137 ret = pci_module_init(&serial_txx9_pci_driver);
1138 #endif
1139 }
1140 return ret;
1141 }
1142
1143 static void __exit serial_txx9_exit(void)
1144 {
1145 int i;
1146
1147 #ifdef ENABLE_SERIAL_TXX9_PCI
1148 pci_unregister_driver(&serial_txx9_pci_driver);
1149 #endif
1150 for (i = 0; i < UART_NR; i++)
1151 uart_remove_one_port(&serial_txx9_reg, &serial_txx9_ports[i].port);
1152
1153 uart_unregister_driver(&serial_txx9_reg);
1154 }
1155
1156 module_init(serial_txx9_init);
1157 module_exit(serial_txx9_exit);
1158
1159 MODULE_LICENSE("GPL");
1160 MODULE_DESCRIPTION("TX39/49 serial driver");
1161
1162 MODULE_ALIAS_CHARDEV_MAJOR(TXX9_TTY_MAJOR);
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