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[TG3]: Set minimal hw interrupt mitigation.
[linux-2.6/verdex.git] / drivers / serial / sunsab.c
blob39b788d95e39d9eb8f11578552f03933ad0b4e52
1 /* sunsab.c: ASYNC Driver for the SIEMENS SAB82532 DUSCC.
2 *
3 * Copyright (C) 1997 Eddie C. Dost (ecd@skynet.be)
4 * Copyright (C) 2002 David S. Miller (davem@redhat.com)
5 *
6 * Rewrote buffer handling to use CIRC(Circular Buffer) macros.
7 * Maxim Krasnyanskiy <maxk@qualcomm.com>
8 *
9 * Fixed to use tty_get_baud_rate, and to allow for arbitrary baud
10 * rates to be programmed into the UART. Also eliminated a lot of
11 * duplicated code in the console setup.
12 * Theodore Ts'o <tytso@mit.edu>, 2001-Oct-12
13 *
14 * Ported to new 2.5.x UART layer.
15 * David S. Miller <davem@redhat.com>
16 */
17
18 #include <linux/config.h>
19 #include <linux/module.h>
20 #include <linux/kernel.h>
21 #include <linux/sched.h>
22 #include <linux/errno.h>
23 #include <linux/tty.h>
24 #include <linux/tty_flip.h>
25 #include <linux/major.h>
26 #include <linux/string.h>
27 #include <linux/ptrace.h>
28 #include <linux/ioport.h>
29 #include <linux/circ_buf.h>
30 #include <linux/serial.h>
31 #include <linux/sysrq.h>
32 #include <linux/console.h>
33 #include <linux/spinlock.h>
34 #include <linux/slab.h>
35 #include <linux/delay.h>
36 #include <linux/init.h>
37
38 #include <asm/io.h>
39 #include <asm/irq.h>
40 #include <asm/oplib.h>
41 #include <asm/ebus.h>
42
43 #if defined(CONFIG_SERIAL_SUNZILOG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
44 #define SUPPORT_SYSRQ
45 #endif
46
47 #include <linux/serial_core.h>
48
49 #include "suncore.h"
50 #include "sunsab.h"
51
52 struct uart_sunsab_port {
53 struct uart_port port; /* Generic UART port */
54 union sab82532_async_regs __iomem *regs; /* Chip registers */
55 unsigned long irqflags; /* IRQ state flags */
56 int dsr; /* Current DSR state */
57 unsigned int cec_timeout; /* Chip poll timeout... */
58 unsigned int tec_timeout; /* likewise */
59 unsigned char interrupt_mask0;/* ISR0 masking */
60 unsigned char interrupt_mask1;/* ISR1 masking */
61 unsigned char pvr_dtr_bit; /* Which PVR bit is DTR */
62 unsigned char pvr_dsr_bit; /* Which PVR bit is DSR */
63 int type; /* SAB82532 version */
64 };
65
66 /*
67 * This assumes you have a 29.4912 MHz clock for your UART.
68 */
69 #define SAB_BASE_BAUD ( 29491200 / 16 )
70
71 static char *sab82532_version[16] = {
72 "V1.0", "V2.0", "V3.2", "V(0x03)",
73 "V(0x04)", "V(0x05)", "V(0x06)", "V(0x07)",
74 "V(0x08)", "V(0x09)", "V(0x0a)", "V(0x0b)",
75 "V(0x0c)", "V(0x0d)", "V(0x0e)", "V(0x0f)"
76 };
77
78 #define SAB82532_MAX_TEC_TIMEOUT 200000 /* 1 character time (at 50 baud) */
79 #define SAB82532_MAX_CEC_TIMEOUT 50000 /* 2.5 TX CLKs (at 50 baud) */
80
81 #define SAB82532_RECV_FIFO_SIZE 32 /* Standard async fifo sizes */
82 #define SAB82532_XMIT_FIFO_SIZE 32
83
84 static __inline__ void sunsab_tec_wait(struct uart_sunsab_port *up)
85 {
86 int timeout = up->tec_timeout;
87
88 while ((readb(&up->regs->r.star) & SAB82532_STAR_TEC) && --timeout)
89 udelay(1);
90 }
91
92 static __inline__ void sunsab_cec_wait(struct uart_sunsab_port *up)
93 {
94 int timeout = up->cec_timeout;
95
96 while ((readb(&up->regs->r.star) & SAB82532_STAR_CEC) && --timeout)
97 udelay(1);
98 }
99
100 static struct tty_struct *
101 receive_chars(struct uart_sunsab_port *up,
102 union sab82532_irq_status *stat,
103 struct pt_regs *regs)
104 {
105 struct tty_struct *tty = NULL;
106 unsigned char buf[32];
107 int saw_console_brk = 0;
108 int free_fifo = 0;
109 int count = 0;
110 int i;
111
112 if (up->port.info != NULL) /* Unopened serial console */
113 tty = up->port.info->tty;
114
115 /* Read number of BYTES (Character + Status) available. */
116 if (stat->sreg.isr0 & SAB82532_ISR0_RPF) {
117 count = SAB82532_RECV_FIFO_SIZE;
118 free_fifo++;
119 }
120
121 if (stat->sreg.isr0 & SAB82532_ISR0_TCD) {
122 count = readb(&up->regs->r.rbcl) & (SAB82532_RECV_FIFO_SIZE - 1);
123 free_fifo++;
124 }
125
126 /* Issue a FIFO read command in case we where idle. */
127 if (stat->sreg.isr0 & SAB82532_ISR0_TIME) {
128 sunsab_cec_wait(up);
129 writeb(SAB82532_CMDR_RFRD, &up->regs->w.cmdr);
130 return tty;
131 }
132
133 if (stat->sreg.isr0 & SAB82532_ISR0_RFO)
134 free_fifo++;
135
136 /* Read the FIFO. */
137 for (i = 0; i < count; i++)
138 buf[i] = readb(&up->regs->r.rfifo[i]);
139
140 /* Issue Receive Message Complete command. */
141 if (free_fifo) {
142 sunsab_cec_wait(up);
143 writeb(SAB82532_CMDR_RMC, &up->regs->w.cmdr);
144 }
145
146 /* Count may be zero for BRK, so we check for it here */
147 if ((stat->sreg.isr1 & SAB82532_ISR1_BRK) &&
148 (up->port.line == up->port.cons->index))
149 saw_console_brk = 1;
150
151 for (i = 0; i < count; i++) {
152 unsigned char ch = buf[i];
153
154 if (tty == NULL) {
155 uart_handle_sysrq_char(&up->port, ch, regs);
156 continue;
157 }
158
159 if (unlikely(tty->flip.count >= TTY_FLIPBUF_SIZE)) {
160 tty->flip.work.func((void *)tty);
161 if (tty->flip.count >= TTY_FLIPBUF_SIZE)
162 return tty; // if TTY_DONT_FLIP is set
163 }
164
165 *tty->flip.char_buf_ptr = ch;
166 *tty->flip.flag_buf_ptr = TTY_NORMAL;
167 up->port.icount.rx++;
168
169 if (unlikely(stat->sreg.isr0 & (SAB82532_ISR0_PERR |
170 SAB82532_ISR0_FERR |
171 SAB82532_ISR0_RFO)) ||
172 unlikely(stat->sreg.isr1 & SAB82532_ISR1_BRK)) {
173 /*
174 * For statistics only
175 */
176 if (stat->sreg.isr1 & SAB82532_ISR1_BRK) {
177 stat->sreg.isr0 &= ~(SAB82532_ISR0_PERR |
178 SAB82532_ISR0_FERR);
179 up->port.icount.brk++;
180 /*
181 * We do the SysRQ and SAK checking
182 * here because otherwise the break
183 * may get masked by ignore_status_mask
184 * or read_status_mask.
185 */
186 if (uart_handle_break(&up->port))
187 continue;
188 } else if (stat->sreg.isr0 & SAB82532_ISR0_PERR)
189 up->port.icount.parity++;
190 else if (stat->sreg.isr0 & SAB82532_ISR0_FERR)
191 up->port.icount.frame++;
192 if (stat->sreg.isr0 & SAB82532_ISR0_RFO)
193 up->port.icount.overrun++;
194
195 /*
196 * Mask off conditions which should be ingored.
197 */
198 stat->sreg.isr0 &= (up->port.read_status_mask & 0xff);
199 stat->sreg.isr1 &= ((up->port.read_status_mask >> 8) & 0xff);
200
201 if (stat->sreg.isr1 & SAB82532_ISR1_BRK) {
202 *tty->flip.flag_buf_ptr = TTY_BREAK;
203 } else if (stat->sreg.isr0 & SAB82532_ISR0_PERR)
204 *tty->flip.flag_buf_ptr = TTY_PARITY;
205 else if (stat->sreg.isr0 & SAB82532_ISR0_FERR)
206 *tty->flip.flag_buf_ptr = TTY_FRAME;
207 }
208
209 if (uart_handle_sysrq_char(&up->port, ch, regs))
210 continue;
211
212 if ((stat->sreg.isr0 & (up->port.ignore_status_mask & 0xff)) == 0 &&
213 (stat->sreg.isr1 & ((up->port.ignore_status_mask >> 8) & 0xff)) == 0){
214 tty->flip.flag_buf_ptr++;
215 tty->flip.char_buf_ptr++;
216 tty->flip.count++;
217 }
218 if ((stat->sreg.isr0 & SAB82532_ISR0_RFO) &&
219 tty->flip.count < TTY_FLIPBUF_SIZE) {
220 /*
221 * Overrun is special, since it's reported
222 * immediately, and doesn't affect the current
223 * character.
224 */
225 *tty->flip.flag_buf_ptr = TTY_OVERRUN;
226 tty->flip.flag_buf_ptr++;
227 tty->flip.char_buf_ptr++;
228 tty->flip.count++;
229 }
230 }
231
232 if (saw_console_brk)
233 sun_do_break();
234
235 return tty;
236 }
237
238 static void sunsab_stop_tx(struct uart_port *, unsigned int);
239
240 static void transmit_chars(struct uart_sunsab_port *up,
241 union sab82532_irq_status *stat)
242 {
243 struct circ_buf *xmit = &up->port.info->xmit;
244 int i;
245
246 if (stat->sreg.isr1 & SAB82532_ISR1_ALLS) {
247 up->interrupt_mask1 |= SAB82532_IMR1_ALLS;
248 writeb(up->interrupt_mask1, &up->regs->w.imr1);
249 set_bit(SAB82532_ALLS, &up->irqflags);
250 }
251
252 #if 0 /* bde@nwlink.com says this check causes problems */
253 if (!(stat->sreg.isr1 & SAB82532_ISR1_XPR))
254 return;
255 #endif
256
257 if (!(readb(&up->regs->r.star) & SAB82532_STAR_XFW))
258 return;
259
260 set_bit(SAB82532_XPR, &up->irqflags);
261
262 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
263 up->interrupt_mask1 |= SAB82532_IMR1_XPR;
264 writeb(up->interrupt_mask1, &up->regs->w.imr1);
265 uart_write_wakeup(&up->port);
266 return;
267 }
268
269 up->interrupt_mask1 &= ~(SAB82532_IMR1_ALLS|SAB82532_IMR1_XPR);
270 writeb(up->interrupt_mask1, &up->regs->w.imr1);
271 clear_bit(SAB82532_ALLS, &up->irqflags);
272
273 /* Stuff 32 bytes into Transmit FIFO. */
274 clear_bit(SAB82532_XPR, &up->irqflags);
275 for (i = 0; i < up->port.fifosize; i++) {
276 writeb(xmit->buf[xmit->tail],
277 &up->regs->w.xfifo[i]);
278 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
279 up->port.icount.tx++;
280 if (uart_circ_empty(xmit))
281 break;
282 }
283
284 /* Issue a Transmit Frame command. */
285 sunsab_cec_wait(up);
286 writeb(SAB82532_CMDR_XF, &up->regs->w.cmdr);
287
288 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
289 uart_write_wakeup(&up->port);
290
291 if (uart_circ_empty(xmit))
292 sunsab_stop_tx(&up->port, 0);
293 }
294
295 static void check_status(struct uart_sunsab_port *up,
296 union sab82532_irq_status *stat)
297 {
298 if (stat->sreg.isr0 & SAB82532_ISR0_CDSC)
299 uart_handle_dcd_change(&up->port,
300 !(readb(&up->regs->r.vstr) & SAB82532_VSTR_CD));
301
302 if (stat->sreg.isr1 & SAB82532_ISR1_CSC)
303 uart_handle_cts_change(&up->port,
304 (readb(&up->regs->r.star) & SAB82532_STAR_CTS));
305
306 if ((readb(&up->regs->r.pvr) & up->pvr_dsr_bit) ^ up->dsr) {
307 up->dsr = (readb(&up->regs->r.pvr) & up->pvr_dsr_bit) ? 0 : 1;
308 up->port.icount.dsr++;
309 }
310
311 wake_up_interruptible(&up->port.info->delta_msr_wait);
312 }
313
314 static irqreturn_t sunsab_interrupt(int irq, void *dev_id, struct pt_regs *regs)
315 {
316 struct uart_sunsab_port *up = dev_id;
317 struct tty_struct *tty;
318 union sab82532_irq_status status;
319 unsigned long flags;
320
321 spin_lock_irqsave(&up->port.lock, flags);
322
323 status.stat = 0;
324 if (readb(&up->regs->r.gis) & SAB82532_GIS_ISA0)
325 status.sreg.isr0 = readb(&up->regs->r.isr0);
326 if (readb(&up->regs->r.gis) & SAB82532_GIS_ISA1)
327 status.sreg.isr1 = readb(&up->regs->r.isr1);
328
329 tty = NULL;
330 if (status.stat) {
331 if ((status.sreg.isr0 & (SAB82532_ISR0_TCD | SAB82532_ISR0_TIME |
332 SAB82532_ISR0_RFO | SAB82532_ISR0_RPF)) ||
333 (status.sreg.isr1 & SAB82532_ISR1_BRK))
334 tty = receive_chars(up, &status, regs);
335 if ((status.sreg.isr0 & SAB82532_ISR0_CDSC) ||
336 (status.sreg.isr1 & SAB82532_ISR1_CSC))
337 check_status(up, &status);
338 if (status.sreg.isr1 & (SAB82532_ISR1_ALLS | SAB82532_ISR1_XPR))
339 transmit_chars(up, &status);
340 }
341
342 spin_unlock(&up->port.lock);
343
344 if (tty)
345 tty_flip_buffer_push(tty);
346
347 up++;
348
349 spin_lock(&up->port.lock);
350
351 status.stat = 0;
352 if (readb(&up->regs->r.gis) & SAB82532_GIS_ISB0)
353 status.sreg.isr0 = readb(&up->regs->r.isr0);
354 if (readb(&up->regs->r.gis) & SAB82532_GIS_ISB1)
355 status.sreg.isr1 = readb(&up->regs->r.isr1);
356
357 tty = NULL;
358 if (status.stat) {
359 if ((status.sreg.isr0 & (SAB82532_ISR0_TCD | SAB82532_ISR0_TIME |
360 SAB82532_ISR0_RFO | SAB82532_ISR0_RPF)) ||
361 (status.sreg.isr1 & SAB82532_ISR1_BRK))
362
363 tty = receive_chars(up, &status, regs);
364 if ((status.sreg.isr0 & SAB82532_ISR0_CDSC) ||
365 (status.sreg.isr1 & (SAB82532_ISR1_BRK | SAB82532_ISR1_CSC)))
366 check_status(up, &status);
367 if (status.sreg.isr1 & (SAB82532_ISR1_ALLS | SAB82532_ISR1_XPR))
368 transmit_chars(up, &status);
369 }
370
371 spin_unlock_irqrestore(&up->port.lock, flags);
372
373 if (tty)
374 tty_flip_buffer_push(tty);
375
376 return IRQ_HANDLED;
377 }
378
379 /* port->lock is not held. */
380 static unsigned int sunsab_tx_empty(struct uart_port *port)
381 {
382 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
383 int ret;
384
385 /* Do not need a lock for a state test like this. */
386 if (test_bit(SAB82532_ALLS, &up->irqflags))
387 ret = TIOCSER_TEMT;
388 else
389 ret = 0;
390
391 return ret;
392 }
393
394 /* port->lock held by caller. */
395 static void sunsab_set_mctrl(struct uart_port *port, unsigned int mctrl)
396 {
397 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
398
399 if (mctrl & TIOCM_RTS) {
400 writeb(readb(&up->regs->rw.mode) & ~SAB82532_MODE_FRTS,
401 &up->regs->rw.mode);
402 writeb(readb(&up->regs->rw.mode) | SAB82532_MODE_RTS,
403 &up->regs->rw.mode);
404 } else {
405 writeb(readb(&up->regs->rw.mode) | SAB82532_MODE_FRTS,
406 &up->regs->rw.mode);
407 writeb(readb(&up->regs->rw.mode) | SAB82532_MODE_RTS,
408 &up->regs->rw.mode);
409 }
410 if (mctrl & TIOCM_DTR) {
411 writeb(readb(&up->regs->rw.pvr) & ~(up->pvr_dtr_bit), &up->regs->rw.pvr);
412 } else {
413 writeb(readb(&up->regs->rw.pvr) | up->pvr_dtr_bit, &up->regs->rw.pvr);
414 }
415 }
416
417 /* port->lock is not held. */
418 static unsigned int sunsab_get_mctrl(struct uart_port *port)
419 {
420 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
421 unsigned long flags;
422 unsigned char val;
423 unsigned int result;
424
425 result = 0;
426
427 spin_lock_irqsave(&up->port.lock, flags);
428
429 val = readb(&up->regs->r.pvr);
430 result |= (val & up->pvr_dsr_bit) ? 0 : TIOCM_DSR;
431
432 val = readb(&up->regs->r.vstr);
433 result |= (val & SAB82532_VSTR_CD) ? 0 : TIOCM_CAR;
434
435 val = readb(&up->regs->r.star);
436 result |= (val & SAB82532_STAR_CTS) ? TIOCM_CTS : 0;
437
438 spin_unlock_irqrestore(&up->port.lock, flags);
439
440 return result;
441 }
442
443 /* port->lock held by caller. */
444 static void sunsab_stop_tx(struct uart_port *port, unsigned int tty_stop)
445 {
446 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
447
448 up->interrupt_mask1 |= SAB82532_IMR1_XPR;
449 writeb(up->interrupt_mask1, &up->regs->w.imr1);
450 }
451
452 /* port->lock held by caller. */
453 static void sunsab_start_tx(struct uart_port *port, unsigned int tty_start)
454 {
455 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
456 struct circ_buf *xmit = &up->port.info->xmit;
457 int i;
458
459 up->interrupt_mask1 &= ~(SAB82532_IMR1_ALLS|SAB82532_IMR1_XPR);
460 writeb(up->interrupt_mask1, &up->regs->w.imr1);
461
462 if (!test_bit(SAB82532_XPR, &up->irqflags))
463 return;
464
465 clear_bit(SAB82532_ALLS, &up->irqflags);
466 clear_bit(SAB82532_XPR, &up->irqflags);
467
468 for (i = 0; i < up->port.fifosize; i++) {
469 writeb(xmit->buf[xmit->tail],
470 &up->regs->w.xfifo[i]);
471 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
472 up->port.icount.tx++;
473 if (uart_circ_empty(xmit))
474 break;
475 }
476
477 /* Issue a Transmit Frame command. */
478 sunsab_cec_wait(up);
479 writeb(SAB82532_CMDR_XF, &up->regs->w.cmdr);
480 }
481
482 /* port->lock is not held. */
483 static void sunsab_send_xchar(struct uart_port *port, char ch)
484 {
485 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
486 unsigned long flags;
487
488 spin_lock_irqsave(&up->port.lock, flags);
489
490 sunsab_tec_wait(up);
491 writeb(ch, &up->regs->w.tic);
492
493 spin_unlock_irqrestore(&up->port.lock, flags);
494 }
495
496 /* port->lock held by caller. */
497 static void sunsab_stop_rx(struct uart_port *port)
498 {
499 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
500
501 up->interrupt_mask0 |= SAB82532_ISR0_TCD;
502 writeb(up->interrupt_mask1, &up->regs->w.imr0);
503 }
504
505 /* port->lock held by caller. */
506 static void sunsab_enable_ms(struct uart_port *port)
507 {
508 /* For now we always receive these interrupts. */
509 }
510
511 /* port->lock is not held. */
512 static void sunsab_break_ctl(struct uart_port *port, int break_state)
513 {
514 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
515 unsigned long flags;
516 unsigned char val;
517
518 spin_lock_irqsave(&up->port.lock, flags);
519
520 val = readb(&up->regs->rw.dafo);
521 if (break_state)
522 val |= SAB82532_DAFO_XBRK;
523 else
524 val &= ~SAB82532_DAFO_XBRK;
525 writeb(val, &up->regs->rw.dafo);
526
527 spin_unlock_irqrestore(&up->port.lock, flags);
528 }
529
530 /* port->lock is not held. */
531 static int sunsab_startup(struct uart_port *port)
532 {
533 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
534 unsigned long flags;
535 unsigned char tmp;
536
537 spin_lock_irqsave(&up->port.lock, flags);
538
539 /*
540 * Wait for any commands or immediate characters
541 */
542 sunsab_cec_wait(up);
543 sunsab_tec_wait(up);
544
545 /*
546 * Clear the FIFO buffers.
547 */
548 writeb(SAB82532_CMDR_RRES, &up->regs->w.cmdr);
549 sunsab_cec_wait(up);
550 writeb(SAB82532_CMDR_XRES, &up->regs->w.cmdr);
551
552 /*
553 * Clear the interrupt registers.
554 */
555 (void) readb(&up->regs->r.isr0);
556 (void) readb(&up->regs->r.isr1);
557
558 /*
559 * Now, initialize the UART
560 */
561 writeb(0, &up->regs->w.ccr0); /* power-down */
562 writeb(SAB82532_CCR0_MCE | SAB82532_CCR0_SC_NRZ |
563 SAB82532_CCR0_SM_ASYNC, &up->regs->w.ccr0);
564 writeb(SAB82532_CCR1_ODS | SAB82532_CCR1_BCR | 7, &up->regs->w.ccr1);
565 writeb(SAB82532_CCR2_BDF | SAB82532_CCR2_SSEL |
566 SAB82532_CCR2_TOE, &up->regs->w.ccr2);
567 writeb(0, &up->regs->w.ccr3);
568 writeb(SAB82532_CCR4_MCK4 | SAB82532_CCR4_EBRG, &up->regs->w.ccr4);
569 writeb(SAB82532_MODE_RTS | SAB82532_MODE_FCTS |
570 SAB82532_MODE_RAC, &up->regs->w.mode);
571 writeb(SAB82532_RFC_DPS|SAB82532_RFC_RFTH_32, &up->regs->w.rfc);
572
573 tmp = readb(&up->regs->rw.ccr0);
574 tmp |= SAB82532_CCR0_PU; /* power-up */
575 writeb(tmp, &up->regs->rw.ccr0);
576
577 /*
578 * Finally, enable interrupts
579 */
580 up->interrupt_mask0 = (SAB82532_IMR0_PERR | SAB82532_IMR0_FERR |
581 SAB82532_IMR0_PLLA);
582 writeb(up->interrupt_mask0, &up->regs->w.imr0);
583 up->interrupt_mask1 = (SAB82532_IMR1_BRKT | SAB82532_IMR1_ALLS |
584 SAB82532_IMR1_XOFF | SAB82532_IMR1_TIN |
585 SAB82532_IMR1_CSC | SAB82532_IMR1_XON |
586 SAB82532_IMR1_XPR);
587 writeb(up->interrupt_mask1, &up->regs->w.imr1);
588 set_bit(SAB82532_ALLS, &up->irqflags);
589 set_bit(SAB82532_XPR, &up->irqflags);
590
591 spin_unlock_irqrestore(&up->port.lock, flags);
592
593 return 0;
594 }
595
596 /* port->lock is not held. */
597 static void sunsab_shutdown(struct uart_port *port)
598 {
599 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
600 unsigned long flags;
601 unsigned char tmp;
602
603 spin_lock_irqsave(&up->port.lock, flags);
604
605 /* Disable Interrupts */
606 up->interrupt_mask0 = 0xff;
607 writeb(up->interrupt_mask0, &up->regs->w.imr0);
608 up->interrupt_mask1 = 0xff;
609 writeb(up->interrupt_mask1, &up->regs->w.imr1);
610
611 /* Disable break condition */
612 tmp = readb(&up->regs->rw.dafo);
613 tmp &= ~SAB82532_DAFO_XBRK;
614 writeb(tmp, &up->regs->rw.dafo);
615
616 /* Disable Receiver */
617 tmp = readb(&up->regs->rw.mode);
618 tmp &= ~SAB82532_MODE_RAC;
619 writeb(tmp, &up->regs->rw.mode);
620
621 /*
622 * XXX FIXME
623 *
624 * If the chip is powered down here the system hangs/crashes during
625 * reboot or shutdown. This needs to be investigated further,
626 * similar behaviour occurs in 2.4 when the driver is configured
627 * as a module only. One hint may be that data is sometimes
628 * transmitted at 9600 baud during shutdown (regardless of the
629 * speed the chip was configured for when the port was open).
630 */
631 #if 0
632 /* Power Down */
633 tmp = readb(&up->regs->rw.ccr0);
634 tmp &= ~SAB82532_CCR0_PU;
635 writeb(tmp, &up->regs->rw.ccr0);
636 #endif
637
638 spin_unlock_irqrestore(&up->port.lock, flags);
639 }
640
641 /*
642 * This is used to figure out the divisor speeds.
643 *
644 * The formula is: Baud = SAB_BASE_BAUD / ((N + 1) * (1 << M)),
645 *
646 * with 0 <= N < 64 and 0 <= M < 16
647 */
648
649 static void calc_ebrg(int baud, int *n_ret, int *m_ret)
650 {
651 int n, m;
652
653 if (baud == 0) {
654 *n_ret = 0;
655 *m_ret = 0;
656 return;
657 }
658
659 /*
660 * We scale numbers by 10 so that we get better accuracy
661 * without having to use floating point. Here we increment m
662 * until n is within the valid range.
663 */
664 n = (SAB_BASE_BAUD * 10) / baud;
665 m = 0;
666 while (n >= 640) {
667 n = n / 2;
668 m++;
669 }
670 n = (n+5) / 10;
671 /*
672 * We try very hard to avoid speeds with M == 0 since they may
673 * not work correctly for XTAL frequences above 10 MHz.
674 */
675 if ((m == 0) && ((n & 1) == 0)) {
676 n = n / 2;
677 m++;
678 }
679 *n_ret = n - 1;
680 *m_ret = m;
681 }
682
683 /* Internal routine, port->lock is held and local interrupts are disabled. */
684 static void sunsab_convert_to_sab(struct uart_sunsab_port *up, unsigned int cflag,
685 unsigned int iflag, unsigned int baud,
686 unsigned int quot)
687 {
688 unsigned int ebrg;
689 unsigned char dafo;
690 int bits, n, m;
691
692 /* Byte size and parity */
693 switch (cflag & CSIZE) {
694 case CS5: dafo = SAB82532_DAFO_CHL5; bits = 7; break;
695 case CS6: dafo = SAB82532_DAFO_CHL6; bits = 8; break;
696 case CS7: dafo = SAB82532_DAFO_CHL7; bits = 9; break;
697 case CS8: dafo = SAB82532_DAFO_CHL8; bits = 10; break;
698 /* Never happens, but GCC is too dumb to figure it out */
699 default: dafo = SAB82532_DAFO_CHL5; bits = 7; break;
700 }
701
702 if (cflag & CSTOPB) {
703 dafo |= SAB82532_DAFO_STOP;
704 bits++;
705 }
706
707 if (cflag & PARENB) {
708 dafo |= SAB82532_DAFO_PARE;
709 bits++;
710 }
711
712 if (cflag & PARODD) {
713 dafo |= SAB82532_DAFO_PAR_ODD;
714 } else {
715 dafo |= SAB82532_DAFO_PAR_EVEN;
716 }
717
718 calc_ebrg(baud, &n, &m);
719
720 ebrg = n | (m << 6);
721
722 up->tec_timeout = (10 * 1000000) / baud;
723 up->cec_timeout = up->tec_timeout >> 2;
724
725 /* CTS flow control flags */
726 /* We encode read_status_mask and ignore_status_mask like so:
727 *
728 * ---------------------
729 * | ... | ISR1 | ISR0 |
730 * ---------------------
731 * .. 15 8 7 0
732 */
733
734 up->port.read_status_mask = (SAB82532_ISR0_TCD | SAB82532_ISR0_TIME |
735 SAB82532_ISR0_RFO | SAB82532_ISR0_RPF |
736 SAB82532_ISR0_CDSC);
737 up->port.read_status_mask |= (SAB82532_ISR1_CSC |
738 SAB82532_ISR1_ALLS |
739 SAB82532_ISR1_XPR) << 8;
740 if (iflag & INPCK)
741 up->port.read_status_mask |= (SAB82532_ISR0_PERR |
742 SAB82532_ISR0_FERR);
743 if (iflag & (BRKINT | PARMRK))
744 up->port.read_status_mask |= (SAB82532_ISR1_BRK << 8);
745
746 /*
747 * Characteres to ignore
748 */
749 up->port.ignore_status_mask = 0;
750 if (iflag & IGNPAR)
751 up->port.ignore_status_mask |= (SAB82532_ISR0_PERR |
752 SAB82532_ISR0_FERR);
753 if (iflag & IGNBRK) {
754 up->port.ignore_status_mask |= (SAB82532_ISR1_BRK << 8);
755 /*
756 * If we're ignoring parity and break indicators,
757 * ignore overruns too (for real raw support).
758 */
759 if (iflag & IGNPAR)
760 up->port.ignore_status_mask |= SAB82532_ISR0_RFO;
761 }
762
763 /*
764 * ignore all characters if CREAD is not set
765 */
766 if ((cflag & CREAD) == 0)
767 up->port.ignore_status_mask |= (SAB82532_ISR0_RPF |
768 SAB82532_ISR0_TCD);
769
770 uart_update_timeout(&up->port, cflag,
771 (up->port.uartclk / (16 * quot)));
772
773 /* Now bang the new settings into the chip. */
774 sunsab_cec_wait(up);
775 sunsab_tec_wait(up);
776 writeb(dafo, &up->regs->w.dafo);
777 writeb(ebrg & 0xff, &up->regs->w.bgr);
778 writeb((readb(&up->regs->rw.ccr2) & ~0xc0) | ((ebrg >> 2) & 0xc0),
779 &up->regs->rw.ccr2);
780
781 writeb(readb(&up->regs->rw.mode) | SAB82532_MODE_RAC, &up->regs->rw.mode);
782
783 }
784
785 /* port->lock is not held. */
786 static void sunsab_set_termios(struct uart_port *port, struct termios *termios,
787 struct termios *old)
788 {
789 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
790 unsigned long flags;
791 unsigned int baud = uart_get_baud_rate(port, termios, old, 0, 4000000);
792 unsigned int quot = uart_get_divisor(port, baud);
793
794 spin_lock_irqsave(&up->port.lock, flags);
795 sunsab_convert_to_sab(up, termios->c_cflag, termios->c_iflag, baud, quot);
796 spin_unlock_irqrestore(&up->port.lock, flags);
797 }
798
799 static const char *sunsab_type(struct uart_port *port)
800 {
801 struct uart_sunsab_port *up = (void *)port;
802 static char buf[36];
803
804 sprintf(buf, "SAB82532 %s", sab82532_version[up->type]);
805 return buf;
806 }
807
808 static void sunsab_release_port(struct uart_port *port)
809 {
810 }
811
812 static int sunsab_request_port(struct uart_port *port)
813 {
814 return 0;
815 }
816
817 static void sunsab_config_port(struct uart_port *port, int flags)
818 {
819 }
820
821 static int sunsab_verify_port(struct uart_port *port, struct serial_struct *ser)
822 {
823 return -EINVAL;
824 }
825
826 static struct uart_ops sunsab_pops = {
827 .tx_empty = sunsab_tx_empty,
828 .set_mctrl = sunsab_set_mctrl,
829 .get_mctrl = sunsab_get_mctrl,
830 .stop_tx = sunsab_stop_tx,
831 .start_tx = sunsab_start_tx,
832 .send_xchar = sunsab_send_xchar,
833 .stop_rx = sunsab_stop_rx,
834 .enable_ms = sunsab_enable_ms,
835 .break_ctl = sunsab_break_ctl,
836 .startup = sunsab_startup,
837 .shutdown = sunsab_shutdown,
838 .set_termios = sunsab_set_termios,
839 .type = sunsab_type,
840 .release_port = sunsab_release_port,
841 .request_port = sunsab_request_port,
842 .config_port = sunsab_config_port,
843 .verify_port = sunsab_verify_port,
844 };
845
846 static struct uart_driver sunsab_reg = {
847 .owner = THIS_MODULE,
848 .driver_name = "serial",
849 .devfs_name = "tts/",
850 .dev_name = "ttyS",
851 .major = TTY_MAJOR,
852 };
853
854 static struct uart_sunsab_port *sunsab_ports;
855 static int num_channels;
856
857 #ifdef CONFIG_SERIAL_SUNSAB_CONSOLE
858
859 static __inline__ void sunsab_console_putchar(struct uart_sunsab_port *up, char c)
860 {
861 unsigned long flags;
862
863 spin_lock_irqsave(&up->port.lock, flags);
864
865 sunsab_tec_wait(up);
866 writeb(c, &up->regs->w.tic);
867
868 spin_unlock_irqrestore(&up->port.lock, flags);
869 }
870
871 static void sunsab_console_write(struct console *con, const char *s, unsigned n)
872 {
873 struct uart_sunsab_port *up = &sunsab_ports[con->index];
874 int i;
875
876 for (i = 0; i < n; i++) {
877 if (*s == '\n')
878 sunsab_console_putchar(up, '\r');
879 sunsab_console_putchar(up, *s++);
880 }
881 sunsab_tec_wait(up);
882 }
883
884 static int sunsab_console_setup(struct console *con, char *options)
885 {
886 struct uart_sunsab_port *up = &sunsab_ports[con->index];
887 unsigned long flags;
888 unsigned int baud, quot;
889
890 printk("Console: ttyS%d (SAB82532)\n",
891 (sunsab_reg.minor - 64) + con->index);
892
893 sunserial_console_termios(con);
894
895 /* Firmware console speed is limited to 150-->38400 baud so
896 * this hackish cflag thing is OK.
897 */
898 switch (con->cflag & CBAUD) {
899 case B150: baud = 150; break;
900 case B300: baud = 300; break;
901 case B600: baud = 600; break;
902 case B1200: baud = 1200; break;
903 case B2400: baud = 2400; break;
904 case B4800: baud = 4800; break;
905 default: case B9600: baud = 9600; break;
906 case B19200: baud = 19200; break;
907 case B38400: baud = 38400; break;
908 };
909
910 /*
911 * Temporary fix.
912 */
913 spin_lock_init(&up->port.lock);
914
915 /*
916 * Initialize the hardware
917 */
918 sunsab_startup(&up->port);
919
920 spin_lock_irqsave(&up->port.lock, flags);
921
922 /*
923 * Finally, enable interrupts
924 */
925 up->interrupt_mask0 = SAB82532_IMR0_PERR | SAB82532_IMR0_FERR |
926 SAB82532_IMR0_PLLA | SAB82532_IMR0_CDSC;
927 writeb(up->interrupt_mask0, &up->regs->w.imr0);
928 up->interrupt_mask1 = SAB82532_IMR1_BRKT | SAB82532_IMR1_ALLS |
929 SAB82532_IMR1_XOFF | SAB82532_IMR1_TIN |
930 SAB82532_IMR1_CSC | SAB82532_IMR1_XON |
931 SAB82532_IMR1_XPR;
932 writeb(up->interrupt_mask1, &up->regs->w.imr1);
933
934 quot = uart_get_divisor(&up->port, baud);
935 sunsab_convert_to_sab(up, con->cflag, 0, baud, quot);
936 sunsab_set_mctrl(&up->port, TIOCM_DTR | TIOCM_RTS);
937
938 spin_unlock_irqrestore(&up->port.lock, flags);
939
940 return 0;
941 }
942
943 static struct console sunsab_console = {
944 .name = "ttyS",
945 .write = sunsab_console_write,
946 .device = uart_console_device,
947 .setup = sunsab_console_setup,
948 .flags = CON_PRINTBUFFER,
949 .index = -1,
950 .data = &sunsab_reg,
951 };
952 #define SUNSAB_CONSOLE (&sunsab_console)
953
954 static void __init sunsab_console_init(void)
955 {
956 int i;
957
958 if (con_is_present())
959 return;
960
961 for (i = 0; i < num_channels; i++) {
962 int this_minor = sunsab_reg.minor + i;
963
964 if ((this_minor - 64) == (serial_console - 1))
965 break;
966 }
967 if (i == num_channels)
968 return;
969
970 sunsab_console.index = i;
971 register_console(&sunsab_console);
972 }
973 #else
974 #define SUNSAB_CONSOLE (NULL)
975 #define sunsab_console_init() do { } while (0)
976 #endif
977
978 static void __init for_each_sab_edev(void (*callback)(struct linux_ebus_device *, void *), void *arg)
979 {
980 struct linux_ebus *ebus;
981 struct linux_ebus_device *edev = NULL;
982
983 for_each_ebus(ebus) {
984 for_each_ebusdev(edev, ebus) {
985 if (!strcmp(edev->prom_name, "se")) {
986 callback(edev, arg);
987 continue;
988 } else if (!strcmp(edev->prom_name, "serial")) {
989 char compat[32];
990 int clen;
991
992 /* On RIO this can be an SE, check it. We could
993 * just check ebus->is_rio, but this is more portable.
994 */
995 clen = prom_getproperty(edev->prom_node, "compatible",
996 compat, sizeof(compat));
997 if (clen > 0) {
998 if (strncmp(compat, "sab82532", 8) == 0) {
999 callback(edev, arg);
1000 continue;
1001 }
1002 }
1003 }
1004 }
1005 }
1006 }
1007
1008 static void __init sab_count_callback(struct linux_ebus_device *edev, void *arg)
1009 {
1010 int *count_p = arg;
1011
1012 (*count_p)++;
1013 }
1014
1015 static void __init sab_attach_callback(struct linux_ebus_device *edev, void *arg)
1016 {
1017 int *instance_p = arg;
1018 struct uart_sunsab_port *up;
1019 unsigned long regs, offset;
1020 int i;
1021
1022 /* Note: ports are located in reverse order */
1023 regs = edev->resource[0].start;
1024 offset = sizeof(union sab82532_async_regs);
1025 for (i = 0; i < 2; i++) {
1026 up = &sunsab_ports[(*instance_p * 2) + 1 - i];
1027
1028 memset(up, 0, sizeof(*up));
1029 up->regs = ioremap(regs + offset, sizeof(union sab82532_async_regs));
1030 up->port.irq = edev->irqs[0];
1031 up->port.fifosize = SAB82532_XMIT_FIFO_SIZE;
1032 up->port.mapbase = (unsigned long)up->regs;
1033 up->port.iotype = SERIAL_IO_MEM;
1034
1035 writeb(SAB82532_IPC_IC_ACT_LOW, &up->regs->w.ipc);
1036
1037 offset -= sizeof(union sab82532_async_regs);
1038 }
1039
1040 (*instance_p)++;
1041 }
1042
1043 static int __init probe_for_sabs(void)
1044 {
1045 int this_sab = 0;
1046
1047 /* Find device instances. */
1048 for_each_sab_edev(&sab_count_callback, &this_sab);
1049 if (!this_sab)
1050 return -ENODEV;
1051
1052 /* Allocate tables. */
1053 sunsab_ports = kmalloc(sizeof(struct uart_sunsab_port) * this_sab * 2,
1054 GFP_KERNEL);
1055 if (!sunsab_ports)
1056 return -ENOMEM;
1057
1058 num_channels = this_sab * 2;
1059
1060 this_sab = 0;
1061 for_each_sab_edev(&sab_attach_callback, &this_sab);
1062 return 0;
1063 }
1064
1065 static void __init sunsab_init_hw(void)
1066 {
1067 int i;
1068
1069 for (i = 0; i < num_channels; i++) {
1070 struct uart_sunsab_port *up = &sunsab_ports[i];
1071
1072 up->port.line = i;
1073 up->port.ops = &sunsab_pops;
1074 up->port.type = PORT_SUNSAB;
1075 up->port.uartclk = SAB_BASE_BAUD;
1076
1077 up->type = readb(&up->regs->r.vstr) & 0x0f;
1078 writeb(~((1 << 1) | (1 << 2) | (1 << 4)), &up->regs->w.pcr);
1079 writeb(0xff, &up->regs->w.pim);
1080 if (up->port.line == 0) {
1081 up->pvr_dsr_bit = (1 << 0);
1082 up->pvr_dtr_bit = (1 << 1);
1083 } else {
1084 up->pvr_dsr_bit = (1 << 3);
1085 up->pvr_dtr_bit = (1 << 2);
1086 }
1087 writeb((1 << 1) | (1 << 2) | (1 << 4), &up->regs->w.pvr);
1088 writeb(readb(&up->regs->rw.mode) | SAB82532_MODE_FRTS,
1089 &up->regs->rw.mode);
1090 writeb(readb(&up->regs->rw.mode) | SAB82532_MODE_RTS,
1091 &up->regs->rw.mode);
1092
1093 up->tec_timeout = SAB82532_MAX_TEC_TIMEOUT;
1094 up->cec_timeout = SAB82532_MAX_CEC_TIMEOUT;
1095
1096 if (!(up->port.line & 0x01)) {
1097 if (request_irq(up->port.irq, sunsab_interrupt,
1098 SA_SHIRQ, "serial(sab82532)", up)) {
1099 printk("sunsab%d: can't get IRQ %x\n",
1100 i, up->port.irq);
1101 continue;
1102 }
1103 }
1104 }
1105 }
1106
1107 static int __init sunsab_init(void)
1108 {
1109 int ret = probe_for_sabs();
1110 int i;
1111
1112 if (ret < 0)
1113 return ret;
1114
1115 sunsab_init_hw();
1116
1117 sunsab_reg.minor = sunserial_current_minor;
1118 sunsab_reg.nr = num_channels;
1119 sunsab_reg.cons = SUNSAB_CONSOLE;
1120
1121 ret = uart_register_driver(&sunsab_reg);
1122 if (ret < 0) {
1123 int i;
1124
1125 for (i = 0; i < num_channels; i++) {
1126 struct uart_sunsab_port *up = &sunsab_ports[i];
1127
1128 if (!(up->port.line & 0x01))
1129 free_irq(up->port.irq, up);
1130 iounmap(up->regs);
1131 }
1132 kfree(sunsab_ports);
1133 sunsab_ports = NULL;
1134
1135 return ret;
1136 }
1137
1138 sunserial_current_minor += num_channels;
1139
1140 sunsab_console_init();
1141
1142 for (i = 0; i < num_channels; i++) {
1143 struct uart_sunsab_port *up = &sunsab_ports[i];
1144
1145 uart_add_one_port(&sunsab_reg, &up->port);
1146 }
1147
1148 return 0;
1149 }
1150
1151 static void __exit sunsab_exit(void)
1152 {
1153 int i;
1154
1155 for (i = 0; i < num_channels; i++) {
1156 struct uart_sunsab_port *up = &sunsab_ports[i];
1157
1158 uart_remove_one_port(&sunsab_reg, &up->port);
1159
1160 if (!(up->port.line & 0x01))
1161 free_irq(up->port.irq, up);
1162 iounmap(up->regs);
1163 }
1164
1165 sunserial_current_minor -= num_channels;
1166 uart_unregister_driver(&sunsab_reg);
1167
1168 kfree(sunsab_ports);
1169 sunsab_ports = NULL;
1170 }
1171
1172 module_init(sunsab_init);
1173 module_exit(sunsab_exit);
1174
1175 MODULE_AUTHOR("Eddie C. Dost and David S. Miller");
1176 MODULE_DESCRIPTION("Sun SAB82532 serial port driver");
1177 MODULE_LICENSE("GPL");
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