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[TG3]: Set minimal hw interrupt mitigation.
[linux-2.6/verdex.git] / drivers / video / aty / radeonfb.h
blob659bc9f62244aa316190dddcfa8a0aa22c78ea71
1 #ifndef __RADEONFB_H__
2 #define __RADEONFB_H__
3
4 #include <linux/config.h>
5 #include <linux/module.h>
6 #include <linux/kernel.h>
7 #include <linux/sched.h>
8 #include <linux/delay.h>
9 #include <linux/pci.h>
10 #include <linux/fb.h>
11
12
13 #include <linux/i2c.h>
14 #include <linux/i2c-id.h>
15 #include <linux/i2c-algo-bit.h>
16
17 #include <asm/io.h>
18
19 #ifdef CONFIG_PPC_OF
20 #include <asm/prom.h>
21 #endif
22
23 #include <video/radeon.h>
24
25 /***************************************************************
26 * Most of the definitions here are adapted right from XFree86 *
27 ***************************************************************/
28
29
30 /*
31 * Chip families. Must fit in the low 16 bits of a long word
32 */
33 enum radeon_family {
34 CHIP_FAMILY_UNKNOW,
35 CHIP_FAMILY_LEGACY,
36 CHIP_FAMILY_RADEON,
37 CHIP_FAMILY_RV100,
38 CHIP_FAMILY_RS100, /* U1 (IGP320M) or A3 (IGP320)*/
39 CHIP_FAMILY_RV200,
40 CHIP_FAMILY_RS200, /* U2 (IGP330M/340M/350M) or A4 (IGP330/340/345/350),
41 RS250 (IGP 7000) */
42 CHIP_FAMILY_R200,
43 CHIP_FAMILY_RV250,
44 CHIP_FAMILY_RS300, /* Radeon 9000 IGP */
45 CHIP_FAMILY_RV280,
46 CHIP_FAMILY_R300,
47 CHIP_FAMILY_R350,
48 CHIP_FAMILY_RV350,
49 CHIP_FAMILY_RV380, /* RV370/RV380/M22/M24 */
50 CHIP_FAMILY_R420, /* R420/R423/M18 */
51 CHIP_FAMILY_LAST,
52 };
53
54 #define IS_RV100_VARIANT(rinfo) (((rinfo)->family == CHIP_FAMILY_RV100) || \
55 ((rinfo)->family == CHIP_FAMILY_RV200) || \
56 ((rinfo)->family == CHIP_FAMILY_RS100) || \
57 ((rinfo)->family == CHIP_FAMILY_RS200) || \
58 ((rinfo)->family == CHIP_FAMILY_RV250) || \
59 ((rinfo)->family == CHIP_FAMILY_RV280) || \
60 ((rinfo)->family == CHIP_FAMILY_RS300))
61
62
63 #define IS_R300_VARIANT(rinfo) (((rinfo)->family == CHIP_FAMILY_R300) || \
64 ((rinfo)->family == CHIP_FAMILY_RV350) || \
65 ((rinfo)->family == CHIP_FAMILY_R350) || \
66 ((rinfo)->family == CHIP_FAMILY_RV380) || \
67 ((rinfo)->family == CHIP_FAMILY_R420))
68
69 /*
70 * Chip flags
71 */
72 enum radeon_chip_flags {
73 CHIP_FAMILY_MASK = 0x0000ffffUL,
74 CHIP_FLAGS_MASK = 0xffff0000UL,
75 CHIP_IS_MOBILITY = 0x00010000UL,
76 CHIP_IS_IGP = 0x00020000UL,
77 CHIP_HAS_CRTC2 = 0x00040000UL,
78 };
79
80 /*
81 * Errata workarounds
82 */
83 enum radeon_errata {
84 CHIP_ERRATA_R300_CG = 0x00000001,
85 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
86 CHIP_ERRATA_PLL_DELAY = 0x00000004,
87 };
88
89
90 /*
91 * Monitor types
92 */
93 enum radeon_montype {
94 MT_NONE = 0,
95 MT_CRT, /* CRT */
96 MT_LCD, /* LCD */
97 MT_DFP, /* DVI */
98 MT_CTV, /* composite TV */
99 MT_STV /* S-Video out */
100 };
101
102 /*
103 * DDC i2c ports
104 */
105 enum ddc_type {
106 ddc_none,
107 ddc_monid,
108 ddc_dvi,
109 ddc_vga,
110 ddc_crt2,
111 };
112
113 /*
114 * Connector types
115 */
116 enum conn_type {
117 conn_none,
118 conn_proprietary,
119 conn_crt,
120 conn_DVI_I,
121 conn_DVI_D,
122 };
123
124
125 /*
126 * PLL infos
127 */
128 struct pll_info {
129 int ppll_max;
130 int ppll_min;
131 int sclk, mclk;
132 int ref_div;
133 int ref_clk;
134 };
135
136
137 /*
138 * This structure contains the various registers manipulated by this
139 * driver for setting or restoring a mode. It's mostly copied from
140 * XFree's RADEONSaveRec structure. A few chip settings might still be
141 * tweaked without beeing reflected or saved in these registers though
142 */
143 struct radeon_regs {
144 /* Common registers */
145 u32 ovr_clr;
146 u32 ovr_wid_left_right;
147 u32 ovr_wid_top_bottom;
148 u32 ov0_scale_cntl;
149 u32 mpp_tb_config;
150 u32 mpp_gp_config;
151 u32 subpic_cntl;
152 u32 viph_control;
153 u32 i2c_cntl_1;
154 u32 gen_int_cntl;
155 u32 cap0_trig_cntl;
156 u32 cap1_trig_cntl;
157 u32 bus_cntl;
158 u32 surface_cntl;
159 u32 bios_5_scratch;
160
161 /* Other registers to save for VT switches or driver load/unload */
162 u32 dp_datatype;
163 u32 rbbm_soft_reset;
164 u32 clock_cntl_index;
165 u32 amcgpio_en_reg;
166 u32 amcgpio_mask;
167
168 /* Surface/tiling registers */
169 u32 surf_lower_bound[8];
170 u32 surf_upper_bound[8];
171 u32 surf_info[8];
172
173 /* CRTC registers */
174 u32 crtc_gen_cntl;
175 u32 crtc_ext_cntl;
176 u32 dac_cntl;
177 u32 crtc_h_total_disp;
178 u32 crtc_h_sync_strt_wid;
179 u32 crtc_v_total_disp;
180 u32 crtc_v_sync_strt_wid;
181 u32 crtc_offset;
182 u32 crtc_offset_cntl;
183 u32 crtc_pitch;
184 u32 disp_merge_cntl;
185 u32 grph_buffer_cntl;
186 u32 crtc_more_cntl;
187
188 /* CRTC2 registers */
189 u32 crtc2_gen_cntl;
190 u32 dac2_cntl;
191 u32 disp_output_cntl;
192 u32 disp_hw_debug;
193 u32 disp2_merge_cntl;
194 u32 grph2_buffer_cntl;
195 u32 crtc2_h_total_disp;
196 u32 crtc2_h_sync_strt_wid;
197 u32 crtc2_v_total_disp;
198 u32 crtc2_v_sync_strt_wid;
199 u32 crtc2_offset;
200 u32 crtc2_offset_cntl;
201 u32 crtc2_pitch;
202
203 /* Flat panel regs */
204 u32 fp_crtc_h_total_disp;
205 u32 fp_crtc_v_total_disp;
206 u32 fp_gen_cntl;
207 u32 fp2_gen_cntl;
208 u32 fp_h_sync_strt_wid;
209 u32 fp2_h_sync_strt_wid;
210 u32 fp_horz_stretch;
211 u32 fp_panel_cntl;
212 u32 fp_v_sync_strt_wid;
213 u32 fp2_v_sync_strt_wid;
214 u32 fp_vert_stretch;
215 u32 lvds_gen_cntl;
216 u32 lvds_pll_cntl;
217 u32 tmds_crc;
218 u32 tmds_transmitter_cntl;
219
220 /* Computed values for PLL */
221 u32 dot_clock_freq;
222 int feedback_div;
223 int post_div;
224
225 /* PLL registers */
226 u32 ppll_div_3;
227 u32 ppll_ref_div;
228 u32 vclk_ecp_cntl;
229 u32 clk_cntl_index;
230
231 /* Computed values for PLL2 */
232 u32 dot_clock_freq_2;
233 int feedback_div_2;
234 int post_div_2;
235
236 /* PLL2 registers */
237 u32 p2pll_ref_div;
238 u32 p2pll_div_0;
239 u32 htotal_cntl2;
240
241 /* Palette */
242 int palette_valid;
243 };
244
245 struct panel_info {
246 int xres, yres;
247 int valid;
248 int clock;
249 int hOver_plus, hSync_width, hblank;
250 int vOver_plus, vSync_width, vblank;
251 int hAct_high, vAct_high, interlaced;
252 int pwr_delay;
253 int use_bios_dividers;
254 int ref_divider;
255 int post_divider;
256 int fbk_divider;
257 };
258
259 struct radeonfb_info;
260
261 #ifdef CONFIG_FB_RADEON_I2C
262 struct radeon_i2c_chan {
263 struct radeonfb_info *rinfo;
264 u32 ddc_reg;
265 struct i2c_adapter adapter;
266 struct i2c_algo_bit_data algo;
267 };
268 #endif
269
270 enum radeon_pm_mode {
271 radeon_pm_none = 0, /* Nothing supported */
272 radeon_pm_d2 = 0x00000001, /* Can do D2 state */
273 radeon_pm_off = 0x00000002, /* Can resume from D3 cold */
274 };
275
276 struct radeonfb_info {
277 struct fb_info *info;
278
279 struct radeon_regs state;
280 struct radeon_regs init_state;
281
282 char name[DEVICE_NAME_SIZE];
283
284 unsigned long mmio_base_phys;
285 unsigned long fb_base_phys;
286
287 void __iomem *mmio_base;
288 void __iomem *fb_base;
289
290 unsigned long fb_local_base;
291
292 struct pci_dev *pdev;
293 #ifdef CONFIG_PPC_OF
294 struct device_node *of_node;
295 #endif
296
297 void __iomem *bios_seg;
298 int fp_bios_start;
299
300 u32 pseudo_palette[17];
301 struct { u8 red, green, blue, pad; }
302 palette[256];
303
304 int chipset;
305 u8 family;
306 u8 rev;
307 unsigned int errata;
308 unsigned long video_ram;
309 unsigned long mapped_vram;
310 int vram_width;
311 int vram_ddr;
312
313 int pitch, bpp, depth;
314
315 int has_CRTC2;
316 int is_mobility;
317 int is_IGP;
318 int reversed_DAC;
319 int reversed_TMDS;
320 struct panel_info panel_info;
321 int mon1_type;
322 u8 *mon1_EDID;
323 struct fb_videomode *mon1_modedb;
324 int mon1_dbsize;
325 int mon2_type;
326 u8 *mon2_EDID;
327
328 u32 dp_gui_master_cntl;
329
330 struct pll_info pll;
331
332 int mtrr_hdl;
333
334 int pm_reg;
335 u32 save_regs[100];
336 int asleep;
337 int lock_blank;
338 int dynclk;
339 int no_schedule;
340 enum radeon_pm_mode pm_mode;
341 void (*reinit_func)(struct radeonfb_info *rinfo);
342
343 /* Lock on register access */
344 spinlock_t reg_lock;
345
346 /* Timer used for delayed LVDS operations */
347 struct timer_list lvds_timer;
348 u32 pending_lvds_gen_cntl;
349
350 #ifdef CONFIG_FB_RADEON_I2C
351 struct radeon_i2c_chan i2c[4];
352 #endif
353
354 u32 cfg_save[64];
355 };
356
357
358 #define PRIMARY_MONITOR(rinfo) (rinfo->mon1_type)
359
360
361 /*
362 * Debugging stuffs
363 */
364 #ifdef CONFIG_FB_RADEON_DEBUG
365 #define DEBUG 1
366 #else
367 #define DEBUG 0
368 #endif
369
370 #if DEBUG
371 #define RTRACE printk
372 #else
373 #define RTRACE if(0) printk
374 #endif
375
376
377 /*
378 * IO macros
379 */
380
381 /* Note about this function: we have some rare cases where we must not schedule,
382 * this typically happen with our special "wake up early" hook which allows us to
383 * wake up the graphic chip (and thus get the console back) before everything else
384 * on some machines that support that mecanism. At this point, interrupts are off
385 * and scheduling is not permitted
386 */
387 static inline void _radeon_msleep(struct radeonfb_info *rinfo, unsigned long ms)
388 {
389 if (rinfo->no_schedule || oops_in_progress)
390 mdelay(ms);
391 else
392 msleep(ms);
393 }
394
395
396 #define INREG8(addr) readb((rinfo->mmio_base)+addr)
397 #define OUTREG8(addr,val) writeb(val, (rinfo->mmio_base)+addr)
398 #define INREG(addr) readl((rinfo->mmio_base)+addr)
399 #define OUTREG(addr,val) writel(val, (rinfo->mmio_base)+addr)
400
401 static inline void _OUTREGP(struct radeonfb_info *rinfo, u32 addr,
402 u32 val, u32 mask)
403 {
404 unsigned long flags;
405 unsigned int tmp;
406
407 spin_lock_irqsave(&rinfo->reg_lock, flags);
408 tmp = INREG(addr);
409 tmp &= (mask);
410 tmp |= (val);
411 OUTREG(addr, tmp);
412 spin_unlock_irqrestore(&rinfo->reg_lock, flags);
413 }
414
415 #define OUTREGP(addr,val,mask) _OUTREGP(rinfo, addr, val,mask)
416
417 /*
418 * Note about PLL register accesses:
419 *
420 * I have removed the spinlock on them on purpose. The driver now
421 * expects that it will only manipulate the PLL registers in normal
422 * task environment, where radeon_msleep() will be called, protected
423 * by a semaphore (currently the console semaphore) so that no conflict
424 * will happen on the PLL register index.
425 *
426 * With the latest changes to the VT layer, this is guaranteed for all
427 * calls except the actual drawing/blits which aren't supposed to use
428 * the PLL registers anyway
429 *
430 * This is very important for the workarounds to work properly. The only
431 * possible exception to this rule is the call to unblank(), which may
432 * be done at irq time if an oops is in progress.
433 */
434 static inline void radeon_pll_errata_after_index(struct radeonfb_info *rinfo)
435 {
436 if (!(rinfo->errata & CHIP_ERRATA_PLL_DUMMYREADS))
437 return;
438
439 (void)INREG(CLOCK_CNTL_DATA);
440 (void)INREG(CRTC_GEN_CNTL);
441 }
442
443 static inline void radeon_pll_errata_after_data(struct radeonfb_info *rinfo)
444 {
445 if (rinfo->errata & CHIP_ERRATA_PLL_DELAY) {
446 /* we can't deal with posted writes here ... */
447 _radeon_msleep(rinfo, 5);
448 }
449 if (rinfo->errata & CHIP_ERRATA_R300_CG) {
450 u32 save, tmp;
451 save = INREG(CLOCK_CNTL_INDEX);
452 tmp = save & ~(0x3f | PLL_WR_EN);
453 OUTREG(CLOCK_CNTL_INDEX, tmp);
454 tmp = INREG(CLOCK_CNTL_DATA);
455 OUTREG(CLOCK_CNTL_INDEX, save);
456 }
457 }
458
459 static inline u32 __INPLL(struct radeonfb_info *rinfo, u32 addr)
460 {
461 u32 data;
462
463 OUTREG8(CLOCK_CNTL_INDEX, addr & 0x0000003f);
464 radeon_pll_errata_after_index(rinfo);
465 data = INREG(CLOCK_CNTL_DATA);
466 radeon_pll_errata_after_data(rinfo);
467 return data;
468 }
469
470 static inline void __OUTPLL(struct radeonfb_info *rinfo, unsigned int index,
471 u32 val)
472 {
473
474 OUTREG8(CLOCK_CNTL_INDEX, (index & 0x0000003f) | 0x00000080);
475 radeon_pll_errata_after_index(rinfo);
476 OUTREG(CLOCK_CNTL_DATA, val);
477 radeon_pll_errata_after_data(rinfo);
478 }
479
480
481 static inline void __OUTPLLP(struct radeonfb_info *rinfo, unsigned int index,
482 u32 val, u32 mask)
483 {
484 unsigned int tmp;
485
486 tmp = __INPLL(rinfo, index);
487 tmp &= (mask);
488 tmp |= (val);
489 __OUTPLL(rinfo, index, tmp);
490 }
491
492
493 #define INPLL(addr) __INPLL(rinfo, addr)
494 #define OUTPLL(index, val) __OUTPLL(rinfo, index, val)
495 #define OUTPLLP(index, val, mask) __OUTPLLP(rinfo, index, val, mask)
496
497
498 #define BIOS_IN8(v) (readb(rinfo->bios_seg + (v)))
499 #define BIOS_IN16(v) (readb(rinfo->bios_seg + (v)) | \
500 (readb(rinfo->bios_seg + (v) + 1) << 8))
501 #define BIOS_IN32(v) (readb(rinfo->bios_seg + (v)) | \
502 (readb(rinfo->bios_seg + (v) + 1) << 8) | \
503 (readb(rinfo->bios_seg + (v) + 2) << 16) | \
504 (readb(rinfo->bios_seg + (v) + 3) << 24))
505
506 /*
507 * Inline utilities
508 */
509 static inline int round_div(int num, int den)
510 {
511 return (num + (den / 2)) / den;
512 }
513
514 static inline int var_to_depth(const struct fb_var_screeninfo *var)
515 {
516 if (var->bits_per_pixel != 16)
517 return var->bits_per_pixel;
518 return (var->green.length == 5) ? 15 : 16;
519 }
520
521 static inline u32 radeon_get_dstbpp(u16 depth)
522 {
523 switch (depth) {
524 case 8:
525 return DST_8BPP;
526 case 15:
527 return DST_15BPP;
528 case 16:
529 return DST_16BPP;
530 case 32:
531 return DST_32BPP;
532 default:
533 return 0;
534 }
535 }
536
537 /*
538 * 2D Engine helper routines
539 */
540 static inline void radeon_engine_flush (struct radeonfb_info *rinfo)
541 {
542 int i;
543
544 /* initiate flush */
545 OUTREGP(RB2D_DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL,
546 ~RB2D_DC_FLUSH_ALL);
547
548 for (i=0; i < 2000000; i++) {
549 if (!(INREG(RB2D_DSTCACHE_CTLSTAT) & RB2D_DC_BUSY))
550 return;
551 udelay(1);
552 }
553 printk(KERN_ERR "radeonfb: Flush Timeout !\n");
554 }
555
556
557 static inline void _radeon_fifo_wait(struct radeonfb_info *rinfo, int entries)
558 {
559 int i;
560
561 for (i=0; i<2000000; i++) {
562 if ((INREG(RBBM_STATUS) & 0x7f) >= entries)
563 return;
564 udelay(1);
565 }
566 printk(KERN_ERR "radeonfb: FIFO Timeout !\n");
567 }
568
569
570 static inline void _radeon_engine_idle(struct radeonfb_info *rinfo)
571 {
572 int i;
573
574 /* ensure FIFO is empty before waiting for idle */
575 _radeon_fifo_wait (rinfo, 64);
576
577 for (i=0; i<2000000; i++) {
578 if (((INREG(RBBM_STATUS) & GUI_ACTIVE)) == 0) {
579 radeon_engine_flush (rinfo);
580 return;
581 }
582 udelay(1);
583 }
584 printk(KERN_ERR "radeonfb: Idle Timeout !\n");
585 }
586
587
588 #define radeon_engine_idle() _radeon_engine_idle(rinfo)
589 #define radeon_fifo_wait(entries) _radeon_fifo_wait(rinfo,entries)
590 #define radeon_msleep(ms) _radeon_msleep(rinfo,ms)
591
592
593 /* I2C Functions */
594 extern void radeon_create_i2c_busses(struct radeonfb_info *rinfo);
595 extern void radeon_delete_i2c_busses(struct radeonfb_info *rinfo);
596 extern int radeon_probe_i2c_connector(struct radeonfb_info *rinfo, int conn, u8 **out_edid);
597
598 /* PM Functions */
599 extern int radeonfb_pci_suspend(struct pci_dev *pdev, pm_message_t state);
600 extern int radeonfb_pci_resume(struct pci_dev *pdev);
601 extern void radeonfb_pm_init(struct radeonfb_info *rinfo, int dynclk);
602 extern void radeonfb_pm_exit(struct radeonfb_info *rinfo);
603
604 /* Monitor probe functions */
605 extern void radeon_probe_screens(struct radeonfb_info *rinfo,
606 const char *monitor_layout, int ignore_edid);
607 extern void radeon_check_modes(struct radeonfb_info *rinfo, const char *mode_option);
608 extern int radeon_match_mode(struct radeonfb_info *rinfo,
609 struct fb_var_screeninfo *dest,
610 const struct fb_var_screeninfo *src);
611
612 /* Accel functions */
613 extern void radeonfb_fillrect(struct fb_info *info, const struct fb_fillrect *region);
614 extern void radeonfb_copyarea(struct fb_info *info, const struct fb_copyarea *area);
615 extern void radeonfb_imageblit(struct fb_info *p, const struct fb_image *image);
616 extern int radeonfb_sync(struct fb_info *info);
617 extern void radeonfb_engine_init (struct radeonfb_info *rinfo);
618 extern void radeonfb_engine_reset(struct radeonfb_info *rinfo);
619
620 /* Other functions */
621 extern int radeon_screen_blank(struct radeonfb_info *rinfo, int blank, int mode_switch);
622 extern void radeon_write_mode (struct radeonfb_info *rinfo, struct radeon_regs *mode,
623 int reg_only);
624
625 #endif /* __RADEONFB_H__ */
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