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[TG3]: Set minimal hw interrupt mitigation.
[linux-2.6/verdex.git] / drivers / video / matrox / matroxfb_g450.c
blob35008af7db75771d007d64715238eba18219f1d4
1 /*
2 *
3 * Hardware accelerated Matrox Millennium I, II, Mystique, G100, G200, G400 and G450.
4 *
5 * (c) 1998-2002 Petr Vandrovec <vandrove@vc.cvut.cz>
6 *
7 * Portions Copyright (c) 2001 Matrox Graphics Inc.
8 *
9 * Version: 1.65 2002/08/14
10 *
11 * See matroxfb_base.c for contributors.
12 *
13 */
14
15 #include "matroxfb_base.h"
16 #include "matroxfb_misc.h"
17 #include "matroxfb_DAC1064.h"
18 #include "g450_pll.h"
19 #include <linux/matroxfb.h>
20 #include <asm/uaccess.h>
21 #include <asm/div64.h>
22
23 /* Definition of the various controls */
24 struct mctl {
25 struct v4l2_queryctrl desc;
26 size_t control;
27 };
28
29 #define BLMIN 0xF3
30 #define WLMAX 0x3FF
31
32 static const struct mctl g450_controls[] =
33 { { { V4L2_CID_BRIGHTNESS, V4L2_CTRL_TYPE_INTEGER,
34 "brightness",
35 0, WLMAX-BLMIN, 1, 370-BLMIN,
36 0,
37 }, offsetof(struct matrox_fb_info, altout.tvo_params.brightness) },
38 { { V4L2_CID_CONTRAST, V4L2_CTRL_TYPE_INTEGER,
39 "contrast",
40 0, 1023, 1, 127,
41 0,
42 }, offsetof(struct matrox_fb_info, altout.tvo_params.contrast) },
43 { { V4L2_CID_SATURATION, V4L2_CTRL_TYPE_INTEGER,
44 "saturation",
45 0, 255, 1, 165,
46 0,
47 }, offsetof(struct matrox_fb_info, altout.tvo_params.saturation) },
48 { { V4L2_CID_HUE, V4L2_CTRL_TYPE_INTEGER,
49 "hue",
50 0, 255, 1, 0,
51 0,
52 }, offsetof(struct matrox_fb_info, altout.tvo_params.hue) },
53 { { MATROXFB_CID_TESTOUT, V4L2_CTRL_TYPE_BOOLEAN,
54 "test output",
55 0, 1, 1, 0,
56 0,
57 }, offsetof(struct matrox_fb_info, altout.tvo_params.testout) },
58 };
59
60 #define G450CTRLS (sizeof(g450_controls)/sizeof(g450_controls[0]))
61
62 /* Return: positive number: id found
63 -EINVAL: id not found, return failure
64 -ENOENT: id not found, create fake disabled control */
65 static int get_ctrl_id(__u32 v4l2_id) {
66 int i;
67
68 for (i = 0; i < G450CTRLS; i++) {
69 if (v4l2_id < g450_controls[i].desc.id) {
70 if (g450_controls[i].desc.id == 0x08000000) {
71 return -EINVAL;
72 }
73 return -ENOENT;
74 }
75 if (v4l2_id == g450_controls[i].desc.id) {
76 return i;
77 }
78 }
79 return -EINVAL;
80 }
81
82 static inline int* get_ctrl_ptr(WPMINFO unsigned int idx) {
83 return (int*)((char*)MINFO + g450_controls[idx].control);
84 }
85
86 static void tvo_fill_defaults(WPMINFO2) {
87 unsigned int i;
88
89 for (i = 0; i < G450CTRLS; i++) {
90 *get_ctrl_ptr(PMINFO i) = g450_controls[i].desc.default_value;
91 }
92 }
93
94 static int cve2_get_reg(WPMINFO int reg) {
95 unsigned long flags;
96 int val;
97
98 matroxfb_DAC_lock_irqsave(flags);
99 matroxfb_DAC_out(PMINFO 0x87, reg);
100 val = matroxfb_DAC_in(PMINFO 0x88);
101 matroxfb_DAC_unlock_irqrestore(flags);
102 return val;
103 }
104
105 static void cve2_set_reg(WPMINFO int reg, int val) {
106 unsigned long flags;
107
108 matroxfb_DAC_lock_irqsave(flags);
109 matroxfb_DAC_out(PMINFO 0x87, reg);
110 matroxfb_DAC_out(PMINFO 0x88, val);
111 matroxfb_DAC_unlock_irqrestore(flags);
112 }
113
114 static void cve2_set_reg10(WPMINFO int reg, int val) {
115 unsigned long flags;
116
117 matroxfb_DAC_lock_irqsave(flags);
118 matroxfb_DAC_out(PMINFO 0x87, reg);
119 matroxfb_DAC_out(PMINFO 0x88, val >> 2);
120 matroxfb_DAC_out(PMINFO 0x87, reg + 1);
121 matroxfb_DAC_out(PMINFO 0x88, val & 3);
122 matroxfb_DAC_unlock_irqrestore(flags);
123 }
124
125 static void g450_compute_bwlevel(CPMINFO int *bl, int *wl) {
126 const int b = ACCESS_FBINFO(altout.tvo_params.brightness) + BLMIN;
127 const int c = ACCESS_FBINFO(altout.tvo_params.contrast);
128
129 *bl = max(b - c, BLMIN);
130 *wl = min(b + c, WLMAX);
131 }
132
133 static int g450_query_ctrl(void* md, struct v4l2_queryctrl *p) {
134 int i;
135
136 i = get_ctrl_id(p->id);
137 if (i >= 0) {
138 *p = g450_controls[i].desc;
139 return 0;
140 }
141 if (i == -ENOENT) {
142 static const struct v4l2_queryctrl disctrl =
143 { .flags = V4L2_CTRL_FLAG_DISABLED };
144
145 i = p->id;
146 *p = disctrl;
147 p->id = i;
148 sprintf(p->name, "Ctrl #%08X", i);
149 return 0;
150 }
151 return -EINVAL;
152 }
153
154 static int g450_set_ctrl(void* md, struct v4l2_control *p) {
155 int i;
156 MINFO_FROM(md);
157
158 i = get_ctrl_id(p->id);
159 if (i < 0) return -EINVAL;
160
161 /*
162 * Check if changed.
163 */
164 if (p->value == *get_ctrl_ptr(PMINFO i)) return 0;
165
166 /*
167 * Check limits.
168 */
169 if (p->value > g450_controls[i].desc.maximum) return -EINVAL;
170 if (p->value < g450_controls[i].desc.minimum) return -EINVAL;
171
172 /*
173 * Store new value.
174 */
175 *get_ctrl_ptr(PMINFO i) = p->value;
176
177 switch (p->id) {
178 case V4L2_CID_BRIGHTNESS:
179 case V4L2_CID_CONTRAST:
180 {
181 int blacklevel, whitelevel;
182 g450_compute_bwlevel(PMINFO &blacklevel, &whitelevel);
183 cve2_set_reg10(PMINFO 0x0e, blacklevel);
184 cve2_set_reg10(PMINFO 0x1e, whitelevel);
185 }
186 break;
187 case V4L2_CID_SATURATION:
188 cve2_set_reg(PMINFO 0x20, p->value);
189 cve2_set_reg(PMINFO 0x22, p->value);
190 break;
191 case V4L2_CID_HUE:
192 cve2_set_reg(PMINFO 0x25, p->value);
193 break;
194 case MATROXFB_CID_TESTOUT:
195 {
196 unsigned char val = cve2_get_reg (PMINFO 0x05);
197 if (p->value) val |= 0x02;
198 else val &= ~0x02;
199 cve2_set_reg(PMINFO 0x05, val);
200 }
201 break;
202 }
203
204
205 return 0;
206 }
207
208 static int g450_get_ctrl(void* md, struct v4l2_control *p) {
209 int i;
210 MINFO_FROM(md);
211
212 i = get_ctrl_id(p->id);
213 if (i < 0) return -EINVAL;
214 p->value = *get_ctrl_ptr(PMINFO i);
215 return 0;
216 }
217
218 struct output_desc {
219 unsigned int h_vis;
220 unsigned int h_f_porch;
221 unsigned int h_sync;
222 unsigned int h_b_porch;
223 unsigned long long int chromasc;
224 unsigned int burst;
225 unsigned int v_total;
226 };
227
228 static void computeRegs(WPMINFO struct mavenregs* r, struct my_timming* mt, const struct output_desc* outd) {
229 u_int32_t chromasc;
230 u_int32_t hlen;
231 u_int32_t hsl;
232 u_int32_t hbp;
233 u_int32_t hfp;
234 u_int32_t hvis;
235 unsigned int pixclock;
236 unsigned long long piic;
237 int mnp;
238 int over;
239
240 r->regs[0x80] = 0x03; /* | 0x40 for SCART */
241
242 hvis = ((mt->HDisplay << 1) + 3) & ~3;
243
244 if (hvis >= 2048) {
245 hvis = 2044;
246 }
247
248 piic = 1000000000ULL * hvis;
249 do_div(piic, outd->h_vis);
250
251 dprintk(KERN_DEBUG "Want %u kHz pixclock\n", (unsigned int)piic);
252
253 mnp = matroxfb_g450_setclk(PMINFO piic, M_VIDEO_PLL);
254
255 mt->mnp = mnp;
256 mt->pixclock = g450_mnp2f(PMINFO mnp);
257
258 dprintk(KERN_DEBUG "MNP=%08X\n", mnp);
259
260 pixclock = 1000000000U / mt->pixclock;
261
262 dprintk(KERN_DEBUG "Got %u ps pixclock\n", pixclock);
263
264 piic = outd->chromasc;
265 do_div(piic, mt->pixclock);
266 chromasc = piic;
267
268 dprintk(KERN_DEBUG "Chroma is %08X\n", chromasc);
269
270 r->regs[0] = piic >> 24;
271 r->regs[1] = piic >> 16;
272 r->regs[2] = piic >> 8;
273 r->regs[3] = piic >> 0;
274 hbp = (((outd->h_b_porch + pixclock) / pixclock)) & ~1;
275 hfp = (((outd->h_f_porch + pixclock) / pixclock)) & ~1;
276 hsl = (((outd->h_sync + pixclock) / pixclock)) & ~1;
277 hlen = hvis + hfp + hsl + hbp;
278 over = hlen & 0x0F;
279
280 dprintk(KERN_DEBUG "WL: vis=%u, hf=%u, hs=%u, hb=%u, total=%u\n", hvis, hfp, hsl, hbp, hlen);
281
282 if (over) {
283 hfp -= over;
284 hlen -= over;
285 if (over <= 2) {
286 } else if (over < 10) {
287 hfp += 4;
288 hlen += 4;
289 } else {
290 hfp += 16;
291 hlen += 16;
292 }
293 }
294
295 /* maybe cve2 has requirement 800 < hlen < 1184 */
296 r->regs[0x08] = hsl;
297 r->regs[0x09] = (outd->burst + pixclock - 1) / pixclock; /* burst length */
298 r->regs[0x0A] = hbp;
299 r->regs[0x2C] = hfp;
300 r->regs[0x31] = hvis / 8;
301 r->regs[0x32] = hvis & 7;
302
303 dprintk(KERN_DEBUG "PG: vis=%04X, hf=%02X, hs=%02X, hb=%02X, total=%04X\n", hvis, hfp, hsl, hbp, hlen);
304
305 r->regs[0x84] = 1; /* x sync point */
306 r->regs[0x85] = 0;
307 hvis = hvis >> 1;
308 hlen = hlen >> 1;
309
310 dprintk(KERN_DEBUG "hlen=%u hvis=%u\n", hlen, hvis);
311
312 mt->interlaced = 1;
313
314 mt->HDisplay = hvis & ~7;
315 mt->HSyncStart = mt->HDisplay + 8;
316 mt->HSyncEnd = (hlen & ~7) - 8;
317 mt->HTotal = hlen;
318
319 {
320 int upper;
321 unsigned int vtotal;
322 unsigned int vsyncend;
323 unsigned int vdisplay;
324
325 vtotal = mt->VTotal;
326 vsyncend = mt->VSyncEnd;
327 vdisplay = mt->VDisplay;
328 if (vtotal < outd->v_total) {
329 unsigned int yovr = outd->v_total - vtotal;
330
331 vsyncend += yovr >> 1;
332 } else if (vtotal > outd->v_total) {
333 vdisplay = outd->v_total - 4;
334 vsyncend = outd->v_total;
335 }
336 upper = (outd->v_total - vsyncend) >> 1; /* in field lines */
337 r->regs[0x17] = outd->v_total / 4;
338 r->regs[0x18] = outd->v_total & 3;
339 r->regs[0x33] = upper - 1; /* upper blanking */
340 r->regs[0x82] = upper; /* y sync point */
341 r->regs[0x83] = upper >> 8;
342
343 mt->VDisplay = vdisplay;
344 mt->VSyncStart = outd->v_total - 2;
345 mt->VSyncEnd = outd->v_total;
346 mt->VTotal = outd->v_total;
347 }
348 }
349
350 static void cve2_init_TVdata(int norm, struct mavenregs* data, const struct output_desc** outd) {
351 static const struct output_desc paloutd = {
352 .h_vis = 52148148, // ps
353 .h_f_porch = 1407407, // ps
354 .h_sync = 4666667, // ps
355 .h_b_porch = 5777778, // ps
356 .chromasc = 19042247534182ULL, // 4433618.750 Hz
357 .burst = 2518518, // ps
358 .v_total = 625,
359 };
360 static const struct output_desc ntscoutd = {
361 .h_vis = 52888889, // ps
362 .h_f_porch = 1333333, // ps
363 .h_sync = 4666667, // ps
364 .h_b_porch = 4666667, // ps
365 .chromasc = 15374030659475ULL, // 3579545.454 Hz
366 .burst = 2418418, // ps
367 .v_total = 525, // lines
368 };
369
370 static const struct mavenregs palregs = { {
371 0x2A, 0x09, 0x8A, 0xCB, /* 00: chroma subcarrier */
372 0x00,
373 0x00, /* test */
374 0xF9, /* modified by code (F9 written...) */
375 0x00, /* ? not written */
376 0x7E, /* 08 */
377 0x44, /* 09 */
378 0x9C, /* 0A */
379 0x2E, /* 0B */
380 0x21, /* 0C */
381 0x00, /* ? not written */
382 // 0x3F, 0x03, /* 0E-0F */
383 0x3C, 0x03,
384 0x3C, 0x03, /* 10-11 */
385 0x1A, /* 12 */
386 0x2A, /* 13 */
387 0x1C, 0x3D, 0x14, /* 14-16 */
388 0x9C, 0x01, /* 17-18 */
389 0x00, /* 19 */
390 0xFE, /* 1A */
391 0x7E, /* 1B */
392 0x60, /* 1C */
393 0x05, /* 1D */
394 // 0x89, 0x03, /* 1E-1F */
395 0xAD, 0x03,
396 // 0x72, /* 20 */
397 0xA5,
398 0x07, /* 21 */
399 // 0x72, /* 22 */
400 0xA5,
401 0x00, /* 23 */
402 0x00, /* 24 */
403 0x00, /* 25 */
404 0x08, /* 26 */
405 0x04, /* 27 */
406 0x00, /* 28 */
407 0x1A, /* 29 */
408 0x55, 0x01, /* 2A-2B */
409 0x26, /* 2C */
410 0x07, 0x7E, /* 2D-2E */
411 0x02, 0x54, /* 2F-30 */
412 0xB0, 0x00, /* 31-32 */
413 0x14, /* 33 */
414 0x49, /* 34 */
415 0x00, /* 35 written multiple times */
416 0x00, /* 36 not written */
417 0xA3, /* 37 */
418 0xC8, /* 38 */
419 0x22, /* 39 */
420 0x02, /* 3A */
421 0x22, /* 3B */
422 0x3F, 0x03, /* 3C-3D */
423 0x00, /* 3E written multiple times */
424 0x00, /* 3F not written */
425 } };
426 static struct mavenregs ntscregs = { {
427 0x21, 0xF0, 0x7C, 0x1F, /* 00: chroma subcarrier */
428 0x00,
429 0x00, /* test */
430 0xF9, /* modified by code (F9 written...) */
431 0x00, /* ? not written */
432 0x7E, /* 08 */
433 0x43, /* 09 */
434 0x7E, /* 0A */
435 0x3D, /* 0B */
436 0x00, /* 0C */
437 0x00, /* ? not written */
438 0x41, 0x00, /* 0E-0F */
439 0x3C, 0x00, /* 10-11 */
440 0x17, /* 12 */
441 0x21, /* 13 */
442 0x1B, 0x1B, 0x24, /* 14-16 */
443 0x83, 0x01, /* 17-18 */
444 0x00, /* 19 */
445 0x0F, /* 1A */
446 0x0F, /* 1B */
447 0x60, /* 1C */
448 0x05, /* 1D */
449 //0x89, 0x02, /* 1E-1F */
450 0xC0, 0x02, /* 1E-1F */
451 //0x5F, /* 20 */
452 0x9C, /* 20 */
453 0x04, /* 21 */
454 //0x5F, /* 22 */
455 0x9C, /* 22 */
456 0x01, /* 23 */
457 0x02, /* 24 */
458 0x00, /* 25 */
459 0x0A, /* 26 */
460 0x05, /* 27 */
461 0x00, /* 28 */
462 0x10, /* 29 */
463 0xFF, 0x03, /* 2A-2B */
464 0x24, /* 2C */
465 0x0F, 0x78, /* 2D-2E */
466 0x00, 0x00, /* 2F-30 */
467 0xB2, 0x04, /* 31-32 */
468 0x14, /* 33 */
469 0x02, /* 34 */
470 0x00, /* 35 written multiple times */
471 0x00, /* 36 not written */
472 0xA3, /* 37 */
473 0xC8, /* 38 */
474 0x15, /* 39 */
475 0x05, /* 3A */
476 0x3B, /* 3B */
477 0x3C, 0x00, /* 3C-3D */
478 0x00, /* 3E written multiple times */
479 0x00, /* never written */
480 } };
481
482 if (norm == MATROXFB_OUTPUT_MODE_PAL) {
483 *data = palregs;
484 *outd = &paloutd;
485 } else {
486 *data = ntscregs;
487 *outd = &ntscoutd;
488 }
489 return;
490 }
491
492 #define LR(x) cve2_set_reg(PMINFO (x), m->regs[(x)])
493 static void cve2_init_TV(WPMINFO const struct mavenregs* m) {
494 int i;
495
496 LR(0x80);
497 LR(0x82); LR(0x83);
498 LR(0x84); LR(0x85);
499
500 cve2_set_reg(PMINFO 0x3E, 0x01);
501
502 for (i = 0; i < 0x3E; i++) {
503 LR(i);
504 }
505 cve2_set_reg(PMINFO 0x3E, 0x00);
506 }
507
508 static int matroxfb_g450_compute(void* md, struct my_timming* mt) {
509 MINFO_FROM(md);
510
511 dprintk(KERN_DEBUG "Computing, mode=%u\n", ACCESS_FBINFO(outputs[1]).mode);
512
513 if (mt->crtc == MATROXFB_SRC_CRTC2 &&
514 ACCESS_FBINFO(outputs[1]).mode != MATROXFB_OUTPUT_MODE_MONITOR) {
515 const struct output_desc* outd;
516
517 cve2_init_TVdata(ACCESS_FBINFO(outputs[1]).mode, &ACCESS_FBINFO(hw).maven, &outd);
518 {
519 int blacklevel, whitelevel;
520 g450_compute_bwlevel(PMINFO &blacklevel, &whitelevel);
521 ACCESS_FBINFO(hw).maven.regs[0x0E] = blacklevel >> 2;
522 ACCESS_FBINFO(hw).maven.regs[0x0F] = blacklevel & 3;
523 ACCESS_FBINFO(hw).maven.regs[0x1E] = whitelevel >> 2;
524 ACCESS_FBINFO(hw).maven.regs[0x1F] = whitelevel & 3;
525
526 ACCESS_FBINFO(hw).maven.regs[0x20] =
527 ACCESS_FBINFO(hw).maven.regs[0x22] = ACCESS_FBINFO(altout.tvo_params.saturation);
528
529 ACCESS_FBINFO(hw).maven.regs[0x25] = ACCESS_FBINFO(altout.tvo_params.hue);
530
531 if (ACCESS_FBINFO(altout.tvo_params.testout)) {
532 ACCESS_FBINFO(hw).maven.regs[0x05] |= 0x02;
533 }
534 }
535 computeRegs(PMINFO &ACCESS_FBINFO(hw).maven, mt, outd);
536 } else if (mt->mnp < 0) {
537 /* We must program clocks before CRTC2, otherwise interlaced mode
538 startup may fail */
539 mt->mnp = matroxfb_g450_setclk(PMINFO mt->pixclock, (mt->crtc == MATROXFB_SRC_CRTC1) ? M_PIXEL_PLL_C : M_VIDEO_PLL);
540 mt->pixclock = g450_mnp2f(PMINFO mt->mnp);
541 }
542 dprintk(KERN_DEBUG "Pixclock = %u\n", mt->pixclock);
543 return 0;
544 }
545
546 static int matroxfb_g450_program(void* md) {
547 MINFO_FROM(md);
548
549 if (ACCESS_FBINFO(outputs[1]).mode != MATROXFB_OUTPUT_MODE_MONITOR) {
550 cve2_init_TV(PMINFO &ACCESS_FBINFO(hw).maven);
551 }
552 return 0;
553 }
554
555 static int matroxfb_g450_verify_mode(void* md, u_int32_t arg) {
556 switch (arg) {
557 case MATROXFB_OUTPUT_MODE_PAL:
558 case MATROXFB_OUTPUT_MODE_NTSC:
559 case MATROXFB_OUTPUT_MODE_MONITOR:
560 return 0;
561 }
562 return -EINVAL;
563 }
564
565 static int g450_dvi_compute(void* md, struct my_timming* mt) {
566 MINFO_FROM(md);
567
568 if (mt->mnp < 0) {
569 mt->mnp = matroxfb_g450_setclk(PMINFO mt->pixclock, (mt->crtc == MATROXFB_SRC_CRTC1) ? M_PIXEL_PLL_C : M_VIDEO_PLL);
570 mt->pixclock = g450_mnp2f(PMINFO mt->mnp);
571 }
572 return 0;
573 }
574
575 static struct matrox_altout matroxfb_g450_altout = {
576 .name = "Secondary output",
577 .compute = matroxfb_g450_compute,
578 .program = matroxfb_g450_program,
579 .verifymode = matroxfb_g450_verify_mode,
580 .getqueryctrl = g450_query_ctrl,
581 .getctrl = g450_get_ctrl,
582 .setctrl = g450_set_ctrl,
583 };
584
585 static struct matrox_altout matroxfb_g450_dvi = {
586 .name = "DVI output",
587 .compute = g450_dvi_compute,
588 };
589
590 void matroxfb_g450_connect(WPMINFO2) {
591 if (ACCESS_FBINFO(devflags.g450dac)) {
592 down_write(&ACCESS_FBINFO(altout.lock));
593 tvo_fill_defaults(PMINFO2);
594 ACCESS_FBINFO(outputs[1]).src = ACCESS_FBINFO(outputs[1]).default_src;
595 ACCESS_FBINFO(outputs[1]).data = MINFO;
596 ACCESS_FBINFO(outputs[1]).output = &matroxfb_g450_altout;
597 ACCESS_FBINFO(outputs[1]).mode = MATROXFB_OUTPUT_MODE_MONITOR;
598 ACCESS_FBINFO(outputs[2]).src = ACCESS_FBINFO(outputs[2]).default_src;
599 ACCESS_FBINFO(outputs[2]).data = MINFO;
600 ACCESS_FBINFO(outputs[2]).output = &matroxfb_g450_dvi;
601 ACCESS_FBINFO(outputs[2]).mode = MATROXFB_OUTPUT_MODE_MONITOR;
602 up_write(&ACCESS_FBINFO(altout.lock));
603 }
604 }
605
606 void matroxfb_g450_shutdown(WPMINFO2) {
607 if (ACCESS_FBINFO(devflags.g450dac)) {
608 down_write(&ACCESS_FBINFO(altout.lock));
609 ACCESS_FBINFO(outputs[1]).src = MATROXFB_SRC_NONE;
610 ACCESS_FBINFO(outputs[1]).output = NULL;
611 ACCESS_FBINFO(outputs[1]).data = NULL;
612 ACCESS_FBINFO(outputs[1]).mode = MATROXFB_OUTPUT_MODE_MONITOR;
613 ACCESS_FBINFO(outputs[2]).src = MATROXFB_SRC_NONE;
614 ACCESS_FBINFO(outputs[2]).output = NULL;
615 ACCESS_FBINFO(outputs[2]).data = NULL;
616 ACCESS_FBINFO(outputs[2]).mode = MATROXFB_OUTPUT_MODE_MONITOR;
617 up_write(&ACCESS_FBINFO(altout.lock));
618 }
619 }
620
621 EXPORT_SYMBOL(matroxfb_g450_connect);
622 EXPORT_SYMBOL(matroxfb_g450_shutdown);
623
624 MODULE_AUTHOR("(c) 2000-2002 Petr Vandrovec <vandrove@vc.cvut.cz>");
625 MODULE_DESCRIPTION("Matrox G450/G550 output driver");
626 MODULE_LICENSE("GPL");
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