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[TG3]: Set minimal hw interrupt mitigation.
[linux-2.6/verdex.git] / drivers / video / nvidia / nv_hw.c
blobb989358437b3723e4e26dddb4b597b85c411fccb
1 /***************************************************************************\
2 |* *|
3 |* Copyright 1993-2003 NVIDIA, Corporation. All rights reserved. *|
4 |* *|
5 |* NOTICE TO USER: The source code is copyrighted under U.S. and *|
6 |* international laws. Users and possessors of this source code are *|
7 |* hereby granted a nonexclusive, royalty-free copyright license to *|
8 |* use this code in individual and commercial software. *|
9 |* *|
10 |* Any use of this source code must include, in the user documenta- *|
11 |* tion and internal comments to the code, notices to the end user *|
12 |* as follows: *|
13 |* *|
14 |* Copyright 1993-2003 NVIDIA, Corporation. All rights reserved. *|
15 |* *|
16 |* NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY *|
17 |* OF THIS SOURCE CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" *|
18 |* WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORPOR- *|
19 |* ATION DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOURCE CODE, *|
20 |* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE- *|
21 |* MENT, AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL *|
22 |* NVIDIA, CORPORATION BE LIABLE FOR ANY SPECIAL, INDIRECT, INCI- *|
23 |* DENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RE- *|
24 |* SULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION *|
25 |* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF *|
26 |* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE. *|
27 |* *|
28 |* U.S. Government End Users. This source code is a "commercial *|
29 |* item," as that term is defined at 48 C.F.R. 2.101 (OCT 1995), *|
30 |* consisting of "commercial computer software" and "commercial *|
31 |* computer software documentation," as such terms are used in *|
32 |* 48 C.F.R. 12.212 (SEPT 1995) and is provided to the U.S. Govern- *|
33 |* ment only as a commercial end item. Consistent with 48 C.F.R. *|
34 |* 12.212 and 48 C.F.R. 227.7202-1 through 227.7202-4 (JUNE 1995), *|
35 |* all U.S. Government End Users acquire the source code with only *|
36 |* those rights set forth herein. *|
37 |* *|
38 \***************************************************************************/
39
40 /*
41 * GPL Licensing Note - According to Mark Vojkovich, author of the Xorg/
42 * XFree86 'nv' driver, this source code is provided under MIT-style licensing
43 * where the source code is provided "as is" without warranty of any kind.
44 * The only usage restriction is for the copyright notices to be retained
45 * whenever code is used.
46 *
47 * Antonino Daplas <adaplas@pol.net> 2005-03-11
48 */
49
50 /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/nv_hw.c,v 1.4 2003/11/03 05:11:25 tsi Exp $ */
51
52 #include <linux/pci.h>
53 #include "nv_type.h"
54 #include "nv_local.h"
55
56 void NVLockUnlock(struct nvidia_par *par, int Lock)
57 {
58 u8 cr11;
59
60 VGA_WR08(par->PCIO, 0x3D4, 0x1F);
61 VGA_WR08(par->PCIO, 0x3D5, Lock ? 0x99 : 0x57);
62
63 VGA_WR08(par->PCIO, 0x3D4, 0x11);
64 cr11 = VGA_RD08(par->PCIO, 0x3D5);
65 if (Lock)
66 cr11 |= 0x80;
67 else
68 cr11 &= ~0x80;
69 VGA_WR08(par->PCIO, 0x3D5, cr11);
70 }
71
72 int NVShowHideCursor(struct nvidia_par *par, int ShowHide)
73 {
74 int cur = par->CurrentState->cursor1;
75
76 par->CurrentState->cursor1 = (par->CurrentState->cursor1 & 0xFE) |
77 (ShowHide & 0x01);
78 VGA_WR08(par->PCIO, 0x3D4, 0x31);
79 VGA_WR08(par->PCIO, 0x3D5, par->CurrentState->cursor1);
80
81 if (par->Architecture == NV_ARCH_40)
82 NV_WR32(par->PRAMDAC, 0x0300, NV_RD32(par->PRAMDAC, 0x0300));
83
84 return (cur & 0x01);
85 }
86
87 /****************************************************************************\
88 * *
89 * The video arbitration routines calculate some "magic" numbers. Fixes *
90 * the snow seen when accessing the framebuffer without it. *
91 * It just works (I hope). *
92 * *
93 \****************************************************************************/
94
95 typedef struct {
96 int graphics_lwm;
97 int video_lwm;
98 int graphics_burst_size;
99 int video_burst_size;
100 int valid;
101 } nv4_fifo_info;
102
103 typedef struct {
104 int pclk_khz;
105 int mclk_khz;
106 int nvclk_khz;
107 char mem_page_miss;
108 char mem_latency;
109 int memory_width;
110 char enable_video;
111 char gr_during_vid;
112 char pix_bpp;
113 char mem_aligned;
114 char enable_mp;
115 } nv4_sim_state;
116
117 typedef struct {
118 int graphics_lwm;
119 int video_lwm;
120 int graphics_burst_size;
121 int video_burst_size;
122 int valid;
123 } nv10_fifo_info;
124
125 typedef struct {
126 int pclk_khz;
127 int mclk_khz;
128 int nvclk_khz;
129 char mem_page_miss;
130 char mem_latency;
131 int memory_type;
132 int memory_width;
133 char enable_video;
134 char gr_during_vid;
135 char pix_bpp;
136 char mem_aligned;
137 char enable_mp;
138 } nv10_sim_state;
139
140 static void nvGetClocks(struct nvidia_par *par, unsigned int *MClk,
141 unsigned int *NVClk)
142 {
143 unsigned int pll, N, M, MB, NB, P;
144
145 if (par->Architecture >= NV_ARCH_40) {
146 pll = NV_RD32(par->PMC, 0x4020);
147 P = (pll >> 16) & 0x03;
148 pll = NV_RD32(par->PMC, 0x4024);
149 M = pll & 0xFF;
150 N = (pll >> 8) & 0xFF;
151 MB = (pll >> 16) & 0xFF;
152 NB = (pll >> 24) & 0xFF;
153 *MClk = ((N * NB * par->CrystalFreqKHz) / (M * MB)) >> P;
154
155 pll = NV_RD32(par->PMC, 0x4000);
156 P = (pll >> 16) & 0x03;
157 pll = NV_RD32(par->PMC, 0x4004);
158 M = pll & 0xFF;
159 N = (pll >> 8) & 0xFF;
160 MB = (pll >> 16) & 0xFF;
161 NB = (pll >> 24) & 0xFF;
162
163 *NVClk = ((N * NB * par->CrystalFreqKHz) / (M * MB)) >> P;
164 } else if (par->twoStagePLL) {
165 pll = NV_RD32(par->PRAMDAC0, 0x0504);
166 M = pll & 0xFF;
167 N = (pll >> 8) & 0xFF;
168 P = (pll >> 16) & 0x0F;
169 pll = NV_RD32(par->PRAMDAC0, 0x0574);
170 if (pll & 0x80000000) {
171 MB = pll & 0xFF;
172 NB = (pll >> 8) & 0xFF;
173 } else {
174 MB = 1;
175 NB = 1;
176 }
177 *MClk = ((N * NB * par->CrystalFreqKHz) / (M * MB)) >> P;
178
179 pll = NV_RD32(par->PRAMDAC0, 0x0500);
180 M = pll & 0xFF;
181 N = (pll >> 8) & 0xFF;
182 P = (pll >> 16) & 0x0F;
183 pll = NV_RD32(par->PRAMDAC0, 0x0570);
184 if (pll & 0x80000000) {
185 MB = pll & 0xFF;
186 NB = (pll >> 8) & 0xFF;
187 } else {
188 MB = 1;
189 NB = 1;
190 }
191 *NVClk = ((N * NB * par->CrystalFreqKHz) / (M * MB)) >> P;
192 } else
193 if (((par->Chipset & 0x0ff0) == 0x0300) ||
194 ((par->Chipset & 0x0ff0) == 0x0330)) {
195 pll = NV_RD32(par->PRAMDAC0, 0x0504);
196 M = pll & 0x0F;
197 N = (pll >> 8) & 0xFF;
198 P = (pll >> 16) & 0x07;
199 if (pll & 0x00000080) {
200 MB = (pll >> 4) & 0x07;
201 NB = (pll >> 19) & 0x1f;
202 } else {
203 MB = 1;
204 NB = 1;
205 }
206 *MClk = ((N * NB * par->CrystalFreqKHz) / (M * MB)) >> P;
207
208 pll = NV_RD32(par->PRAMDAC0, 0x0500);
209 M = pll & 0x0F;
210 N = (pll >> 8) & 0xFF;
211 P = (pll >> 16) & 0x07;
212 if (pll & 0x00000080) {
213 MB = (pll >> 4) & 0x07;
214 NB = (pll >> 19) & 0x1f;
215 } else {
216 MB = 1;
217 NB = 1;
218 }
219 *NVClk = ((N * NB * par->CrystalFreqKHz) / (M * MB)) >> P;
220 } else {
221 pll = NV_RD32(par->PRAMDAC0, 0x0504);
222 M = pll & 0xFF;
223 N = (pll >> 8) & 0xFF;
224 P = (pll >> 16) & 0x0F;
225 *MClk = (N * par->CrystalFreqKHz / M) >> P;
226
227 pll = NV_RD32(par->PRAMDAC0, 0x0500);
228 M = pll & 0xFF;
229 N = (pll >> 8) & 0xFF;
230 P = (pll >> 16) & 0x0F;
231 *NVClk = (N * par->CrystalFreqKHz / M) >> P;
232 }
233 }
234
235 static void nv4CalcArbitration(nv4_fifo_info * fifo, nv4_sim_state * arb)
236 {
237 int data, pagemiss, cas, width, video_enable, bpp;
238 int nvclks, mclks, pclks, vpagemiss, crtpagemiss, vbs;
239 int found, mclk_extra, mclk_loop, cbs, m1, p1;
240 int mclk_freq, pclk_freq, nvclk_freq, mp_enable;
241 int us_m, us_n, us_p, video_drain_rate, crtc_drain_rate;
242 int vpm_us, us_video, vlwm, video_fill_us, cpm_us, us_crt, clwm;
243
244 fifo->valid = 1;
245 pclk_freq = arb->pclk_khz;
246 mclk_freq = arb->mclk_khz;
247 nvclk_freq = arb->nvclk_khz;
248 pagemiss = arb->mem_page_miss;
249 cas = arb->mem_latency;
250 width = arb->memory_width >> 6;
251 video_enable = arb->enable_video;
252 bpp = arb->pix_bpp;
253 mp_enable = arb->enable_mp;
254 clwm = 0;
255 vlwm = 0;
256 cbs = 128;
257 pclks = 2;
258 nvclks = 2;
259 nvclks += 2;
260 nvclks += 1;
261 mclks = 5;
262 mclks += 3;
263 mclks += 1;
264 mclks += cas;
265 mclks += 1;
266 mclks += 1;
267 mclks += 1;
268 mclks += 1;
269 mclk_extra = 3;
270 nvclks += 2;
271 nvclks += 1;
272 nvclks += 1;
273 nvclks += 1;
274 if (mp_enable)
275 mclks += 4;
276 nvclks += 0;
277 pclks += 0;
278 found = 0;
279 vbs = 0;
280 while (found != 1) {
281 fifo->valid = 1;
282 found = 1;
283 mclk_loop = mclks + mclk_extra;
284 us_m = mclk_loop * 1000 * 1000 / mclk_freq;
285 us_n = nvclks * 1000 * 1000 / nvclk_freq;
286 us_p = nvclks * 1000 * 1000 / pclk_freq;
287 if (video_enable) {
288 video_drain_rate = pclk_freq * 2;
289 crtc_drain_rate = pclk_freq * bpp / 8;
290 vpagemiss = 2;
291 vpagemiss += 1;
292 crtpagemiss = 2;
293 vpm_us =
294 (vpagemiss * pagemiss) * 1000 * 1000 / mclk_freq;
295 if (nvclk_freq * 2 > mclk_freq * width)
296 video_fill_us =
297 cbs * 1000 * 1000 / 16 / nvclk_freq;
298 else
299 video_fill_us =
300 cbs * 1000 * 1000 / (8 * width) /
301 mclk_freq;
302 us_video = vpm_us + us_m + us_n + us_p + video_fill_us;
303 vlwm = us_video * video_drain_rate / (1000 * 1000);
304 vlwm++;
305 vbs = 128;
306 if (vlwm > 128)
307 vbs = 64;
308 if (vlwm > (256 - 64))
309 vbs = 32;
310 if (nvclk_freq * 2 > mclk_freq * width)
311 video_fill_us =
312 vbs * 1000 * 1000 / 16 / nvclk_freq;
313 else
314 video_fill_us =
315 vbs * 1000 * 1000 / (8 * width) /
316 mclk_freq;
317 cpm_us =
318 crtpagemiss * pagemiss * 1000 * 1000 / mclk_freq;
319 us_crt =
320 us_video + video_fill_us + cpm_us + us_m + us_n +
321 us_p;
322 clwm = us_crt * crtc_drain_rate / (1000 * 1000);
323 clwm++;
324 } else {
325 crtc_drain_rate = pclk_freq * bpp / 8;
326 crtpagemiss = 2;
327 crtpagemiss += 1;
328 cpm_us =
329 crtpagemiss * pagemiss * 1000 * 1000 / mclk_freq;
330 us_crt = cpm_us + us_m + us_n + us_p;
331 clwm = us_crt * crtc_drain_rate / (1000 * 1000);
332 clwm++;
333 }
334 m1 = clwm + cbs - 512;
335 p1 = m1 * pclk_freq / mclk_freq;
336 p1 = p1 * bpp / 8;
337 if ((p1 < m1) && (m1 > 0)) {
338 fifo->valid = 0;
339 found = 0;
340 if (mclk_extra == 0)
341 found = 1;
342 mclk_extra--;
343 } else if (video_enable) {
344 if ((clwm > 511) || (vlwm > 255)) {
345 fifo->valid = 0;
346 found = 0;
347 if (mclk_extra == 0)
348 found = 1;
349 mclk_extra--;
350 }
351 } else {
352 if (clwm > 519) {
353 fifo->valid = 0;
354 found = 0;
355 if (mclk_extra == 0)
356 found = 1;
357 mclk_extra--;
358 }
359 }
360 if (clwm < 384)
361 clwm = 384;
362 if (vlwm < 128)
363 vlwm = 128;
364 data = (int)(clwm);
365 fifo->graphics_lwm = data;
366 fifo->graphics_burst_size = 128;
367 data = (int)((vlwm + 15));
368 fifo->video_lwm = data;
369 fifo->video_burst_size = vbs;
370 }
371 }
372
373 static void nv4UpdateArbitrationSettings(unsigned VClk,
374 unsigned pixelDepth,
375 unsigned *burst,
376 unsigned *lwm, struct nvidia_par *par)
377 {
378 nv4_fifo_info fifo_data;
379 nv4_sim_state sim_data;
380 unsigned int MClk, NVClk, cfg1;
381
382 nvGetClocks(par, &MClk, &NVClk);
383
384 cfg1 = NV_RD32(par->PFB, 0x00000204);
385 sim_data.pix_bpp = (char)pixelDepth;
386 sim_data.enable_video = 0;
387 sim_data.enable_mp = 0;
388 sim_data.memory_width = (NV_RD32(par->PEXTDEV, 0x0000) & 0x10) ?
389 128 : 64;
390 sim_data.mem_latency = (char)cfg1 & 0x0F;
391 sim_data.mem_aligned = 1;
392 sim_data.mem_page_miss =
393 (char)(((cfg1 >> 4) & 0x0F) + ((cfg1 >> 31) & 0x01));
394 sim_data.gr_during_vid = 0;
395 sim_data.pclk_khz = VClk;
396 sim_data.mclk_khz = MClk;
397 sim_data.nvclk_khz = NVClk;
398 nv4CalcArbitration(&fifo_data, &sim_data);
399 if (fifo_data.valid) {
400 int b = fifo_data.graphics_burst_size >> 4;
401 *burst = 0;
402 while (b >>= 1)
403 (*burst)++;
404 *lwm = fifo_data.graphics_lwm >> 3;
405 }
406 }
407
408 static void nv10CalcArbitration(nv10_fifo_info * fifo, nv10_sim_state * arb)
409 {
410 int data, pagemiss, width, video_enable, bpp;
411 int nvclks, mclks, pclks, vpagemiss, crtpagemiss;
412 int nvclk_fill;
413 int found, mclk_extra, mclk_loop, cbs, m1;
414 int mclk_freq, pclk_freq, nvclk_freq, mp_enable;
415 int us_m, us_m_min, us_n, us_p, crtc_drain_rate;
416 int vus_m;
417 int vpm_us, us_video, cpm_us, us_crt, clwm;
418 int clwm_rnd_down;
419 int m2us, us_pipe_min, p1clk, p2;
420 int min_mclk_extra;
421 int us_min_mclk_extra;
422
423 fifo->valid = 1;
424 pclk_freq = arb->pclk_khz; /* freq in KHz */
425 mclk_freq = arb->mclk_khz;
426 nvclk_freq = arb->nvclk_khz;
427 pagemiss = arb->mem_page_miss;
428 width = arb->memory_width / 64;
429 video_enable = arb->enable_video;
430 bpp = arb->pix_bpp;
431 mp_enable = arb->enable_mp;
432 clwm = 0;
433
434 cbs = 512;
435
436 pclks = 4; /* lwm detect. */
437
438 nvclks = 3; /* lwm -> sync. */
439 nvclks += 2; /* fbi bus cycles (1 req + 1 busy) */
440 /* 2 edge sync. may be very close to edge so just put one. */
441 mclks = 1;
442 mclks += 1; /* arb_hp_req */
443 mclks += 5; /* ap_hp_req tiling pipeline */
444
445 mclks += 2; /* tc_req latency fifo */
446 mclks += 2; /* fb_cas_n_ memory request to fbio block */
447 mclks += 7; /* sm_d_rdv data returned from fbio block */
448
449 /* fb.rd.d.Put_gc need to accumulate 256 bits for read */
450 if (arb->memory_type == 0)
451 if (arb->memory_width == 64) /* 64 bit bus */
452 mclks += 4;
453 else
454 mclks += 2;
455 else if (arb->memory_width == 64) /* 64 bit bus */
456 mclks += 2;
457 else
458 mclks += 1;
459
460 if ((!video_enable) && (arb->memory_width == 128)) {
461 mclk_extra = (bpp == 32) ? 31 : 42; /* Margin of error */
462 min_mclk_extra = 17;
463 } else {
464 mclk_extra = (bpp == 32) ? 8 : 4; /* Margin of error */
465 /* mclk_extra = 4; *//* Margin of error */
466 min_mclk_extra = 18;
467 }
468
469 /* 2 edge sync. may be very close to edge so just put one. */
470 nvclks += 1;
471 nvclks += 1; /* fbi_d_rdv_n */
472 nvclks += 1; /* Fbi_d_rdata */
473 nvclks += 1; /* crtfifo load */
474
475 if (mp_enable)
476 mclks += 4; /* Mp can get in with a burst of 8. */
477 /* Extra clocks determined by heuristics */
478
479 nvclks += 0;
480 pclks += 0;
481 found = 0;
482 while (found != 1) {
483 fifo->valid = 1;
484 found = 1;
485 mclk_loop = mclks + mclk_extra;
486 /* Mclk latency in us */
487 us_m = mclk_loop * 1000 * 1000 / mclk_freq;
488 /* Minimum Mclk latency in us */
489 us_m_min = mclks * 1000 * 1000 / mclk_freq;
490 us_min_mclk_extra = min_mclk_extra * 1000 * 1000 / mclk_freq;
491 /* nvclk latency in us */
492 us_n = nvclks * 1000 * 1000 / nvclk_freq;
493 /* nvclk latency in us */
494 us_p = pclks * 1000 * 1000 / pclk_freq;
495 us_pipe_min = us_m_min + us_n + us_p;
496
497 /* Mclk latency in us */
498 vus_m = mclk_loop * 1000 * 1000 / mclk_freq;
499
500 if (video_enable) {
501 crtc_drain_rate = pclk_freq * bpp / 8; /* MB/s */
502
503 vpagemiss = 1; /* self generating page miss */
504 vpagemiss += 1; /* One higher priority before */
505
506 crtpagemiss = 2; /* self generating page miss */
507 if (mp_enable)
508 crtpagemiss += 1; /* if MA0 conflict */
509
510 vpm_us =
511 (vpagemiss * pagemiss) * 1000 * 1000 / mclk_freq;
512
513 /* Video has separate read return path */
514 us_video = vpm_us + vus_m;
515
516 cpm_us =
517 crtpagemiss * pagemiss * 1000 * 1000 / mclk_freq;
518 /* Wait for video */
519 us_crt = us_video
520 + cpm_us /* CRT Page miss */
521 + us_m + us_n + us_p /* other latency */
522 ;
523
524 clwm = us_crt * crtc_drain_rate / (1000 * 1000);
525 /* fixed point <= float_point - 1. Fixes that */
526 clwm++;
527 } else {
528 /* bpp * pclk/8 */
529 crtc_drain_rate = pclk_freq * bpp / 8;
530
531 crtpagemiss = 1; /* self generating page miss */
532 crtpagemiss += 1; /* MA0 page miss */
533 if (mp_enable)
534 crtpagemiss += 1; /* if MA0 conflict */
535 cpm_us =
536 crtpagemiss * pagemiss * 1000 * 1000 / mclk_freq;
537 us_crt = cpm_us + us_m + us_n + us_p;
538 clwm = us_crt * crtc_drain_rate / (1000 * 1000);
539 /* fixed point <= float_point - 1. Fixes that */
540 clwm++;
541
542 /* Finally, a heuristic check when width == 64 bits */
543 if (width == 1) {
544 nvclk_fill = nvclk_freq * 8;
545 if (crtc_drain_rate * 100 >= nvclk_fill * 102)
546 /*Large number to fail */
547 clwm = 0xfff;
548
549 else if (crtc_drain_rate * 100 >=
550 nvclk_fill * 98) {
551 clwm = 1024;
552 cbs = 512;
553 }
554 }
555 }
556
557 /*
558 Overfill check:
559 */
560
561 clwm_rnd_down = ((int)clwm / 8) * 8;
562 if (clwm_rnd_down < clwm)
563 clwm += 8;
564
565 m1 = clwm + cbs - 1024; /* Amount of overfill */
566 m2us = us_pipe_min + us_min_mclk_extra;
567
568 /* pclk cycles to drain */
569 p1clk = m2us * pclk_freq / (1000 * 1000);
570 p2 = p1clk * bpp / 8; /* bytes drained. */
571
572 if ((p2 < m1) && (m1 > 0)) {
573 fifo->valid = 0;
574 found = 0;
575 if (min_mclk_extra == 0) {
576 if (cbs <= 32) {
577 /* Can't adjust anymore! */
578 found = 1;
579 } else {
580 /* reduce the burst size */
581 cbs = cbs / 2;
582 }
583 } else {
584 min_mclk_extra--;
585 }
586 } else {
587 if (clwm > 1023) { /* Have some margin */
588 fifo->valid = 0;
589 found = 0;
590 if (min_mclk_extra == 0)
591 /* Can't adjust anymore! */
592 found = 1;
593 else
594 min_mclk_extra--;
595 }
596 }
597
598 if (clwm < (1024 - cbs + 8))
599 clwm = 1024 - cbs + 8;
600 data = (int)(clwm);
601 /* printf("CRT LWM: %f bytes, prog: 0x%x, bs: 256\n",
602 clwm, data ); */
603 fifo->graphics_lwm = data;
604 fifo->graphics_burst_size = cbs;
605
606 fifo->video_lwm = 1024;
607 fifo->video_burst_size = 512;
608 }
609 }
610
611 static void nv10UpdateArbitrationSettings(unsigned VClk,
612 unsigned pixelDepth,
613 unsigned *burst,
614 unsigned *lwm,
615 struct nvidia_par *par)
616 {
617 nv10_fifo_info fifo_data;
618 nv10_sim_state sim_data;
619 unsigned int MClk, NVClk, cfg1;
620
621 nvGetClocks(par, &MClk, &NVClk);
622
623 cfg1 = NV_RD32(par->PFB, 0x0204);
624 sim_data.pix_bpp = (char)pixelDepth;
625 sim_data.enable_video = 1;
626 sim_data.enable_mp = 0;
627 sim_data.memory_type = (NV_RD32(par->PFB, 0x0200) & 0x01) ? 1 : 0;
628 sim_data.memory_width = (NV_RD32(par->PEXTDEV, 0x0000) & 0x10) ?
629 128 : 64;
630 sim_data.mem_latency = (char)cfg1 & 0x0F;
631 sim_data.mem_aligned = 1;
632 sim_data.mem_page_miss =
633 (char)(((cfg1 >> 4) & 0x0F) + ((cfg1 >> 31) & 0x01));
634 sim_data.gr_during_vid = 0;
635 sim_data.pclk_khz = VClk;
636 sim_data.mclk_khz = MClk;
637 sim_data.nvclk_khz = NVClk;
638 nv10CalcArbitration(&fifo_data, &sim_data);
639 if (fifo_data.valid) {
640 int b = fifo_data.graphics_burst_size >> 4;
641 *burst = 0;
642 while (b >>= 1)
643 (*burst)++;
644 *lwm = fifo_data.graphics_lwm >> 3;
645 }
646 }
647
648 static void nv30UpdateArbitrationSettings (
649 struct nvidia_par *par,
650 unsigned int *burst,
651 unsigned int *lwm
652 )
653 {
654 unsigned int MClk, NVClk;
655 unsigned int fifo_size, burst_size, graphics_lwm;
656
657 fifo_size = 2048;
658 burst_size = 512;
659 graphics_lwm = fifo_size - burst_size;
660
661 nvGetClocks(par, &MClk, &NVClk);
662
663 *burst = 0;
664 burst_size >>= 5;
665 while(burst_size >>= 1) (*burst)++;
666 *lwm = graphics_lwm >> 3;
667 }
668
669 static void nForceUpdateArbitrationSettings(unsigned VClk,
670 unsigned pixelDepth,
671 unsigned *burst,
672 unsigned *lwm,
673 struct nvidia_par *par)
674 {
675 nv10_fifo_info fifo_data;
676 nv10_sim_state sim_data;
677 unsigned int M, N, P, pll, MClk, NVClk, memctrl;
678 struct pci_dev *dev;
679
680 if ((par->Chipset & 0x0FF0) == 0x01A0) {
681 unsigned int uMClkPostDiv;
682 dev = pci_find_slot(0, 3);
683 pci_read_config_dword(dev, 0x6C, &uMClkPostDiv);
684 uMClkPostDiv = (uMClkPostDiv >> 8) & 0xf;
685
686 if (!uMClkPostDiv)
687 uMClkPostDiv = 4;
688 MClk = 400000 / uMClkPostDiv;
689 } else {
690 dev = pci_find_slot(0, 5);
691 pci_read_config_dword(dev, 0x4c, &MClk);
692 MClk /= 1000;
693 }
694
695 pll = NV_RD32(par->PRAMDAC0, 0x0500);
696 M = (pll >> 0) & 0xFF;
697 N = (pll >> 8) & 0xFF;
698 P = (pll >> 16) & 0x0F;
699 NVClk = (N * par->CrystalFreqKHz / M) >> P;
700 sim_data.pix_bpp = (char)pixelDepth;
701 sim_data.enable_video = 0;
702 sim_data.enable_mp = 0;
703 pci_find_slot(0, 1);
704 pci_read_config_dword(dev, 0x7C, &sim_data.memory_type);
705 sim_data.memory_type = (sim_data.memory_type >> 12) & 1;
706 sim_data.memory_width = 64;
707
708 dev = pci_find_slot(0, 3);
709 pci_read_config_dword(dev, 0, &memctrl);
710 memctrl >>= 16;
711
712 if ((memctrl == 0x1A9) || (memctrl == 0x1AB) || (memctrl == 0x1ED)) {
713 int dimm[3];
714
715 pci_find_slot(0, 2);
716 pci_read_config_dword(dev, 0x40, &dimm[0]);
717 dimm[0] = (dimm[0] >> 8) & 0x4f;
718 pci_read_config_dword(dev, 0x44, &dimm[1]);
719 dimm[1] = (dimm[1] >> 8) & 0x4f;
720 pci_read_config_dword(dev, 0x48, &dimm[2]);
721 dimm[2] = (dimm[2] >> 8) & 0x4f;
722
723 if ((dimm[0] + dimm[1]) != dimm[2]) {
724 printk("nvidiafb: your nForce DIMMs are not arranged "
725 "in optimal banks!\n");
726 }
727 }
728
729 sim_data.mem_latency = 3;
730 sim_data.mem_aligned = 1;
731 sim_data.mem_page_miss = 10;
732 sim_data.gr_during_vid = 0;
733 sim_data.pclk_khz = VClk;
734 sim_data.mclk_khz = MClk;
735 sim_data.nvclk_khz = NVClk;
736 nv10CalcArbitration(&fifo_data, &sim_data);
737 if (fifo_data.valid) {
738 int b = fifo_data.graphics_burst_size >> 4;
739 *burst = 0;
740 while (b >>= 1)
741 (*burst)++;
742 *lwm = fifo_data.graphics_lwm >> 3;
743 }
744 }
745
746 /****************************************************************************\
747 * *
748 * RIVA Mode State Routines *
749 * *
750 \****************************************************************************/
751
752 /*
753 * Calculate the Video Clock parameters for the PLL.
754 */
755 static void CalcVClock(int clockIn,
756 int *clockOut, u32 * pllOut, struct nvidia_par *par)
757 {
758 unsigned lowM, highM;
759 unsigned DeltaNew, DeltaOld;
760 unsigned VClk, Freq;
761 unsigned M, N, P;
762
763 DeltaOld = 0xFFFFFFFF;
764
765 VClk = (unsigned)clockIn;
766
767 if (par->CrystalFreqKHz == 13500) {
768 lowM = 7;
769 highM = 13;
770 } else {
771 lowM = 8;
772 highM = 14;
773 }
774
775 for (P = 0; P <= 4; P++) {
776 Freq = VClk << P;
777 if ((Freq >= 128000) && (Freq <= 350000)) {
778 for (M = lowM; M <= highM; M++) {
779 N = ((VClk << P) * M) / par->CrystalFreqKHz;
780 if (N <= 255) {
781 Freq =
782 ((par->CrystalFreqKHz * N) /
783 M) >> P;
784 if (Freq > VClk)
785 DeltaNew = Freq - VClk;
786 else
787 DeltaNew = VClk - Freq;
788 if (DeltaNew < DeltaOld) {
789 *pllOut =
790 (P << 16) | (N << 8) | M;
791 *clockOut = Freq;
792 DeltaOld = DeltaNew;
793 }
794 }
795 }
796 }
797 }
798 }
799
800 static void CalcVClock2Stage(int clockIn,
801 int *clockOut,
802 u32 * pllOut,
803 u32 * pllBOut, struct nvidia_par *par)
804 {
805 unsigned DeltaNew, DeltaOld;
806 unsigned VClk, Freq;
807 unsigned M, N, P;
808
809 DeltaOld = 0xFFFFFFFF;
810
811 *pllBOut = 0x80000401; /* fixed at x4 for now */
812
813 VClk = (unsigned)clockIn;
814
815 for (P = 0; P <= 6; P++) {
816 Freq = VClk << P;
817 if ((Freq >= 400000) && (Freq <= 1000000)) {
818 for (M = 1; M <= 13; M++) {
819 N = ((VClk << P) * M) /
820 (par->CrystalFreqKHz << 2);
821 if ((N >= 5) && (N <= 255)) {
822 Freq =
823 (((par->CrystalFreqKHz << 2) * N) /
824 M) >> P;
825 if (Freq > VClk)
826 DeltaNew = Freq - VClk;
827 else
828 DeltaNew = VClk - Freq;
829 if (DeltaNew < DeltaOld) {
830 *pllOut =
831 (P << 16) | (N << 8) | M;
832 *clockOut = Freq;
833 DeltaOld = DeltaNew;
834 }
835 }
836 }
837 }
838 }
839 }
840
841 /*
842 * Calculate extended mode parameters (SVGA) and save in a
843 * mode state structure.
844 */
845 void NVCalcStateExt(struct nvidia_par *par,
846 RIVA_HW_STATE * state,
847 int bpp,
848 int width,
849 int hDisplaySize, int height, int dotClock, int flags)
850 {
851 int pixelDepth, VClk;
852 /*
853 * Save mode parameters.
854 */
855 state->bpp = bpp; /* this is not bitsPerPixel, it's 8,15,16,32 */
856 state->width = width;
857 state->height = height;
858 /*
859 * Extended RIVA registers.
860 */
861 pixelDepth = (bpp + 1) / 8;
862 if (par->twoStagePLL)
863 CalcVClock2Stage(dotClock, &VClk, &state->pll, &state->pllB,
864 par);
865 else
866 CalcVClock(dotClock, &VClk, &state->pll, par);
867
868 switch (par->Architecture) {
869 case NV_ARCH_04:
870 nv4UpdateArbitrationSettings(VClk,
871 pixelDepth * 8,
872 &(state->arbitration0),
873 &(state->arbitration1), par);
874 state->cursor0 = 0x00;
875 state->cursor1 = 0xbC;
876 if (flags & FB_VMODE_DOUBLE)
877 state->cursor1 |= 2;
878 state->cursor2 = 0x00000000;
879 state->pllsel = 0x10000700;
880 state->config = 0x00001114;
881 state->general = bpp == 16 ? 0x00101100 : 0x00100100;
882 state->repaint1 = hDisplaySize < 1280 ? 0x04 : 0x00;
883 break;
884 case NV_ARCH_10:
885 case NV_ARCH_20:
886 case NV_ARCH_30:
887 default:
888 if (((par->Chipset & 0xffff) == 0x01A0) ||
889 ((par->Chipset & 0xffff) == 0x01f0)) {
890 nForceUpdateArbitrationSettings(VClk,
891 pixelDepth * 8,
892 &(state->arbitration0),
893 &(state->arbitration1),
894 par);
895 } else if (par->Architecture < NV_ARCH_30) {
896 nv10UpdateArbitrationSettings(VClk,
897 pixelDepth * 8,
898 &(state->arbitration0),
899 &(state->arbitration1),
900 par);
901 } else {
902 nv30UpdateArbitrationSettings(par,
903 &(state->arbitration0),
904 &(state->arbitration1));
905 }
906
907 state->cursor0 = 0x80 | (par->CursorStart >> 17);
908 state->cursor1 = (par->CursorStart >> 11) << 2;
909 state->cursor2 = par->CursorStart >> 24;
910 if (flags & FB_VMODE_DOUBLE)
911 state->cursor1 |= 2;
912 state->pllsel = 0x10000700;
913 state->config = NV_RD32(par->PFB, 0x00000200);
914 state->general = bpp == 16 ? 0x00101100 : 0x00100100;
915 state->repaint1 = hDisplaySize < 1280 ? 0x04 : 0x00;
916 break;
917 }
918
919 if (bpp != 8) /* DirectColor */
920 state->general |= 0x00000030;
921
922 state->repaint0 = (((width / 8) * pixelDepth) & 0x700) >> 3;
923 state->pixel = (pixelDepth > 2) ? 3 : pixelDepth;
924 }
925
926 void NVLoadStateExt(struct nvidia_par *par, RIVA_HW_STATE * state)
927 {
928 int i;
929
930 NV_WR32(par->PMC, 0x0140, 0x00000000);
931 NV_WR32(par->PMC, 0x0200, 0xFFFF00FF);
932 NV_WR32(par->PMC, 0x0200, 0xFFFFFFFF);
933
934 NV_WR32(par->PTIMER, 0x0200 * 4, 0x00000008);
935 NV_WR32(par->PTIMER, 0x0210 * 4, 0x00000003);
936 NV_WR32(par->PTIMER, 0x0140 * 4, 0x00000000);
937 NV_WR32(par->PTIMER, 0x0100 * 4, 0xFFFFFFFF);
938
939 if (par->Architecture == NV_ARCH_04) {
940 NV_WR32(par->PFB, 0x0200, state->config);
941 } else if ((par->Chipset & 0xfff0) == 0x0090) {
942 for (i = 0; i < 15; i++) {
943 NV_WR32(par->PFB, 0x0600 + (i * 0x10), 0);
944 NV_WR32(par->PFB, 0x0604 + (i * 0x10), par->FbMapSize - 1);
945 }
946 } else {
947 for (i = 0; i < 8; i++) {
948 NV_WR32(par->PFB, 0x0240 + (i * 0x10), 0);
949 NV_WR32(par->PFB, 0x0244 + (i * 0x10), par->FbMapSize - 1);
950 }
951 }
952
953 if (par->Architecture >= NV_ARCH_40) {
954 NV_WR32(par->PRAMIN, 0x0000 * 4, 0x80000010);
955 NV_WR32(par->PRAMIN, 0x0001 * 4, 0x00101202);
956 NV_WR32(par->PRAMIN, 0x0002 * 4, 0x80000011);
957 NV_WR32(par->PRAMIN, 0x0003 * 4, 0x00101204);
958 NV_WR32(par->PRAMIN, 0x0004 * 4, 0x80000012);
959 NV_WR32(par->PRAMIN, 0x0005 * 4, 0x00101206);
960 NV_WR32(par->PRAMIN, 0x0006 * 4, 0x80000013);
961 NV_WR32(par->PRAMIN, 0x0007 * 4, 0x00101208);
962 NV_WR32(par->PRAMIN, 0x0008 * 4, 0x80000014);
963 NV_WR32(par->PRAMIN, 0x0009 * 4, 0x0010120A);
964 NV_WR32(par->PRAMIN, 0x000A * 4, 0x80000015);
965 NV_WR32(par->PRAMIN, 0x000B * 4, 0x0010120C);
966 NV_WR32(par->PRAMIN, 0x000C * 4, 0x80000016);
967 NV_WR32(par->PRAMIN, 0x000D * 4, 0x0010120E);
968 NV_WR32(par->PRAMIN, 0x000E * 4, 0x80000017);
969 NV_WR32(par->PRAMIN, 0x000F * 4, 0x00101210);
970 NV_WR32(par->PRAMIN, 0x0800 * 4, 0x00003000);
971 NV_WR32(par->PRAMIN, 0x0801 * 4, par->FbMapSize - 1);
972 NV_WR32(par->PRAMIN, 0x0802 * 4, 0x00000002);
973 NV_WR32(par->PRAMIN, 0x0808 * 4, 0x02080062);
974 NV_WR32(par->PRAMIN, 0x0809 * 4, 0x00000000);
975 NV_WR32(par->PRAMIN, 0x080A * 4, 0x00001200);
976 NV_WR32(par->PRAMIN, 0x080B * 4, 0x00001200);
977 NV_WR32(par->PRAMIN, 0x080C * 4, 0x00000000);
978 NV_WR32(par->PRAMIN, 0x080D * 4, 0x00000000);
979 NV_WR32(par->PRAMIN, 0x0810 * 4, 0x02080043);
980 NV_WR32(par->PRAMIN, 0x0811 * 4, 0x00000000);
981 NV_WR32(par->PRAMIN, 0x0812 * 4, 0x00000000);
982 NV_WR32(par->PRAMIN, 0x0813 * 4, 0x00000000);
983 NV_WR32(par->PRAMIN, 0x0814 * 4, 0x00000000);
984 NV_WR32(par->PRAMIN, 0x0815 * 4, 0x00000000);
985 NV_WR32(par->PRAMIN, 0x0818 * 4, 0x02080044);
986 NV_WR32(par->PRAMIN, 0x0819 * 4, 0x02000000);
987 NV_WR32(par->PRAMIN, 0x081A * 4, 0x00000000);
988 NV_WR32(par->PRAMIN, 0x081B * 4, 0x00000000);
989 NV_WR32(par->PRAMIN, 0x081C * 4, 0x00000000);
990 NV_WR32(par->PRAMIN, 0x081D * 4, 0x00000000);
991 NV_WR32(par->PRAMIN, 0x0820 * 4, 0x02080019);
992 NV_WR32(par->PRAMIN, 0x0821 * 4, 0x00000000);
993 NV_WR32(par->PRAMIN, 0x0822 * 4, 0x00000000);
994 NV_WR32(par->PRAMIN, 0x0823 * 4, 0x00000000);
995 NV_WR32(par->PRAMIN, 0x0824 * 4, 0x00000000);
996 NV_WR32(par->PRAMIN, 0x0825 * 4, 0x00000000);
997 NV_WR32(par->PRAMIN, 0x0828 * 4, 0x020A005C);
998 NV_WR32(par->PRAMIN, 0x0829 * 4, 0x00000000);
999 NV_WR32(par->PRAMIN, 0x082A * 4, 0x00000000);
1000 NV_WR32(par->PRAMIN, 0x082B * 4, 0x00000000);
1001 NV_WR32(par->PRAMIN, 0x082C * 4, 0x00000000);
1002 NV_WR32(par->PRAMIN, 0x082D * 4, 0x00000000);
1003 NV_WR32(par->PRAMIN, 0x0830 * 4, 0x0208009F);
1004 NV_WR32(par->PRAMIN, 0x0831 * 4, 0x00000000);
1005 NV_WR32(par->PRAMIN, 0x0832 * 4, 0x00001200);
1006 NV_WR32(par->PRAMIN, 0x0833 * 4, 0x00001200);
1007 NV_WR32(par->PRAMIN, 0x0834 * 4, 0x00000000);
1008 NV_WR32(par->PRAMIN, 0x0835 * 4, 0x00000000);
1009 NV_WR32(par->PRAMIN, 0x0838 * 4, 0x0208004A);
1010 NV_WR32(par->PRAMIN, 0x0839 * 4, 0x02000000);
1011 NV_WR32(par->PRAMIN, 0x083A * 4, 0x00000000);
1012 NV_WR32(par->PRAMIN, 0x083B * 4, 0x00000000);
1013 NV_WR32(par->PRAMIN, 0x083C * 4, 0x00000000);
1014 NV_WR32(par->PRAMIN, 0x083D * 4, 0x00000000);
1015 NV_WR32(par->PRAMIN, 0x0840 * 4, 0x02080077);
1016 NV_WR32(par->PRAMIN, 0x0841 * 4, 0x00000000);
1017 NV_WR32(par->PRAMIN, 0x0842 * 4, 0x00001200);
1018 NV_WR32(par->PRAMIN, 0x0843 * 4, 0x00001200);
1019 NV_WR32(par->PRAMIN, 0x0844 * 4, 0x00000000);
1020 NV_WR32(par->PRAMIN, 0x0845 * 4, 0x00000000);
1021 NV_WR32(par->PRAMIN, 0x084C * 4, 0x00003002);
1022 NV_WR32(par->PRAMIN, 0x084D * 4, 0x00007FFF);
1023 NV_WR32(par->PRAMIN, 0x084E * 4,
1024 par->FbUsableSize | 0x00000002);
1025
1026 #ifdef __BIG_ENDIAN
1027 NV_WR32(par->PRAMIN, 0x080A * 4,
1028 NV_RD32(par->PRAMIN, 0x080A * 4) | 0x01000000);
1029 NV_WR32(par->PRAMIN, 0x0812 * 4,
1030 NV_RD32(par->PRAMIN, 0x0812 * 4) | 0x01000000);
1031 NV_WR32(par->PRAMIN, 0x081A * 4,
1032 NV_RD32(par->PRAMIN, 0x081A * 4) | 0x01000000);
1033 NV_WR32(par->PRAMIN, 0x0822 * 4,
1034 NV_RD32(par->PRAMIN, 0x0822 * 4) | 0x01000000);
1035 NV_WR32(par->PRAMIN, 0x082A * 4,
1036 NV_RD32(par->PRAMIN, 0x082A * 4) | 0x01000000);
1037 NV_WR32(par->PRAMIN, 0x0832 * 4,
1038 NV_RD32(par->PRAMIN, 0x0832 * 4) | 0x01000000);
1039 NV_WR32(par->PRAMIN, 0x083A * 4,
1040 NV_RD32(par->PRAMIN, 0x083A * 4) | 0x01000000);
1041 NV_WR32(par->PRAMIN, 0x0842 * 4,
1042 NV_RD32(par->PRAMIN, 0x0842 * 4) | 0x01000000);
1043 NV_WR32(par->PRAMIN, 0x0819 * 4, 0x01000000);
1044 NV_WR32(par->PRAMIN, 0x0839 * 4, 0x01000000);
1045 #endif
1046 } else {
1047 NV_WR32(par->PRAMIN, 0x0000 * 4, 0x80000010);
1048 NV_WR32(par->PRAMIN, 0x0001 * 4, 0x80011201);
1049 NV_WR32(par->PRAMIN, 0x0002 * 4, 0x80000011);
1050 NV_WR32(par->PRAMIN, 0x0003 * 4, 0x80011202);
1051 NV_WR32(par->PRAMIN, 0x0004 * 4, 0x80000012);
1052 NV_WR32(par->PRAMIN, 0x0005 * 4, 0x80011203);
1053 NV_WR32(par->PRAMIN, 0x0006 * 4, 0x80000013);
1054 NV_WR32(par->PRAMIN, 0x0007 * 4, 0x80011204);
1055 NV_WR32(par->PRAMIN, 0x0008 * 4, 0x80000014);
1056 NV_WR32(par->PRAMIN, 0x0009 * 4, 0x80011205);
1057 NV_WR32(par->PRAMIN, 0x000A * 4, 0x80000015);
1058 NV_WR32(par->PRAMIN, 0x000B * 4, 0x80011206);
1059 NV_WR32(par->PRAMIN, 0x000C * 4, 0x80000016);
1060 NV_WR32(par->PRAMIN, 0x000D * 4, 0x80011207);
1061 NV_WR32(par->PRAMIN, 0x000E * 4, 0x80000017);
1062 NV_WR32(par->PRAMIN, 0x000F * 4, 0x80011208);
1063 NV_WR32(par->PRAMIN, 0x0800 * 4, 0x00003000);
1064 NV_WR32(par->PRAMIN, 0x0801 * 4, par->FbMapSize - 1);
1065 NV_WR32(par->PRAMIN, 0x0802 * 4, 0x00000002);
1066 NV_WR32(par->PRAMIN, 0x0803 * 4, 0x00000002);
1067 if (par->Architecture >= NV_ARCH_10)
1068 NV_WR32(par->PRAMIN, 0x0804 * 4, 0x01008062);
1069 else
1070 NV_WR32(par->PRAMIN, 0x0804 * 4, 0x01008042);
1071 NV_WR32(par->PRAMIN, 0x0805 * 4, 0x00000000);
1072 NV_WR32(par->PRAMIN, 0x0806 * 4, 0x12001200);
1073 NV_WR32(par->PRAMIN, 0x0807 * 4, 0x00000000);
1074 NV_WR32(par->PRAMIN, 0x0808 * 4, 0x01008043);
1075 NV_WR32(par->PRAMIN, 0x0809 * 4, 0x00000000);
1076 NV_WR32(par->PRAMIN, 0x080A * 4, 0x00000000);
1077 NV_WR32(par->PRAMIN, 0x080B * 4, 0x00000000);
1078 NV_WR32(par->PRAMIN, 0x080C * 4, 0x01008044);
1079 NV_WR32(par->PRAMIN, 0x080D * 4, 0x00000002);
1080 NV_WR32(par->PRAMIN, 0x080E * 4, 0x00000000);
1081 NV_WR32(par->PRAMIN, 0x080F * 4, 0x00000000);
1082 NV_WR32(par->PRAMIN, 0x0810 * 4, 0x01008019);
1083 NV_WR32(par->PRAMIN, 0x0811 * 4, 0x00000000);
1084 NV_WR32(par->PRAMIN, 0x0812 * 4, 0x00000000);
1085 NV_WR32(par->PRAMIN, 0x0813 * 4, 0x00000000);
1086 NV_WR32(par->PRAMIN, 0x0814 * 4, 0x0100A05C);
1087 NV_WR32(par->PRAMIN, 0x0815 * 4, 0x00000000);
1088 NV_WR32(par->PRAMIN, 0x0816 * 4, 0x00000000);
1089 NV_WR32(par->PRAMIN, 0x0817 * 4, 0x00000000);
1090 if (par->WaitVSyncPossible)
1091 NV_WR32(par->PRAMIN, 0x0818 * 4, 0x0100809F);
1092 else
1093 NV_WR32(par->PRAMIN, 0x0818 * 4, 0x0100805F);
1094 NV_WR32(par->PRAMIN, 0x0819 * 4, 0x00000000);
1095 NV_WR32(par->PRAMIN, 0x081A * 4, 0x12001200);
1096 NV_WR32(par->PRAMIN, 0x081B * 4, 0x00000000);
1097 NV_WR32(par->PRAMIN, 0x081C * 4, 0x0100804A);
1098 NV_WR32(par->PRAMIN, 0x081D * 4, 0x00000002);
1099 NV_WR32(par->PRAMIN, 0x081E * 4, 0x00000000);
1100 NV_WR32(par->PRAMIN, 0x081F * 4, 0x00000000);
1101 NV_WR32(par->PRAMIN, 0x0820 * 4, 0x01018077);
1102 NV_WR32(par->PRAMIN, 0x0821 * 4, 0x00000000);
1103 NV_WR32(par->PRAMIN, 0x0822 * 4, 0x12001200);
1104 NV_WR32(par->PRAMIN, 0x0823 * 4, 0x00000000);
1105 NV_WR32(par->PRAMIN, 0x0824 * 4, 0x00003002);
1106 NV_WR32(par->PRAMIN, 0x0825 * 4, 0x00007FFF);
1107 NV_WR32(par->PRAMIN, 0x0826 * 4,
1108 par->FbUsableSize | 0x00000002);
1109 NV_WR32(par->PRAMIN, 0x0827 * 4, 0x00000002);
1110 #ifdef __BIG_ENDIAN
1111 NV_WR32(par->PRAMIN, 0x0804 * 4,
1112 NV_RD32(par->PRAMIN, 0x0804 * 4) | 0x00080000);
1113 NV_WR32(par->PRAMIN, 0x0808 * 4,
1114 NV_RD32(par->PRAMIN, 0x0808 * 4) | 0x00080000);
1115 NV_WR32(par->PRAMIN, 0x080C * 4,
1116 NV_RD32(par->PRAMIN, 0x080C * 4) | 0x00080000);
1117 NV_WR32(par->PRAMIN, 0x0810 * 4,
1118 NV_RD32(par->PRAMIN, 0x0810 * 4) | 0x00080000);
1119 NV_WR32(par->PRAMIN, 0x0814 * 4,
1120 NV_RD32(par->PRAMIN, 0x0814 * 4) | 0x00080000);
1121 NV_WR32(par->PRAMIN, 0x0818 * 4,
1122 NV_RD32(par->PRAMIN, 0x0818 * 4) | 0x00080000);
1123 NV_WR32(par->PRAMIN, 0x081C * 4,
1124 NV_RD32(par->PRAMIN, 0x081C * 4) | 0x00080000);
1125 NV_WR32(par->PRAMIN, 0x0820 * 4,
1126 NV_RD32(par->PRAMIN, 0x0820 * 4) | 0x00080000);
1127 NV_WR32(par->PRAMIN, 0x080D * 4, 0x00000001);
1128 NV_WR32(par->PRAMIN, 0x081D * 4, 0x00000001);
1129 #endif
1130 }
1131 if (par->Architecture < NV_ARCH_10) {
1132 if ((par->Chipset & 0x0fff) == 0x0020) {
1133 NV_WR32(par->PRAMIN, 0x0824 * 4,
1134 NV_RD32(par->PRAMIN, 0x0824 * 4) | 0x00020000);
1135 NV_WR32(par->PRAMIN, 0x0826 * 4,
1136 NV_RD32(par->PRAMIN,
1137 0x0826 * 4) + par->FbAddress);
1138 }
1139 NV_WR32(par->PGRAPH, 0x0080, 0x000001FF);
1140 NV_WR32(par->PGRAPH, 0x0080, 0x1230C000);
1141 NV_WR32(par->PGRAPH, 0x0084, 0x72111101);
1142 NV_WR32(par->PGRAPH, 0x0088, 0x11D5F071);
1143 NV_WR32(par->PGRAPH, 0x008C, 0x0004FF31);
1144 NV_WR32(par->PGRAPH, 0x008C, 0x4004FF31);
1145 NV_WR32(par->PGRAPH, 0x0140, 0x00000000);
1146 NV_WR32(par->PGRAPH, 0x0100, 0xFFFFFFFF);
1147 NV_WR32(par->PGRAPH, 0x0170, 0x10010100);
1148 NV_WR32(par->PGRAPH, 0x0710, 0xFFFFFFFF);
1149 NV_WR32(par->PGRAPH, 0x0720, 0x00000001);
1150 NV_WR32(par->PGRAPH, 0x0810, 0x00000000);
1151 NV_WR32(par->PGRAPH, 0x0608, 0xFFFFFFFF);
1152 } else {
1153 NV_WR32(par->PGRAPH, 0x0080, 0xFFFFFFFF);
1154 NV_WR32(par->PGRAPH, 0x0080, 0x00000000);
1155
1156 NV_WR32(par->PGRAPH, 0x0140, 0x00000000);
1157 NV_WR32(par->PGRAPH, 0x0100, 0xFFFFFFFF);
1158 NV_WR32(par->PGRAPH, 0x0144, 0x10010100);
1159 NV_WR32(par->PGRAPH, 0x0714, 0xFFFFFFFF);
1160 NV_WR32(par->PGRAPH, 0x0720, 0x00000001);
1161 NV_WR32(par->PGRAPH, 0x0710,
1162 NV_RD32(par->PGRAPH, 0x0710) & 0x0007ff00);
1163 NV_WR32(par->PGRAPH, 0x0710,
1164 NV_RD32(par->PGRAPH, 0x0710) | 0x00020100);
1165
1166 if (par->Architecture == NV_ARCH_10) {
1167 NV_WR32(par->PGRAPH, 0x0084, 0x00118700);
1168 NV_WR32(par->PGRAPH, 0x0088, 0x24E00810);
1169 NV_WR32(par->PGRAPH, 0x008C, 0x55DE0030);
1170
1171 for (i = 0; i < 32; i++)
1172 NV_WR32(&par->PGRAPH[(0x0B00 / 4) + i], 0,
1173 NV_RD32(&par->PFB[(0x0240 / 4) + i],
1174 0));
1175
1176 NV_WR32(par->PGRAPH, 0x640, 0);
1177 NV_WR32(par->PGRAPH, 0x644, 0);
1178 NV_WR32(par->PGRAPH, 0x684, par->FbMapSize - 1);
1179 NV_WR32(par->PGRAPH, 0x688, par->FbMapSize - 1);
1180
1181 NV_WR32(par->PGRAPH, 0x0810, 0x00000000);
1182 NV_WR32(par->PGRAPH, 0x0608, 0xFFFFFFFF);
1183 } else {
1184 if (par->Architecture >= NV_ARCH_40) {
1185 NV_WR32(par->PGRAPH, 0x0084, 0x401287c0);
1186 NV_WR32(par->PGRAPH, 0x008C, 0x60de8051);
1187 NV_WR32(par->PGRAPH, 0x0090, 0x00008000);
1188 NV_WR32(par->PGRAPH, 0x0610, 0x00be3c5f);
1189
1190 if ((par->Chipset & 0xfff0) == 0x0040) {
1191 NV_WR32(par->PGRAPH, 0x09b0,
1192 0x83280fff);
1193 NV_WR32(par->PGRAPH, 0x09b4,
1194 0x000000a0);
1195 } else {
1196 NV_WR32(par->PGRAPH, 0x0820,
1197 0x83280eff);
1198 NV_WR32(par->PGRAPH, 0x0824,
1199 0x000000a0);
1200 }
1201
1202 switch (par->Chipset & 0xfff0) {
1203 case 0x0040:
1204 case 0x0210:
1205 NV_WR32(par->PGRAPH, 0x09b8,
1206 0x0078e366);
1207 NV_WR32(par->PGRAPH, 0x09bc,
1208 0x0000014c);
1209 NV_WR32(par->PFB, 0x033C,
1210 NV_RD32(par->PFB, 0x33C) &
1211 0xffff7fff);
1212 break;
1213 case 0x00C0:
1214 NV_WR32(par->PGRAPH, 0x0828,
1215 0x007596ff);
1216 NV_WR32(par->PGRAPH, 0x082C,
1217 0x00000108);
1218 break;
1219 case 0x0160:
1220 case 0x01D0:
1221 NV_WR32(par->PMC, 0x1700,
1222 NV_RD32(par->PFB, 0x020C));
1223 NV_WR32(par->PMC, 0x1704, 0);
1224 NV_WR32(par->PMC, 0x1708, 0);
1225 NV_WR32(par->PMC, 0x170C,
1226 NV_RD32(par->PFB, 0x020C));
1227 NV_WR32(par->PGRAPH, 0x0860, 0);
1228 NV_WR32(par->PGRAPH, 0x0864, 0);
1229 NV_WR32(par->PRAMDAC, 0x0608,
1230 NV_RD32(par->PRAMDAC,
1231 0x0608) | 0x00100000);
1232 break;
1233 case 0x0140:
1234 NV_WR32(par->PGRAPH, 0x0828,
1235 0x0072cb77);
1236 NV_WR32(par->PGRAPH, 0x082C,
1237 0x00000108);
1238 break;
1239 case 0x0220:
1240 case 0x0230:
1241 NV_WR32(par->PGRAPH, 0x0860, 0);
1242 NV_WR32(par->PGRAPH, 0x0864, 0);
1243 NV_WR32(par->PRAMDAC, 0x0608,
1244 NV_RD32(par->PRAMDAC, 0x0608) |
1245 0x00100000);
1246 break;
1247 case 0x0090:
1248 NV_WR32(par->PRAMDAC, 0x0608,
1249 NV_RD32(par->PRAMDAC, 0x0608) |
1250 0x00100000);
1251 NV_WR32(par->PGRAPH, 0x0828,
1252 0x07830610);
1253 NV_WR32(par->PGRAPH, 0x082C,
1254 0x0000016A);
1255 break;
1256 default:
1257 break;
1258 };
1259
1260 NV_WR32(par->PGRAPH, 0x0b38, 0x2ffff800);
1261 NV_WR32(par->PGRAPH, 0x0b3c, 0x00006000);
1262 NV_WR32(par->PGRAPH, 0x032C, 0x01000000);
1263 NV_WR32(par->PGRAPH, 0x0220, 0x00001200);
1264 } else if (par->Architecture == NV_ARCH_30) {
1265 NV_WR32(par->PGRAPH, 0x0084, 0x40108700);
1266 NV_WR32(par->PGRAPH, 0x0890, 0x00140000);
1267 NV_WR32(par->PGRAPH, 0x008C, 0xf00e0431);
1268 NV_WR32(par->PGRAPH, 0x0090, 0x00008000);
1269 NV_WR32(par->PGRAPH, 0x0610, 0xf04b1f36);
1270 NV_WR32(par->PGRAPH, 0x0B80, 0x1002d888);
1271 NV_WR32(par->PGRAPH, 0x0B88, 0x62ff007f);
1272 } else {
1273 NV_WR32(par->PGRAPH, 0x0084, 0x00118700);
1274 NV_WR32(par->PGRAPH, 0x008C, 0xF20E0431);
1275 NV_WR32(par->PGRAPH, 0x0090, 0x00000000);
1276 NV_WR32(par->PGRAPH, 0x009C, 0x00000040);
1277
1278 if ((par->Chipset & 0x0ff0) >= 0x0250) {
1279 NV_WR32(par->PGRAPH, 0x0890,
1280 0x00080000);
1281 NV_WR32(par->PGRAPH, 0x0610,
1282 0x304B1FB6);
1283 NV_WR32(par->PGRAPH, 0x0B80,
1284 0x18B82880);
1285 NV_WR32(par->PGRAPH, 0x0B84,
1286 0x44000000);
1287 NV_WR32(par->PGRAPH, 0x0098,
1288 0x40000080);
1289 NV_WR32(par->PGRAPH, 0x0B88,
1290 0x000000ff);
1291 } else {
1292 NV_WR32(par->PGRAPH, 0x0880,
1293 0x00080000);
1294 NV_WR32(par->PGRAPH, 0x0094,
1295 0x00000005);
1296 NV_WR32(par->PGRAPH, 0x0B80,
1297 0x45CAA208);
1298 NV_WR32(par->PGRAPH, 0x0B84,
1299 0x24000000);
1300 NV_WR32(par->PGRAPH, 0x0098,
1301 0x00000040);
1302 NV_WR32(par->PGRAPH, 0x0750,
1303 0x00E00038);
1304 NV_WR32(par->PGRAPH, 0x0754,
1305 0x00000030);
1306 NV_WR32(par->PGRAPH, 0x0750,
1307 0x00E10038);
1308 NV_WR32(par->PGRAPH, 0x0754,
1309 0x00000030);
1310 }
1311 }
1312
1313 if ((par->Chipset & 0xfff0) == 0x0090) {
1314 for (i = 0; i < 60; i++)
1315 NV_WR32(par->PGRAPH, 0x0D00 + i,
1316 NV_RD32(par->PFB, 0x0600 + i));
1317 } else {
1318 for (i = 0; i < 32; i++)
1319 NV_WR32(par->PGRAPH, 0x0900 + i,
1320 NV_RD32(par->PFB, 0x0240 + i));
1321 }
1322
1323 if (par->Architecture >= NV_ARCH_40) {
1324 if ((par->Chipset & 0xfff0) == 0x0040) {
1325 NV_WR32(par->PGRAPH, 0x09A4,
1326 NV_RD32(par->PFB, 0x0200));
1327 NV_WR32(par->PGRAPH, 0x09A8,
1328 NV_RD32(par->PFB, 0x0204));
1329 NV_WR32(par->PGRAPH, 0x69A4,
1330 NV_RD32(par->PFB, 0x0200));
1331 NV_WR32(par->PGRAPH, 0x69A8,
1332 NV_RD32(par->PFB, 0x0204));
1333
1334 NV_WR32(par->PGRAPH, 0x0820, 0);
1335 NV_WR32(par->PGRAPH, 0x0824, 0);
1336 NV_WR32(par->PGRAPH, 0x0864,
1337 par->FbMapSize - 1);
1338 NV_WR32(par->PGRAPH, 0x0868,
1339 par->FbMapSize - 1);
1340 } else {
1341 if((par->Chipset & 0xfff0) == 0x0090) {
1342 NV_WR32(par->PGRAPH, 0x0DF0,
1343 NV_RD32(par->PFB, 0x0200));
1344 NV_WR32(par->PGRAPH, 0x0DF4,
1345 NV_RD32(par->PFB, 0x0204));
1346 } else {
1347 NV_WR32(par->PGRAPH, 0x09F0,
1348 NV_RD32(par->PFB, 0x0200));
1349 NV_WR32(par->PGRAPH, 0x09F4,
1350 NV_RD32(par->PFB, 0x0204));
1351 }
1352 NV_WR32(par->PGRAPH, 0x69F0,
1353 NV_RD32(par->PFB, 0x0200));
1354 NV_WR32(par->PGRAPH, 0x69F4,
1355 NV_RD32(par->PFB, 0x0204));
1356
1357 NV_WR32(par->PGRAPH, 0x0840, 0);
1358 NV_WR32(par->PGRAPH, 0x0844, 0);
1359 NV_WR32(par->PGRAPH, 0x08a0,
1360 par->FbMapSize - 1);
1361 NV_WR32(par->PGRAPH, 0x08a4,
1362 par->FbMapSize - 1);
1363 }
1364 } else {
1365 NV_WR32(par->PGRAPH, 0x09A4,
1366 NV_RD32(par->PFB, 0x0200));
1367 NV_WR32(par->PGRAPH, 0x09A8,
1368 NV_RD32(par->PFB, 0x0204));
1369 NV_WR32(par->PGRAPH, 0x0750, 0x00EA0000);
1370 NV_WR32(par->PGRAPH, 0x0754,
1371 NV_RD32(par->PFB, 0x0200));
1372 NV_WR32(par->PGRAPH, 0x0750, 0x00EA0004);
1373 NV_WR32(par->PGRAPH, 0x0754,
1374 NV_RD32(par->PFB, 0x0204));
1375
1376 NV_WR32(par->PGRAPH, 0x0820, 0);
1377 NV_WR32(par->PGRAPH, 0x0824, 0);
1378 NV_WR32(par->PGRAPH, 0x0864,
1379 par->FbMapSize - 1);
1380 NV_WR32(par->PGRAPH, 0x0868,
1381 par->FbMapSize - 1);
1382 }
1383 NV_WR32(par->PGRAPH, 0x0B20, 0x00000000);
1384 NV_WR32(par->PGRAPH, 0x0B04, 0xFFFFFFFF);
1385 }
1386 }
1387 NV_WR32(par->PGRAPH, 0x053C, 0);
1388 NV_WR32(par->PGRAPH, 0x0540, 0);
1389 NV_WR32(par->PGRAPH, 0x0544, 0x00007FFF);
1390 NV_WR32(par->PGRAPH, 0x0548, 0x00007FFF);
1391
1392 NV_WR32(par->PFIFO, 0x0140 * 4, 0x00000000);
1393 NV_WR32(par->PFIFO, 0x0141 * 4, 0x00000001);
1394 NV_WR32(par->PFIFO, 0x0480 * 4, 0x00000000);
1395 NV_WR32(par->PFIFO, 0x0494 * 4, 0x00000000);
1396 if (par->Architecture >= NV_ARCH_40)
1397 NV_WR32(par->PFIFO, 0x0481 * 4, 0x00010000);
1398 else
1399 NV_WR32(par->PFIFO, 0x0481 * 4, 0x00000100);
1400 NV_WR32(par->PFIFO, 0x0490 * 4, 0x00000000);
1401 NV_WR32(par->PFIFO, 0x0491 * 4, 0x00000000);
1402 if (par->Architecture >= NV_ARCH_40)
1403 NV_WR32(par->PFIFO, 0x048B * 4, 0x00001213);
1404 else
1405 NV_WR32(par->PFIFO, 0x048B * 4, 0x00001209);
1406 NV_WR32(par->PFIFO, 0x0400 * 4, 0x00000000);
1407 NV_WR32(par->PFIFO, 0x0414 * 4, 0x00000000);
1408 NV_WR32(par->PFIFO, 0x0084 * 4, 0x03000100);
1409 NV_WR32(par->PFIFO, 0x0085 * 4, 0x00000110);
1410 NV_WR32(par->PFIFO, 0x0086 * 4, 0x00000112);
1411 NV_WR32(par->PFIFO, 0x0143 * 4, 0x0000FFFF);
1412 NV_WR32(par->PFIFO, 0x0496 * 4, 0x0000FFFF);
1413 NV_WR32(par->PFIFO, 0x0050 * 4, 0x00000000);
1414 NV_WR32(par->PFIFO, 0x0040 * 4, 0xFFFFFFFF);
1415 NV_WR32(par->PFIFO, 0x0415 * 4, 0x00000001);
1416 NV_WR32(par->PFIFO, 0x048C * 4, 0x00000000);
1417 NV_WR32(par->PFIFO, 0x04A0 * 4, 0x00000000);
1418 #ifdef __BIG_ENDIAN
1419 NV_WR32(par->PFIFO, 0x0489 * 4, 0x800F0078);
1420 #else
1421 NV_WR32(par->PFIFO, 0x0489 * 4, 0x000F0078);
1422 #endif
1423 NV_WR32(par->PFIFO, 0x0488 * 4, 0x00000001);
1424 NV_WR32(par->PFIFO, 0x0480 * 4, 0x00000001);
1425 NV_WR32(par->PFIFO, 0x0494 * 4, 0x00000001);
1426 NV_WR32(par->PFIFO, 0x0495 * 4, 0x00000001);
1427 NV_WR32(par->PFIFO, 0x0140 * 4, 0x00000001);
1428 if (par->Architecture >= NV_ARCH_10) {
1429 if (par->twoHeads) {
1430 NV_WR32(par->PCRTC0, 0x0860, state->head);
1431 NV_WR32(par->PCRTC0, 0x2860, state->head2);
1432 }
1433 NV_WR32(par->PRAMDAC, 0x0404, NV_RD32(par->PRAMDAC, 0x0404) |
1434 (1 << 25));
1435
1436 NV_WR32(par->PMC, 0x8704, 1);
1437 NV_WR32(par->PMC, 0x8140, 0);
1438 NV_WR32(par->PMC, 0x8920, 0);
1439 NV_WR32(par->PMC, 0x8924, 0);
1440 NV_WR32(par->PMC, 0x8908, par->FbMapSize - 1);
1441 NV_WR32(par->PMC, 0x890C, par->FbMapSize - 1);
1442 NV_WR32(par->PMC, 0x1588, 0);
1443
1444 NV_WR32(par->PCRTC, 0x0810, state->cursorConfig);
1445 NV_WR32(par->PCRTC, 0x0830, state->displayV - 3);
1446 NV_WR32(par->PCRTC, 0x0834, state->displayV - 1);
1447
1448 if (par->FlatPanel) {
1449 if ((par->Chipset & 0x0ff0) == 0x0110) {
1450 NV_WR32(par->PRAMDAC, 0x0528, state->dither);
1451 } else if (par->twoHeads) {
1452 NV_WR32(par->PRAMDAC, 0x083C, state->dither);
1453 }
1454
1455 VGA_WR08(par->PCIO, 0x03D4, 0x53);
1456 VGA_WR08(par->PCIO, 0x03D5, state->timingH);
1457 VGA_WR08(par->PCIO, 0x03D4, 0x54);
1458 VGA_WR08(par->PCIO, 0x03D5, state->timingV);
1459 VGA_WR08(par->PCIO, 0x03D4, 0x21);
1460 VGA_WR08(par->PCIO, 0x03D5, 0xfa);
1461 }
1462
1463 VGA_WR08(par->PCIO, 0x03D4, 0x41);
1464 VGA_WR08(par->PCIO, 0x03D5, state->extra);
1465 }
1466
1467 VGA_WR08(par->PCIO, 0x03D4, 0x19);
1468 VGA_WR08(par->PCIO, 0x03D5, state->repaint0);
1469 VGA_WR08(par->PCIO, 0x03D4, 0x1A);
1470 VGA_WR08(par->PCIO, 0x03D5, state->repaint1);
1471 VGA_WR08(par->PCIO, 0x03D4, 0x25);
1472 VGA_WR08(par->PCIO, 0x03D5, state->screen);
1473 VGA_WR08(par->PCIO, 0x03D4, 0x28);
1474 VGA_WR08(par->PCIO, 0x03D5, state->pixel);
1475 VGA_WR08(par->PCIO, 0x03D4, 0x2D);
1476 VGA_WR08(par->PCIO, 0x03D5, state->horiz);
1477 VGA_WR08(par->PCIO, 0x03D4, 0x1C);
1478 VGA_WR08(par->PCIO, 0x03D5, state->fifo);
1479 VGA_WR08(par->PCIO, 0x03D4, 0x1B);
1480 VGA_WR08(par->PCIO, 0x03D5, state->arbitration0);
1481 VGA_WR08(par->PCIO, 0x03D4, 0x20);
1482 VGA_WR08(par->PCIO, 0x03D5, state->arbitration1);
1483
1484 if(par->Architecture >= NV_ARCH_30) {
1485 VGA_WR08(par->PCIO, 0x03D4, 0x47);
1486 VGA_WR08(par->PCIO, 0x03D5, state->arbitration1 >> 8);
1487 }
1488
1489 VGA_WR08(par->PCIO, 0x03D4, 0x30);
1490 VGA_WR08(par->PCIO, 0x03D5, state->cursor0);
1491 VGA_WR08(par->PCIO, 0x03D4, 0x31);
1492 VGA_WR08(par->PCIO, 0x03D5, state->cursor1);
1493 VGA_WR08(par->PCIO, 0x03D4, 0x2F);
1494 VGA_WR08(par->PCIO, 0x03D5, state->cursor2);
1495 VGA_WR08(par->PCIO, 0x03D4, 0x39);
1496 VGA_WR08(par->PCIO, 0x03D5, state->interlace);
1497
1498 if (!par->FlatPanel) {
1499 NV_WR32(par->PRAMDAC0, 0x050C, state->pllsel);
1500 NV_WR32(par->PRAMDAC0, 0x0508, state->vpll);
1501 if (par->twoHeads)
1502 NV_WR32(par->PRAMDAC0, 0x0520, state->vpll2);
1503 if (par->twoStagePLL) {
1504 NV_WR32(par->PRAMDAC0, 0x0578, state->vpllB);
1505 NV_WR32(par->PRAMDAC0, 0x057C, state->vpll2B);
1506 }
1507 } else {
1508 NV_WR32(par->PRAMDAC, 0x0848, state->scale);
1509 NV_WR32(par->PRAMDAC, 0x0828, state->crtcSync +
1510 par->PanelTweak);
1511 }
1512
1513 NV_WR32(par->PRAMDAC, 0x0600, state->general);
1514
1515 NV_WR32(par->PCRTC, 0x0140, 0);
1516 NV_WR32(par->PCRTC, 0x0100, 1);
1517
1518 par->CurrentState = state;
1519 }
1520
1521 void NVUnloadStateExt(struct nvidia_par *par, RIVA_HW_STATE * state) {
1522 VGA_WR08(par->PCIO, 0x03D4, 0x19);
1523 state->repaint0 = VGA_RD08(par->PCIO, 0x03D5);
1524 VGA_WR08(par->PCIO, 0x03D4, 0x1A);
1525 state->repaint1 = VGA_RD08(par->PCIO, 0x03D5);
1526 VGA_WR08(par->PCIO, 0x03D4, 0x25);
1527 state->screen = VGA_RD08(par->PCIO, 0x03D5);
1528 VGA_WR08(par->PCIO, 0x03D4, 0x28);
1529 state->pixel = VGA_RD08(par->PCIO, 0x03D5);
1530 VGA_WR08(par->PCIO, 0x03D4, 0x2D);
1531 state->horiz = VGA_RD08(par->PCIO, 0x03D5);
1532 VGA_WR08(par->PCIO, 0x03D4, 0x1C);
1533 state->fifo = VGA_RD08(par->PCIO, 0x03D5);
1534 VGA_WR08(par->PCIO, 0x03D4, 0x1B);
1535 state->arbitration0 = VGA_RD08(par->PCIO, 0x03D5);
1536 VGA_WR08(par->PCIO, 0x03D4, 0x20);
1537 state->arbitration1 = VGA_RD08(par->PCIO, 0x03D5);
1538
1539 if(par->Architecture >= NV_ARCH_30) {
1540 VGA_WR08(par->PCIO, 0x03D4, 0x47);
1541 state->arbitration1 |= (VGA_RD08(par->PCIO, 0x03D5) & 1) << 8;
1542 }
1543
1544 VGA_WR08(par->PCIO, 0x03D4, 0x30);
1545 state->cursor0 = VGA_RD08(par->PCIO, 0x03D5);
1546 VGA_WR08(par->PCIO, 0x03D4, 0x31);
1547 state->cursor1 = VGA_RD08(par->PCIO, 0x03D5);
1548 VGA_WR08(par->PCIO, 0x03D4, 0x2F);
1549 state->cursor2 = VGA_RD08(par->PCIO, 0x03D5);
1550 VGA_WR08(par->PCIO, 0x03D4, 0x39);
1551 state->interlace = VGA_RD08(par->PCIO, 0x03D5);
1552 state->vpll = NV_RD32(par->PRAMDAC0, 0x0508);
1553 if (par->twoHeads)
1554 state->vpll2 = NV_RD32(par->PRAMDAC0, 0x0520);
1555 if (par->twoStagePLL) {
1556 state->vpllB = NV_RD32(par->PRAMDAC0, 0x0578);
1557 state->vpll2B = NV_RD32(par->PRAMDAC0, 0x057C);
1558 }
1559 state->pllsel = NV_RD32(par->PRAMDAC0, 0x050C);
1560 state->general = NV_RD32(par->PRAMDAC, 0x0600);
1561 state->scale = NV_RD32(par->PRAMDAC, 0x0848);
1562 state->config = NV_RD32(par->PFB, 0x0200);
1563
1564 if (par->Architecture >= NV_ARCH_10) {
1565 if (par->twoHeads) {
1566 state->head = NV_RD32(par->PCRTC0, 0x0860);
1567 state->head2 = NV_RD32(par->PCRTC0, 0x2860);
1568 VGA_WR08(par->PCIO, 0x03D4, 0x44);
1569 state->crtcOwner = VGA_RD08(par->PCIO, 0x03D5);
1570 }
1571 VGA_WR08(par->PCIO, 0x03D4, 0x41);
1572 state->extra = VGA_RD08(par->PCIO, 0x03D5);
1573 state->cursorConfig = NV_RD32(par->PCRTC, 0x0810);
1574
1575 if ((par->Chipset & 0x0ff0) == 0x0110) {
1576 state->dither = NV_RD32(par->PRAMDAC, 0x0528);
1577 } else if (par->twoHeads) {
1578 state->dither = NV_RD32(par->PRAMDAC, 0x083C);
1579 }
1580
1581 if (par->FlatPanel) {
1582 VGA_WR08(par->PCIO, 0x03D4, 0x53);
1583 state->timingH = VGA_RD08(par->PCIO, 0x03D5);
1584 VGA_WR08(par->PCIO, 0x03D4, 0x54);
1585 state->timingV = VGA_RD08(par->PCIO, 0x03D5);
1586 }
1587 }
1588 }
1589
1590 void NVSetStartAddress(struct nvidia_par *par, u32 start)
1591 {
1592 NV_WR32(par->PCRTC, 0x800, start);
1593 }
Verdex Pro support