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[TG3]: Set minimal hw interrupt mitigation.
[linux-2.6/verdex.git] / drivers / video / riva / fbdev.c
blobb0c886de04043c1ad872377e3739a0f48f3d34a2
1 /*
2 * linux/drivers/video/riva/fbdev.c - nVidia RIVA 128/TNT/TNT2 fb driver
3 *
4 * Maintained by Ani Joshi <ajoshi@shell.unixbox.com>
5 *
6 * Copyright 1999-2000 Jeff Garzik
7 *
8 * Contributors:
9 *
10 * Ani Joshi: Lots of debugging and cleanup work, really helped
11 * get the driver going
12 *
13 * Ferenc Bakonyi: Bug fixes, cleanup, modularization
14 *
15 * Jindrich Makovicka: Accel code help, hw cursor, mtrr
16 *
17 * Paul Richards: Bug fixes, updates
18 *
19 * Initial template from skeletonfb.c, created 28 Dec 1997 by Geert Uytterhoeven
20 * Includes riva_hw.c from nVidia, see copyright below.
21 * KGI code provided the basis for state storage, init, and mode switching.
22 *
23 * This file is subject to the terms and conditions of the GNU General Public
24 * License. See the file COPYING in the main directory of this archive
25 * for more details.
26 *
27 * Known bugs and issues:
28 * restoring text mode fails
29 * doublescan modes are broken
30 */
31
32 #include <linux/config.h>
33 #include <linux/module.h>
34 #include <linux/kernel.h>
35 #include <linux/errno.h>
36 #include <linux/string.h>
37 #include <linux/mm.h>
38 #include <linux/tty.h>
39 #include <linux/slab.h>
40 #include <linux/delay.h>
41 #include <linux/fb.h>
42 #include <linux/init.h>
43 #include <linux/pci.h>
44 #ifdef CONFIG_MTRR
45 #include <asm/mtrr.h>
46 #endif
47 #ifdef CONFIG_PPC_OF
48 #include <asm/prom.h>
49 #include <asm/pci-bridge.h>
50 #endif
51 #ifdef CONFIG_PMAC_BACKLIGHT
52 #include <asm/backlight.h>
53 #endif
54
55 #include "rivafb.h"
56 #include "nvreg.h"
57
58 #ifndef CONFIG_PCI /* sanity check */
59 #error This driver requires PCI support.
60 #endif
61
62 /* version number of this driver */
63 #define RIVAFB_VERSION "0.9.5b"
64
65 /* ------------------------------------------------------------------------- *
66 *
67 * various helpful macros and constants
68 *
69 * ------------------------------------------------------------------------- */
70 #ifdef CONFIG_FB_RIVA_DEBUG
71 #define NVTRACE printk
72 #else
73 #define NVTRACE if(0) printk
74 #endif
75
76 #define NVTRACE_ENTER(...) NVTRACE("%s START\n", __FUNCTION__)
77 #define NVTRACE_LEAVE(...) NVTRACE("%s END\n", __FUNCTION__)
78
79 #ifdef CONFIG_FB_RIVA_DEBUG
80 #define assert(expr) \
81 if(!(expr)) { \
82 printk( "Assertion failed! %s,%s,%s,line=%d\n",\
83 #expr,__FILE__,__FUNCTION__,__LINE__); \
84 BUG(); \
85 }
86 #else
87 #define assert(expr)
88 #endif
89
90 #define PFX "rivafb: "
91
92 /* macro that allows you to set overflow bits */
93 #define SetBitField(value,from,to) SetBF(to,GetBF(value,from))
94 #define SetBit(n) (1<<(n))
95 #define Set8Bits(value) ((value)&0xff)
96
97 /* HW cursor parameters */
98 #define MAX_CURS 32
99
100 /* ------------------------------------------------------------------------- *
101 *
102 * prototypes
103 *
104 * ------------------------------------------------------------------------- */
105
106 static int rivafb_blank(int blank, struct fb_info *info);
107
108 /* ------------------------------------------------------------------------- *
109 *
110 * card identification
111 *
112 * ------------------------------------------------------------------------- */
113
114 static struct pci_device_id rivafb_pci_tbl[] = {
115 { PCI_VENDOR_ID_NVIDIA_SGS, PCI_DEVICE_ID_NVIDIA_SGS_RIVA128,
116 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
117 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TNT,
118 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
119 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TNT2,
120 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
121 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_UTNT2,
122 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
123 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_VTNT2,
124 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
125 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_UVTNT2,
126 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
127 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_ITNT2,
128 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
129 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_SDR,
130 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
131 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_DDR,
132 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
133 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO,
134 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
135 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX,
136 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
137 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX2,
138 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
139 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GO,
140 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
141 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO2_MXR,
142 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
143 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS,
144 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
145 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS2,
146 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
147 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_ULTRA,
148 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
149 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO2_PRO,
150 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
151 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_460,
152 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
153 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440,
154 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
155 // NF2/IGP version, GeForce 4 MX, NV18
156 { PCI_VENDOR_ID_NVIDIA, 0x01f0,
157 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
158 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_420,
159 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
160 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO,
161 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
162 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO,
163 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
164 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO_M32,
165 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
166 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_500XGL,
167 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
168 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO_M64,
169 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
170 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_200,
171 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
172 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_550XGL,
173 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
174 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_500_GOGL,
175 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
176 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_IGEFORCE2,
177 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
178 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3,
179 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
180 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3_1,
181 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
182 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3_2,
183 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
184 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_DDC,
185 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
186 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4600,
187 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
188 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4400,
189 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
190 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4200,
191 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
192 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_900XGL,
193 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
194 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_750XGL,
195 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
196 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_700XGL,
197 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
198 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO_5200,
199 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
200 { 0, } /* terminate list */
201 };
202 MODULE_DEVICE_TABLE(pci, rivafb_pci_tbl);
203
204 /* ------------------------------------------------------------------------- *
205 *
206 * global variables
207 *
208 * ------------------------------------------------------------------------- */
209
210 /* command line data, set in rivafb_setup() */
211 static int flatpanel __devinitdata = -1; /* Autodetect later */
212 static int forceCRTC __devinitdata = -1;
213 static int noaccel __devinitdata = 0;
214 #ifdef CONFIG_MTRR
215 static int nomtrr __devinitdata = 0;
216 #endif
217
218 static char *mode_option __devinitdata = NULL;
219 static int strictmode = 0;
220
221 static struct fb_fix_screeninfo __devinitdata rivafb_fix = {
222 .type = FB_TYPE_PACKED_PIXELS,
223 .xpanstep = 1,
224 .ypanstep = 1,
225 };
226
227 static struct fb_var_screeninfo __devinitdata rivafb_default_var = {
228 .xres = 640,
229 .yres = 480,
230 .xres_virtual = 640,
231 .yres_virtual = 480,
232 .bits_per_pixel = 8,
233 .red = {0, 8, 0},
234 .green = {0, 8, 0},
235 .blue = {0, 8, 0},
236 .transp = {0, 0, 0},
237 .activate = FB_ACTIVATE_NOW,
238 .height = -1,
239 .width = -1,
240 .pixclock = 39721,
241 .left_margin = 40,
242 .right_margin = 24,
243 .upper_margin = 32,
244 .lower_margin = 11,
245 .hsync_len = 96,
246 .vsync_len = 2,
247 .vmode = FB_VMODE_NONINTERLACED
248 };
249
250 /* from GGI */
251 static const struct riva_regs reg_template = {
252 {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, /* ATTR */
253 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F,
254 0x41, 0x01, 0x0F, 0x00, 0x00},
255 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* CRT */
256 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00,
257 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE3, /* 0x10 */
258 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
259 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x20 */
260 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
261 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x30 */
262 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
263 0x00, /* 0x40 */
264 },
265 {0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0F, /* GRA */
266 0xFF},
267 {0x03, 0x01, 0x0F, 0x00, 0x0E}, /* SEQ */
268 0xEB /* MISC */
269 };
270
271 /*
272 * Backlight control
273 */
274 #ifdef CONFIG_PMAC_BACKLIGHT
275
276 static int riva_backlight_levels[] = {
277 0x158,
278 0x192,
279 0x1c6,
280 0x200,
281 0x234,
282 0x268,
283 0x2a2,
284 0x2d6,
285 0x310,
286 0x344,
287 0x378,
288 0x3b2,
289 0x3e6,
290 0x41a,
291 0x454,
292 0x534,
293 };
294
295 static int riva_set_backlight_enable(int on, int level, void *data);
296 static int riva_set_backlight_level(int level, void *data);
297 static struct backlight_controller riva_backlight_controller = {
298 riva_set_backlight_enable,
299 riva_set_backlight_level
300 };
301 #endif /* CONFIG_PMAC_BACKLIGHT */
302
303 /* ------------------------------------------------------------------------- *
304 *
305 * MMIO access macros
306 *
307 * ------------------------------------------------------------------------- */
308
309 static inline void CRTCout(struct riva_par *par, unsigned char index,
310 unsigned char val)
311 {
312 VGA_WR08(par->riva.PCIO, 0x3d4, index);
313 VGA_WR08(par->riva.PCIO, 0x3d5, val);
314 }
315
316 static inline unsigned char CRTCin(struct riva_par *par,
317 unsigned char index)
318 {
319 VGA_WR08(par->riva.PCIO, 0x3d4, index);
320 return (VGA_RD08(par->riva.PCIO, 0x3d5));
321 }
322
323 static inline void GRAout(struct riva_par *par, unsigned char index,
324 unsigned char val)
325 {
326 VGA_WR08(par->riva.PVIO, 0x3ce, index);
327 VGA_WR08(par->riva.PVIO, 0x3cf, val);
328 }
329
330 static inline unsigned char GRAin(struct riva_par *par,
331 unsigned char index)
332 {
333 VGA_WR08(par->riva.PVIO, 0x3ce, index);
334 return (VGA_RD08(par->riva.PVIO, 0x3cf));
335 }
336
337 static inline void SEQout(struct riva_par *par, unsigned char index,
338 unsigned char val)
339 {
340 VGA_WR08(par->riva.PVIO, 0x3c4, index);
341 VGA_WR08(par->riva.PVIO, 0x3c5, val);
342 }
343
344 static inline unsigned char SEQin(struct riva_par *par,
345 unsigned char index)
346 {
347 VGA_WR08(par->riva.PVIO, 0x3c4, index);
348 return (VGA_RD08(par->riva.PVIO, 0x3c5));
349 }
350
351 static inline void ATTRout(struct riva_par *par, unsigned char index,
352 unsigned char val)
353 {
354 VGA_WR08(par->riva.PCIO, 0x3c0, index);
355 VGA_WR08(par->riva.PCIO, 0x3c0, val);
356 }
357
358 static inline unsigned char ATTRin(struct riva_par *par,
359 unsigned char index)
360 {
361 VGA_WR08(par->riva.PCIO, 0x3c0, index);
362 return (VGA_RD08(par->riva.PCIO, 0x3c1));
363 }
364
365 static inline void MISCout(struct riva_par *par, unsigned char val)
366 {
367 VGA_WR08(par->riva.PVIO, 0x3c2, val);
368 }
369
370 static inline unsigned char MISCin(struct riva_par *par)
371 {
372 return (VGA_RD08(par->riva.PVIO, 0x3cc));
373 }
374
375 static u8 byte_rev[256] = {
376 0x00, 0x80, 0x40, 0xc0, 0x20, 0xa0, 0x60, 0xe0,
377 0x10, 0x90, 0x50, 0xd0, 0x30, 0xb0, 0x70, 0xf0,
378 0x08, 0x88, 0x48, 0xc8, 0x28, 0xa8, 0x68, 0xe8,
379 0x18, 0x98, 0x58, 0xd8, 0x38, 0xb8, 0x78, 0xf8,
380 0x04, 0x84, 0x44, 0xc4, 0x24, 0xa4, 0x64, 0xe4,
381 0x14, 0x94, 0x54, 0xd4, 0x34, 0xb4, 0x74, 0xf4,
382 0x0c, 0x8c, 0x4c, 0xcc, 0x2c, 0xac, 0x6c, 0xec,
383 0x1c, 0x9c, 0x5c, 0xdc, 0x3c, 0xbc, 0x7c, 0xfc,
384 0x02, 0x82, 0x42, 0xc2, 0x22, 0xa2, 0x62, 0xe2,
385 0x12, 0x92, 0x52, 0xd2, 0x32, 0xb2, 0x72, 0xf2,
386 0x0a, 0x8a, 0x4a, 0xca, 0x2a, 0xaa, 0x6a, 0xea,
387 0x1a, 0x9a, 0x5a, 0xda, 0x3a, 0xba, 0x7a, 0xfa,
388 0x06, 0x86, 0x46, 0xc6, 0x26, 0xa6, 0x66, 0xe6,
389 0x16, 0x96, 0x56, 0xd6, 0x36, 0xb6, 0x76, 0xf6,
390 0x0e, 0x8e, 0x4e, 0xce, 0x2e, 0xae, 0x6e, 0xee,
391 0x1e, 0x9e, 0x5e, 0xde, 0x3e, 0xbe, 0x7e, 0xfe,
392 0x01, 0x81, 0x41, 0xc1, 0x21, 0xa1, 0x61, 0xe1,
393 0x11, 0x91, 0x51, 0xd1, 0x31, 0xb1, 0x71, 0xf1,
394 0x09, 0x89, 0x49, 0xc9, 0x29, 0xa9, 0x69, 0xe9,
395 0x19, 0x99, 0x59, 0xd9, 0x39, 0xb9, 0x79, 0xf9,
396 0x05, 0x85, 0x45, 0xc5, 0x25, 0xa5, 0x65, 0xe5,
397 0x15, 0x95, 0x55, 0xd5, 0x35, 0xb5, 0x75, 0xf5,
398 0x0d, 0x8d, 0x4d, 0xcd, 0x2d, 0xad, 0x6d, 0xed,
399 0x1d, 0x9d, 0x5d, 0xdd, 0x3d, 0xbd, 0x7d, 0xfd,
400 0x03, 0x83, 0x43, 0xc3, 0x23, 0xa3, 0x63, 0xe3,
401 0x13, 0x93, 0x53, 0xd3, 0x33, 0xb3, 0x73, 0xf3,
402 0x0b, 0x8b, 0x4b, 0xcb, 0x2b, 0xab, 0x6b, 0xeb,
403 0x1b, 0x9b, 0x5b, 0xdb, 0x3b, 0xbb, 0x7b, 0xfb,
404 0x07, 0x87, 0x47, 0xc7, 0x27, 0xa7, 0x67, 0xe7,
405 0x17, 0x97, 0x57, 0xd7, 0x37, 0xb7, 0x77, 0xf7,
406 0x0f, 0x8f, 0x4f, 0xcf, 0x2f, 0xaf, 0x6f, 0xef,
407 0x1f, 0x9f, 0x5f, 0xdf, 0x3f, 0xbf, 0x7f, 0xff,
408 };
409
410 static inline void reverse_order(u32 *l)
411 {
412 u8 *a = (u8 *)l;
413 *a = byte_rev[*a], a++;
414 *a = byte_rev[*a], a++;
415 *a = byte_rev[*a], a++;
416 *a = byte_rev[*a];
417 }
418
419 /* ------------------------------------------------------------------------- *
420 *
421 * cursor stuff
422 *
423 * ------------------------------------------------------------------------- */
424
425 /**
426 * rivafb_load_cursor_image - load cursor image to hardware
427 * @data: address to monochrome bitmap (1 = foreground color, 0 = background)
428 * @par: pointer to private data
429 * @w: width of cursor image in pixels
430 * @h: height of cursor image in scanlines
431 * @bg: background color (ARGB1555) - alpha bit determines opacity
432 * @fg: foreground color (ARGB1555)
433 *
434 * DESCRIPTiON:
435 * Loads cursor image based on a monochrome source and mask bitmap. The
436 * image bits determines the color of the pixel, 0 for background, 1 for
437 * foreground. Only the affected region (as determined by @w and @h
438 * parameters) will be updated.
439 *
440 * CALLED FROM:
441 * rivafb_cursor()
442 */
443 static void rivafb_load_cursor_image(struct riva_par *par, u8 *data8,
444 u16 bg, u16 fg, u32 w, u32 h)
445 {
446 int i, j, k = 0;
447 u32 b, tmp;
448 u32 *data = (u32 *)data8;
449 bg = le16_to_cpu(bg);
450 fg = le16_to_cpu(fg);
451
452 w = (w + 1) & ~1;
453
454 for (i = 0; i < h; i++) {
455 b = *data++;
456 reverse_order(&b);
457
458 for (j = 0; j < w/2; j++) {
459 tmp = 0;
460 #if defined (__BIG_ENDIAN)
461 tmp = (b & (1 << 31)) ? fg << 16 : bg << 16;
462 b <<= 1;
463 tmp |= (b & (1 << 31)) ? fg : bg;
464 b <<= 1;
465 #else
466 tmp = (b & 1) ? fg : bg;
467 b >>= 1;
468 tmp |= (b & 1) ? fg << 16 : bg << 16;
469 b >>= 1;
470 #endif
471 writel(tmp, &par->riva.CURSOR[k++]);
472 }
473 k += (MAX_CURS - w)/2;
474 }
475 }
476
477 /* ------------------------------------------------------------------------- *
478 *
479 * general utility functions
480 *
481 * ------------------------------------------------------------------------- */
482
483 /**
484 * riva_wclut - set CLUT entry
485 * @chip: pointer to RIVA_HW_INST object
486 * @regnum: register number
487 * @red: red component
488 * @green: green component
489 * @blue: blue component
490 *
491 * DESCRIPTION:
492 * Sets color register @regnum.
493 *
494 * CALLED FROM:
495 * rivafb_setcolreg()
496 */
497 static void riva_wclut(RIVA_HW_INST *chip,
498 unsigned char regnum, unsigned char red,
499 unsigned char green, unsigned char blue)
500 {
501 VGA_WR08(chip->PDIO, 0x3c8, regnum);
502 VGA_WR08(chip->PDIO, 0x3c9, red);
503 VGA_WR08(chip->PDIO, 0x3c9, green);
504 VGA_WR08(chip->PDIO, 0x3c9, blue);
505 }
506
507 /**
508 * riva_rclut - read fromCLUT register
509 * @chip: pointer to RIVA_HW_INST object
510 * @regnum: register number
511 * @red: red component
512 * @green: green component
513 * @blue: blue component
514 *
515 * DESCRIPTION:
516 * Reads red, green, and blue from color register @regnum.
517 *
518 * CALLED FROM:
519 * rivafb_setcolreg()
520 */
521 static void riva_rclut(RIVA_HW_INST *chip,
522 unsigned char regnum, unsigned char *red,
523 unsigned char *green, unsigned char *blue)
524 {
525
526 VGA_WR08(chip->PDIO, 0x3c7, regnum);
527 *red = VGA_RD08(chip->PDIO, 0x3c9);
528 *green = VGA_RD08(chip->PDIO, 0x3c9);
529 *blue = VGA_RD08(chip->PDIO, 0x3c9);
530 }
531
532 /**
533 * riva_save_state - saves current chip state
534 * @par: pointer to riva_par object containing info for current riva board
535 * @regs: pointer to riva_regs object
536 *
537 * DESCRIPTION:
538 * Saves current chip state to @regs.
539 *
540 * CALLED FROM:
541 * rivafb_probe()
542 */
543 /* from GGI */
544 static void riva_save_state(struct riva_par *par, struct riva_regs *regs)
545 {
546 int i;
547
548 NVTRACE_ENTER();
549 par->riva.LockUnlock(&par->riva, 0);
550
551 par->riva.UnloadStateExt(&par->riva, &regs->ext);
552
553 regs->misc_output = MISCin(par);
554
555 for (i = 0; i < NUM_CRT_REGS; i++)
556 regs->crtc[i] = CRTCin(par, i);
557
558 for (i = 0; i < NUM_ATC_REGS; i++)
559 regs->attr[i] = ATTRin(par, i);
560
561 for (i = 0; i < NUM_GRC_REGS; i++)
562 regs->gra[i] = GRAin(par, i);
563
564 for (i = 0; i < NUM_SEQ_REGS; i++)
565 regs->seq[i] = SEQin(par, i);
566 NVTRACE_LEAVE();
567 }
568
569 /**
570 * riva_load_state - loads current chip state
571 * @par: pointer to riva_par object containing info for current riva board
572 * @regs: pointer to riva_regs object
573 *
574 * DESCRIPTION:
575 * Loads chip state from @regs.
576 *
577 * CALLED FROM:
578 * riva_load_video_mode()
579 * rivafb_probe()
580 * rivafb_remove()
581 */
582 /* from GGI */
583 static void riva_load_state(struct riva_par *par, struct riva_regs *regs)
584 {
585 RIVA_HW_STATE *state = &regs->ext;
586 int i;
587
588 NVTRACE_ENTER();
589 CRTCout(par, 0x11, 0x00);
590
591 par->riva.LockUnlock(&par->riva, 0);
592
593 par->riva.LoadStateExt(&par->riva, state);
594
595 MISCout(par, regs->misc_output);
596
597 for (i = 0; i < NUM_CRT_REGS; i++) {
598 switch (i) {
599 case 0x19:
600 case 0x20 ... 0x40:
601 break;
602 default:
603 CRTCout(par, i, regs->crtc[i]);
604 }
605 }
606
607 for (i = 0; i < NUM_ATC_REGS; i++)
608 ATTRout(par, i, regs->attr[i]);
609
610 for (i = 0; i < NUM_GRC_REGS; i++)
611 GRAout(par, i, regs->gra[i]);
612
613 for (i = 0; i < NUM_SEQ_REGS; i++)
614 SEQout(par, i, regs->seq[i]);
615 NVTRACE_LEAVE();
616 }
617
618 /**
619 * riva_load_video_mode - calculate timings
620 * @info: pointer to fb_info object containing info for current riva board
621 *
622 * DESCRIPTION:
623 * Calculate some timings and then send em off to riva_load_state().
624 *
625 * CALLED FROM:
626 * rivafb_set_par()
627 */
628 static void riva_load_video_mode(struct fb_info *info)
629 {
630 int bpp, width, hDisplaySize, hDisplay, hStart,
631 hEnd, hTotal, height, vDisplay, vStart, vEnd, vTotal, dotClock;
632 int hBlankStart, hBlankEnd, vBlankStart, vBlankEnd;
633 struct riva_par *par = (struct riva_par *) info->par;
634 struct riva_regs newmode;
635
636 NVTRACE_ENTER();
637 /* time to calculate */
638 rivafb_blank(1, info);
639
640 bpp = info->var.bits_per_pixel;
641 if (bpp == 16 && info->var.green.length == 5)
642 bpp = 15;
643 width = info->var.xres_virtual;
644 hDisplaySize = info->var.xres;
645 hDisplay = (hDisplaySize / 8) - 1;
646 hStart = (hDisplaySize + info->var.right_margin) / 8 - 1;
647 hEnd = (hDisplaySize + info->var.right_margin +
648 info->var.hsync_len) / 8 - 1;
649 hTotal = (hDisplaySize + info->var.right_margin +
650 info->var.hsync_len + info->var.left_margin) / 8 - 5;
651 hBlankStart = hDisplay;
652 hBlankEnd = hTotal + 4;
653
654 height = info->var.yres_virtual;
655 vDisplay = info->var.yres - 1;
656 vStart = info->var.yres + info->var.lower_margin - 1;
657 vEnd = info->var.yres + info->var.lower_margin +
658 info->var.vsync_len - 1;
659 vTotal = info->var.yres + info->var.lower_margin +
660 info->var.vsync_len + info->var.upper_margin + 2;
661 vBlankStart = vDisplay;
662 vBlankEnd = vTotal + 1;
663 dotClock = 1000000000 / info->var.pixclock;
664
665 memcpy(&newmode, &reg_template, sizeof(struct riva_regs));
666
667 if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED)
668 vTotal |= 1;
669
670 if (par->FlatPanel) {
671 vStart = vTotal - 3;
672 vEnd = vTotal - 2;
673 vBlankStart = vStart;
674 hStart = hTotal - 3;
675 hEnd = hTotal - 2;
676 hBlankEnd = hTotal + 4;
677 }
678
679 newmode.crtc[0x0] = Set8Bits (hTotal);
680 newmode.crtc[0x1] = Set8Bits (hDisplay);
681 newmode.crtc[0x2] = Set8Bits (hBlankStart);
682 newmode.crtc[0x3] = SetBitField (hBlankEnd, 4: 0, 4:0) | SetBit (7);
683 newmode.crtc[0x4] = Set8Bits (hStart);
684 newmode.crtc[0x5] = SetBitField (hBlankEnd, 5: 5, 7:7)
685 | SetBitField (hEnd, 4: 0, 4:0);
686 newmode.crtc[0x6] = SetBitField (vTotal, 7: 0, 7:0);
687 newmode.crtc[0x7] = SetBitField (vTotal, 8: 8, 0:0)
688 | SetBitField (vDisplay, 8: 8, 1:1)
689 | SetBitField (vStart, 8: 8, 2:2)
690 | SetBitField (vBlankStart, 8: 8, 3:3)
691 | SetBit (4)
692 | SetBitField (vTotal, 9: 9, 5:5)
693 | SetBitField (vDisplay, 9: 9, 6:6)
694 | SetBitField (vStart, 9: 9, 7:7);
695 newmode.crtc[0x9] = SetBitField (vBlankStart, 9: 9, 5:5)
696 | SetBit (6);
697 newmode.crtc[0x10] = Set8Bits (vStart);
698 newmode.crtc[0x11] = SetBitField (vEnd, 3: 0, 3:0)
699 | SetBit (5);
700 newmode.crtc[0x12] = Set8Bits (vDisplay);
701 newmode.crtc[0x13] = (width / 8) * ((bpp + 1) / 8);
702 newmode.crtc[0x15] = Set8Bits (vBlankStart);
703 newmode.crtc[0x16] = Set8Bits (vBlankEnd);
704
705 newmode.ext.screen = SetBitField(hBlankEnd,6:6,4:4)
706 | SetBitField(vBlankStart,10:10,3:3)
707 | SetBitField(vStart,10:10,2:2)
708 | SetBitField(vDisplay,10:10,1:1)
709 | SetBitField(vTotal,10:10,0:0);
710 newmode.ext.horiz = SetBitField(hTotal,8:8,0:0)
711 | SetBitField(hDisplay,8:8,1:1)
712 | SetBitField(hBlankStart,8:8,2:2)
713 | SetBitField(hStart,8:8,3:3);
714 newmode.ext.extra = SetBitField(vTotal,11:11,0:0)
715 | SetBitField(vDisplay,11:11,2:2)
716 | SetBitField(vStart,11:11,4:4)
717 | SetBitField(vBlankStart,11:11,6:6);
718
719 if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED) {
720 int tmp = (hTotal >> 1) & ~1;
721 newmode.ext.interlace = Set8Bits(tmp);
722 newmode.ext.horiz |= SetBitField(tmp, 8:8,4:4);
723 } else
724 newmode.ext.interlace = 0xff; /* interlace off */
725
726 if (par->riva.Architecture >= NV_ARCH_10)
727 par->riva.CURSOR = (U032 __iomem *)(info->screen_base + par->riva.CursorStart);
728
729 if (info->var.sync & FB_SYNC_HOR_HIGH_ACT)
730 newmode.misc_output &= ~0x40;
731 else
732 newmode.misc_output |= 0x40;
733 if (info->var.sync & FB_SYNC_VERT_HIGH_ACT)
734 newmode.misc_output &= ~0x80;
735 else
736 newmode.misc_output |= 0x80;
737
738 par->riva.CalcStateExt(&par->riva, &newmode.ext, bpp, width,
739 hDisplaySize, height, dotClock);
740
741 newmode.ext.scale = NV_RD32(par->riva.PRAMDAC, 0x00000848) &
742 0xfff000ff;
743 if (par->FlatPanel == 1) {
744 newmode.ext.pixel |= (1 << 7);
745 newmode.ext.scale |= (1 << 8);
746 }
747 if (par->SecondCRTC) {
748 newmode.ext.head = NV_RD32(par->riva.PCRTC0, 0x00000860) &
749 ~0x00001000;
750 newmode.ext.head2 = NV_RD32(par->riva.PCRTC0, 0x00002860) |
751 0x00001000;
752 newmode.ext.crtcOwner = 3;
753 newmode.ext.pllsel |= 0x20000800;
754 newmode.ext.vpll2 = newmode.ext.vpll;
755 } else if (par->riva.twoHeads) {
756 newmode.ext.head = NV_RD32(par->riva.PCRTC0, 0x00000860) |
757 0x00001000;
758 newmode.ext.head2 = NV_RD32(par->riva.PCRTC0, 0x00002860) &
759 ~0x00001000;
760 newmode.ext.crtcOwner = 0;
761 newmode.ext.vpll2 = NV_RD32(par->riva.PRAMDAC0, 0x00000520);
762 }
763 if (par->FlatPanel == 1) {
764 newmode.ext.pixel |= (1 << 7);
765 newmode.ext.scale |= (1 << 8);
766 }
767 newmode.ext.cursorConfig = 0x02000100;
768 par->current_state = newmode;
769 riva_load_state(par, &par->current_state);
770 par->riva.LockUnlock(&par->riva, 0); /* important for HW cursor */
771 rivafb_blank(0, info);
772 NVTRACE_LEAVE();
773 }
774
775 static void riva_update_var(struct fb_var_screeninfo *var, struct fb_videomode *modedb)
776 {
777 NVTRACE_ENTER();
778 var->xres = var->xres_virtual = modedb->xres;
779 var->yres = modedb->yres;
780 if (var->yres_virtual < var->yres)
781 var->yres_virtual = var->yres;
782 var->xoffset = var->yoffset = 0;
783 var->pixclock = modedb->pixclock;
784 var->left_margin = modedb->left_margin;
785 var->right_margin = modedb->right_margin;
786 var->upper_margin = modedb->upper_margin;
787 var->lower_margin = modedb->lower_margin;
788 var->hsync_len = modedb->hsync_len;
789 var->vsync_len = modedb->vsync_len;
790 var->sync = modedb->sync;
791 var->vmode = modedb->vmode;
792 NVTRACE_LEAVE();
793 }
794
795 /**
796 * rivafb_do_maximize -
797 * @info: pointer to fb_info object containing info for current riva board
798 * @var:
799 * @nom:
800 * @den:
801 *
802 * DESCRIPTION:
803 * .
804 *
805 * RETURNS:
806 * -EINVAL on failure, 0 on success
807 *
808 *
809 * CALLED FROM:
810 * rivafb_check_var()
811 */
812 static int rivafb_do_maximize(struct fb_info *info,
813 struct fb_var_screeninfo *var,
814 int nom, int den)
815 {
816 static struct {
817 int xres, yres;
818 } modes[] = {
819 {1600, 1280},
820 {1280, 1024},
821 {1024, 768},
822 {800, 600},
823 {640, 480},
824 {-1, -1}
825 };
826 int i;
827
828 NVTRACE_ENTER();
829 /* use highest possible virtual resolution */
830 if (var->xres_virtual == -1 && var->yres_virtual == -1) {
831 printk(KERN_WARNING PFX
832 "using maximum available virtual resolution\n");
833 for (i = 0; modes[i].xres != -1; i++) {
834 if (modes[i].xres * nom / den * modes[i].yres <
835 info->fix.smem_len)
836 break;
837 }
838 if (modes[i].xres == -1) {
839 printk(KERN_ERR PFX
840 "could not find a virtual resolution that fits into video memory!!\n");
841 NVTRACE("EXIT - EINVAL error\n");
842 return -EINVAL;
843 }
844 var->xres_virtual = modes[i].xres;
845 var->yres_virtual = modes[i].yres;
846
847 printk(KERN_INFO PFX
848 "virtual resolution set to maximum of %dx%d\n",
849 var->xres_virtual, var->yres_virtual);
850 } else if (var->xres_virtual == -1) {
851 var->xres_virtual = (info->fix.smem_len * den /
852 (nom * var->yres_virtual)) & ~15;
853 printk(KERN_WARNING PFX
854 "setting virtual X resolution to %d\n", var->xres_virtual);
855 } else if (var->yres_virtual == -1) {
856 var->xres_virtual = (var->xres_virtual + 15) & ~15;
857 var->yres_virtual = info->fix.smem_len * den /
858 (nom * var->xres_virtual);
859 printk(KERN_WARNING PFX
860 "setting virtual Y resolution to %d\n", var->yres_virtual);
861 } else {
862 var->xres_virtual = (var->xres_virtual + 15) & ~15;
863 if (var->xres_virtual * nom / den * var->yres_virtual > info->fix.smem_len) {
864 printk(KERN_ERR PFX
865 "mode %dx%dx%d rejected...resolution too high to fit into video memory!\n",
866 var->xres, var->yres, var->bits_per_pixel);
867 NVTRACE("EXIT - EINVAL error\n");
868 return -EINVAL;
869 }
870 }
871
872 if (var->xres_virtual * nom / den >= 8192) {
873 printk(KERN_WARNING PFX
874 "virtual X resolution (%d) is too high, lowering to %d\n",
875 var->xres_virtual, 8192 * den / nom - 16);
876 var->xres_virtual = 8192 * den / nom - 16;
877 }
878
879 if (var->xres_virtual < var->xres) {
880 printk(KERN_ERR PFX
881 "virtual X resolution (%d) is smaller than real\n", var->xres_virtual);
882 return -EINVAL;
883 }
884
885 if (var->yres_virtual < var->yres) {
886 printk(KERN_ERR PFX
887 "virtual Y resolution (%d) is smaller than real\n", var->yres_virtual);
888 return -EINVAL;
889 }
890 if (var->yres_virtual > 0x7fff/nom)
891 var->yres_virtual = 0x7fff/nom;
892 if (var->xres_virtual > 0x7fff/nom)
893 var->xres_virtual = 0x7fff/nom;
894 NVTRACE_LEAVE();
895 return 0;
896 }
897
898 static void
899 riva_set_pattern(struct riva_par *par, int clr0, int clr1, int pat0, int pat1)
900 {
901 RIVA_FIFO_FREE(par->riva, Patt, 4);
902 NV_WR32(&par->riva.Patt->Color0, 0, clr0);
903 NV_WR32(&par->riva.Patt->Color1, 0, clr1);
904 NV_WR32(par->riva.Patt->Monochrome, 0, pat0);
905 NV_WR32(par->riva.Patt->Monochrome, 4, pat1);
906 }
907
908 /* acceleration routines */
909 static inline void wait_for_idle(struct riva_par *par)
910 {
911 while (par->riva.Busy(&par->riva));
912 }
913
914 /*
915 * Set ROP. Translate X rop into ROP3. Internal routine.
916 */
917 static void
918 riva_set_rop_solid(struct riva_par *par, int rop)
919 {
920 riva_set_pattern(par, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF);
921 RIVA_FIFO_FREE(par->riva, Rop, 1);
922 NV_WR32(&par->riva.Rop->Rop3, 0, rop);
923
924 }
925
926 static void riva_setup_accel(struct fb_info *info)
927 {
928 struct riva_par *par = (struct riva_par *) info->par;
929
930 RIVA_FIFO_FREE(par->riva, Clip, 2);
931 NV_WR32(&par->riva.Clip->TopLeft, 0, 0x0);
932 NV_WR32(&par->riva.Clip->WidthHeight, 0,
933 (info->var.xres_virtual & 0xffff) |
934 (info->var.yres_virtual << 16));
935 riva_set_rop_solid(par, 0xcc);
936 wait_for_idle(par);
937 }
938
939 /**
940 * riva_get_cmap_len - query current color map length
941 * @var: standard kernel fb changeable data
942 *
943 * DESCRIPTION:
944 * Get current color map length.
945 *
946 * RETURNS:
947 * Length of color map
948 *
949 * CALLED FROM:
950 * rivafb_setcolreg()
951 */
952 static int riva_get_cmap_len(const struct fb_var_screeninfo *var)
953 {
954 int rc = 256; /* reasonable default */
955
956 switch (var->green.length) {
957 case 8:
958 rc = 256; /* 256 entries (2^8), 8 bpp and RGB8888 */
959 break;
960 case 5:
961 rc = 32; /* 32 entries (2^5), 16 bpp, RGB555 */
962 break;
963 case 6:
964 rc = 64; /* 64 entries (2^6), 16 bpp, RGB565 */
965 break;
966 default:
967 /* should not occur */
968 break;
969 }
970 return rc;
971 }
972
973 /* ------------------------------------------------------------------------- *
974 *
975 * Backlight operations
976 *
977 * ------------------------------------------------------------------------- */
978
979 #ifdef CONFIG_PMAC_BACKLIGHT
980 static int riva_set_backlight_enable(int on, int level, void *data)
981 {
982 struct riva_par *par = (struct riva_par *)data;
983 U032 tmp_pcrt, tmp_pmc;
984
985 tmp_pmc = par->riva.PMC[0x10F0/4] & 0x0000FFFF;
986 tmp_pcrt = par->riva.PCRTC0[0x081C/4] & 0xFFFFFFFC;
987 if(on && (level > BACKLIGHT_OFF)) {
988 tmp_pcrt |= 0x1;
989 tmp_pmc |= (1 << 31); // backlight bit
990 tmp_pmc |= riva_backlight_levels[level-1] << 16; // level
991 }
992 par->riva.PCRTC0[0x081C/4] = tmp_pcrt;
993 par->riva.PMC[0x10F0/4] = tmp_pmc;
994 return 0;
995 }
996
997 static int riva_set_backlight_level(int level, void *data)
998 {
999 return riva_set_backlight_enable(1, level, data);
1000 }
1001 #endif /* CONFIG_PMAC_BACKLIGHT */
1002
1003 /* ------------------------------------------------------------------------- *
1004 *
1005 * framebuffer operations
1006 *
1007 * ------------------------------------------------------------------------- */
1008
1009 static int rivafb_open(struct fb_info *info, int user)
1010 {
1011 struct riva_par *par = (struct riva_par *) info->par;
1012 int cnt = atomic_read(&par->ref_count);
1013
1014 NVTRACE_ENTER();
1015 if (!cnt) {
1016 #ifdef CONFIG_X86
1017 memset(&par->state, 0, sizeof(struct vgastate));
1018 par->state.flags = VGA_SAVE_MODE | VGA_SAVE_FONTS;
1019 /* save the DAC for Riva128 */
1020 if (par->riva.Architecture == NV_ARCH_03)
1021 par->state.flags |= VGA_SAVE_CMAP;
1022 save_vga(&par->state);
1023 #endif
1024 /* vgaHWunlock() + riva unlock (0x7F) */
1025 CRTCout(par, 0x11, 0xFF);
1026 par->riva.LockUnlock(&par->riva, 0);
1027
1028 riva_save_state(par, &par->initial_state);
1029 }
1030 atomic_inc(&par->ref_count);
1031 NVTRACE_LEAVE();
1032 return 0;
1033 }
1034
1035 static int rivafb_release(struct fb_info *info, int user)
1036 {
1037 struct riva_par *par = (struct riva_par *) info->par;
1038 int cnt = atomic_read(&par->ref_count);
1039
1040 NVTRACE_ENTER();
1041 if (!cnt)
1042 return -EINVAL;
1043 if (cnt == 1) {
1044 par->riva.LockUnlock(&par->riva, 0);
1045 par->riva.LoadStateExt(&par->riva, &par->initial_state.ext);
1046 riva_load_state(par, &par->initial_state);
1047 #ifdef CONFIG_X86
1048 restore_vga(&par->state);
1049 #endif
1050 par->riva.LockUnlock(&par->riva, 1);
1051 }
1052 atomic_dec(&par->ref_count);
1053 NVTRACE_LEAVE();
1054 return 0;
1055 }
1056
1057 static int rivafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
1058 {
1059 struct fb_videomode *mode;
1060 struct riva_par *par = (struct riva_par *) info->par;
1061 int nom, den; /* translating from pixels->bytes */
1062 int mode_valid = 0;
1063
1064 NVTRACE_ENTER();
1065 switch (var->bits_per_pixel) {
1066 case 1 ... 8:
1067 var->red.offset = var->green.offset = var->blue.offset = 0;
1068 var->red.length = var->green.length = var->blue.length = 8;
1069 var->bits_per_pixel = 8;
1070 nom = den = 1;
1071 break;
1072 case 9 ... 15:
1073 var->green.length = 5;
1074 /* fall through */
1075 case 16:
1076 var->bits_per_pixel = 16;
1077 /* The Riva128 supports RGB555 only */
1078 if (par->riva.Architecture == NV_ARCH_03)
1079 var->green.length = 5;
1080 if (var->green.length == 5) {
1081 /* 0rrrrrgg gggbbbbb */
1082 var->red.offset = 10;
1083 var->green.offset = 5;
1084 var->blue.offset = 0;
1085 var->red.length = 5;
1086 var->green.length = 5;
1087 var->blue.length = 5;
1088 } else {
1089 /* rrrrrggg gggbbbbb */
1090 var->red.offset = 11;
1091 var->green.offset = 5;
1092 var->blue.offset = 0;
1093 var->red.length = 5;
1094 var->green.length = 6;
1095 var->blue.length = 5;
1096 }
1097 nom = 2;
1098 den = 1;
1099 break;
1100 case 17 ... 32:
1101 var->red.length = var->green.length = var->blue.length = 8;
1102 var->bits_per_pixel = 32;
1103 var->red.offset = 16;
1104 var->green.offset = 8;
1105 var->blue.offset = 0;
1106 nom = 4;
1107 den = 1;
1108 break;
1109 default:
1110 printk(KERN_ERR PFX
1111 "mode %dx%dx%d rejected...color depth not supported.\n",
1112 var->xres, var->yres, var->bits_per_pixel);
1113 NVTRACE("EXIT, returning -EINVAL\n");
1114 return -EINVAL;
1115 }
1116
1117 if (!strictmode) {
1118 if (!info->monspecs.vfmax || !info->monspecs.hfmax ||
1119 !info->monspecs.dclkmax || !fb_validate_mode(var, info))
1120 mode_valid = 1;
1121 }
1122
1123 /* calculate modeline if supported by monitor */
1124 if (!mode_valid && info->monspecs.gtf) {
1125 if (!fb_get_mode(FB_MAXTIMINGS, 0, var, info))
1126 mode_valid = 1;
1127 }
1128
1129 if (!mode_valid) {
1130 mode = fb_find_best_mode(var, &info->modelist);
1131 if (mode) {
1132 riva_update_var(var, mode);
1133 mode_valid = 1;
1134 }
1135 }
1136
1137 if (!mode_valid && info->monspecs.modedb_len)
1138 return -EINVAL;
1139
1140 if (var->xres_virtual < var->xres)
1141 var->xres_virtual = var->xres;
1142 if (var->yres_virtual <= var->yres)
1143 var->yres_virtual = -1;
1144 if (rivafb_do_maximize(info, var, nom, den) < 0)
1145 return -EINVAL;
1146
1147 if (var->xoffset < 0)
1148 var->xoffset = 0;
1149 if (var->yoffset < 0)
1150 var->yoffset = 0;
1151
1152 /* truncate xoffset and yoffset to maximum if too high */
1153 if (var->xoffset > var->xres_virtual - var->xres)
1154 var->xoffset = var->xres_virtual - var->xres - 1;
1155
1156 if (var->yoffset > var->yres_virtual - var->yres)
1157 var->yoffset = var->yres_virtual - var->yres - 1;
1158
1159 var->red.msb_right =
1160 var->green.msb_right =
1161 var->blue.msb_right =
1162 var->transp.offset = var->transp.length = var->transp.msb_right = 0;
1163 NVTRACE_LEAVE();
1164 return 0;
1165 }
1166
1167 static int rivafb_set_par(struct fb_info *info)
1168 {
1169 struct riva_par *par = (struct riva_par *) info->par;
1170
1171 NVTRACE_ENTER();
1172 /* vgaHWunlock() + riva unlock (0x7F) */
1173 CRTCout(par, 0x11, 0xFF);
1174 par->riva.LockUnlock(&par->riva, 0);
1175 riva_load_video_mode(info);
1176 if(!(info->flags & FBINFO_HWACCEL_DISABLED))
1177 riva_setup_accel(info);
1178
1179 par->cursor_reset = 1;
1180 info->fix.line_length = (info->var.xres_virtual * (info->var.bits_per_pixel >> 3));
1181 info->fix.visual = (info->var.bits_per_pixel == 8) ?
1182 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
1183
1184 if (info->flags & FBINFO_HWACCEL_DISABLED)
1185 info->pixmap.scan_align = 1;
1186 else
1187 info->pixmap.scan_align = 4;
1188 NVTRACE_LEAVE();
1189 return 0;
1190 }
1191
1192 /**
1193 * rivafb_pan_display
1194 * @var: standard kernel fb changeable data
1195 * @con: TODO
1196 * @info: pointer to fb_info object containing info for current riva board
1197 *
1198 * DESCRIPTION:
1199 * Pan (or wrap, depending on the `vmode' field) the display using the
1200 * `xoffset' and `yoffset' fields of the `var' structure.
1201 * If the values don't fit, return -EINVAL.
1202 *
1203 * This call looks only at xoffset, yoffset and the FB_VMODE_YWRAP flag
1204 */
1205 static int rivafb_pan_display(struct fb_var_screeninfo *var,
1206 struct fb_info *info)
1207 {
1208 struct riva_par *par = (struct riva_par *)info->par;
1209 unsigned int base;
1210
1211 NVTRACE_ENTER();
1212 if (var->xoffset > (var->xres_virtual - var->xres))
1213 return -EINVAL;
1214 if (var->yoffset > (var->yres_virtual - var->yres))
1215 return -EINVAL;
1216
1217 if (var->vmode & FB_VMODE_YWRAP) {
1218 if (var->yoffset < 0
1219 || var->yoffset >= info->var.yres_virtual
1220 || var->xoffset) return -EINVAL;
1221 } else {
1222 if (var->xoffset + info->var.xres > info->var.xres_virtual ||
1223 var->yoffset + info->var.yres > info->var.yres_virtual)
1224 return -EINVAL;
1225 }
1226
1227 base = var->yoffset * info->fix.line_length + var->xoffset;
1228
1229 par->riva.SetStartAddress(&par->riva, base);
1230
1231 info->var.xoffset = var->xoffset;
1232 info->var.yoffset = var->yoffset;
1233
1234 if (var->vmode & FB_VMODE_YWRAP)
1235 info->var.vmode |= FB_VMODE_YWRAP;
1236 else
1237 info->var.vmode &= ~FB_VMODE_YWRAP;
1238 NVTRACE_LEAVE();
1239 return 0;
1240 }
1241
1242 static int rivafb_blank(int blank, struct fb_info *info)
1243 {
1244 struct riva_par *par= (struct riva_par *)info->par;
1245 unsigned char tmp, vesa;
1246
1247 tmp = SEQin(par, 0x01) & ~0x20; /* screen on/off */
1248 vesa = CRTCin(par, 0x1a) & ~0xc0; /* sync on/off */
1249
1250 NVTRACE_ENTER();
1251
1252 if (blank)
1253 tmp |= 0x20;
1254
1255 switch (blank) {
1256 case FB_BLANK_UNBLANK:
1257 case FB_BLANK_NORMAL:
1258 break;
1259 case FB_BLANK_VSYNC_SUSPEND:
1260 vesa |= 0x80;
1261 break;
1262 case FB_BLANK_HSYNC_SUSPEND:
1263 vesa |= 0x40;
1264 break;
1265 case FB_BLANK_POWERDOWN:
1266 vesa |= 0xc0;
1267 break;
1268 }
1269
1270 SEQout(par, 0x01, tmp);
1271 CRTCout(par, 0x1a, vesa);
1272
1273 #ifdef CONFIG_PMAC_BACKLIGHT
1274 if ( par->FlatPanel && _machine == _MACH_Pmac) {
1275 set_backlight_enable(!blank);
1276 }
1277 #endif
1278
1279 NVTRACE_LEAVE();
1280
1281 return 0;
1282 }
1283
1284 /**
1285 * rivafb_setcolreg
1286 * @regno: register index
1287 * @red: red component
1288 * @green: green component
1289 * @blue: blue component
1290 * @transp: transparency
1291 * @info: pointer to fb_info object containing info for current riva board
1292 *
1293 * DESCRIPTION:
1294 * Set a single color register. The values supplied have a 16 bit
1295 * magnitude.
1296 *
1297 * RETURNS:
1298 * Return != 0 for invalid regno.
1299 *
1300 * CALLED FROM:
1301 * fbcmap.c:fb_set_cmap()
1302 */
1303 static int rivafb_setcolreg(unsigned regno, unsigned red, unsigned green,
1304 unsigned blue, unsigned transp,
1305 struct fb_info *info)
1306 {
1307 struct riva_par *par = (struct riva_par *)info->par;
1308 RIVA_HW_INST *chip = &par->riva;
1309 int i;
1310
1311 if (regno >= riva_get_cmap_len(&info->var))
1312 return -EINVAL;
1313
1314 if (info->var.grayscale) {
1315 /* gray = 0.30*R + 0.59*G + 0.11*B */
1316 red = green = blue =
1317 (red * 77 + green * 151 + blue * 28) >> 8;
1318 }
1319
1320 if (regno < 16 && info->fix.visual == FB_VISUAL_DIRECTCOLOR) {
1321 ((u32 *) info->pseudo_palette)[regno] =
1322 (regno << info->var.red.offset) |
1323 (regno << info->var.green.offset) |
1324 (regno << info->var.blue.offset);
1325 /*
1326 * The Riva128 2D engine requires color information in
1327 * TrueColor format even if framebuffer is in DirectColor
1328 */
1329 if (par->riva.Architecture == NV_ARCH_03) {
1330 switch (info->var.bits_per_pixel) {
1331 case 16:
1332 par->palette[regno] = ((red & 0xf800) >> 1) |
1333 ((green & 0xf800) >> 6) |
1334 ((blue & 0xf800) >> 11);
1335 break;
1336 case 32:
1337 par->palette[regno] = ((red & 0xff00) << 8) |
1338 ((green & 0xff00)) |
1339 ((blue & 0xff00) >> 8);
1340 break;
1341 }
1342 }
1343 }
1344
1345 switch (info->var.bits_per_pixel) {
1346 case 8:
1347 /* "transparent" stuff is completely ignored. */
1348 riva_wclut(chip, regno, red >> 8, green >> 8, blue >> 8);
1349 break;
1350 case 16:
1351 if (info->var.green.length == 5) {
1352 for (i = 0; i < 8; i++) {
1353 riva_wclut(chip, regno*8+i, red >> 8,
1354 green >> 8, blue >> 8);
1355 }
1356 } else {
1357 u8 r, g, b;
1358
1359 if (regno < 32) {
1360 for (i = 0; i < 8; i++) {
1361 riva_wclut(chip, regno*8+i,
1362 red >> 8, green >> 8,
1363 blue >> 8);
1364 }
1365 }
1366 riva_rclut(chip, regno*4, &r, &g, &b);
1367 for (i = 0; i < 4; i++)
1368 riva_wclut(chip, regno*4+i, r,
1369 green >> 8, b);
1370 }
1371 break;
1372 case 32:
1373 riva_wclut(chip, regno, red >> 8, green >> 8, blue >> 8);
1374 break;
1375 default:
1376 /* do nothing */
1377 break;
1378 }
1379 return 0;
1380 }
1381
1382 /**
1383 * rivafb_fillrect - hardware accelerated color fill function
1384 * @info: pointer to fb_info structure
1385 * @rect: pointer to fb_fillrect structure
1386 *
1387 * DESCRIPTION:
1388 * This function fills up a region of framebuffer memory with a solid
1389 * color with a choice of two different ROP's, copy or invert.
1390 *
1391 * CALLED FROM:
1392 * framebuffer hook
1393 */
1394 static void rivafb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
1395 {
1396 struct riva_par *par = (struct riva_par *) info->par;
1397 u_int color, rop = 0;
1398
1399 if ((info->flags & FBINFO_HWACCEL_DISABLED)) {
1400 cfb_fillrect(info, rect);
1401 return;
1402 }
1403
1404 if (info->var.bits_per_pixel == 8)
1405 color = rect->color;
1406 else {
1407 if (par->riva.Architecture != NV_ARCH_03)
1408 color = ((u32 *)info->pseudo_palette)[rect->color];
1409 else
1410 color = par->palette[rect->color];
1411 }
1412
1413 switch (rect->rop) {
1414 case ROP_XOR:
1415 rop = 0x66;
1416 break;
1417 case ROP_COPY:
1418 default:
1419 rop = 0xCC;
1420 break;
1421 }
1422
1423 riva_set_rop_solid(par, rop);
1424
1425 RIVA_FIFO_FREE(par->riva, Bitmap, 1);
1426 NV_WR32(&par->riva.Bitmap->Color1A, 0, color);
1427
1428 RIVA_FIFO_FREE(par->riva, Bitmap, 2);
1429 NV_WR32(&par->riva.Bitmap->UnclippedRectangle[0].TopLeft, 0,
1430 (rect->dx << 16) | rect->dy);
1431 mb();
1432 NV_WR32(&par->riva.Bitmap->UnclippedRectangle[0].WidthHeight, 0,
1433 (rect->width << 16) | rect->height);
1434 mb();
1435 riva_set_rop_solid(par, 0xcc);
1436
1437 }
1438
1439 /**
1440 * rivafb_copyarea - hardware accelerated blit function
1441 * @info: pointer to fb_info structure
1442 * @region: pointer to fb_copyarea structure
1443 *
1444 * DESCRIPTION:
1445 * This copies an area of pixels from one location to another
1446 *
1447 * CALLED FROM:
1448 * framebuffer hook
1449 */
1450 static void rivafb_copyarea(struct fb_info *info, const struct fb_copyarea *region)
1451 {
1452 struct riva_par *par = (struct riva_par *) info->par;
1453
1454 if ((info->flags & FBINFO_HWACCEL_DISABLED)) {
1455 cfb_copyarea(info, region);
1456 return;
1457 }
1458
1459 RIVA_FIFO_FREE(par->riva, Blt, 3);
1460 NV_WR32(&par->riva.Blt->TopLeftSrc, 0,
1461 (region->sy << 16) | region->sx);
1462 NV_WR32(&par->riva.Blt->TopLeftDst, 0,
1463 (region->dy << 16) | region->dx);
1464 mb();
1465 NV_WR32(&par->riva.Blt->WidthHeight, 0,
1466 (region->height << 16) | region->width);
1467 mb();
1468 }
1469
1470 static inline void convert_bgcolor_16(u32 *col)
1471 {
1472 *col = ((*col & 0x0000F800) << 8)
1473 | ((*col & 0x00007E0) << 5)
1474 | ((*col & 0x0000001F) << 3)
1475 | 0xFF000000;
1476 mb();
1477 }
1478
1479 /**
1480 * rivafb_imageblit: hardware accelerated color expand function
1481 * @info: pointer to fb_info structure
1482 * @image: pointer to fb_image structure
1483 *
1484 * DESCRIPTION:
1485 * If the source is a monochrome bitmap, the function fills up a a region
1486 * of framebuffer memory with pixels whose color is determined by the bit
1487 * setting of the bitmap, 1 - foreground, 0 - background.
1488 *
1489 * If the source is not a monochrome bitmap, color expansion is not done.
1490 * In this case, it is channeled to a software function.
1491 *
1492 * CALLED FROM:
1493 * framebuffer hook
1494 */
1495 static void rivafb_imageblit(struct fb_info *info,
1496 const struct fb_image *image)
1497 {
1498 struct riva_par *par = (struct riva_par *) info->par;
1499 u32 fgx = 0, bgx = 0, width, tmp;
1500 u8 *cdat = (u8 *) image->data;
1501 volatile u32 __iomem *d;
1502 int i, size;
1503
1504 if ((info->flags & FBINFO_HWACCEL_DISABLED) || image->depth != 1) {
1505 cfb_imageblit(info, image);
1506 return;
1507 }
1508
1509 switch (info->var.bits_per_pixel) {
1510 case 8:
1511 fgx = image->fg_color;
1512 bgx = image->bg_color;
1513 break;
1514 case 16:
1515 case 32:
1516 if (par->riva.Architecture != NV_ARCH_03) {
1517 fgx = ((u32 *)info->pseudo_palette)[image->fg_color];
1518 bgx = ((u32 *)info->pseudo_palette)[image->bg_color];
1519 } else {
1520 fgx = par->palette[image->fg_color];
1521 bgx = par->palette[image->bg_color];
1522 }
1523 if (info->var.green.length == 6)
1524 convert_bgcolor_16(&bgx);
1525 break;
1526 }
1527
1528 RIVA_FIFO_FREE(par->riva, Bitmap, 7);
1529 NV_WR32(&par->riva.Bitmap->ClipE.TopLeft, 0,
1530 (image->dy << 16) | (image->dx & 0xFFFF));
1531 NV_WR32(&par->riva.Bitmap->ClipE.BottomRight, 0,
1532 (((image->dy + image->height) << 16) |
1533 ((image->dx + image->width) & 0xffff)));
1534 NV_WR32(&par->riva.Bitmap->Color0E, 0, bgx);
1535 NV_WR32(&par->riva.Bitmap->Color1E, 0, fgx);
1536 NV_WR32(&par->riva.Bitmap->WidthHeightInE, 0,
1537 (image->height << 16) | ((image->width + 31) & ~31));
1538 NV_WR32(&par->riva.Bitmap->WidthHeightOutE, 0,
1539 (image->height << 16) | ((image->width + 31) & ~31));
1540 NV_WR32(&par->riva.Bitmap->PointE, 0,
1541 (image->dy << 16) | (image->dx & 0xFFFF));
1542
1543 d = &par->riva.Bitmap->MonochromeData01E;
1544
1545 width = (image->width + 31)/32;
1546 size = width * image->height;
1547 while (size >= 16) {
1548 RIVA_FIFO_FREE(par->riva, Bitmap, 16);
1549 for (i = 0; i < 16; i++) {
1550 tmp = *((u32 *)cdat);
1551 cdat = (u8 *)((u32 *)cdat + 1);
1552 reverse_order(&tmp);
1553 NV_WR32(d, i*4, tmp);
1554 }
1555 size -= 16;
1556 }
1557 if (size) {
1558 RIVA_FIFO_FREE(par->riva, Bitmap, size);
1559 for (i = 0; i < size; i++) {
1560 tmp = *((u32 *) cdat);
1561 cdat = (u8 *)((u32 *)cdat + 1);
1562 reverse_order(&tmp);
1563 NV_WR32(d, i*4, tmp);
1564 }
1565 }
1566 }
1567
1568 /**
1569 * rivafb_cursor - hardware cursor function
1570 * @info: pointer to info structure
1571 * @cursor: pointer to fbcursor structure
1572 *
1573 * DESCRIPTION:
1574 * A cursor function that supports displaying a cursor image via hardware.
1575 * Within the kernel, copy and invert rops are supported. If exported
1576 * to user space, only the copy rop will be supported.
1577 *
1578 * CALLED FROM
1579 * framebuffer hook
1580 */
1581 static int rivafb_cursor(struct fb_info *info, struct fb_cursor *cursor)
1582 {
1583 struct riva_par *par = (struct riva_par *) info->par;
1584 u8 data[MAX_CURS * MAX_CURS/8];
1585 u16 fg, bg;
1586 int i, set = cursor->set;
1587
1588 if (cursor->image.width > MAX_CURS ||
1589 cursor->image.height > MAX_CURS)
1590 return soft_cursor(info, cursor);
1591
1592 par->riva.ShowHideCursor(&par->riva, 0);
1593
1594 if (par->cursor_reset) {
1595 set = FB_CUR_SETALL;
1596 par->cursor_reset = 0;
1597 }
1598
1599 if (set & FB_CUR_SETSIZE)
1600 memset_io(par->riva.CURSOR, 0, MAX_CURS * MAX_CURS * 2);
1601
1602 if (set & FB_CUR_SETPOS) {
1603 u32 xx, yy, temp;
1604
1605 yy = cursor->image.dy - info->var.yoffset;
1606 xx = cursor->image.dx - info->var.xoffset;
1607 temp = xx & 0xFFFF;
1608 temp |= yy << 16;
1609
1610 NV_WR32(par->riva.PRAMDAC, 0x0000300, temp);
1611 }
1612
1613
1614 if (set & (FB_CUR_SETSHAPE | FB_CUR_SETCMAP | FB_CUR_SETIMAGE)) {
1615 u32 bg_idx = cursor->image.bg_color;
1616 u32 fg_idx = cursor->image.fg_color;
1617 u32 s_pitch = (cursor->image.width+7) >> 3;
1618 u32 d_pitch = MAX_CURS/8;
1619 u8 *dat = (u8 *) cursor->image.data;
1620 u8 *msk = (u8 *) cursor->mask;
1621 u8 *src;
1622
1623 src = kmalloc(s_pitch * cursor->image.height, GFP_ATOMIC);
1624
1625 if (src) {
1626 switch (cursor->rop) {
1627 case ROP_XOR:
1628 for (i = 0; i < s_pitch * cursor->image.height;
1629 i++)
1630 src[i] = dat[i] ^ msk[i];
1631 break;
1632 case ROP_COPY:
1633 default:
1634 for (i = 0; i < s_pitch * cursor->image.height;
1635 i++)
1636 src[i] = dat[i] & msk[i];
1637 break;
1638 }
1639
1640 fb_sysmove_buf_aligned(info, &info->pixmap, data,
1641 d_pitch, src, s_pitch,
1642 cursor->image.height);
1643
1644 bg = ((info->cmap.red[bg_idx] & 0xf8) << 7) |
1645 ((info->cmap.green[bg_idx] & 0xf8) << 2) |
1646 ((info->cmap.blue[bg_idx] & 0xf8) >> 3) |
1647 1 << 15;
1648
1649 fg = ((info->cmap.red[fg_idx] & 0xf8) << 7) |
1650 ((info->cmap.green[fg_idx] & 0xf8) << 2) |
1651 ((info->cmap.blue[fg_idx] & 0xf8) >> 3) |
1652 1 << 15;
1653
1654 par->riva.LockUnlock(&par->riva, 0);
1655
1656 rivafb_load_cursor_image(par, data, bg, fg,
1657 cursor->image.width,
1658 cursor->image.height);
1659 kfree(src);
1660 }
1661 }
1662
1663 if (cursor->enable)
1664 par->riva.ShowHideCursor(&par->riva, 1);
1665
1666 return 0;
1667 }
1668
1669 static int rivafb_sync(struct fb_info *info)
1670 {
1671 struct riva_par *par = (struct riva_par *)info->par;
1672
1673 wait_for_idle(par);
1674 return 0;
1675 }
1676
1677 /* ------------------------------------------------------------------------- *
1678 *
1679 * initialization helper functions
1680 *
1681 * ------------------------------------------------------------------------- */
1682
1683 /* kernel interface */
1684 static struct fb_ops riva_fb_ops = {
1685 .owner = THIS_MODULE,
1686 .fb_open = rivafb_open,
1687 .fb_release = rivafb_release,
1688 .fb_check_var = rivafb_check_var,
1689 .fb_set_par = rivafb_set_par,
1690 .fb_setcolreg = rivafb_setcolreg,
1691 .fb_pan_display = rivafb_pan_display,
1692 .fb_blank = rivafb_blank,
1693 .fb_fillrect = rivafb_fillrect,
1694 .fb_copyarea = rivafb_copyarea,
1695 .fb_imageblit = rivafb_imageblit,
1696 .fb_cursor = rivafb_cursor,
1697 .fb_sync = rivafb_sync,
1698 };
1699
1700 static int __devinit riva_set_fbinfo(struct fb_info *info)
1701 {
1702 unsigned int cmap_len;
1703 struct riva_par *par = (struct riva_par *) info->par;
1704
1705 NVTRACE_ENTER();
1706 info->flags = FBINFO_DEFAULT
1707 | FBINFO_HWACCEL_XPAN
1708 | FBINFO_HWACCEL_YPAN
1709 | FBINFO_HWACCEL_COPYAREA
1710 | FBINFO_HWACCEL_FILLRECT
1711 | FBINFO_HWACCEL_IMAGEBLIT;
1712
1713 /* Accel seems to not work properly on NV30 yet...*/
1714 if ((par->riva.Architecture == NV_ARCH_30) || noaccel) {
1715 printk(KERN_DEBUG PFX "disabling acceleration\n");
1716 info->flags |= FBINFO_HWACCEL_DISABLED;
1717 }
1718
1719 info->var = rivafb_default_var;
1720 info->fix.visual = (info->var.bits_per_pixel == 8) ?
1721 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
1722
1723 info->pseudo_palette = par->pseudo_palette;
1724
1725 cmap_len = riva_get_cmap_len(&info->var);
1726 fb_alloc_cmap(&info->cmap, cmap_len, 0);
1727
1728 info->pixmap.size = 8 * 1024;
1729 info->pixmap.buf_align = 4;
1730 info->pixmap.flags = FB_PIXMAP_SYSTEM;
1731 info->var.yres_virtual = -1;
1732 NVTRACE_LEAVE();
1733 return (rivafb_check_var(&info->var, info));
1734 }
1735
1736 #ifdef CONFIG_PPC_OF
1737 static int __devinit riva_get_EDID_OF(struct fb_info *info, struct pci_dev *pd)
1738 {
1739 struct riva_par *par = (struct riva_par *) info->par;
1740 struct device_node *dp;
1741 unsigned char *pedid = NULL;
1742 unsigned char *disptype = NULL;
1743 static char *propnames[] = {
1744 "DFP,EDID", "LCD,EDID", "EDID", "EDID1", "EDID,B", "EDID,A", NULL };
1745 int i;
1746
1747 NVTRACE_ENTER();
1748 dp = pci_device_to_OF_node(pd);
1749 for (; dp != NULL; dp = dp->child) {
1750 disptype = (unsigned char *)get_property(dp, "display-type", NULL);
1751 if (disptype == NULL)
1752 continue;
1753 if (strncmp(disptype, "LCD", 3) != 0)
1754 continue;
1755 for (i = 0; propnames[i] != NULL; ++i) {
1756 pedid = (unsigned char *)
1757 get_property(dp, propnames[i], NULL);
1758 if (pedid != NULL) {
1759 par->EDID = pedid;
1760 NVTRACE("LCD found.\n");
1761 return 1;
1762 }
1763 }
1764 }
1765 NVTRACE_LEAVE();
1766 return 0;
1767 }
1768 #endif /* CONFIG_PPC_OF */
1769
1770 #if defined(CONFIG_FB_RIVA_I2C) && !defined(CONFIG_PPC_OF)
1771 static int __devinit riva_get_EDID_i2c(struct fb_info *info)
1772 {
1773 struct riva_par *par = (struct riva_par *) info->par;
1774 struct fb_var_screeninfo var;
1775 int i;
1776
1777 NVTRACE_ENTER();
1778 riva_create_i2c_busses(par);
1779 for (i = 0; i < par->bus; i++) {
1780 riva_probe_i2c_connector(par, i+1, &par->EDID);
1781 if (par->EDID && !fb_parse_edid(par->EDID, &var)) {
1782 printk(PFX "Found EDID Block from BUS %i\n", i);
1783 break;
1784 }
1785 }
1786
1787 NVTRACE_LEAVE();
1788 return (par->EDID) ? 1 : 0;
1789 }
1790 #endif /* CONFIG_FB_RIVA_I2C */
1791
1792 static void __devinit riva_update_default_var(struct fb_var_screeninfo *var,
1793 struct fb_info *info)
1794 {
1795 struct fb_monspecs *specs = &info->monspecs;
1796 struct fb_videomode modedb;
1797
1798 NVTRACE_ENTER();
1799 /* respect mode options */
1800 if (mode_option) {
1801 fb_find_mode(var, info, mode_option,
1802 specs->modedb, specs->modedb_len,
1803 NULL, 8);
1804 } else if (specs->modedb != NULL) {
1805 /* get preferred timing */
1806 if (info->monspecs.misc & FB_MISC_1ST_DETAIL) {
1807 int i;
1808
1809 for (i = 0; i < specs->modedb_len; i++) {
1810 if (specs->modedb[i].flag & FB_MODE_IS_FIRST) {
1811 modedb = specs->modedb[i];
1812 break;
1813 }
1814 }
1815 } else {
1816 /* otherwise, get first mode in database */
1817 modedb = specs->modedb[0];
1818 }
1819 var->bits_per_pixel = 8;
1820 riva_update_var(var, &modedb);
1821 }
1822 NVTRACE_LEAVE();
1823 }
1824
1825
1826 static void __devinit riva_get_EDID(struct fb_info *info, struct pci_dev *pdev)
1827 {
1828 NVTRACE_ENTER();
1829 #ifdef CONFIG_PPC_OF
1830 if (!riva_get_EDID_OF(info, pdev))
1831 printk(PFX "could not retrieve EDID from OF\n");
1832 #elif CONFIG_FB_RIVA_I2C
1833 if (!riva_get_EDID_i2c(info))
1834 printk(PFX "could not retrieve EDID from DDC/I2C\n");
1835 #endif
1836 NVTRACE_LEAVE();
1837 }
1838
1839
1840 static void __devinit riva_get_edidinfo(struct fb_info *info)
1841 {
1842 struct fb_var_screeninfo *var = &rivafb_default_var;
1843 struct riva_par *par = (struct riva_par *) info->par;
1844
1845 fb_edid_to_monspecs(par->EDID, &info->monspecs);
1846 fb_videomode_to_modelist(info->monspecs.modedb, info->monspecs.modedb_len,
1847 &info->modelist);
1848 riva_update_default_var(var, info);
1849
1850 /* if user specified flatpanel, we respect that */
1851 if (info->monspecs.input & FB_DISP_DDI)
1852 par->FlatPanel = 1;
1853 }
1854
1855 /* ------------------------------------------------------------------------- *
1856 *
1857 * PCI bus
1858 *
1859 * ------------------------------------------------------------------------- */
1860
1861 static u32 __devinit riva_get_arch(struct pci_dev *pd)
1862 {
1863 u32 arch = 0;
1864
1865 switch (pd->device & 0x0ff0) {
1866 case 0x0100: /* GeForce 256 */
1867 case 0x0110: /* GeForce2 MX */
1868 case 0x0150: /* GeForce2 */
1869 case 0x0170: /* GeForce4 MX */
1870 case 0x0180: /* GeForce4 MX (8x AGP) */
1871 case 0x01A0: /* nForce */
1872 case 0x01F0: /* nForce2 */
1873 arch = NV_ARCH_10;
1874 break;
1875 case 0x0200: /* GeForce3 */
1876 case 0x0250: /* GeForce4 Ti */
1877 case 0x0280: /* GeForce4 Ti (8x AGP) */
1878 arch = NV_ARCH_20;
1879 break;
1880 case 0x0300: /* GeForceFX 5800 */
1881 case 0x0310: /* GeForceFX 5600 */
1882 case 0x0320: /* GeForceFX 5200 */
1883 case 0x0330: /* GeForceFX 5900 */
1884 case 0x0340: /* GeForceFX 5700 */
1885 arch = NV_ARCH_30;
1886 break;
1887 case 0x0020: /* TNT, TNT2 */
1888 arch = NV_ARCH_04;
1889 break;
1890 case 0x0010: /* Riva128 */
1891 arch = NV_ARCH_03;
1892 break;
1893 default: /* unknown architecture */
1894 break;
1895 }
1896 return arch;
1897 }
1898
1899 static int __devinit rivafb_probe(struct pci_dev *pd,
1900 const struct pci_device_id *ent)
1901 {
1902 struct riva_par *default_par;
1903 struct fb_info *info;
1904 int ret;
1905
1906 NVTRACE_ENTER();
1907 assert(pd != NULL);
1908
1909 info = framebuffer_alloc(sizeof(struct riva_par), &pd->dev);
1910 if (!info) {
1911 printk (KERN_ERR PFX "could not allocate memory\n");
1912 ret = -ENOMEM;
1913 goto err_ret;
1914 }
1915 default_par = (struct riva_par *) info->par;
1916 default_par->pdev = pd;
1917
1918 info->pixmap.addr = kmalloc(8 * 1024, GFP_KERNEL);
1919 if (info->pixmap.addr == NULL) {
1920 ret = -ENOMEM;
1921 goto err_framebuffer_release;
1922 }
1923 memset(info->pixmap.addr, 0, 8 * 1024);
1924
1925 ret = pci_enable_device(pd);
1926 if (ret < 0) {
1927 printk(KERN_ERR PFX "cannot enable PCI device\n");
1928 goto err_free_pixmap;
1929 }
1930
1931 ret = pci_request_regions(pd, "rivafb");
1932 if (ret < 0) {
1933 printk(KERN_ERR PFX "cannot request PCI regions\n");
1934 goto err_disable_device;
1935 }
1936
1937 default_par->riva.Architecture = riva_get_arch(pd);
1938
1939 default_par->Chipset = (pd->vendor << 16) | pd->device;
1940 printk(KERN_INFO PFX "nVidia device/chipset %X\n",default_par->Chipset);
1941
1942 #ifdef CONFIG_PCI_NAMES
1943 printk(KERN_INFO PFX "%s\n", pd->pretty_name);
1944 #endif
1945
1946 if(default_par->riva.Architecture == 0) {
1947 printk(KERN_ERR PFX "unknown NV_ARCH\n");
1948 ret=-ENODEV;
1949 goto err_release_region;
1950 }
1951 if(default_par->riva.Architecture == NV_ARCH_10 ||
1952 default_par->riva.Architecture == NV_ARCH_20 ||
1953 default_par->riva.Architecture == NV_ARCH_30) {
1954 sprintf(rivafb_fix.id, "NV%x", (pd->device & 0x0ff0) >> 4);
1955 } else {
1956 sprintf(rivafb_fix.id, "NV%x", default_par->riva.Architecture);
1957 }
1958
1959 default_par->FlatPanel = flatpanel;
1960 if (flatpanel == 1)
1961 printk(KERN_INFO PFX "flatpanel support enabled\n");
1962 default_par->forceCRTC = forceCRTC;
1963
1964 rivafb_fix.mmio_len = pci_resource_len(pd, 0);
1965 rivafb_fix.smem_len = pci_resource_len(pd, 1);
1966
1967 {
1968 /* enable IO and mem if not already done */
1969 unsigned short cmd;
1970
1971 pci_read_config_word(pd, PCI_COMMAND, &cmd);
1972 cmd |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
1973 pci_write_config_word(pd, PCI_COMMAND, cmd);
1974 }
1975
1976 rivafb_fix.mmio_start = pci_resource_start(pd, 0);
1977 rivafb_fix.smem_start = pci_resource_start(pd, 1);
1978
1979 default_par->ctrl_base = ioremap(rivafb_fix.mmio_start,
1980 rivafb_fix.mmio_len);
1981 if (!default_par->ctrl_base) {
1982 printk(KERN_ERR PFX "cannot ioremap MMIO base\n");
1983 ret = -EIO;
1984 goto err_release_region;
1985 }
1986
1987 switch (default_par->riva.Architecture) {
1988 case NV_ARCH_03:
1989 /* Riva128's PRAMIN is in the "framebuffer" space
1990 * Since these cards were never made with more than 8 megabytes
1991 * we can safely allocate this separately.
1992 */
1993 default_par->riva.PRAMIN = ioremap(rivafb_fix.smem_start + 0x00C00000, 0x00008000);
1994 if (!default_par->riva.PRAMIN) {
1995 printk(KERN_ERR PFX "cannot ioremap PRAMIN region\n");
1996 ret = -EIO;
1997 goto err_iounmap_ctrl_base;
1998 }
1999 break;
2000 case NV_ARCH_04:
2001 case NV_ARCH_10:
2002 case NV_ARCH_20:
2003 case NV_ARCH_30:
2004 default_par->riva.PCRTC0 =
2005 (u32 __iomem *)(default_par->ctrl_base + 0x00600000);
2006 default_par->riva.PRAMIN =
2007 (u32 __iomem *)(default_par->ctrl_base + 0x00710000);
2008 break;
2009 }
2010 riva_common_setup(default_par);
2011
2012 if (default_par->riva.Architecture == NV_ARCH_03) {
2013 default_par->riva.PCRTC = default_par->riva.PCRTC0
2014 = default_par->riva.PGRAPH;
2015 }
2016
2017 rivafb_fix.smem_len = riva_get_memlen(default_par) * 1024;
2018 default_par->dclk_max = riva_get_maxdclk(default_par) * 1000;
2019 info->screen_base = ioremap(rivafb_fix.smem_start,
2020 rivafb_fix.smem_len);
2021 if (!info->screen_base) {
2022 printk(KERN_ERR PFX "cannot ioremap FB base\n");
2023 ret = -EIO;
2024 goto err_iounmap_pramin;
2025 }
2026
2027 #ifdef CONFIG_MTRR
2028 if (!nomtrr) {
2029 default_par->mtrr.vram = mtrr_add(rivafb_fix.smem_start,
2030 rivafb_fix.smem_len,
2031 MTRR_TYPE_WRCOMB, 1);
2032 if (default_par->mtrr.vram < 0) {
2033 printk(KERN_ERR PFX "unable to setup MTRR\n");
2034 } else {
2035 default_par->mtrr.vram_valid = 1;
2036 /* let there be speed */
2037 printk(KERN_INFO PFX "RIVA MTRR set to ON\n");
2038 }
2039 }
2040 #endif /* CONFIG_MTRR */
2041
2042 info->fbops = &riva_fb_ops;
2043 info->fix = rivafb_fix;
2044 riva_get_EDID(info, pd);
2045 riva_get_edidinfo(info);
2046
2047 ret=riva_set_fbinfo(info);
2048 if (ret < 0) {
2049 printk(KERN_ERR PFX "error setting initial video mode\n");
2050 goto err_iounmap_screen_base;
2051 }
2052
2053 fb_destroy_modedb(info->monspecs.modedb);
2054 info->monspecs.modedb = NULL;
2055 ret = register_framebuffer(info);
2056 if (ret < 0) {
2057 printk(KERN_ERR PFX
2058 "error registering riva framebuffer\n");
2059 goto err_iounmap_screen_base;
2060 }
2061
2062 pci_set_drvdata(pd, info);
2063
2064 printk(KERN_INFO PFX
2065 "PCI nVidia %s framebuffer ver %s (%dMB @ 0x%lX)\n",
2066 info->fix.id,
2067 RIVAFB_VERSION,
2068 info->fix.smem_len / (1024 * 1024),
2069 info->fix.smem_start);
2070 #ifdef CONFIG_PMAC_BACKLIGHT
2071 if (default_par->FlatPanel && _machine == _MACH_Pmac)
2072 register_backlight_controller(&riva_backlight_controller,
2073 default_par, "mnca");
2074 #endif
2075 NVTRACE_LEAVE();
2076 return 0;
2077
2078 err_iounmap_screen_base:
2079 #ifdef CONFIG_FB_RIVA_I2C
2080 riva_delete_i2c_busses((struct riva_par *) info->par);
2081 #endif
2082 iounmap(info->screen_base);
2083 err_iounmap_pramin:
2084 if (default_par->riva.Architecture == NV_ARCH_03)
2085 iounmap(default_par->riva.PRAMIN);
2086 err_iounmap_ctrl_base:
2087 iounmap(default_par->ctrl_base);
2088 err_release_region:
2089 pci_release_regions(pd);
2090 err_disable_device:
2091 pci_disable_device(pd);
2092 err_free_pixmap:
2093 kfree(info->pixmap.addr);
2094 err_framebuffer_release:
2095 framebuffer_release(info);
2096 err_ret:
2097 return ret;
2098 }
2099
2100 static void __exit rivafb_remove(struct pci_dev *pd)
2101 {
2102 struct fb_info *info = pci_get_drvdata(pd);
2103 struct riva_par *par = (struct riva_par *) info->par;
2104
2105 NVTRACE_ENTER();
2106 if (!info)
2107 return;
2108
2109 #ifdef CONFIG_FB_RIVA_I2C
2110 riva_delete_i2c_busses(par);
2111 kfree(par->EDID);
2112 #endif
2113
2114 unregister_framebuffer(info);
2115 #ifdef CONFIG_MTRR
2116 if (par->mtrr.vram_valid)
2117 mtrr_del(par->mtrr.vram, info->fix.smem_start,
2118 info->fix.smem_len);
2119 #endif /* CONFIG_MTRR */
2120
2121 iounmap(par->ctrl_base);
2122 iounmap(info->screen_base);
2123 if (par->riva.Architecture == NV_ARCH_03)
2124 iounmap(par->riva.PRAMIN);
2125 pci_release_regions(pd);
2126 pci_disable_device(pd);
2127 kfree(info->pixmap.addr);
2128 framebuffer_release(info);
2129 pci_set_drvdata(pd, NULL);
2130 NVTRACE_LEAVE();
2131 }
2132
2133 /* ------------------------------------------------------------------------- *
2134 *
2135 * initialization
2136 *
2137 * ------------------------------------------------------------------------- */
2138
2139 #ifndef MODULE
2140 static int __init rivafb_setup(char *options)
2141 {
2142 char *this_opt;
2143
2144 NVTRACE_ENTER();
2145 if (!options || !*options)
2146 return 0;
2147
2148 while ((this_opt = strsep(&options, ",")) != NULL) {
2149 if (!strncmp(this_opt, "forceCRTC", 9)) {
2150 char *p;
2151
2152 p = this_opt + 9;
2153 if (!*p || !*(++p)) continue;
2154 forceCRTC = *p - '0';
2155 if (forceCRTC < 0 || forceCRTC > 1)
2156 forceCRTC = -1;
2157 } else if (!strncmp(this_opt, "flatpanel", 9)) {
2158 flatpanel = 1;
2159 #ifdef CONFIG_MTRR
2160 } else if (!strncmp(this_opt, "nomtrr", 6)) {
2161 nomtrr = 1;
2162 #endif
2163 } else if (!strncmp(this_opt, "strictmode", 10)) {
2164 strictmode = 1;
2165 } else if (!strncmp(this_opt, "noaccel", 7)) {
2166 noaccel = 1;
2167 } else
2168 mode_option = this_opt;
2169 }
2170 NVTRACE_LEAVE();
2171 return 0;
2172 }
2173 #endif /* !MODULE */
2174
2175 static struct pci_driver rivafb_driver = {
2176 .name = "rivafb",
2177 .id_table = rivafb_pci_tbl,
2178 .probe = rivafb_probe,
2179 .remove = __exit_p(rivafb_remove),
2180 };
2181
2182
2183
2184 /* ------------------------------------------------------------------------- *
2185 *
2186 * modularization
2187 *
2188 * ------------------------------------------------------------------------- */
2189
2190 static int __devinit rivafb_init(void)
2191 {
2192 #ifndef MODULE
2193 char *option = NULL;
2194
2195 if (fb_get_options("rivafb", &option))
2196 return -ENODEV;
2197 rivafb_setup(option);
2198 #endif
2199 return pci_register_driver(&rivafb_driver);
2200 }
2201
2202
2203 module_init(rivafb_init);
2204
2205 #ifdef MODULE
2206 static void __exit rivafb_exit(void)
2207 {
2208 pci_unregister_driver(&rivafb_driver);
2209 }
2210
2211 module_exit(rivafb_exit);
2212 #endif /* MODULE */
2213
2214 module_param(noaccel, bool, 0);
2215 MODULE_PARM_DESC(noaccel, "bool: disable acceleration");
2216 module_param(flatpanel, int, 0);
2217 MODULE_PARM_DESC(flatpanel, "Enables experimental flat panel support for some chipsets. (0 or 1=enabled) (default=0)");
2218 module_param(forceCRTC, int, 0);
2219 MODULE_PARM_DESC(forceCRTC, "Forces usage of a particular CRTC in case autodetection fails. (0 or 1) (default=autodetect)");
2220 #ifdef CONFIG_MTRR
2221 module_param(nomtrr, bool, 0);
2222 MODULE_PARM_DESC(nomtrr, "Disables MTRR support (0 or 1=disabled) (default=0)");
2223 #endif
2224 module_param(strictmode, bool, 0);
2225 MODULE_PARM_DESC(strictmode, "Only use video modes from EDID");
2226
2227 MODULE_AUTHOR("Ani Joshi, maintainer");
2228 MODULE_DESCRIPTION("Framebuffer driver for nVidia Riva 128, TNT, TNT2, and the GeForce series");
2229 MODULE_LICENSE("GPL");
Verdex Pro support