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[TG3]: Set minimal hw interrupt mitigation.
[linux-2.6/verdex.git] / sound / oss / esssolo1.c
blob6b3b9a99579dbf8fb05490e889a05d8dbcf4a3c3
1 /****************************************************************************/
2
3 /*
4 * esssolo1.c -- ESS Technology Solo1 (ES1946) audio driver.
5 *
6 * Copyright (C) 1998-2001, 2003 Thomas Sailer (t.sailer@alumni.ethz.ch)
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 *
22 * Module command line parameters:
23 * none so far
24 *
25 * Supported devices:
26 * /dev/dsp standard /dev/dsp device, (mostly) OSS compatible
27 * /dev/mixer standard /dev/mixer device, (mostly) OSS compatible
28 * /dev/midi simple MIDI UART interface, no ioctl
29 *
30 * Revision history
31 * 10.11.1998 0.1 Initial release (without any hardware)
32 * 22.03.1999 0.2 cinfo.blocks should be reset after GETxPTR ioctl.
33 * reported by Johan Maes <joma@telindus.be>
34 * return EAGAIN instead of EBUSY when O_NONBLOCK
35 * read/write cannot be executed
36 * 07.04.1999 0.3 implemented the following ioctl's: SOUND_PCM_READ_RATE,
37 * SOUND_PCM_READ_CHANNELS, SOUND_PCM_READ_BITS;
38 * Alpha fixes reported by Peter Jones <pjones@redhat.com>
39 * 15.06.1999 0.4 Fix bad allocation bug.
40 * Thanks to Deti Fliegl <fliegl@in.tum.de>
41 * 28.06.1999 0.5 Add pci_set_master
42 * 12.08.1999 0.6 Fix MIDI UART crashing the driver
43 * Changed mixer semantics from OSS documented
44 * behaviour to OSS "code behaviour".
45 * Recording might actually work now.
46 * The real DDMA controller address register is at PCI config
47 * 0x60, while the register at 0x18 is used as a placeholder
48 * register for BIOS address allocation. This register
49 * is supposed to be copied into 0x60, according
50 * to the Solo1 datasheet. When I do that, I can access
51 * the DDMA registers except the mask bit, which
52 * is stuck at 1. When I copy the contents of 0x18 +0x10
53 * to the DDMA base register, everything seems to work.
54 * The fun part is that the Windows Solo1 driver doesn't
55 * seem to do these tricks.
56 * Bugs remaining: plops and clicks when starting/stopping playback
57 * 31.08.1999 0.7 add spin_lock_init
58 * replaced current->state = x with set_current_state(x)
59 * 03.09.1999 0.8 change read semantics for MIDI to match
60 * OSS more closely; remove possible wakeup race
61 * 07.10.1999 0.9 Fix initialization; complain if sequencer writes time out
62 * Revised resource grabbing for the FM synthesizer
63 * 28.10.1999 0.10 More waitqueue races fixed
64 * 09.12.1999 0.11 Work around stupid Alpha port issue (virt_to_bus(kmalloc(GFP_DMA)) > 16M)
65 * Disabling recording on Alpha
66 * 12.01.2000 0.12 Prevent some ioctl's from returning bad count values on underrun/overrun;
67 * Tim Janik's BSE (Bedevilled Sound Engine) found this
68 * Integrated (aka redid 8-)) APM support patch by Zach Brown
69 * 07.02.2000 0.13 Use pci_alloc_consistent and pci_register_driver
70 * 19.02.2000 0.14 Use pci_dma_supported to determine if recording should be disabled
71 * 13.03.2000 0.15 Reintroduce initialization of a couple of PCI config space registers
72 * 21.11.2000 0.16 Initialize dma buffers in poll, otherwise poll may return a bogus mask
73 * 12.12.2000 0.17 More dma buffer initializations, patch from
74 * Tjeerd Mulder <tjeerd.mulder@fujitsu-siemens.com>
75 * 31.01.2001 0.18 Register/Unregister gameport, original patch from
76 * Nathaniel Daw <daw@cs.cmu.edu>
77 * Fix SETTRIGGER non OSS API conformity
78 * 10.03.2001 provide abs function, prevent picking up a bogus kernel macro
79 * for abs. Bug report by Andrew Morton <andrewm@uow.edu.au>
80 * 15.05.2001 pci_enable_device moved, return values in probe cleaned
81 * up. Marcus Meissner <mm@caldera.de>
82 * 22.05.2001 0.19 more cleanups, changed PM to PCI 2.4 style, got rid
83 * of global list of devices, using pci device data.
84 * Marcus Meissner <mm@caldera.de>
85 * 03.01.2003 0.20 open_mode fixes from Georg Acher <acher@in.tum.de>
86 */
87
88 /*****************************************************************************/
89
90 #include <linux/interrupt.h>
91 #include <linux/module.h>
92 #include <linux/string.h>
93 #include <linux/ioport.h>
94 #include <linux/sched.h>
95 #include <linux/delay.h>
96 #include <linux/sound.h>
97 #include <linux/slab.h>
98 #include <linux/soundcard.h>
99 #include <linux/pci.h>
100 #include <linux/bitops.h>
101 #include <linux/init.h>
102 #include <linux/poll.h>
103 #include <linux/spinlock.h>
104 #include <linux/smp_lock.h>
105 #include <linux/gameport.h>
106 #include <linux/wait.h>
107
108 #include <asm/io.h>
109 #include <asm/page.h>
110 #include <asm/uaccess.h>
111
112 #include "dm.h"
113
114 /* --------------------------------------------------------------------- */
115
116 #undef OSS_DOCUMENTED_MIXER_SEMANTICS
117
118 /* --------------------------------------------------------------------- */
119
120 #ifndef PCI_VENDOR_ID_ESS
121 #define PCI_VENDOR_ID_ESS 0x125d
122 #endif
123 #ifndef PCI_DEVICE_ID_ESS_SOLO1
124 #define PCI_DEVICE_ID_ESS_SOLO1 0x1969
125 #endif
126
127 #define SOLO1_MAGIC ((PCI_VENDOR_ID_ESS<<16)|PCI_DEVICE_ID_ESS_SOLO1)
128
129 #define DDMABASE_OFFSET 0 /* chip bug workaround kludge */
130 #define DDMABASE_EXTENT 16
131
132 #define IOBASE_EXTENT 16
133 #define SBBASE_EXTENT 16
134 #define VCBASE_EXTENT (DDMABASE_EXTENT+DDMABASE_OFFSET)
135 #define MPUBASE_EXTENT 4
136 #define GPBASE_EXTENT 4
137 #define GAMEPORT_EXTENT 4
138
139 #define FMSYNTH_EXTENT 4
140
141 /* MIDI buffer sizes */
142
143 #define MIDIINBUF 256
144 #define MIDIOUTBUF 256
145
146 #define FMODE_MIDI_SHIFT 3
147 #define FMODE_MIDI_READ (FMODE_READ << FMODE_MIDI_SHIFT)
148 #define FMODE_MIDI_WRITE (FMODE_WRITE << FMODE_MIDI_SHIFT)
149
150 #define FMODE_DMFM 0x10
151
152 static struct pci_driver solo1_driver;
153
154 /* --------------------------------------------------------------------- */
155
156 struct solo1_state {
157 /* magic */
158 unsigned int magic;
159
160 /* the corresponding pci_dev structure */
161 struct pci_dev *dev;
162
163 /* soundcore stuff */
164 int dev_audio;
165 int dev_mixer;
166 int dev_midi;
167 int dev_dmfm;
168
169 /* hardware resources */
170 unsigned long iobase, sbbase, vcbase, ddmabase, mpubase; /* long for SPARC */
171 unsigned int irq;
172
173 /* mixer registers */
174 struct {
175 unsigned short vol[10];
176 unsigned int recsrc;
177 unsigned int modcnt;
178 unsigned short micpreamp;
179 } mix;
180
181 /* wave stuff */
182 unsigned fmt;
183 unsigned channels;
184 unsigned rate;
185 unsigned char clkdiv;
186 unsigned ena;
187
188 spinlock_t lock;
189 struct semaphore open_sem;
190 mode_t open_mode;
191 wait_queue_head_t open_wait;
192
193 struct dmabuf {
194 void *rawbuf;
195 dma_addr_t dmaaddr;
196 unsigned buforder;
197 unsigned numfrag;
198 unsigned fragshift;
199 unsigned hwptr, swptr;
200 unsigned total_bytes;
201 int count;
202 unsigned error; /* over/underrun */
203 wait_queue_head_t wait;
204 /* redundant, but makes calculations easier */
205 unsigned fragsize;
206 unsigned dmasize;
207 unsigned fragsamples;
208 /* OSS stuff */
209 unsigned mapped:1;
210 unsigned ready:1;
211 unsigned endcleared:1;
212 unsigned enabled:1;
213 unsigned ossfragshift;
214 int ossmaxfrags;
215 unsigned subdivision;
216 } dma_dac, dma_adc;
217
218 /* midi stuff */
219 struct {
220 unsigned ird, iwr, icnt;
221 unsigned ord, owr, ocnt;
222 wait_queue_head_t iwait;
223 wait_queue_head_t owait;
224 struct timer_list timer;
225 unsigned char ibuf[MIDIINBUF];
226 unsigned char obuf[MIDIOUTBUF];
227 } midi;
228
229 struct gameport *gameport;
230 };
231
232 /* --------------------------------------------------------------------- */
233
234 static inline void write_seq(struct solo1_state *s, unsigned char data)
235 {
236 int i;
237 unsigned long flags;
238
239 /* the local_irq_save stunt is to send the data within the command window */
240 for (i = 0; i < 0xffff; i++) {
241 local_irq_save(flags);
242 if (!(inb(s->sbbase+0xc) & 0x80)) {
243 outb(data, s->sbbase+0xc);
244 local_irq_restore(flags);
245 return;
246 }
247 local_irq_restore(flags);
248 }
249 printk(KERN_ERR "esssolo1: write_seq timeout\n");
250 outb(data, s->sbbase+0xc);
251 }
252
253 static inline int read_seq(struct solo1_state *s, unsigned char *data)
254 {
255 int i;
256
257 if (!data)
258 return 0;
259 for (i = 0; i < 0xffff; i++)
260 if (inb(s->sbbase+0xe) & 0x80) {
261 *data = inb(s->sbbase+0xa);
262 return 1;
263 }
264 printk(KERN_ERR "esssolo1: read_seq timeout\n");
265 return 0;
266 }
267
268 static inline int reset_ctrl(struct solo1_state *s)
269 {
270 int i;
271
272 outb(3, s->sbbase+6); /* clear sequencer and FIFO */
273 udelay(10);
274 outb(0, s->sbbase+6);
275 for (i = 0; i < 0xffff; i++)
276 if (inb(s->sbbase+0xe) & 0x80)
277 if (inb(s->sbbase+0xa) == 0xaa) {
278 write_seq(s, 0xc6); /* enter enhanced mode */
279 return 1;
280 }
281 return 0;
282 }
283
284 static void write_ctrl(struct solo1_state *s, unsigned char reg, unsigned char data)
285 {
286 write_seq(s, reg);
287 write_seq(s, data);
288 }
289
290 #if 0 /* unused */
291 static unsigned char read_ctrl(struct solo1_state *s, unsigned char reg)
292 {
293 unsigned char r;
294
295 write_seq(s, 0xc0);
296 write_seq(s, reg);
297 read_seq(s, &r);
298 return r;
299 }
300 #endif /* unused */
301
302 static void write_mixer(struct solo1_state *s, unsigned char reg, unsigned char data)
303 {
304 outb(reg, s->sbbase+4);
305 outb(data, s->sbbase+5);
306 }
307
308 static unsigned char read_mixer(struct solo1_state *s, unsigned char reg)
309 {
310 outb(reg, s->sbbase+4);
311 return inb(s->sbbase+5);
312 }
313
314 /* --------------------------------------------------------------------- */
315
316 static inline unsigned ld2(unsigned int x)
317 {
318 unsigned r = 0;
319
320 if (x >= 0x10000) {
321 x >>= 16;
322 r += 16;
323 }
324 if (x >= 0x100) {
325 x >>= 8;
326 r += 8;
327 }
328 if (x >= 0x10) {
329 x >>= 4;
330 r += 4;
331 }
332 if (x >= 4) {
333 x >>= 2;
334 r += 2;
335 }
336 if (x >= 2)
337 r++;
338 return r;
339 }
340
341 /* --------------------------------------------------------------------- */
342
343 static inline void stop_dac(struct solo1_state *s)
344 {
345 unsigned long flags;
346
347 spin_lock_irqsave(&s->lock, flags);
348 s->ena &= ~FMODE_WRITE;
349 write_mixer(s, 0x78, 0x10);
350 spin_unlock_irqrestore(&s->lock, flags);
351 }
352
353 static void start_dac(struct solo1_state *s)
354 {
355 unsigned long flags;
356
357 spin_lock_irqsave(&s->lock, flags);
358 if (!(s->ena & FMODE_WRITE) && (s->dma_dac.mapped || s->dma_dac.count > 0) && s->dma_dac.ready) {
359 s->ena |= FMODE_WRITE;
360 write_mixer(s, 0x78, 0x12);
361 udelay(10);
362 write_mixer(s, 0x78, 0x13);
363 }
364 spin_unlock_irqrestore(&s->lock, flags);
365 }
366
367 static inline void stop_adc(struct solo1_state *s)
368 {
369 unsigned long flags;
370
371 spin_lock_irqsave(&s->lock, flags);
372 s->ena &= ~FMODE_READ;
373 write_ctrl(s, 0xb8, 0xe);
374 spin_unlock_irqrestore(&s->lock, flags);
375 }
376
377 static void start_adc(struct solo1_state *s)
378 {
379 unsigned long flags;
380
381 spin_lock_irqsave(&s->lock, flags);
382 if (!(s->ena & FMODE_READ) && (s->dma_adc.mapped || s->dma_adc.count < (signed)(s->dma_adc.dmasize - 2*s->dma_adc.fragsize))
383 && s->dma_adc.ready) {
384 s->ena |= FMODE_READ;
385 write_ctrl(s, 0xb8, 0xf);
386 #if 0
387 printk(KERN_DEBUG "solo1: DMAbuffer: 0x%08lx\n", (long)s->dma_adc.rawbuf);
388 printk(KERN_DEBUG "solo1: DMA: mask: 0x%02x cnt: 0x%04x addr: 0x%08x stat: 0x%02x\n",
389 inb(s->ddmabase+0xf), inw(s->ddmabase+4), inl(s->ddmabase), inb(s->ddmabase+8));
390 #endif
391 outb(0, s->ddmabase+0xd); /* master reset */
392 outb(1, s->ddmabase+0xf); /* mask */
393 outb(0x54/*0x14*/, s->ddmabase+0xb); /* DMA_MODE_READ | DMA_MODE_AUTOINIT */
394 outl(virt_to_bus(s->dma_adc.rawbuf), s->ddmabase);
395 outw(s->dma_adc.dmasize-1, s->ddmabase+4);
396 outb(0, s->ddmabase+0xf);
397 }
398 spin_unlock_irqrestore(&s->lock, flags);
399 #if 0
400 printk(KERN_DEBUG "solo1: start DMA: reg B8: 0x%02x SBstat: 0x%02x\n"
401 KERN_DEBUG "solo1: DMA: stat: 0x%02x cnt: 0x%04x mask: 0x%02x\n",
402 read_ctrl(s, 0xb8), inb(s->sbbase+0xc),
403 inb(s->ddmabase+8), inw(s->ddmabase+4), inb(s->ddmabase+0xf));
404 printk(KERN_DEBUG "solo1: A1: 0x%02x A2: 0x%02x A4: 0x%02x A5: 0x%02x A8: 0x%02x\n"
405 KERN_DEBUG "solo1: B1: 0x%02x B2: 0x%02x B4: 0x%02x B7: 0x%02x B8: 0x%02x B9: 0x%02x\n",
406 read_ctrl(s, 0xa1), read_ctrl(s, 0xa2), read_ctrl(s, 0xa4), read_ctrl(s, 0xa5), read_ctrl(s, 0xa8),
407 read_ctrl(s, 0xb1), read_ctrl(s, 0xb2), read_ctrl(s, 0xb4), read_ctrl(s, 0xb7), read_ctrl(s, 0xb8),
408 read_ctrl(s, 0xb9));
409 #endif
410 }
411
412 /* --------------------------------------------------------------------- */
413
414 #define DMABUF_DEFAULTORDER (15-PAGE_SHIFT)
415 #define DMABUF_MINORDER 1
416
417 static inline void dealloc_dmabuf(struct solo1_state *s, struct dmabuf *db)
418 {
419 struct page *page, *pend;
420
421 if (db->rawbuf) {
422 /* undo marking the pages as reserved */
423 pend = virt_to_page(db->rawbuf + (PAGE_SIZE << db->buforder) - 1);
424 for (page = virt_to_page(db->rawbuf); page <= pend; page++)
425 ClearPageReserved(page);
426 pci_free_consistent(s->dev, PAGE_SIZE << db->buforder, db->rawbuf, db->dmaaddr);
427 }
428 db->rawbuf = NULL;
429 db->mapped = db->ready = 0;
430 }
431
432 static int prog_dmabuf(struct solo1_state *s, struct dmabuf *db)
433 {
434 int order;
435 unsigned bytespersec;
436 unsigned bufs, sample_shift = 0;
437 struct page *page, *pend;
438
439 db->hwptr = db->swptr = db->total_bytes = db->count = db->error = db->endcleared = 0;
440 if (!db->rawbuf) {
441 db->ready = db->mapped = 0;
442 for (order = DMABUF_DEFAULTORDER; order >= DMABUF_MINORDER; order--)
443 if ((db->rawbuf = pci_alloc_consistent(s->dev, PAGE_SIZE << order, &db->dmaaddr)))
444 break;
445 if (!db->rawbuf)
446 return -ENOMEM;
447 db->buforder = order;
448 /* now mark the pages as reserved; otherwise remap_pfn_range doesn't do what we want */
449 pend = virt_to_page(db->rawbuf + (PAGE_SIZE << db->buforder) - 1);
450 for (page = virt_to_page(db->rawbuf); page <= pend; page++)
451 SetPageReserved(page);
452 }
453 if (s->fmt & (AFMT_S16_LE | AFMT_U16_LE))
454 sample_shift++;
455 if (s->channels > 1)
456 sample_shift++;
457 bytespersec = s->rate << sample_shift;
458 bufs = PAGE_SIZE << db->buforder;
459 if (db->ossfragshift) {
460 if ((1000 << db->ossfragshift) < bytespersec)
461 db->fragshift = ld2(bytespersec/1000);
462 else
463 db->fragshift = db->ossfragshift;
464 } else {
465 db->fragshift = ld2(bytespersec/100/(db->subdivision ? db->subdivision : 1));
466 if (db->fragshift < 3)
467 db->fragshift = 3;
468 }
469 db->numfrag = bufs >> db->fragshift;
470 while (db->numfrag < 4 && db->fragshift > 3) {
471 db->fragshift--;
472 db->numfrag = bufs >> db->fragshift;
473 }
474 db->fragsize = 1 << db->fragshift;
475 if (db->ossmaxfrags >= 4 && db->ossmaxfrags < db->numfrag)
476 db->numfrag = db->ossmaxfrags;
477 db->fragsamples = db->fragsize >> sample_shift;
478 db->dmasize = db->numfrag << db->fragshift;
479 db->enabled = 1;
480 return 0;
481 }
482
483 static inline int prog_dmabuf_adc(struct solo1_state *s)
484 {
485 unsigned long va;
486 int c;
487
488 stop_adc(s);
489 /* check if PCI implementation supports 24bit busmaster DMA */
490 if (s->dev->dma_mask > 0xffffff)
491 return -EIO;
492 if ((c = prog_dmabuf(s, &s->dma_adc)))
493 return c;
494 va = s->dma_adc.dmaaddr;
495 if ((va & ~((1<<24)-1)))
496 panic("solo1: buffer above 16M boundary");
497 outb(0, s->ddmabase+0xd); /* clear */
498 outb(1, s->ddmabase+0xf); /* mask */
499 /*outb(0, s->ddmabase+8);*/ /* enable (enable is active low!) */
500 outb(0x54, s->ddmabase+0xb); /* DMA_MODE_READ | DMA_MODE_AUTOINIT */
501 outl(va, s->ddmabase);
502 outw(s->dma_adc.dmasize-1, s->ddmabase+4);
503 c = - s->dma_adc.fragsamples;
504 write_ctrl(s, 0xa4, c);
505 write_ctrl(s, 0xa5, c >> 8);
506 outb(0, s->ddmabase+0xf);
507 s->dma_adc.ready = 1;
508 return 0;
509 }
510
511 static inline int prog_dmabuf_dac(struct solo1_state *s)
512 {
513 unsigned long va;
514 int c;
515
516 stop_dac(s);
517 if ((c = prog_dmabuf(s, &s->dma_dac)))
518 return c;
519 memset(s->dma_dac.rawbuf, (s->fmt & (AFMT_U8 | AFMT_U16_LE)) ? 0 : 0x80, s->dma_dac.dmasize); /* almost correct for U16 */
520 va = s->dma_dac.dmaaddr;
521 if ((va ^ (va + s->dma_dac.dmasize - 1)) & ~((1<<20)-1))
522 panic("solo1: buffer crosses 1M boundary");
523 outl(va, s->iobase);
524 /* warning: s->dma_dac.dmasize & 0xffff must not be zero! i.e. this limits us to a 32k buffer */
525 outw(s->dma_dac.dmasize, s->iobase+4);
526 c = - s->dma_dac.fragsamples;
527 write_mixer(s, 0x74, c);
528 write_mixer(s, 0x76, c >> 8);
529 outb(0xa, s->iobase+6);
530 s->dma_dac.ready = 1;
531 return 0;
532 }
533
534 static inline void clear_advance(void *buf, unsigned bsize, unsigned bptr, unsigned len, unsigned char c)
535 {
536 if (bptr + len > bsize) {
537 unsigned x = bsize - bptr;
538 memset(((char *)buf) + bptr, c, x);
539 bptr = 0;
540 len -= x;
541 }
542 memset(((char *)buf) + bptr, c, len);
543 }
544
545 /* call with spinlock held! */
546
547 static void solo1_update_ptr(struct solo1_state *s)
548 {
549 int diff;
550 unsigned hwptr;
551
552 /* update ADC pointer */
553 if (s->ena & FMODE_READ) {
554 hwptr = (s->dma_adc.dmasize - 1 - inw(s->ddmabase+4)) % s->dma_adc.dmasize;
555 diff = (s->dma_adc.dmasize + hwptr - s->dma_adc.hwptr) % s->dma_adc.dmasize;
556 s->dma_adc.hwptr = hwptr;
557 s->dma_adc.total_bytes += diff;
558 s->dma_adc.count += diff;
559 #if 0
560 printk(KERN_DEBUG "solo1: rd: hwptr %u swptr %u dmasize %u count %u\n",
561 s->dma_adc.hwptr, s->dma_adc.swptr, s->dma_adc.dmasize, s->dma_adc.count);
562 #endif
563 if (s->dma_adc.mapped) {
564 if (s->dma_adc.count >= (signed)s->dma_adc.fragsize)
565 wake_up(&s->dma_adc.wait);
566 } else {
567 if (s->dma_adc.count > (signed)(s->dma_adc.dmasize - ((3 * s->dma_adc.fragsize) >> 1))) {
568 s->ena &= ~FMODE_READ;
569 write_ctrl(s, 0xb8, 0xe);
570 s->dma_adc.error++;
571 }
572 if (s->dma_adc.count > 0)
573 wake_up(&s->dma_adc.wait);
574 }
575 }
576 /* update DAC pointer */
577 if (s->ena & FMODE_WRITE) {
578 hwptr = (s->dma_dac.dmasize - inw(s->iobase+4)) % s->dma_dac.dmasize;
579 diff = (s->dma_dac.dmasize + hwptr - s->dma_dac.hwptr) % s->dma_dac.dmasize;
580 s->dma_dac.hwptr = hwptr;
581 s->dma_dac.total_bytes += diff;
582 #if 0
583 printk(KERN_DEBUG "solo1: wr: hwptr %u swptr %u dmasize %u count %u\n",
584 s->dma_dac.hwptr, s->dma_dac.swptr, s->dma_dac.dmasize, s->dma_dac.count);
585 #endif
586 if (s->dma_dac.mapped) {
587 s->dma_dac.count += diff;
588 if (s->dma_dac.count >= (signed)s->dma_dac.fragsize)
589 wake_up(&s->dma_dac.wait);
590 } else {
591 s->dma_dac.count -= diff;
592 if (s->dma_dac.count <= 0) {
593 s->ena &= ~FMODE_WRITE;
594 write_mixer(s, 0x78, 0x12);
595 s->dma_dac.error++;
596 } else if (s->dma_dac.count <= (signed)s->dma_dac.fragsize && !s->dma_dac.endcleared) {
597 clear_advance(s->dma_dac.rawbuf, s->dma_dac.dmasize, s->dma_dac.swptr,
598 s->dma_dac.fragsize, (s->fmt & (AFMT_U8 | AFMT_U16_LE)) ? 0 : 0x80);
599 s->dma_dac.endcleared = 1;
600 }
601 if (s->dma_dac.count < (signed)s->dma_dac.dmasize)
602 wake_up(&s->dma_dac.wait);
603 }
604 }
605 }
606
607 /* --------------------------------------------------------------------- */
608
609 static void prog_codec(struct solo1_state *s)
610 {
611 unsigned long flags;
612 int fdiv, filter;
613 unsigned char c;
614
615 reset_ctrl(s);
616 write_seq(s, 0xd3);
617 /* program sampling rates */
618 filter = s->rate * 9 / 20; /* Set filter roll-off to 90% of rate/2 */
619 fdiv = 256 - 7160000 / (filter * 82);
620 spin_lock_irqsave(&s->lock, flags);
621 write_ctrl(s, 0xa1, s->clkdiv);
622 write_ctrl(s, 0xa2, fdiv);
623 write_mixer(s, 0x70, s->clkdiv);
624 write_mixer(s, 0x72, fdiv);
625 /* program ADC parameters */
626 write_ctrl(s, 0xb8, 0xe);
627 write_ctrl(s, 0xb9, /*0x1*/0);
628 write_ctrl(s, 0xa8, (s->channels > 1) ? 0x11 : 0x12);
629 c = 0xd0;
630 if (s->fmt & (AFMT_S16_LE | AFMT_U16_LE))
631 c |= 0x04;
632 if (s->fmt & (AFMT_S16_LE | AFMT_S8))
633 c |= 0x20;
634 if (s->channels > 1)
635 c ^= 0x48;
636 write_ctrl(s, 0xb7, (c & 0x70) | 1);
637 write_ctrl(s, 0xb7, c);
638 write_ctrl(s, 0xb1, 0x50);
639 write_ctrl(s, 0xb2, 0x50);
640 /* program DAC parameters */
641 c = 0x40;
642 if (s->fmt & (AFMT_S16_LE | AFMT_U16_LE))
643 c |= 1;
644 if (s->fmt & (AFMT_S16_LE | AFMT_S8))
645 c |= 4;
646 if (s->channels > 1)
647 c |= 2;
648 write_mixer(s, 0x7a, c);
649 write_mixer(s, 0x78, 0x10);
650 s->ena = 0;
651 spin_unlock_irqrestore(&s->lock, flags);
652 }
653
654 /* --------------------------------------------------------------------- */
655
656 static const char invalid_magic[] = KERN_CRIT "solo1: invalid magic value\n";
657
658 #define VALIDATE_STATE(s) \
659 ({ \
660 if (!(s) || (s)->magic != SOLO1_MAGIC) { \
661 printk(invalid_magic); \
662 return -ENXIO; \
663 } \
664 })
665
666 /* --------------------------------------------------------------------- */
667
668 static int mixer_ioctl(struct solo1_state *s, unsigned int cmd, unsigned long arg)
669 {
670 static const unsigned int mixer_src[8] = {
671 SOUND_MASK_MIC, SOUND_MASK_MIC, SOUND_MASK_CD, SOUND_MASK_VOLUME,
672 SOUND_MASK_MIC, 0, SOUND_MASK_LINE, 0
673 };
674 static const unsigned char mixtable1[SOUND_MIXER_NRDEVICES] = {
675 [SOUND_MIXER_PCM] = 1, /* voice */
676 [SOUND_MIXER_SYNTH] = 2, /* FM */
677 [SOUND_MIXER_CD] = 3, /* CD */
678 [SOUND_MIXER_LINE] = 4, /* Line */
679 [SOUND_MIXER_LINE1] = 5, /* AUX */
680 [SOUND_MIXER_MIC] = 6, /* Mic */
681 [SOUND_MIXER_LINE2] = 7, /* Mono in */
682 [SOUND_MIXER_SPEAKER] = 8, /* Speaker */
683 [SOUND_MIXER_RECLEV] = 9, /* Recording level */
684 [SOUND_MIXER_VOLUME] = 10 /* Master Volume */
685 };
686 static const unsigned char mixreg[] = {
687 0x7c, /* voice */
688 0x36, /* FM */
689 0x38, /* CD */
690 0x3e, /* Line */
691 0x3a, /* AUX */
692 0x1a, /* Mic */
693 0x6d /* Mono in */
694 };
695 unsigned char l, r, rl, rr, vidx;
696 int i, val;
697 int __user *p = (int __user *)arg;
698
699 VALIDATE_STATE(s);
700
701 if (cmd == SOUND_MIXER_PRIVATE1) {
702 /* enable/disable/query mixer preamp */
703 if (get_user(val, p))
704 return -EFAULT;
705 if (val != -1) {
706 val = val ? 0xff : 0xf7;
707 write_mixer(s, 0x7d, (read_mixer(s, 0x7d) | 0x08) & val);
708 }
709 val = (read_mixer(s, 0x7d) & 0x08) ? 1 : 0;
710 return put_user(val, p);
711 }
712 if (cmd == SOUND_MIXER_PRIVATE2) {
713 /* enable/disable/query spatializer */
714 if (get_user(val, p))
715 return -EFAULT;
716 if (val != -1) {
717 val &= 0x3f;
718 write_mixer(s, 0x52, val);
719 write_mixer(s, 0x50, val ? 0x08 : 0);
720 }
721 return put_user(read_mixer(s, 0x52), p);
722 }
723 if (cmd == SOUND_MIXER_INFO) {
724 mixer_info info;
725 strncpy(info.id, "Solo1", sizeof(info.id));
726 strncpy(info.name, "ESS Solo1", sizeof(info.name));
727 info.modify_counter = s->mix.modcnt;
728 if (copy_to_user((void __user *)arg, &info, sizeof(info)))
729 return -EFAULT;
730 return 0;
731 }
732 if (cmd == SOUND_OLD_MIXER_INFO) {
733 _old_mixer_info info;
734 strncpy(info.id, "Solo1", sizeof(info.id));
735 strncpy(info.name, "ESS Solo1", sizeof(info.name));
736 if (copy_to_user((void __user *)arg, &info, sizeof(info)))
737 return -EFAULT;
738 return 0;
739 }
740 if (cmd == OSS_GETVERSION)
741 return put_user(SOUND_VERSION, p);
742 if (_IOC_TYPE(cmd) != 'M' || _SIOC_SIZE(cmd) != sizeof(int))
743 return -EINVAL;
744 if (_SIOC_DIR(cmd) == _SIOC_READ) {
745 switch (_IOC_NR(cmd)) {
746 case SOUND_MIXER_RECSRC: /* Arg contains a bit for each recording source */
747 return put_user(mixer_src[read_mixer(s, 0x1c) & 7], p);
748
749 case SOUND_MIXER_DEVMASK: /* Arg contains a bit for each supported device */
750 return put_user(SOUND_MASK_PCM | SOUND_MASK_SYNTH | SOUND_MASK_CD |
751 SOUND_MASK_LINE | SOUND_MASK_LINE1 | SOUND_MASK_MIC |
752 SOUND_MASK_VOLUME | SOUND_MASK_LINE2 | SOUND_MASK_RECLEV |
753 SOUND_MASK_SPEAKER, p);
754
755 case SOUND_MIXER_RECMASK: /* Arg contains a bit for each supported recording source */
756 return put_user(SOUND_MASK_LINE | SOUND_MASK_MIC | SOUND_MASK_CD | SOUND_MASK_VOLUME, p);
757
758 case SOUND_MIXER_STEREODEVS: /* Mixer channels supporting stereo */
759 return put_user(SOUND_MASK_PCM | SOUND_MASK_SYNTH | SOUND_MASK_CD |
760 SOUND_MASK_LINE | SOUND_MASK_LINE1 | SOUND_MASK_MIC |
761 SOUND_MASK_VOLUME | SOUND_MASK_LINE2 | SOUND_MASK_RECLEV, p);
762
763 case SOUND_MIXER_CAPS:
764 return put_user(SOUND_CAP_EXCL_INPUT, p);
765
766 default:
767 i = _IOC_NR(cmd);
768 if (i >= SOUND_MIXER_NRDEVICES || !(vidx = mixtable1[i]))
769 return -EINVAL;
770 return put_user(s->mix.vol[vidx-1], p);
771 }
772 }
773 if (_SIOC_DIR(cmd) != (_SIOC_READ|_SIOC_WRITE))
774 return -EINVAL;
775 s->mix.modcnt++;
776 switch (_IOC_NR(cmd)) {
777 case SOUND_MIXER_RECSRC: /* Arg contains a bit for each recording source */
778 #if 0
779 {
780 static const unsigned char regs[] = {
781 0x1c, 0x1a, 0x36, 0x38, 0x3a, 0x3c, 0x3e, 0x60, 0x62, 0x6d, 0x7c
782 };
783 int i;
784
785 for (i = 0; i < sizeof(regs); i++)
786 printk(KERN_DEBUG "solo1: mixer reg 0x%02x: 0x%02x\n",
787 regs[i], read_mixer(s, regs[i]));
788 printk(KERN_DEBUG "solo1: ctrl reg 0x%02x: 0x%02x\n",
789 0xb4, read_ctrl(s, 0xb4));
790 }
791 #endif
792 if (get_user(val, p))
793 return -EFAULT;
794 i = hweight32(val);
795 if (i == 0)
796 return 0;
797 else if (i > 1)
798 val &= ~mixer_src[read_mixer(s, 0x1c) & 7];
799 for (i = 0; i < 8; i++) {
800 if (mixer_src[i] & val)
801 break;
802 }
803 if (i > 7)
804 return 0;
805 write_mixer(s, 0x1c, i);
806 return 0;
807
808 case SOUND_MIXER_VOLUME:
809 if (get_user(val, p))
810 return -EFAULT;
811 l = val & 0xff;
812 if (l > 100)
813 l = 100;
814 r = (val >> 8) & 0xff;
815 if (r > 100)
816 r = 100;
817 if (l < 6) {
818 rl = 0x40;
819 l = 0;
820 } else {
821 rl = (l * 2 - 11) / 3;
822 l = (rl * 3 + 11) / 2;
823 }
824 if (r < 6) {
825 rr = 0x40;
826 r = 0;
827 } else {
828 rr = (r * 2 - 11) / 3;
829 r = (rr * 3 + 11) / 2;
830 }
831 write_mixer(s, 0x60, rl);
832 write_mixer(s, 0x62, rr);
833 #ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
834 s->mix.vol[9] = ((unsigned int)r << 8) | l;
835 #else
836 s->mix.vol[9] = val;
837 #endif
838 return put_user(s->mix.vol[9], p);
839
840 case SOUND_MIXER_SPEAKER:
841 if (get_user(val, p))
842 return -EFAULT;
843 l = val & 0xff;
844 if (l > 100)
845 l = 100;
846 else if (l < 2)
847 l = 2;
848 rl = (l - 2) / 14;
849 l = rl * 14 + 2;
850 write_mixer(s, 0x3c, rl);
851 #ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
852 s->mix.vol[7] = l * 0x101;
853 #else
854 s->mix.vol[7] = val;
855 #endif
856 return put_user(s->mix.vol[7], p);
857
858 case SOUND_MIXER_RECLEV:
859 if (get_user(val, p))
860 return -EFAULT;
861 l = (val << 1) & 0x1fe;
862 if (l > 200)
863 l = 200;
864 else if (l < 5)
865 l = 5;
866 r = (val >> 7) & 0x1fe;
867 if (r > 200)
868 r = 200;
869 else if (r < 5)
870 r = 5;
871 rl = (l - 5) / 13;
872 rr = (r - 5) / 13;
873 r = (rl * 13 + 5) / 2;
874 l = (rr * 13 + 5) / 2;
875 write_ctrl(s, 0xb4, (rl << 4) | rr);
876 #ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
877 s->mix.vol[8] = ((unsigned int)r << 8) | l;
878 #else
879 s->mix.vol[8] = val;
880 #endif
881 return put_user(s->mix.vol[8], p);
882
883 default:
884 i = _IOC_NR(cmd);
885 if (i >= SOUND_MIXER_NRDEVICES || !(vidx = mixtable1[i]))
886 return -EINVAL;
887 if (get_user(val, p))
888 return -EFAULT;
889 l = (val << 1) & 0x1fe;
890 if (l > 200)
891 l = 200;
892 else if (l < 5)
893 l = 5;
894 r = (val >> 7) & 0x1fe;
895 if (r > 200)
896 r = 200;
897 else if (r < 5)
898 r = 5;
899 rl = (l - 5) / 13;
900 rr = (r - 5) / 13;
901 r = (rl * 13 + 5) / 2;
902 l = (rr * 13 + 5) / 2;
903 write_mixer(s, mixreg[vidx-1], (rl << 4) | rr);
904 #ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
905 s->mix.vol[vidx-1] = ((unsigned int)r << 8) | l;
906 #else
907 s->mix.vol[vidx-1] = val;
908 #endif
909 return put_user(s->mix.vol[vidx-1], p);
910 }
911 }
912
913 /* --------------------------------------------------------------------- */
914
915 static int solo1_open_mixdev(struct inode *inode, struct file *file)
916 {
917 unsigned int minor = iminor(inode);
918 struct solo1_state *s = NULL;
919 struct pci_dev *pci_dev = NULL;
920
921 while ((pci_dev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, pci_dev)) != NULL) {
922 struct pci_driver *drvr;
923 drvr = pci_dev_driver (pci_dev);
924 if (drvr != &solo1_driver)
925 continue;
926 s = (struct solo1_state*)pci_get_drvdata(pci_dev);
927 if (!s)
928 continue;
929 if (s->dev_mixer == minor)
930 break;
931 }
932 if (!s)
933 return -ENODEV;
934 VALIDATE_STATE(s);
935 file->private_data = s;
936 return nonseekable_open(inode, file);
937 }
938
939 static int solo1_release_mixdev(struct inode *inode, struct file *file)
940 {
941 struct solo1_state *s = (struct solo1_state *)file->private_data;
942
943 VALIDATE_STATE(s);
944 return 0;
945 }
946
947 static int solo1_ioctl_mixdev(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
948 {
949 return mixer_ioctl((struct solo1_state *)file->private_data, cmd, arg);
950 }
951
952 static /*const*/ struct file_operations solo1_mixer_fops = {
953 .owner = THIS_MODULE,
954 .llseek = no_llseek,
955 .ioctl = solo1_ioctl_mixdev,
956 .open = solo1_open_mixdev,
957 .release = solo1_release_mixdev,
958 };
959
960 /* --------------------------------------------------------------------- */
961
962 static int drain_dac(struct solo1_state *s, int nonblock)
963 {
964 DECLARE_WAITQUEUE(wait, current);
965 unsigned long flags;
966 int count;
967 unsigned tmo;
968
969 if (s->dma_dac.mapped)
970 return 0;
971 add_wait_queue(&s->dma_dac.wait, &wait);
972 for (;;) {
973 set_current_state(TASK_INTERRUPTIBLE);
974 spin_lock_irqsave(&s->lock, flags);
975 count = s->dma_dac.count;
976 spin_unlock_irqrestore(&s->lock, flags);
977 if (count <= 0)
978 break;
979 if (signal_pending(current))
980 break;
981 if (nonblock) {
982 remove_wait_queue(&s->dma_dac.wait, &wait);
983 set_current_state(TASK_RUNNING);
984 return -EBUSY;
985 }
986 tmo = 3 * HZ * (count + s->dma_dac.fragsize) / 2 / s->rate;
987 if (s->fmt & (AFMT_S16_LE | AFMT_U16_LE))
988 tmo >>= 1;
989 if (s->channels > 1)
990 tmo >>= 1;
991 if (!schedule_timeout(tmo + 1))
992 printk(KERN_DEBUG "solo1: dma timed out??\n");
993 }
994 remove_wait_queue(&s->dma_dac.wait, &wait);
995 set_current_state(TASK_RUNNING);
996 if (signal_pending(current))
997 return -ERESTARTSYS;
998 return 0;
999 }
1000
1001 /* --------------------------------------------------------------------- */
1002
1003 static ssize_t solo1_read(struct file *file, char __user *buffer, size_t count, loff_t *ppos)
1004 {
1005 struct solo1_state *s = (struct solo1_state *)file->private_data;
1006 DECLARE_WAITQUEUE(wait, current);
1007 ssize_t ret;
1008 unsigned long flags;
1009 unsigned swptr;
1010 int cnt;
1011
1012 VALIDATE_STATE(s);
1013 if (s->dma_adc.mapped)
1014 return -ENXIO;
1015 if (!s->dma_adc.ready && (ret = prog_dmabuf_adc(s)))
1016 return ret;
1017 if (!access_ok(VERIFY_WRITE, buffer, count))
1018 return -EFAULT;
1019 ret = 0;
1020 add_wait_queue(&s->dma_adc.wait, &wait);
1021 while (count > 0) {
1022 spin_lock_irqsave(&s->lock, flags);
1023 swptr = s->dma_adc.swptr;
1024 cnt = s->dma_adc.dmasize-swptr;
1025 if (s->dma_adc.count < cnt)
1026 cnt = s->dma_adc.count;
1027 if (cnt <= 0)
1028 __set_current_state(TASK_INTERRUPTIBLE);
1029 spin_unlock_irqrestore(&s->lock, flags);
1030 if (cnt > count)
1031 cnt = count;
1032 #ifdef DEBUGREC
1033 printk(KERN_DEBUG "solo1_read: reg B8: 0x%02x DMAstat: 0x%02x DMAcnt: 0x%04x SBstat: 0x%02x cnt: %u\n",
1034 read_ctrl(s, 0xb8), inb(s->ddmabase+8), inw(s->ddmabase+4), inb(s->sbbase+0xc), cnt);
1035 #endif
1036 if (cnt <= 0) {
1037 if (s->dma_adc.enabled)
1038 start_adc(s);
1039 #ifdef DEBUGREC
1040 printk(KERN_DEBUG "solo1_read: regs: A1: 0x%02x A2: 0x%02x A4: 0x%02x A5: 0x%02x A8: 0x%02x\n"
1041 KERN_DEBUG "solo1_read: regs: B1: 0x%02x B2: 0x%02x B7: 0x%02x B8: 0x%02x B9: 0x%02x\n"
1042 KERN_DEBUG "solo1_read: DMA: addr: 0x%08x cnt: 0x%04x stat: 0x%02x mask: 0x%02x\n"
1043 KERN_DEBUG "solo1_read: SBstat: 0x%02x cnt: %u\n",
1044 read_ctrl(s, 0xa1), read_ctrl(s, 0xa2), read_ctrl(s, 0xa4), read_ctrl(s, 0xa5), read_ctrl(s, 0xa8),
1045 read_ctrl(s, 0xb1), read_ctrl(s, 0xb2), read_ctrl(s, 0xb7), read_ctrl(s, 0xb8), read_ctrl(s, 0xb9),
1046 inl(s->ddmabase), inw(s->ddmabase+4), inb(s->ddmabase+8), inb(s->ddmabase+15), inb(s->sbbase+0xc), cnt);
1047 #endif
1048 if (inb(s->ddmabase+15) & 1)
1049 printk(KERN_ERR "solo1: cannot start recording, DDMA mask bit stuck at 1\n");
1050 if (file->f_flags & O_NONBLOCK) {
1051 if (!ret)
1052 ret = -EAGAIN;
1053 break;
1054 }
1055 schedule();
1056 #ifdef DEBUGREC
1057 printk(KERN_DEBUG "solo1_read: regs: A1: 0x%02x A2: 0x%02x A4: 0x%02x A5: 0x%02x A8: 0x%02x\n"
1058 KERN_DEBUG "solo1_read: regs: B1: 0x%02x B2: 0x%02x B7: 0x%02x B8: 0x%02x B9: 0x%02x\n"
1059 KERN_DEBUG "solo1_read: DMA: addr: 0x%08x cnt: 0x%04x stat: 0x%02x mask: 0x%02x\n"
1060 KERN_DEBUG "solo1_read: SBstat: 0x%02x cnt: %u\n",
1061 read_ctrl(s, 0xa1), read_ctrl(s, 0xa2), read_ctrl(s, 0xa4), read_ctrl(s, 0xa5), read_ctrl(s, 0xa8),
1062 read_ctrl(s, 0xb1), read_ctrl(s, 0xb2), read_ctrl(s, 0xb7), read_ctrl(s, 0xb8), read_ctrl(s, 0xb9),
1063 inl(s->ddmabase), inw(s->ddmabase+4), inb(s->ddmabase+8), inb(s->ddmabase+15), inb(s->sbbase+0xc), cnt);
1064 #endif
1065 if (signal_pending(current)) {
1066 if (!ret)
1067 ret = -ERESTARTSYS;
1068 break;
1069 }
1070 continue;
1071 }
1072 if (copy_to_user(buffer, s->dma_adc.rawbuf + swptr, cnt)) {
1073 if (!ret)
1074 ret = -EFAULT;
1075 break;
1076 }
1077 swptr = (swptr + cnt) % s->dma_adc.dmasize;
1078 spin_lock_irqsave(&s->lock, flags);
1079 s->dma_adc.swptr = swptr;
1080 s->dma_adc.count -= cnt;
1081 spin_unlock_irqrestore(&s->lock, flags);
1082 count -= cnt;
1083 buffer += cnt;
1084 ret += cnt;
1085 if (s->dma_adc.enabled)
1086 start_adc(s);
1087 #ifdef DEBUGREC
1088 printk(KERN_DEBUG "solo1_read: reg B8: 0x%02x DMAstat: 0x%02x DMAcnt: 0x%04x SBstat: 0x%02x\n",
1089 read_ctrl(s, 0xb8), inb(s->ddmabase+8), inw(s->ddmabase+4), inb(s->sbbase+0xc));
1090 #endif
1091 }
1092 remove_wait_queue(&s->dma_adc.wait, &wait);
1093 set_current_state(TASK_RUNNING);
1094 return ret;
1095 }
1096
1097 static ssize_t solo1_write(struct file *file, const char __user *buffer, size_t count, loff_t *ppos)
1098 {
1099 struct solo1_state *s = (struct solo1_state *)file->private_data;
1100 DECLARE_WAITQUEUE(wait, current);
1101 ssize_t ret;
1102 unsigned long flags;
1103 unsigned swptr;
1104 int cnt;
1105
1106 VALIDATE_STATE(s);
1107 if (s->dma_dac.mapped)
1108 return -ENXIO;
1109 if (!s->dma_dac.ready && (ret = prog_dmabuf_dac(s)))
1110 return ret;
1111 if (!access_ok(VERIFY_READ, buffer, count))
1112 return -EFAULT;
1113 #if 0
1114 printk(KERN_DEBUG "solo1_write: reg 70: 0x%02x 71: 0x%02x 72: 0x%02x 74: 0x%02x 76: 0x%02x 78: 0x%02x 7A: 0x%02x\n"
1115 KERN_DEBUG "solo1_write: DMA: addr: 0x%08x cnt: 0x%04x stat: 0x%02x SBstat: 0x%02x\n",
1116 read_mixer(s, 0x70), read_mixer(s, 0x71), read_mixer(s, 0x72), read_mixer(s, 0x74), read_mixer(s, 0x76),
1117 read_mixer(s, 0x78), read_mixer(s, 0x7a), inl(s->iobase), inw(s->iobase+4), inb(s->iobase+6), inb(s->sbbase+0xc));
1118 printk(KERN_DEBUG "solo1_write: reg 78: 0x%02x reg 7A: 0x%02x DMAcnt: 0x%04x DMAstat: 0x%02x SBstat: 0x%02x\n",
1119 read_mixer(s, 0x78), read_mixer(s, 0x7a), inw(s->iobase+4), inb(s->iobase+6), inb(s->sbbase+0xc));
1120 #endif
1121 ret = 0;
1122 add_wait_queue(&s->dma_dac.wait, &wait);
1123 while (count > 0) {
1124 spin_lock_irqsave(&s->lock, flags);
1125 if (s->dma_dac.count < 0) {
1126 s->dma_dac.count = 0;
1127 s->dma_dac.swptr = s->dma_dac.hwptr;
1128 }
1129 swptr = s->dma_dac.swptr;
1130 cnt = s->dma_dac.dmasize-swptr;
1131 if (s->dma_dac.count + cnt > s->dma_dac.dmasize)
1132 cnt = s->dma_dac.dmasize - s->dma_dac.count;
1133 if (cnt <= 0)
1134 __set_current_state(TASK_INTERRUPTIBLE);
1135 spin_unlock_irqrestore(&s->lock, flags);
1136 if (cnt > count)
1137 cnt = count;
1138 if (cnt <= 0) {
1139 if (s->dma_dac.enabled)
1140 start_dac(s);
1141 if (file->f_flags & O_NONBLOCK) {
1142 if (!ret)
1143 ret = -EAGAIN;
1144 break;
1145 }
1146 schedule();
1147 if (signal_pending(current)) {
1148 if (!ret)
1149 ret = -ERESTARTSYS;
1150 break;
1151 }
1152 continue;
1153 }
1154 if (copy_from_user(s->dma_dac.rawbuf + swptr, buffer, cnt)) {
1155 if (!ret)
1156 ret = -EFAULT;
1157 break;
1158 }
1159 swptr = (swptr + cnt) % s->dma_dac.dmasize;
1160 spin_lock_irqsave(&s->lock, flags);
1161 s->dma_dac.swptr = swptr;
1162 s->dma_dac.count += cnt;
1163 s->dma_dac.endcleared = 0;
1164 spin_unlock_irqrestore(&s->lock, flags);
1165 count -= cnt;
1166 buffer += cnt;
1167 ret += cnt;
1168 if (s->dma_dac.enabled)
1169 start_dac(s);
1170 }
1171 remove_wait_queue(&s->dma_dac.wait, &wait);
1172 set_current_state(TASK_RUNNING);
1173 return ret;
1174 }
1175
1176 /* No kernel lock - we have our own spinlock */
1177 static unsigned int solo1_poll(struct file *file, struct poll_table_struct *wait)
1178 {
1179 struct solo1_state *s = (struct solo1_state *)file->private_data;
1180 unsigned long flags;
1181 unsigned int mask = 0;
1182
1183 VALIDATE_STATE(s);
1184 if (file->f_mode & FMODE_WRITE) {
1185 if (!s->dma_dac.ready && prog_dmabuf_dac(s))
1186 return 0;
1187 poll_wait(file, &s->dma_dac.wait, wait);
1188 }
1189 if (file->f_mode & FMODE_READ) {
1190 if (!s->dma_adc.ready && prog_dmabuf_adc(s))
1191 return 0;
1192 poll_wait(file, &s->dma_adc.wait, wait);
1193 }
1194 spin_lock_irqsave(&s->lock, flags);
1195 solo1_update_ptr(s);
1196 if (file->f_mode & FMODE_READ) {
1197 if (s->dma_adc.mapped) {
1198 if (s->dma_adc.count >= (signed)s->dma_adc.fragsize)
1199 mask |= POLLIN | POLLRDNORM;
1200 } else {
1201 if (s->dma_adc.count > 0)
1202 mask |= POLLIN | POLLRDNORM;
1203 }
1204 }
1205 if (file->f_mode & FMODE_WRITE) {
1206 if (s->dma_dac.mapped) {
1207 if (s->dma_dac.count >= (signed)s->dma_dac.fragsize)
1208 mask |= POLLOUT | POLLWRNORM;
1209 } else {
1210 if ((signed)s->dma_dac.dmasize > s->dma_dac.count)
1211 mask |= POLLOUT | POLLWRNORM;
1212 }
1213 }
1214 spin_unlock_irqrestore(&s->lock, flags);
1215 return mask;
1216 }
1217
1218
1219 static int solo1_mmap(struct file *file, struct vm_area_struct *vma)
1220 {
1221 struct solo1_state *s = (struct solo1_state *)file->private_data;
1222 struct dmabuf *db;
1223 int ret = -EINVAL;
1224 unsigned long size;
1225
1226 VALIDATE_STATE(s);
1227 lock_kernel();
1228 if (vma->vm_flags & VM_WRITE) {
1229 if ((ret = prog_dmabuf_dac(s)) != 0)
1230 goto out;
1231 db = &s->dma_dac;
1232 } else if (vma->vm_flags & VM_READ) {
1233 if ((ret = prog_dmabuf_adc(s)) != 0)
1234 goto out;
1235 db = &s->dma_adc;
1236 } else
1237 goto out;
1238 ret = -EINVAL;
1239 if (vma->vm_pgoff != 0)
1240 goto out;
1241 size = vma->vm_end - vma->vm_start;
1242 if (size > (PAGE_SIZE << db->buforder))
1243 goto out;
1244 ret = -EAGAIN;
1245 if (remap_pfn_range(vma, vma->vm_start,
1246 virt_to_phys(db->rawbuf) >> PAGE_SHIFT,
1247 size, vma->vm_page_prot))
1248 goto out;
1249 db->mapped = 1;
1250 ret = 0;
1251 out:
1252 unlock_kernel();
1253 return ret;
1254 }
1255
1256 static int solo1_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
1257 {
1258 struct solo1_state *s = (struct solo1_state *)file->private_data;
1259 unsigned long flags;
1260 audio_buf_info abinfo;
1261 count_info cinfo;
1262 int val, mapped, ret, count;
1263 int div1, div2;
1264 unsigned rate1, rate2;
1265 void __user *argp = (void __user *)arg;
1266 int __user *p = argp;
1267
1268 VALIDATE_STATE(s);
1269 mapped = ((file->f_mode & FMODE_WRITE) && s->dma_dac.mapped) ||
1270 ((file->f_mode & FMODE_READ) && s->dma_adc.mapped);
1271 switch (cmd) {
1272 case OSS_GETVERSION:
1273 return put_user(SOUND_VERSION, p);
1274
1275 case SNDCTL_DSP_SYNC:
1276 if (file->f_mode & FMODE_WRITE)
1277 return drain_dac(s, 0/*file->f_flags & O_NONBLOCK*/);
1278 return 0;
1279
1280 case SNDCTL_DSP_SETDUPLEX:
1281 return 0;
1282
1283 case SNDCTL_DSP_GETCAPS:
1284 return put_user(DSP_CAP_DUPLEX | DSP_CAP_REALTIME | DSP_CAP_TRIGGER | DSP_CAP_MMAP, p);
1285
1286 case SNDCTL_DSP_RESET:
1287 if (file->f_mode & FMODE_WRITE) {
1288 stop_dac(s);
1289 synchronize_irq(s->irq);
1290 s->dma_dac.swptr = s->dma_dac.hwptr = s->dma_dac.count = s->dma_dac.total_bytes = 0;
1291 }
1292 if (file->f_mode & FMODE_READ) {
1293 stop_adc(s);
1294 synchronize_irq(s->irq);
1295 s->dma_adc.swptr = s->dma_adc.hwptr = s->dma_adc.count = s->dma_adc.total_bytes = 0;
1296 }
1297 prog_codec(s);
1298 return 0;
1299
1300 case SNDCTL_DSP_SPEED:
1301 if (get_user(val, p))
1302 return -EFAULT;
1303 if (val >= 0) {
1304 stop_adc(s);
1305 stop_dac(s);
1306 s->dma_adc.ready = s->dma_dac.ready = 0;
1307 /* program sampling rates */
1308 if (val > 48000)
1309 val = 48000;
1310 if (val < 6300)
1311 val = 6300;
1312 div1 = (768000 + val / 2) / val;
1313 rate1 = (768000 + div1 / 2) / div1;
1314 div1 = -div1;
1315 div2 = (793800 + val / 2) / val;
1316 rate2 = (793800 + div2 / 2) / div2;
1317 div2 = (-div2) & 0x7f;
1318 if (abs(val - rate2) < abs(val - rate1)) {
1319 rate1 = rate2;
1320 div1 = div2;
1321 }
1322 s->rate = rate1;
1323 s->clkdiv = div1;
1324 prog_codec(s);
1325 }
1326 return put_user(s->rate, p);
1327
1328 case SNDCTL_DSP_STEREO:
1329 if (get_user(val, p))
1330 return -EFAULT;
1331 stop_adc(s);
1332 stop_dac(s);
1333 s->dma_adc.ready = s->dma_dac.ready = 0;
1334 /* program channels */
1335 s->channels = val ? 2 : 1;
1336 prog_codec(s);
1337 return 0;
1338
1339 case SNDCTL_DSP_CHANNELS:
1340 if (get_user(val, p))
1341 return -EFAULT;
1342 if (val != 0) {
1343 stop_adc(s);
1344 stop_dac(s);
1345 s->dma_adc.ready = s->dma_dac.ready = 0;
1346 /* program channels */
1347 s->channels = (val >= 2) ? 2 : 1;
1348 prog_codec(s);
1349 }
1350 return put_user(s->channels, p);
1351
1352 case SNDCTL_DSP_GETFMTS: /* Returns a mask */
1353 return put_user(AFMT_S16_LE|AFMT_U16_LE|AFMT_S8|AFMT_U8, p);
1354
1355 case SNDCTL_DSP_SETFMT: /* Selects ONE fmt*/
1356 if (get_user(val, p))
1357 return -EFAULT;
1358 if (val != AFMT_QUERY) {
1359 stop_adc(s);
1360 stop_dac(s);
1361 s->dma_adc.ready = s->dma_dac.ready = 0;
1362 /* program format */
1363 if (val != AFMT_S16_LE && val != AFMT_U16_LE &&
1364 val != AFMT_S8 && val != AFMT_U8)
1365 val = AFMT_U8;
1366 s->fmt = val;
1367 prog_codec(s);
1368 }
1369 return put_user(s->fmt, p);
1370
1371 case SNDCTL_DSP_POST:
1372 return 0;
1373
1374 case SNDCTL_DSP_GETTRIGGER:
1375 val = 0;
1376 if (file->f_mode & s->ena & FMODE_READ)
1377 val |= PCM_ENABLE_INPUT;
1378 if (file->f_mode & s->ena & FMODE_WRITE)
1379 val |= PCM_ENABLE_OUTPUT;
1380 return put_user(val, p);
1381
1382 case SNDCTL_DSP_SETTRIGGER:
1383 if (get_user(val, p))
1384 return -EFAULT;
1385 if (file->f_mode & FMODE_READ) {
1386 if (val & PCM_ENABLE_INPUT) {
1387 if (!s->dma_adc.ready && (ret = prog_dmabuf_adc(s)))
1388 return ret;
1389 s->dma_dac.enabled = 1;
1390 start_adc(s);
1391 if (inb(s->ddmabase+15) & 1)
1392 printk(KERN_ERR "solo1: cannot start recording, DDMA mask bit stuck at 1\n");
1393 } else {
1394 s->dma_dac.enabled = 0;
1395 stop_adc(s);
1396 }
1397 }
1398 if (file->f_mode & FMODE_WRITE) {
1399 if (val & PCM_ENABLE_OUTPUT) {
1400 if (!s->dma_dac.ready && (ret = prog_dmabuf_dac(s)))
1401 return ret;
1402 s->dma_dac.enabled = 1;
1403 start_dac(s);
1404 } else {
1405 s->dma_dac.enabled = 0;
1406 stop_dac(s);
1407 }
1408 }
1409 return 0;
1410
1411 case SNDCTL_DSP_GETOSPACE:
1412 if (!(file->f_mode & FMODE_WRITE))
1413 return -EINVAL;
1414 if (!s->dma_dac.ready && (val = prog_dmabuf_dac(s)) != 0)
1415 return val;
1416 spin_lock_irqsave(&s->lock, flags);
1417 solo1_update_ptr(s);
1418 abinfo.fragsize = s->dma_dac.fragsize;
1419 count = s->dma_dac.count;
1420 if (count < 0)
1421 count = 0;
1422 abinfo.bytes = s->dma_dac.dmasize - count;
1423 abinfo.fragstotal = s->dma_dac.numfrag;
1424 abinfo.fragments = abinfo.bytes >> s->dma_dac.fragshift;
1425 spin_unlock_irqrestore(&s->lock, flags);
1426 return copy_to_user(argp, &abinfo, sizeof(abinfo)) ? -EFAULT : 0;
1427
1428 case SNDCTL_DSP_GETISPACE:
1429 if (!(file->f_mode & FMODE_READ))
1430 return -EINVAL;
1431 if (!s->dma_adc.ready && (val = prog_dmabuf_adc(s)) != 0)
1432 return val;
1433 spin_lock_irqsave(&s->lock, flags);
1434 solo1_update_ptr(s);
1435 abinfo.fragsize = s->dma_adc.fragsize;
1436 abinfo.bytes = s->dma_adc.count;
1437 abinfo.fragstotal = s->dma_adc.numfrag;
1438 abinfo.fragments = abinfo.bytes >> s->dma_adc.fragshift;
1439 spin_unlock_irqrestore(&s->lock, flags);
1440 return copy_to_user(argp, &abinfo, sizeof(abinfo)) ? -EFAULT : 0;
1441
1442 case SNDCTL_DSP_NONBLOCK:
1443 file->f_flags |= O_NONBLOCK;
1444 return 0;
1445
1446 case SNDCTL_DSP_GETODELAY:
1447 if (!(file->f_mode & FMODE_WRITE))
1448 return -EINVAL;
1449 if (!s->dma_dac.ready && (val = prog_dmabuf_dac(s)) != 0)
1450 return val;
1451 spin_lock_irqsave(&s->lock, flags);
1452 solo1_update_ptr(s);
1453 count = s->dma_dac.count;
1454 spin_unlock_irqrestore(&s->lock, flags);
1455 if (count < 0)
1456 count = 0;
1457 return put_user(count, p);
1458
1459 case SNDCTL_DSP_GETIPTR:
1460 if (!(file->f_mode & FMODE_READ))
1461 return -EINVAL;
1462 if (!s->dma_adc.ready && (val = prog_dmabuf_adc(s)) != 0)
1463 return val;
1464 spin_lock_irqsave(&s->lock, flags);
1465 solo1_update_ptr(s);
1466 cinfo.bytes = s->dma_adc.total_bytes;
1467 cinfo.blocks = s->dma_adc.count >> s->dma_adc.fragshift;
1468 cinfo.ptr = s->dma_adc.hwptr;
1469 if (s->dma_adc.mapped)
1470 s->dma_adc.count &= s->dma_adc.fragsize-1;
1471 spin_unlock_irqrestore(&s->lock, flags);
1472 if (copy_to_user(argp, &cinfo, sizeof(cinfo)))
1473 return -EFAULT;
1474 return 0;
1475
1476 case SNDCTL_DSP_GETOPTR:
1477 if (!(file->f_mode & FMODE_WRITE))
1478 return -EINVAL;
1479 if (!s->dma_dac.ready && (val = prog_dmabuf_dac(s)) != 0)
1480 return val;
1481 spin_lock_irqsave(&s->lock, flags);
1482 solo1_update_ptr(s);
1483 cinfo.bytes = s->dma_dac.total_bytes;
1484 count = s->dma_dac.count;
1485 if (count < 0)
1486 count = 0;
1487 cinfo.blocks = count >> s->dma_dac.fragshift;
1488 cinfo.ptr = s->dma_dac.hwptr;
1489 if (s->dma_dac.mapped)
1490 s->dma_dac.count &= s->dma_dac.fragsize-1;
1491 spin_unlock_irqrestore(&s->lock, flags);
1492 #if 0
1493 printk(KERN_DEBUG "esssolo1: GETOPTR: bytes %u blocks %u ptr %u, buforder %u numfrag %u fragshift %u\n"
1494 KERN_DEBUG "esssolo1: swptr %u count %u fragsize %u dmasize %u fragsamples %u\n",
1495 cinfo.bytes, cinfo.blocks, cinfo.ptr, s->dma_dac.buforder, s->dma_dac.numfrag, s->dma_dac.fragshift,
1496 s->dma_dac.swptr, s->dma_dac.count, s->dma_dac.fragsize, s->dma_dac.dmasize, s->dma_dac.fragsamples);
1497 #endif
1498 if (copy_to_user(argp, &cinfo, sizeof(cinfo)))
1499 return -EFAULT;
1500 return 0;
1501
1502 case SNDCTL_DSP_GETBLKSIZE:
1503 if (file->f_mode & FMODE_WRITE) {
1504 if ((val = prog_dmabuf_dac(s)))
1505 return val;
1506 return put_user(s->dma_dac.fragsize, p);
1507 }
1508 if ((val = prog_dmabuf_adc(s)))
1509 return val;
1510 return put_user(s->dma_adc.fragsize, p);
1511
1512 case SNDCTL_DSP_SETFRAGMENT:
1513 if (get_user(val, p))
1514 return -EFAULT;
1515 if (file->f_mode & FMODE_READ) {
1516 s->dma_adc.ossfragshift = val & 0xffff;
1517 s->dma_adc.ossmaxfrags = (val >> 16) & 0xffff;
1518 if (s->dma_adc.ossfragshift < 4)
1519 s->dma_adc.ossfragshift = 4;
1520 if (s->dma_adc.ossfragshift > 15)
1521 s->dma_adc.ossfragshift = 15;
1522 if (s->dma_adc.ossmaxfrags < 4)
1523 s->dma_adc.ossmaxfrags = 4;
1524 }
1525 if (file->f_mode & FMODE_WRITE) {
1526 s->dma_dac.ossfragshift = val & 0xffff;
1527 s->dma_dac.ossmaxfrags = (val >> 16) & 0xffff;
1528 if (s->dma_dac.ossfragshift < 4)
1529 s->dma_dac.ossfragshift = 4;
1530 if (s->dma_dac.ossfragshift > 15)
1531 s->dma_dac.ossfragshift = 15;
1532 if (s->dma_dac.ossmaxfrags < 4)
1533 s->dma_dac.ossmaxfrags = 4;
1534 }
1535 return 0;
1536
1537 case SNDCTL_DSP_SUBDIVIDE:
1538 if ((file->f_mode & FMODE_READ && s->dma_adc.subdivision) ||
1539 (file->f_mode & FMODE_WRITE && s->dma_dac.subdivision))
1540 return -EINVAL;
1541 if (get_user(val, p))
1542 return -EFAULT;
1543 if (val != 1 && val != 2 && val != 4)
1544 return -EINVAL;
1545 if (file->f_mode & FMODE_READ)
1546 s->dma_adc.subdivision = val;
1547 if (file->f_mode & FMODE_WRITE)
1548 s->dma_dac.subdivision = val;
1549 return 0;
1550
1551 case SOUND_PCM_READ_RATE:
1552 return put_user(s->rate, p);
1553
1554 case SOUND_PCM_READ_CHANNELS:
1555 return put_user(s->channels, p);
1556
1557 case SOUND_PCM_READ_BITS:
1558 return put_user((s->fmt & (AFMT_S8|AFMT_U8)) ? 8 : 16, p);
1559
1560 case SOUND_PCM_WRITE_FILTER:
1561 case SNDCTL_DSP_SETSYNCRO:
1562 case SOUND_PCM_READ_FILTER:
1563 return -EINVAL;
1564
1565 }
1566 return mixer_ioctl(s, cmd, arg);
1567 }
1568
1569 static int solo1_release(struct inode *inode, struct file *file)
1570 {
1571 struct solo1_state *s = (struct solo1_state *)file->private_data;
1572
1573 VALIDATE_STATE(s);
1574 lock_kernel();
1575 if (file->f_mode & FMODE_WRITE)
1576 drain_dac(s, file->f_flags & O_NONBLOCK);
1577 down(&s->open_sem);
1578 if (file->f_mode & FMODE_WRITE) {
1579 stop_dac(s);
1580 outb(0, s->iobase+6); /* disable DMA */
1581 dealloc_dmabuf(s, &s->dma_dac);
1582 }
1583 if (file->f_mode & FMODE_READ) {
1584 stop_adc(s);
1585 outb(1, s->ddmabase+0xf); /* mask DMA channel */
1586 outb(0, s->ddmabase+0xd); /* DMA master clear */
1587 dealloc_dmabuf(s, &s->dma_adc);
1588 }
1589 s->open_mode &= ~(FMODE_READ | FMODE_WRITE);
1590 wake_up(&s->open_wait);
1591 up(&s->open_sem);
1592 unlock_kernel();
1593 return 0;
1594 }
1595
1596 static int solo1_open(struct inode *inode, struct file *file)
1597 {
1598 unsigned int minor = iminor(inode);
1599 DECLARE_WAITQUEUE(wait, current);
1600 struct solo1_state *s = NULL;
1601 struct pci_dev *pci_dev = NULL;
1602
1603 while ((pci_dev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, pci_dev)) != NULL) {
1604 struct pci_driver *drvr;
1605
1606 drvr = pci_dev_driver(pci_dev);
1607 if (drvr != &solo1_driver)
1608 continue;
1609 s = (struct solo1_state*)pci_get_drvdata(pci_dev);
1610 if (!s)
1611 continue;
1612 if (!((s->dev_audio ^ minor) & ~0xf))
1613 break;
1614 }
1615 if (!s)
1616 return -ENODEV;
1617 VALIDATE_STATE(s);
1618 file->private_data = s;
1619 /* wait for device to become free */
1620 down(&s->open_sem);
1621 while (s->open_mode & (FMODE_READ | FMODE_WRITE)) {
1622 if (file->f_flags & O_NONBLOCK) {
1623 up(&s->open_sem);
1624 return -EBUSY;
1625 }
1626 add_wait_queue(&s->open_wait, &wait);
1627 __set_current_state(TASK_INTERRUPTIBLE);
1628 up(&s->open_sem);
1629 schedule();
1630 remove_wait_queue(&s->open_wait, &wait);
1631 set_current_state(TASK_RUNNING);
1632 if (signal_pending(current))
1633 return -ERESTARTSYS;
1634 down(&s->open_sem);
1635 }
1636 s->fmt = AFMT_U8;
1637 s->channels = 1;
1638 s->rate = 8000;
1639 s->clkdiv = 96 | 0x80;
1640 s->ena = 0;
1641 s->dma_adc.ossfragshift = s->dma_adc.ossmaxfrags = s->dma_adc.subdivision = 0;
1642 s->dma_adc.enabled = 1;
1643 s->dma_dac.ossfragshift = s->dma_dac.ossmaxfrags = s->dma_dac.subdivision = 0;
1644 s->dma_dac.enabled = 1;
1645 s->open_mode |= file->f_mode & (FMODE_READ | FMODE_WRITE);
1646 up(&s->open_sem);
1647 prog_codec(s);
1648 return nonseekable_open(inode, file);
1649 }
1650
1651 static /*const*/ struct file_operations solo1_audio_fops = {
1652 .owner = THIS_MODULE,
1653 .llseek = no_llseek,
1654 .read = solo1_read,
1655 .write = solo1_write,
1656 .poll = solo1_poll,
1657 .ioctl = solo1_ioctl,
1658 .mmap = solo1_mmap,
1659 .open = solo1_open,
1660 .release = solo1_release,
1661 };
1662
1663 /* --------------------------------------------------------------------- */
1664
1665 /* hold spinlock for the following! */
1666 static void solo1_handle_midi(struct solo1_state *s)
1667 {
1668 unsigned char ch;
1669 int wake;
1670
1671 if (!(s->mpubase))
1672 return;
1673 wake = 0;
1674 while (!(inb(s->mpubase+1) & 0x80)) {
1675 ch = inb(s->mpubase);
1676 if (s->midi.icnt < MIDIINBUF) {
1677 s->midi.ibuf[s->midi.iwr] = ch;
1678 s->midi.iwr = (s->midi.iwr + 1) % MIDIINBUF;
1679 s->midi.icnt++;
1680 }
1681 wake = 1;
1682 }
1683 if (wake)
1684 wake_up(&s->midi.iwait);
1685 wake = 0;
1686 while (!(inb(s->mpubase+1) & 0x40) && s->midi.ocnt > 0) {
1687 outb(s->midi.obuf[s->midi.ord], s->mpubase);
1688 s->midi.ord = (s->midi.ord + 1) % MIDIOUTBUF;
1689 s->midi.ocnt--;
1690 if (s->midi.ocnt < MIDIOUTBUF-16)
1691 wake = 1;
1692 }
1693 if (wake)
1694 wake_up(&s->midi.owait);
1695 }
1696
1697 static irqreturn_t solo1_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1698 {
1699 struct solo1_state *s = (struct solo1_state *)dev_id;
1700 unsigned int intsrc;
1701
1702 /* fastpath out, to ease interrupt sharing */
1703 intsrc = inb(s->iobase+7); /* get interrupt source(s) */
1704 if (!intsrc)
1705 return IRQ_NONE;
1706 (void)inb(s->sbbase+0xe); /* clear interrupt */
1707 spin_lock(&s->lock);
1708 /* clear audio interrupts first */
1709 if (intsrc & 0x20)
1710 write_mixer(s, 0x7a, read_mixer(s, 0x7a) & 0x7f);
1711 solo1_update_ptr(s);
1712 solo1_handle_midi(s);
1713 spin_unlock(&s->lock);
1714 return IRQ_HANDLED;
1715 }
1716
1717 static void solo1_midi_timer(unsigned long data)
1718 {
1719 struct solo1_state *s = (struct solo1_state *)data;
1720 unsigned long flags;
1721
1722 spin_lock_irqsave(&s->lock, flags);
1723 solo1_handle_midi(s);
1724 spin_unlock_irqrestore(&s->lock, flags);
1725 s->midi.timer.expires = jiffies+1;
1726 add_timer(&s->midi.timer);
1727 }
1728
1729 /* --------------------------------------------------------------------- */
1730
1731 static ssize_t solo1_midi_read(struct file *file, char __user *buffer, size_t count, loff_t *ppos)
1732 {
1733 struct solo1_state *s = (struct solo1_state *)file->private_data;
1734 DECLARE_WAITQUEUE(wait, current);
1735 ssize_t ret;
1736 unsigned long flags;
1737 unsigned ptr;
1738 int cnt;
1739
1740 VALIDATE_STATE(s);
1741 if (!access_ok(VERIFY_WRITE, buffer, count))
1742 return -EFAULT;
1743 if (count == 0)
1744 return 0;
1745 ret = 0;
1746 add_wait_queue(&s->midi.iwait, &wait);
1747 while (count > 0) {
1748 spin_lock_irqsave(&s->lock, flags);
1749 ptr = s->midi.ird;
1750 cnt = MIDIINBUF - ptr;
1751 if (s->midi.icnt < cnt)
1752 cnt = s->midi.icnt;
1753 if (cnt <= 0)
1754 __set_current_state(TASK_INTERRUPTIBLE);
1755 spin_unlock_irqrestore(&s->lock, flags);
1756 if (cnt > count)
1757 cnt = count;
1758 if (cnt <= 0) {
1759 if (file->f_flags & O_NONBLOCK) {
1760 if (!ret)
1761 ret = -EAGAIN;
1762 break;
1763 }
1764 schedule();
1765 if (signal_pending(current)) {
1766 if (!ret)
1767 ret = -ERESTARTSYS;
1768 break;
1769 }
1770 continue;
1771 }
1772 if (copy_to_user(buffer, s->midi.ibuf + ptr, cnt)) {
1773 if (!ret)
1774 ret = -EFAULT;
1775 break;
1776 }
1777 ptr = (ptr + cnt) % MIDIINBUF;
1778 spin_lock_irqsave(&s->lock, flags);
1779 s->midi.ird = ptr;
1780 s->midi.icnt -= cnt;
1781 spin_unlock_irqrestore(&s->lock, flags);
1782 count -= cnt;
1783 buffer += cnt;
1784 ret += cnt;
1785 break;
1786 }
1787 __set_current_state(TASK_RUNNING);
1788 remove_wait_queue(&s->midi.iwait, &wait);
1789 return ret;
1790 }
1791
1792 static ssize_t solo1_midi_write(struct file *file, const char __user *buffer, size_t count, loff_t *ppos)
1793 {
1794 struct solo1_state *s = (struct solo1_state *)file->private_data;
1795 DECLARE_WAITQUEUE(wait, current);
1796 ssize_t ret;
1797 unsigned long flags;
1798 unsigned ptr;
1799 int cnt;
1800
1801 VALIDATE_STATE(s);
1802 if (!access_ok(VERIFY_READ, buffer, count))
1803 return -EFAULT;
1804 if (count == 0)
1805 return 0;
1806 ret = 0;
1807 add_wait_queue(&s->midi.owait, &wait);
1808 while (count > 0) {
1809 spin_lock_irqsave(&s->lock, flags);
1810 ptr = s->midi.owr;
1811 cnt = MIDIOUTBUF - ptr;
1812 if (s->midi.ocnt + cnt > MIDIOUTBUF)
1813 cnt = MIDIOUTBUF - s->midi.ocnt;
1814 if (cnt <= 0) {
1815 __set_current_state(TASK_INTERRUPTIBLE);
1816 solo1_handle_midi(s);
1817 }
1818 spin_unlock_irqrestore(&s->lock, flags);
1819 if (cnt > count)
1820 cnt = count;
1821 if (cnt <= 0) {
1822 if (file->f_flags & O_NONBLOCK) {
1823 if (!ret)
1824 ret = -EAGAIN;
1825 break;
1826 }
1827 schedule();
1828 if (signal_pending(current)) {
1829 if (!ret)
1830 ret = -ERESTARTSYS;
1831 break;
1832 }
1833 continue;
1834 }
1835 if (copy_from_user(s->midi.obuf + ptr, buffer, cnt)) {
1836 if (!ret)
1837 ret = -EFAULT;
1838 break;
1839 }
1840 ptr = (ptr + cnt) % MIDIOUTBUF;
1841 spin_lock_irqsave(&s->lock, flags);
1842 s->midi.owr = ptr;
1843 s->midi.ocnt += cnt;
1844 spin_unlock_irqrestore(&s->lock, flags);
1845 count -= cnt;
1846 buffer += cnt;
1847 ret += cnt;
1848 spin_lock_irqsave(&s->lock, flags);
1849 solo1_handle_midi(s);
1850 spin_unlock_irqrestore(&s->lock, flags);
1851 }
1852 __set_current_state(TASK_RUNNING);
1853 remove_wait_queue(&s->midi.owait, &wait);
1854 return ret;
1855 }
1856
1857 /* No kernel lock - we have our own spinlock */
1858 static unsigned int solo1_midi_poll(struct file *file, struct poll_table_struct *wait)
1859 {
1860 struct solo1_state *s = (struct solo1_state *)file->private_data;
1861 unsigned long flags;
1862 unsigned int mask = 0;
1863
1864 VALIDATE_STATE(s);
1865 if (file->f_flags & FMODE_WRITE)
1866 poll_wait(file, &s->midi.owait, wait);
1867 if (file->f_flags & FMODE_READ)
1868 poll_wait(file, &s->midi.iwait, wait);
1869 spin_lock_irqsave(&s->lock, flags);
1870 if (file->f_flags & FMODE_READ) {
1871 if (s->midi.icnt > 0)
1872 mask |= POLLIN | POLLRDNORM;
1873 }
1874 if (file->f_flags & FMODE_WRITE) {
1875 if (s->midi.ocnt < MIDIOUTBUF)
1876 mask |= POLLOUT | POLLWRNORM;
1877 }
1878 spin_unlock_irqrestore(&s->lock, flags);
1879 return mask;
1880 }
1881
1882 static int solo1_midi_open(struct inode *inode, struct file *file)
1883 {
1884 unsigned int minor = iminor(inode);
1885 DECLARE_WAITQUEUE(wait, current);
1886 unsigned long flags;
1887 struct solo1_state *s = NULL;
1888 struct pci_dev *pci_dev = NULL;
1889
1890 while ((pci_dev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, pci_dev)) != NULL) {
1891 struct pci_driver *drvr;
1892
1893 drvr = pci_dev_driver(pci_dev);
1894 if (drvr != &solo1_driver)
1895 continue;
1896 s = (struct solo1_state*)pci_get_drvdata(pci_dev);
1897 if (!s)
1898 continue;
1899 if (s->dev_midi == minor)
1900 break;
1901 }
1902 if (!s)
1903 return -ENODEV;
1904 VALIDATE_STATE(s);
1905 file->private_data = s;
1906 /* wait for device to become free */
1907 down(&s->open_sem);
1908 while (s->open_mode & (file->f_mode << FMODE_MIDI_SHIFT)) {
1909 if (file->f_flags & O_NONBLOCK) {
1910 up(&s->open_sem);
1911 return -EBUSY;
1912 }
1913 add_wait_queue(&s->open_wait, &wait);
1914 __set_current_state(TASK_INTERRUPTIBLE);
1915 up(&s->open_sem);
1916 schedule();
1917 remove_wait_queue(&s->open_wait, &wait);
1918 set_current_state(TASK_RUNNING);
1919 if (signal_pending(current))
1920 return -ERESTARTSYS;
1921 down(&s->open_sem);
1922 }
1923 spin_lock_irqsave(&s->lock, flags);
1924 if (!(s->open_mode & (FMODE_MIDI_READ | FMODE_MIDI_WRITE))) {
1925 s->midi.ird = s->midi.iwr = s->midi.icnt = 0;
1926 s->midi.ord = s->midi.owr = s->midi.ocnt = 0;
1927 outb(0xff, s->mpubase+1); /* reset command */
1928 outb(0x3f, s->mpubase+1); /* uart command */
1929 if (!(inb(s->mpubase+1) & 0x80))
1930 inb(s->mpubase);
1931 s->midi.ird = s->midi.iwr = s->midi.icnt = 0;
1932 outb(0xb0, s->iobase + 7); /* enable A1, A2, MPU irq's */
1933 init_timer(&s->midi.timer);
1934 s->midi.timer.expires = jiffies+1;
1935 s->midi.timer.data = (unsigned long)s;
1936 s->midi.timer.function = solo1_midi_timer;
1937 add_timer(&s->midi.timer);
1938 }
1939 if (file->f_mode & FMODE_READ) {
1940 s->midi.ird = s->midi.iwr = s->midi.icnt = 0;
1941 }
1942 if (file->f_mode & FMODE_WRITE) {
1943 s->midi.ord = s->midi.owr = s->midi.ocnt = 0;
1944 }
1945 spin_unlock_irqrestore(&s->lock, flags);
1946 s->open_mode |= (file->f_mode << FMODE_MIDI_SHIFT) & (FMODE_MIDI_READ | FMODE_MIDI_WRITE);
1947 up(&s->open_sem);
1948 return nonseekable_open(inode, file);
1949 }
1950
1951 static int solo1_midi_release(struct inode *inode, struct file *file)
1952 {
1953 struct solo1_state *s = (struct solo1_state *)file->private_data;
1954 DECLARE_WAITQUEUE(wait, current);
1955 unsigned long flags;
1956 unsigned count, tmo;
1957
1958 VALIDATE_STATE(s);
1959
1960 lock_kernel();
1961 if (file->f_mode & FMODE_WRITE) {
1962 add_wait_queue(&s->midi.owait, &wait);
1963 for (;;) {
1964 __set_current_state(TASK_INTERRUPTIBLE);
1965 spin_lock_irqsave(&s->lock, flags);
1966 count = s->midi.ocnt;
1967 spin_unlock_irqrestore(&s->lock, flags);
1968 if (count <= 0)
1969 break;
1970 if (signal_pending(current))
1971 break;
1972 if (file->f_flags & O_NONBLOCK)
1973 break;
1974 tmo = (count * HZ) / 3100;
1975 if (!schedule_timeout(tmo ? : 1) && tmo)
1976 printk(KERN_DEBUG "solo1: midi timed out??\n");
1977 }
1978 remove_wait_queue(&s->midi.owait, &wait);
1979 set_current_state(TASK_RUNNING);
1980 }
1981 down(&s->open_sem);
1982 s->open_mode &= ~((file->f_mode << FMODE_MIDI_SHIFT) & (FMODE_MIDI_READ|FMODE_MIDI_WRITE));
1983 spin_lock_irqsave(&s->lock, flags);
1984 if (!(s->open_mode & (FMODE_MIDI_READ | FMODE_MIDI_WRITE))) {
1985 outb(0x30, s->iobase + 7); /* enable A1, A2 irq's */
1986 del_timer(&s->midi.timer);
1987 }
1988 spin_unlock_irqrestore(&s->lock, flags);
1989 wake_up(&s->open_wait);
1990 up(&s->open_sem);
1991 unlock_kernel();
1992 return 0;
1993 }
1994
1995 static /*const*/ struct file_operations solo1_midi_fops = {
1996 .owner = THIS_MODULE,
1997 .llseek = no_llseek,
1998 .read = solo1_midi_read,
1999 .write = solo1_midi_write,
2000 .poll = solo1_midi_poll,
2001 .open = solo1_midi_open,
2002 .release = solo1_midi_release,
2003 };
2004
2005 /* --------------------------------------------------------------------- */
2006
2007 static int solo1_dmfm_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
2008 {
2009 static const unsigned char op_offset[18] = {
2010 0x00, 0x01, 0x02, 0x03, 0x04, 0x05,
2011 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D,
2012 0x10, 0x11, 0x12, 0x13, 0x14, 0x15
2013 };
2014 struct solo1_state *s = (struct solo1_state *)file->private_data;
2015 struct dm_fm_voice v;
2016 struct dm_fm_note n;
2017 struct dm_fm_params p;
2018 unsigned int io;
2019 unsigned int regb;
2020
2021 switch (cmd) {
2022 case FM_IOCTL_RESET:
2023 for (regb = 0xb0; regb < 0xb9; regb++) {
2024 outb(regb, s->sbbase);
2025 outb(0, s->sbbase+1);
2026 outb(regb, s->sbbase+2);
2027 outb(0, s->sbbase+3);
2028 }
2029 return 0;
2030
2031 case FM_IOCTL_PLAY_NOTE:
2032 if (copy_from_user(&n, (void __user *)arg, sizeof(n)))
2033 return -EFAULT;
2034 if (n.voice >= 18)
2035 return -EINVAL;
2036 if (n.voice >= 9) {
2037 regb = n.voice - 9;
2038 io = s->sbbase+2;
2039 } else {
2040 regb = n.voice;
2041 io = s->sbbase;
2042 }
2043 outb(0xa0 + regb, io);
2044 outb(n.fnum & 0xff, io+1);
2045 outb(0xb0 + regb, io);
2046 outb(((n.fnum >> 8) & 3) | ((n.octave & 7) << 2) | ((n.key_on & 1) << 5), io+1);
2047 return 0;
2048
2049 case FM_IOCTL_SET_VOICE:
2050 if (copy_from_user(&v, (void __user *)arg, sizeof(v)))
2051 return -EFAULT;
2052 if (v.voice >= 18)
2053 return -EINVAL;
2054 regb = op_offset[v.voice];
2055 io = s->sbbase + ((v.op & 1) << 1);
2056 outb(0x20 + regb, io);
2057 outb(((v.am & 1) << 7) | ((v.vibrato & 1) << 6) | ((v.do_sustain & 1) << 5) |
2058 ((v.kbd_scale & 1) << 4) | (v.harmonic & 0xf), io+1);
2059 outb(0x40 + regb, io);
2060 outb(((v.scale_level & 0x3) << 6) | (v.volume & 0x3f), io+1);
2061 outb(0x60 + regb, io);
2062 outb(((v.attack & 0xf) << 4) | (v.decay & 0xf), io+1);
2063 outb(0x80 + regb, io);
2064 outb(((v.sustain & 0xf) << 4) | (v.release & 0xf), io+1);
2065 outb(0xe0 + regb, io);
2066 outb(v.waveform & 0x7, io+1);
2067 if (n.voice >= 9) {
2068 regb = n.voice - 9;
2069 io = s->sbbase+2;
2070 } else {
2071 regb = n.voice;
2072 io = s->sbbase;
2073 }
2074 outb(0xc0 + regb, io);
2075 outb(((v.right & 1) << 5) | ((v.left & 1) << 4) | ((v.feedback & 7) << 1) |
2076 (v.connection & 1), io+1);
2077 return 0;
2078
2079 case FM_IOCTL_SET_PARAMS:
2080 if (copy_from_user(&p, (void __user *)arg, sizeof(p)))
2081 return -EFAULT;
2082 outb(0x08, s->sbbase);
2083 outb((p.kbd_split & 1) << 6, s->sbbase+1);
2084 outb(0xbd, s->sbbase);
2085 outb(((p.am_depth & 1) << 7) | ((p.vib_depth & 1) << 6) | ((p.rhythm & 1) << 5) | ((p.bass & 1) << 4) |
2086 ((p.snare & 1) << 3) | ((p.tomtom & 1) << 2) | ((p.cymbal & 1) << 1) | (p.hihat & 1), s->sbbase+1);
2087 return 0;
2088
2089 case FM_IOCTL_SET_OPL:
2090 outb(4, s->sbbase+2);
2091 outb(arg, s->sbbase+3);
2092 return 0;
2093
2094 case FM_IOCTL_SET_MODE:
2095 outb(5, s->sbbase+2);
2096 outb(arg & 1, s->sbbase+3);
2097 return 0;
2098
2099 default:
2100 return -EINVAL;
2101 }
2102 }
2103
2104 static int solo1_dmfm_open(struct inode *inode, struct file *file)
2105 {
2106 unsigned int minor = iminor(inode);
2107 DECLARE_WAITQUEUE(wait, current);
2108 struct solo1_state *s = NULL;
2109 struct pci_dev *pci_dev = NULL;
2110
2111 while ((pci_dev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, pci_dev)) != NULL) {
2112 struct pci_driver *drvr;
2113
2114 drvr = pci_dev_driver(pci_dev);
2115 if (drvr != &solo1_driver)
2116 continue;
2117 s = (struct solo1_state*)pci_get_drvdata(pci_dev);
2118 if (!s)
2119 continue;
2120 if (s->dev_dmfm == minor)
2121 break;
2122 }
2123 if (!s)
2124 return -ENODEV;
2125 VALIDATE_STATE(s);
2126 file->private_data = s;
2127 /* wait for device to become free */
2128 down(&s->open_sem);
2129 while (s->open_mode & FMODE_DMFM) {
2130 if (file->f_flags & O_NONBLOCK) {
2131 up(&s->open_sem);
2132 return -EBUSY;
2133 }
2134 add_wait_queue(&s->open_wait, &wait);
2135 __set_current_state(TASK_INTERRUPTIBLE);
2136 up(&s->open_sem);
2137 schedule();
2138 remove_wait_queue(&s->open_wait, &wait);
2139 set_current_state(TASK_RUNNING);
2140 if (signal_pending(current))
2141 return -ERESTARTSYS;
2142 down(&s->open_sem);
2143 }
2144 if (!request_region(s->sbbase, FMSYNTH_EXTENT, "ESS Solo1")) {
2145 up(&s->open_sem);
2146 printk(KERN_ERR "solo1: FM synth io ports in use, opl3 loaded?\n");
2147 return -EBUSY;
2148 }
2149 /* init the stuff */
2150 outb(1, s->sbbase);
2151 outb(0x20, s->sbbase+1); /* enable waveforms */
2152 outb(4, s->sbbase+2);
2153 outb(0, s->sbbase+3); /* no 4op enabled */
2154 outb(5, s->sbbase+2);
2155 outb(1, s->sbbase+3); /* enable OPL3 */
2156 s->open_mode |= FMODE_DMFM;
2157 up(&s->open_sem);
2158 return nonseekable_open(inode, file);
2159 }
2160
2161 static int solo1_dmfm_release(struct inode *inode, struct file *file)
2162 {
2163 struct solo1_state *s = (struct solo1_state *)file->private_data;
2164 unsigned int regb;
2165
2166 VALIDATE_STATE(s);
2167 lock_kernel();
2168 down(&s->open_sem);
2169 s->open_mode &= ~FMODE_DMFM;
2170 for (regb = 0xb0; regb < 0xb9; regb++) {
2171 outb(regb, s->sbbase);
2172 outb(0, s->sbbase+1);
2173 outb(regb, s->sbbase+2);
2174 outb(0, s->sbbase+3);
2175 }
2176 release_region(s->sbbase, FMSYNTH_EXTENT);
2177 wake_up(&s->open_wait);
2178 up(&s->open_sem);
2179 unlock_kernel();
2180 return 0;
2181 }
2182
2183 static /*const*/ struct file_operations solo1_dmfm_fops = {
2184 .owner = THIS_MODULE,
2185 .llseek = no_llseek,
2186 .ioctl = solo1_dmfm_ioctl,
2187 .open = solo1_dmfm_open,
2188 .release = solo1_dmfm_release,
2189 };
2190
2191 /* --------------------------------------------------------------------- */
2192
2193 static struct initvol {
2194 int mixch;
2195 int vol;
2196 } initvol[] __devinitdata = {
2197 { SOUND_MIXER_WRITE_VOLUME, 0x4040 },
2198 { SOUND_MIXER_WRITE_PCM, 0x4040 },
2199 { SOUND_MIXER_WRITE_SYNTH, 0x4040 },
2200 { SOUND_MIXER_WRITE_CD, 0x4040 },
2201 { SOUND_MIXER_WRITE_LINE, 0x4040 },
2202 { SOUND_MIXER_WRITE_LINE1, 0x4040 },
2203 { SOUND_MIXER_WRITE_LINE2, 0x4040 },
2204 { SOUND_MIXER_WRITE_RECLEV, 0x4040 },
2205 { SOUND_MIXER_WRITE_SPEAKER, 0x4040 },
2206 { SOUND_MIXER_WRITE_MIC, 0x4040 }
2207 };
2208
2209 static int setup_solo1(struct solo1_state *s)
2210 {
2211 struct pci_dev *pcidev = s->dev;
2212 mm_segment_t fs;
2213 int i, val;
2214
2215 /* initialize DDMA base address */
2216 printk(KERN_DEBUG "solo1: ddma base address: 0x%lx\n", s->ddmabase);
2217 pci_write_config_word(pcidev, 0x60, (s->ddmabase & (~0xf)) | 1);
2218 /* set DMA policy to DDMA, IRQ emulation off (CLKRUN disabled for now) */
2219 pci_write_config_dword(pcidev, 0x50, 0);
2220 /* disable legacy audio address decode */
2221 pci_write_config_word(pcidev, 0x40, 0x907f);
2222
2223 /* initialize the chips */
2224 if (!reset_ctrl(s)) {
2225 printk(KERN_ERR "esssolo1: cannot reset controller\n");
2226 return -1;
2227 }
2228 outb(0xb0, s->iobase+7); /* enable A1, A2, MPU irq's */
2229
2230 /* initialize mixer regs */
2231 write_mixer(s, 0x7f, 0); /* disable music digital recording */
2232 write_mixer(s, 0x7d, 0x0c); /* enable mic preamp, MONO_OUT is 2nd DAC right channel */
2233 write_mixer(s, 0x64, 0x45); /* volume control */
2234 write_mixer(s, 0x48, 0x10); /* enable music DAC/ES6xx interface */
2235 write_mixer(s, 0x50, 0); /* disable spatializer */
2236 write_mixer(s, 0x52, 0);
2237 write_mixer(s, 0x14, 0); /* DAC1 minimum volume */
2238 write_mixer(s, 0x71, 0x20); /* enable new 0xA1 reg format */
2239 outb(0, s->ddmabase+0xd); /* DMA master clear */
2240 outb(1, s->ddmabase+0xf); /* mask channel */
2241 /*outb(0, s->ddmabase+0x8);*/ /* enable controller (enable is low active!!) */
2242
2243 pci_set_master(pcidev); /* enable bus mastering */
2244
2245 fs = get_fs();
2246 set_fs(KERNEL_DS);
2247 val = SOUND_MASK_LINE;
2248 mixer_ioctl(s, SOUND_MIXER_WRITE_RECSRC, (unsigned long)&val);
2249 for (i = 0; i < sizeof(initvol)/sizeof(initvol[0]); i++) {
2250 val = initvol[i].vol;
2251 mixer_ioctl(s, initvol[i].mixch, (unsigned long)&val);
2252 }
2253 val = 1; /* enable mic preamp */
2254 mixer_ioctl(s, SOUND_MIXER_PRIVATE1, (unsigned long)&val);
2255 set_fs(fs);
2256 return 0;
2257 }
2258
2259 static int
2260 solo1_suspend(struct pci_dev *pci_dev, pm_message_t state) {
2261 struct solo1_state *s = (struct solo1_state*)pci_get_drvdata(pci_dev);
2262 if (!s)
2263 return 1;
2264 outb(0, s->iobase+6);
2265 /* DMA master clear */
2266 outb(0, s->ddmabase+0xd);
2267 /* reset sequencer and FIFO */
2268 outb(3, s->sbbase+6);
2269 /* turn off DDMA controller address space */
2270 pci_write_config_word(s->dev, 0x60, 0);
2271 return 0;
2272 }
2273
2274 static int
2275 solo1_resume(struct pci_dev *pci_dev) {
2276 struct solo1_state *s = (struct solo1_state*)pci_get_drvdata(pci_dev);
2277 if (!s)
2278 return 1;
2279 setup_solo1(s);
2280 return 0;
2281 }
2282
2283 static int __devinit solo1_register_gameport(struct solo1_state *s, int io_port)
2284 {
2285 struct gameport *gp;
2286
2287 if (!request_region(io_port, GAMEPORT_EXTENT, "ESS Solo1")) {
2288 printk(KERN_ERR "solo1: gameport io ports are in use\n");
2289 return -EBUSY;
2290 }
2291
2292 s->gameport = gp = gameport_allocate_port();
2293 if (!gp) {
2294 printk(KERN_ERR "solo1: can not allocate memory for gameport\n");
2295 release_region(io_port, GAMEPORT_EXTENT);
2296 return -ENOMEM;
2297 }
2298
2299 gameport_set_name(gp, "ESS Solo1 Gameport");
2300 gameport_set_phys(gp, "isa%04x/gameport0", io_port);
2301 gp->dev.parent = &s->dev->dev;
2302 gp->io = io_port;
2303
2304 gameport_register_port(gp);
2305
2306 return 0;
2307 }
2308
2309 static int __devinit solo1_probe(struct pci_dev *pcidev, const struct pci_device_id *pciid)
2310 {
2311 struct solo1_state *s;
2312 int gpio;
2313 int ret;
2314
2315 if ((ret=pci_enable_device(pcidev)))
2316 return ret;
2317 if (!(pci_resource_flags(pcidev, 0) & IORESOURCE_IO) ||
2318 !(pci_resource_flags(pcidev, 1) & IORESOURCE_IO) ||
2319 !(pci_resource_flags(pcidev, 2) & IORESOURCE_IO) ||
2320 !(pci_resource_flags(pcidev, 3) & IORESOURCE_IO))
2321 return -ENODEV;
2322 if (pcidev->irq == 0)
2323 return -ENODEV;
2324
2325 /* Recording requires 24-bit DMA, so attempt to set dma mask
2326 * to 24 bits first, then 32 bits (playback only) if that fails.
2327 */
2328 if (pci_set_dma_mask(pcidev, 0x00ffffff) &&
2329 pci_set_dma_mask(pcidev, 0xffffffff)) {
2330 printk(KERN_WARNING "solo1: architecture does not support 24bit or 32bit PCI busmaster DMA\n");
2331 return -ENODEV;
2332 }
2333
2334 if (!(s = kmalloc(sizeof(struct solo1_state), GFP_KERNEL))) {
2335 printk(KERN_WARNING "solo1: out of memory\n");
2336 return -ENOMEM;
2337 }
2338 memset(s, 0, sizeof(struct solo1_state));
2339 init_waitqueue_head(&s->dma_adc.wait);
2340 init_waitqueue_head(&s->dma_dac.wait);
2341 init_waitqueue_head(&s->open_wait);
2342 init_waitqueue_head(&s->midi.iwait);
2343 init_waitqueue_head(&s->midi.owait);
2344 init_MUTEX(&s->open_sem);
2345 spin_lock_init(&s->lock);
2346 s->magic = SOLO1_MAGIC;
2347 s->dev = pcidev;
2348 s->iobase = pci_resource_start(pcidev, 0);
2349 s->sbbase = pci_resource_start(pcidev, 1);
2350 s->vcbase = pci_resource_start(pcidev, 2);
2351 s->ddmabase = s->vcbase + DDMABASE_OFFSET;
2352 s->mpubase = pci_resource_start(pcidev, 3);
2353 gpio = pci_resource_start(pcidev, 4);
2354 s->irq = pcidev->irq;
2355 ret = -EBUSY;
2356 if (!request_region(s->iobase, IOBASE_EXTENT, "ESS Solo1")) {
2357 printk(KERN_ERR "solo1: io ports in use\n");
2358 goto err_region1;
2359 }
2360 if (!request_region(s->sbbase+FMSYNTH_EXTENT, SBBASE_EXTENT-FMSYNTH_EXTENT, "ESS Solo1")) {
2361 printk(KERN_ERR "solo1: io ports in use\n");
2362 goto err_region2;
2363 }
2364 if (!request_region(s->ddmabase, DDMABASE_EXTENT, "ESS Solo1")) {
2365 printk(KERN_ERR "solo1: io ports in use\n");
2366 goto err_region3;
2367 }
2368 if (!request_region(s->mpubase, MPUBASE_EXTENT, "ESS Solo1")) {
2369 printk(KERN_ERR "solo1: io ports in use\n");
2370 goto err_region4;
2371 }
2372 if ((ret=request_irq(s->irq,solo1_interrupt,SA_SHIRQ,"ESS Solo1",s))) {
2373 printk(KERN_ERR "solo1: irq %u in use\n", s->irq);
2374 goto err_irq;
2375 }
2376 /* register devices */
2377 if ((s->dev_audio = register_sound_dsp(&solo1_audio_fops, -1)) < 0) {
2378 ret = s->dev_audio;
2379 goto err_dev1;
2380 }
2381 if ((s->dev_mixer = register_sound_mixer(&solo1_mixer_fops, -1)) < 0) {
2382 ret = s->dev_mixer;
2383 goto err_dev2;
2384 }
2385 if ((s->dev_midi = register_sound_midi(&solo1_midi_fops, -1)) < 0) {
2386 ret = s->dev_midi;
2387 goto err_dev3;
2388 }
2389 if ((s->dev_dmfm = register_sound_special(&solo1_dmfm_fops, 15 /* ?? */)) < 0) {
2390 ret = s->dev_dmfm;
2391 goto err_dev4;
2392 }
2393 if (setup_solo1(s)) {
2394 ret = -EIO;
2395 goto err;
2396 }
2397 /* register gameport */
2398 solo1_register_gameport(s, gpio);
2399 /* store it in the driver field */
2400 pci_set_drvdata(pcidev, s);
2401 return 0;
2402
2403 err:
2404 unregister_sound_special(s->dev_dmfm);
2405 err_dev4:
2406 unregister_sound_midi(s->dev_midi);
2407 err_dev3:
2408 unregister_sound_mixer(s->dev_mixer);
2409 err_dev2:
2410 unregister_sound_dsp(s->dev_audio);
2411 err_dev1:
2412 printk(KERN_ERR "solo1: initialisation error\n");
2413 free_irq(s->irq, s);
2414 err_irq:
2415 release_region(s->mpubase, MPUBASE_EXTENT);
2416 err_region4:
2417 release_region(s->ddmabase, DDMABASE_EXTENT);
2418 err_region3:
2419 release_region(s->sbbase+FMSYNTH_EXTENT, SBBASE_EXTENT-FMSYNTH_EXTENT);
2420 err_region2:
2421 release_region(s->iobase, IOBASE_EXTENT);
2422 err_region1:
2423 kfree(s);
2424 return ret;
2425 }
2426
2427 static void __devexit solo1_remove(struct pci_dev *dev)
2428 {
2429 struct solo1_state *s = pci_get_drvdata(dev);
2430
2431 if (!s)
2432 return;
2433 /* stop DMA controller */
2434 outb(0, s->iobase+6);
2435 outb(0, s->ddmabase+0xd); /* DMA master clear */
2436 outb(3, s->sbbase+6); /* reset sequencer and FIFO */
2437 synchronize_irq(s->irq);
2438 pci_write_config_word(s->dev, 0x60, 0); /* turn off DDMA controller address space */
2439 free_irq(s->irq, s);
2440 if (s->gameport) {
2441 int gpio = s->gameport->io;
2442 gameport_unregister_port(s->gameport);
2443 release_region(gpio, GAMEPORT_EXTENT);
2444 }
2445 release_region(s->iobase, IOBASE_EXTENT);
2446 release_region(s->sbbase+FMSYNTH_EXTENT, SBBASE_EXTENT-FMSYNTH_EXTENT);
2447 release_region(s->ddmabase, DDMABASE_EXTENT);
2448 release_region(s->mpubase, MPUBASE_EXTENT);
2449 unregister_sound_dsp(s->dev_audio);
2450 unregister_sound_mixer(s->dev_mixer);
2451 unregister_sound_midi(s->dev_midi);
2452 unregister_sound_special(s->dev_dmfm);
2453 kfree(s);
2454 pci_set_drvdata(dev, NULL);
2455 }
2456
2457 static struct pci_device_id id_table[] = {
2458 { PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_SOLO1, PCI_ANY_ID, PCI_ANY_ID, 0, 0 },
2459 { 0, }
2460 };
2461
2462 MODULE_DEVICE_TABLE(pci, id_table);
2463
2464 static struct pci_driver solo1_driver = {
2465 .name = "ESS Solo1",
2466 .id_table = id_table,
2467 .probe = solo1_probe,
2468 .remove = __devexit_p(solo1_remove),
2469 .suspend = solo1_suspend,
2470 .resume = solo1_resume,
2471 };
2472
2473
2474 static int __init init_solo1(void)
2475 {
2476 printk(KERN_INFO "solo1: version v0.20 time " __TIME__ " " __DATE__ "\n");
2477 return pci_register_driver(&solo1_driver);
2478 }
2479
2480 /* --------------------------------------------------------------------- */
2481
2482 MODULE_AUTHOR("Thomas M. Sailer, sailer@ife.ee.ethz.ch, hb9jnx@hb9w.che.eu");
2483 MODULE_DESCRIPTION("ESS Solo1 Driver");
2484 MODULE_LICENSE("GPL");
2485
2486
2487 static void __exit cleanup_solo1(void)
2488 {
2489 printk(KERN_INFO "solo1: unloading\n");
2490 pci_unregister_driver(&solo1_driver);
2491 }
2492
2493 /* --------------------------------------------------------------------- */
2494
2495 module_init(init_solo1);
2496 module_exit(cleanup_solo1);
2497
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