?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
[TG3]: Set minimal hw interrupt mitigation.
[linux-2.6/verdex.git] / sound / pci / cmipci.c
blob113208fbde1bc3487063f2106cc55db578f40b47
1 /*
2 * Driver for C-Media CMI8338 and 8738 PCI soundcards.
3 * Copyright (c) 2000 by Takashi Iwai <tiwai@suse.de>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20 /* Does not work. Warning may block system in capture mode */
21 /* #define USE_VAR48KRATE */
22
23 #include <sound/driver.h>
24 #include <asm/io.h>
25 #include <linux/delay.h>
26 #include <linux/interrupt.h>
27 #include <linux/init.h>
28 #include <linux/pci.h>
29 #include <linux/slab.h>
30 #include <linux/gameport.h>
31 #include <linux/moduleparam.h>
32 #include <sound/core.h>
33 #include <sound/info.h>
34 #include <sound/control.h>
35 #include <sound/pcm.h>
36 #include <sound/rawmidi.h>
37 #include <sound/mpu401.h>
38 #include <sound/opl3.h>
39 #include <sound/sb.h>
40 #include <sound/asoundef.h>
41 #include <sound/initval.h>
42
43 MODULE_AUTHOR("Takashi Iwai <tiwai@suse.de>");
44 MODULE_DESCRIPTION("C-Media CMI8x38 PCI");
45 MODULE_LICENSE("GPL");
46 MODULE_SUPPORTED_DEVICE("{{C-Media,CMI8738},"
47 "{C-Media,CMI8738B},"
48 "{C-Media,CMI8338A},"
49 "{C-Media,CMI8338B}}");
50
51 #if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
52 #define SUPPORT_JOYSTICK 1
53 #endif
54
55 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
56 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
57 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable switches */
58 static long mpu_port[SNDRV_CARDS];
59 static long fm_port[SNDRV_CARDS];
60 static int soft_ac3[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)]=1};
61 #ifdef SUPPORT_JOYSTICK
62 static int joystick_port[SNDRV_CARDS];
63 #endif
64
65 module_param_array(index, int, NULL, 0444);
66 MODULE_PARM_DESC(index, "Index value for C-Media PCI soundcard.");
67 module_param_array(id, charp, NULL, 0444);
68 MODULE_PARM_DESC(id, "ID string for C-Media PCI soundcard.");
69 module_param_array(enable, bool, NULL, 0444);
70 MODULE_PARM_DESC(enable, "Enable C-Media PCI soundcard.");
71 module_param_array(mpu_port, long, NULL, 0444);
72 MODULE_PARM_DESC(mpu_port, "MPU-401 port.");
73 module_param_array(fm_port, long, NULL, 0444);
74 MODULE_PARM_DESC(fm_port, "FM port.");
75 module_param_array(soft_ac3, bool, NULL, 0444);
76 MODULE_PARM_DESC(soft_ac3, "Sofware-conversion of raw SPDIF packets (model 033 only).");
77 #ifdef SUPPORT_JOYSTICK
78 module_param_array(joystick_port, int, NULL, 0444);
79 MODULE_PARM_DESC(joystick_port, "Joystick port address.");
80 #endif
81
82 #ifndef PCI_DEVICE_ID_CMEDIA_CM8738
83 #define PCI_DEVICE_ID_CMEDIA_CM8738 0x0111
84 #endif
85 #ifndef PCI_DEVICE_ID_CMEDIA_CM8738B
86 #define PCI_DEVICE_ID_CMEDIA_CM8738B 0x0112
87 #endif
88
89 /*
90 * CM8x38 registers definition
91 */
92
93 #define CM_REG_FUNCTRL0 0x00
94 #define CM_RST_CH1 0x00080000
95 #define CM_RST_CH0 0x00040000
96 #define CM_CHEN1 0x00020000 /* ch1: enable */
97 #define CM_CHEN0 0x00010000 /* ch0: enable */
98 #define CM_PAUSE1 0x00000008 /* ch1: pause */
99 #define CM_PAUSE0 0x00000004 /* ch0: pause */
100 #define CM_CHADC1 0x00000002 /* ch1, 0:playback, 1:record */
101 #define CM_CHADC0 0x00000001 /* ch0, 0:playback, 1:record */
102
103 #define CM_REG_FUNCTRL1 0x04
104 #define CM_ASFC_MASK 0x0000E000 /* ADC sampling frequency */
105 #define CM_ASFC_SHIFT 13
106 #define CM_DSFC_MASK 0x00001C00 /* DAC sampling frequency */
107 #define CM_DSFC_SHIFT 10
108 #define CM_SPDF_1 0x00000200 /* SPDIF IN/OUT at channel B */
109 #define CM_SPDF_0 0x00000100 /* SPDIF OUT only channel A */
110 #define CM_SPDFLOOP 0x00000080 /* ext. SPDIIF/OUT -> IN loopback */
111 #define CM_SPDO2DAC 0x00000040 /* SPDIF/OUT can be heard from internal DAC */
112 #define CM_INTRM 0x00000020 /* master control block (MCB) interrupt enabled */
113 #define CM_BREQ 0x00000010 /* bus master enabled */
114 #define CM_VOICE_EN 0x00000008 /* legacy voice (SB16,FM) */
115 #define CM_UART_EN 0x00000004 /* UART */
116 #define CM_JYSTK_EN 0x00000002 /* joy stick */
117
118 #define CM_REG_CHFORMAT 0x08
119
120 #define CM_CHB3D5C 0x80000000 /* 5,6 channels */
121 #define CM_CHB3D 0x20000000 /* 4 channels */
122
123 #define CM_CHIP_MASK1 0x1f000000
124 #define CM_CHIP_037 0x01000000
125
126 #define CM_SPDIF_SELECT1 0x00080000 /* for model <= 037 ? */
127 #define CM_AC3EN1 0x00100000 /* enable AC3: model 037 */
128 #define CM_SPD24SEL 0x00020000 /* 24bit spdif: model 037 */
129 /* #define CM_SPDIF_INVERSE 0x00010000 */ /* ??? */
130
131 #define CM_ADCBITLEN_MASK 0x0000C000
132 #define CM_ADCBITLEN_16 0x00000000
133 #define CM_ADCBITLEN_15 0x00004000
134 #define CM_ADCBITLEN_14 0x00008000
135 #define CM_ADCBITLEN_13 0x0000C000
136
137 #define CM_ADCDACLEN_MASK 0x00003000
138 #define CM_ADCDACLEN_060 0x00000000
139 #define CM_ADCDACLEN_066 0x00001000
140 #define CM_ADCDACLEN_130 0x00002000
141 #define CM_ADCDACLEN_280 0x00003000
142
143 #define CM_CH1_SRATE_176K 0x00000800
144 #define CM_CH1_SRATE_88K 0x00000400
145 #define CM_CH0_SRATE_176K 0x00000200
146 #define CM_CH0_SRATE_88K 0x00000100
147
148 #define CM_SPDIF_INVERSE2 0x00000080 /* model 055? */
149
150 #define CM_CH1FMT_MASK 0x0000000C
151 #define CM_CH1FMT_SHIFT 2
152 #define CM_CH0FMT_MASK 0x00000003
153 #define CM_CH0FMT_SHIFT 0
154
155 #define CM_REG_INT_HLDCLR 0x0C
156 #define CM_CHIP_MASK2 0xff000000
157 #define CM_CHIP_039 0x04000000
158 #define CM_CHIP_039_6CH 0x01000000
159 #define CM_CHIP_055 0x08000000
160 #define CM_CHIP_8768 0x20000000
161 #define CM_TDMA_INT_EN 0x00040000
162 #define CM_CH1_INT_EN 0x00020000
163 #define CM_CH0_INT_EN 0x00010000
164 #define CM_INT_HOLD 0x00000002
165 #define CM_INT_CLEAR 0x00000001
166
167 #define CM_REG_INT_STATUS 0x10
168 #define CM_INTR 0x80000000
169 #define CM_VCO 0x08000000 /* Voice Control? CMI8738 */
170 #define CM_MCBINT 0x04000000 /* Master Control Block abort cond.? */
171 #define CM_UARTINT 0x00010000
172 #define CM_LTDMAINT 0x00008000
173 #define CM_HTDMAINT 0x00004000
174 #define CM_XDO46 0x00000080 /* Modell 033? Direct programming EEPROM (read data register) */
175 #define CM_LHBTOG 0x00000040 /* High/Low status from DMA ctrl register */
176 #define CM_LEG_HDMA 0x00000020 /* Legacy is in High DMA channel */
177 #define CM_LEG_STEREO 0x00000010 /* Legacy is in Stereo mode */
178 #define CM_CH1BUSY 0x00000008
179 #define CM_CH0BUSY 0x00000004
180 #define CM_CHINT1 0x00000002
181 #define CM_CHINT0 0x00000001
182
183 #define CM_REG_LEGACY_CTRL 0x14
184 #define CM_NXCHG 0x80000000 /* h/w multi channels? */
185 #define CM_VMPU_MASK 0x60000000 /* MPU401 i/o port address */
186 #define CM_VMPU_330 0x00000000
187 #define CM_VMPU_320 0x20000000
188 #define CM_VMPU_310 0x40000000
189 #define CM_VMPU_300 0x60000000
190 #define CM_VSBSEL_MASK 0x0C000000 /* SB16 base address */
191 #define CM_VSBSEL_220 0x00000000
192 #define CM_VSBSEL_240 0x04000000
193 #define CM_VSBSEL_260 0x08000000
194 #define CM_VSBSEL_280 0x0C000000
195 #define CM_FMSEL_MASK 0x03000000 /* FM OPL3 base address */
196 #define CM_FMSEL_388 0x00000000
197 #define CM_FMSEL_3C8 0x01000000
198 #define CM_FMSEL_3E0 0x02000000
199 #define CM_FMSEL_3E8 0x03000000
200 #define CM_ENSPDOUT 0x00800000 /* enable XPDIF/OUT to I/O interface */
201 #define CM_SPDCOPYRHT 0x00400000 /* set copyright spdif in/out */
202 #define CM_DAC2SPDO 0x00200000 /* enable wave+fm_midi -> SPDIF/OUT */
203 #define CM_SETRETRY 0x00010000 /* 0: legacy i/o wait (default), 1: legacy i/o bus retry */
204 #define CM_CHB3D6C 0x00008000 /* 5.1 channels support */
205 #define CM_LINE_AS_BASS 0x00006000 /* use line-in as bass */
206
207 #define CM_REG_MISC_CTRL 0x18
208 #define CM_PWD 0x80000000
209 #define CM_RESET 0x40000000
210 #define CM_SFIL_MASK 0x30000000
211 #define CM_TXVX 0x08000000
212 #define CM_N4SPK3D 0x04000000 /* 4ch output */
213 #define CM_SPDO5V 0x02000000 /* 5V spdif output (1 = 0.5v (coax)) */
214 #define CM_SPDIF48K 0x01000000 /* write */
215 #define CM_SPATUS48K 0x01000000 /* read */
216 #define CM_ENDBDAC 0x00800000 /* enable dual dac */
217 #define CM_XCHGDAC 0x00400000 /* 0: front=ch0, 1: front=ch1 */
218 #define CM_SPD32SEL 0x00200000 /* 0: 16bit SPDIF, 1: 32bit */
219 #define CM_SPDFLOOPI 0x00100000 /* int. SPDIF-IN -> int. OUT */
220 #define CM_FM_EN 0x00080000 /* enalbe FM */
221 #define CM_AC3EN2 0x00040000 /* enable AC3: model 039 */
222 #define CM_VIDWPDSB 0x00010000
223 #define CM_SPDF_AC97 0x00008000 /* 0: SPDIF/OUT 44.1K, 1: 48K */
224 #define CM_MASK_EN 0x00004000
225 #define CM_VIDWPPRT 0x00002000
226 #define CM_SFILENB 0x00001000
227 #define CM_MMODE_MASK 0x00000E00
228 #define CM_SPDIF_SELECT2 0x00000100 /* for model > 039 ? */
229 #define CM_ENCENTER 0x00000080
230 #define CM_FLINKON 0x00000040
231 #define CM_FLINKOFF 0x00000020
232 #define CM_MIDSMP 0x00000010
233 #define CM_UPDDMA_MASK 0x0000000C
234 #define CM_TWAIT_MASK 0x00000003
235
236 /* byte */
237 #define CM_REG_MIXER0 0x20
238
239 #define CM_REG_SB16_DATA 0x22
240 #define CM_REG_SB16_ADDR 0x23
241
242 #define CM_REFFREQ_XIN (315*1000*1000)/22 /* 14.31818 Mhz reference clock frequency pin XIN */
243 #define CM_ADCMULT_XIN 512 /* Guessed (487 best for 44.1kHz, not for 88/176kHz) */
244 #define CM_TOLERANCE_RATE 0.001 /* Tolerance sample rate pitch (1000ppm) */
245 #define CM_MAXIMUM_RATE 80000000 /* Note more than 80MHz */
246
247 #define CM_REG_MIXER1 0x24
248 #define CM_FMMUTE 0x80 /* mute FM */
249 #define CM_FMMUTE_SHIFT 7
250 #define CM_WSMUTE 0x40 /* mute PCM */
251 #define CM_WSMUTE_SHIFT 6
252 #define CM_SPK4 0x20 /* lin-in -> rear line out */
253 #define CM_SPK4_SHIFT 5
254 #define CM_REAR2FRONT 0x10 /* exchange rear/front */
255 #define CM_REAR2FRONT_SHIFT 4
256 #define CM_WAVEINL 0x08 /* digital wave rec. left chan */
257 #define CM_WAVEINL_SHIFT 3
258 #define CM_WAVEINR 0x04 /* digical wave rec. right */
259 #define CM_WAVEINR_SHIFT 2
260 #define CM_X3DEN 0x02 /* 3D surround enable */
261 #define CM_X3DEN_SHIFT 1
262 #define CM_CDPLAY 0x01 /* enable SPDIF/IN PCM -> DAC */
263 #define CM_CDPLAY_SHIFT 0
264
265 #define CM_REG_MIXER2 0x25
266 #define CM_RAUXREN 0x80 /* AUX right capture */
267 #define CM_RAUXREN_SHIFT 7
268 #define CM_RAUXLEN 0x40 /* AUX left capture */
269 #define CM_RAUXLEN_SHIFT 6
270 #define CM_VAUXRM 0x20 /* AUX right mute */
271 #define CM_VAUXRM_SHIFT 5
272 #define CM_VAUXLM 0x10 /* AUX left mute */
273 #define CM_VAUXLM_SHIFT 4
274 #define CM_VADMIC_MASK 0x0e /* mic gain level (0-3) << 1 */
275 #define CM_VADMIC_SHIFT 1
276 #define CM_MICGAINZ 0x01 /* mic boost */
277 #define CM_MICGAINZ_SHIFT 0
278
279 #define CM_REG_AUX_VOL 0x26
280 #define CM_VAUXL_MASK 0xf0
281 #define CM_VAUXR_MASK 0x0f
282
283 #define CM_REG_MISC 0x27
284 #define CM_XGPO1 0x20
285 // #define CM_XGPBIO 0x04
286 #define CM_MIC_CENTER_LFE 0x04 /* mic as center/lfe out? (model 039 or later?) */
287 #define CM_SPDIF_INVERSE 0x04 /* spdif input phase inverse (model 037) */
288 #define CM_SPDVALID 0x02 /* spdif input valid check */
289 #define CM_DMAUTO 0x01
290
291 #define CM_REG_AC97 0x28 /* hmmm.. do we have ac97 link? */
292 /*
293 * For CMI-8338 (0x28 - 0x2b) .. is this valid for CMI-8738
294 * or identical with AC97 codec?
295 */
296 #define CM_REG_EXTERN_CODEC CM_REG_AC97
297
298 /*
299 * MPU401 pci port index address 0x40 - 0x4f (CMI-8738 spec ver. 0.6)
300 */
301 #define CM_REG_MPU_PCI 0x40
302
303 /*
304 * FM pci port index address 0x50 - 0x5f (CMI-8738 spec ver. 0.6)
305 */
306 #define CM_REG_FM_PCI 0x50
307
308 /*
309 * for CMI-8338 .. this is not valid for CMI-8738.
310 */
311 #define CM_REG_EXTENT_IND 0xf0
312 #define CM_VPHONE_MASK 0xe0 /* Phone volume control (0-3) << 5 */
313 #define CM_VPHONE_SHIFT 5
314 #define CM_VPHOM 0x10 /* Phone mute control */
315 #define CM_VSPKM 0x08 /* Speaker mute control, default high */
316 #define CM_RLOOPREN 0x04 /* Rec. R-channel enable */
317 #define CM_RLOOPLEN 0x02 /* Rec. L-channel enable */
318
319 /*
320 * CMI-8338 spec ver 0.5 (this is not valid for CMI-8738):
321 * the 8 registers 0xf8 - 0xff are used for programming m/n counter by the PLL
322 * unit (readonly?).
323 */
324 #define CM_REG_PLL 0xf8
325
326 /*
327 * extended registers
328 */
329 #define CM_REG_CH0_FRAME1 0x80 /* base address */
330 #define CM_REG_CH0_FRAME2 0x84
331 #define CM_REG_CH1_FRAME1 0x88 /* 0-15: count of samples at bus master; buffer size */
332 #define CM_REG_CH1_FRAME2 0x8C /* 16-31: count of samples at codec; fragment size */
333 #define CM_REG_MISC_CTRL_8768 0x92 /* reg. name the same as 0x18 */
334 #define CM_CHB3D8C 0x20 /* 7.1 channels support */
335 #define CM_SPD32FMT 0x10 /* SPDIF/IN 32k */
336 #define CM_ADC2SPDIF 0x08 /* ADC output to SPDIF/OUT */
337 #define CM_SHAREADC 0x04 /* DAC in ADC as Center/LFE */
338 #define CM_REALTCMP 0x02 /* monitor the CMPL/CMPR of ADC */
339 #define CM_INVLRCK 0x01 /* invert ZVPORT's LRCK */
340
341 /*
342 * size of i/o region
343 */
344 #define CM_EXTENT_CODEC 0x100
345 #define CM_EXTENT_MIDI 0x2
346 #define CM_EXTENT_SYNTH 0x4
347
348
349 /*
350 * pci ids
351 */
352 #ifndef PCI_VENDOR_ID_CMEDIA
353 #define PCI_VENDOR_ID_CMEDIA 0x13F6
354 #endif
355 #ifndef PCI_DEVICE_ID_CMEDIA_CM8338A
356 #define PCI_DEVICE_ID_CMEDIA_CM8338A 0x0100
357 #endif
358 #ifndef PCI_DEVICE_ID_CMEDIA_CM8338B
359 #define PCI_DEVICE_ID_CMEDIA_CM8338B 0x0101
360 #endif
361 #ifndef PCI_DEVICE_ID_CMEDIA_CM8738
362 #define PCI_DEVICE_ID_CMEDIA_CM8738 0x0111
363 #endif
364 #ifndef PCI_DEVICE_ID_CMEDIA_CM8738B
365 #define PCI_DEVICE_ID_CMEDIA_CM8738B 0x0112
366 #endif
367
368 /*
369 * channels for playback / capture
370 */
371 #define CM_CH_PLAY 0
372 #define CM_CH_CAPT 1
373
374 /*
375 * flags to check device open/close
376 */
377 #define CM_OPEN_NONE 0
378 #define CM_OPEN_CH_MASK 0x01
379 #define CM_OPEN_DAC 0x10
380 #define CM_OPEN_ADC 0x20
381 #define CM_OPEN_SPDIF 0x40
382 #define CM_OPEN_MCHAN 0x80
383 #define CM_OPEN_PLAYBACK (CM_CH_PLAY | CM_OPEN_DAC)
384 #define CM_OPEN_PLAYBACK2 (CM_CH_CAPT | CM_OPEN_DAC)
385 #define CM_OPEN_PLAYBACK_MULTI (CM_CH_PLAY | CM_OPEN_DAC | CM_OPEN_MCHAN)
386 #define CM_OPEN_CAPTURE (CM_CH_CAPT | CM_OPEN_ADC)
387 #define CM_OPEN_SPDIF_PLAYBACK (CM_CH_PLAY | CM_OPEN_DAC | CM_OPEN_SPDIF)
388 #define CM_OPEN_SPDIF_CAPTURE (CM_CH_CAPT | CM_OPEN_ADC | CM_OPEN_SPDIF)
389
390
391 #if CM_CH_PLAY == 1
392 #define CM_PLAYBACK_SRATE_176K CM_CH1_SRATE_176K
393 #define CM_PLAYBACK_SPDF CM_SPDF_1
394 #define CM_CAPTURE_SPDF CM_SPDF_0
395 #else
396 #define CM_PLAYBACK_SRATE_176K CM_CH0_SRATE_176K
397 #define CM_PLAYBACK_SPDF CM_SPDF_0
398 #define CM_CAPTURE_SPDF CM_SPDF_1
399 #endif
400
401
402 /*
403 * driver data
404 */
405
406 typedef struct snd_stru_cmipci cmipci_t;
407 typedef struct snd_stru_cmipci_pcm cmipci_pcm_t;
408
409 struct snd_stru_cmipci_pcm {
410 snd_pcm_substream_t *substream;
411 int running; /* dac/adc running? */
412 unsigned int dma_size; /* in frames */
413 unsigned int period_size; /* in frames */
414 unsigned int offset; /* physical address of the buffer */
415 unsigned int fmt; /* format bits */
416 int ch; /* channel (0/1) */
417 unsigned int is_dac; /* is dac? */
418 int bytes_per_frame;
419 int shift;
420 };
421
422 /* mixer elements toggled/resumed during ac3 playback */
423 struct cmipci_mixer_auto_switches {
424 const char *name; /* switch to toggle */
425 int toggle_on; /* value to change when ac3 mode */
426 };
427 static const struct cmipci_mixer_auto_switches cm_saved_mixer[] = {
428 {"PCM Playback Switch", 0},
429 {"IEC958 Output Switch", 1},
430 {"IEC958 Mix Analog", 0},
431 // {"IEC958 Out To DAC", 1}, // no longer used
432 {"IEC958 Loop", 0},
433 };
434 #define CM_SAVED_MIXERS ARRAY_SIZE(cm_saved_mixer)
435
436 struct snd_stru_cmipci {
437 snd_card_t *card;
438
439 struct pci_dev *pci;
440 unsigned int device; /* device ID */
441 int irq;
442
443 unsigned long iobase;
444 unsigned int ctrl; /* FUNCTRL0 current value */
445
446 snd_pcm_t *pcm; /* DAC/ADC PCM */
447 snd_pcm_t *pcm2; /* 2nd DAC */
448 snd_pcm_t *pcm_spdif; /* SPDIF */
449
450 int chip_version;
451 int max_channels;
452 unsigned int has_dual_dac: 1;
453 unsigned int can_ac3_sw: 1;
454 unsigned int can_ac3_hw: 1;
455 unsigned int can_multi_ch: 1;
456 unsigned int do_soft_ac3: 1;
457
458 unsigned int spdif_playback_avail: 1; /* spdif ready? */
459 unsigned int spdif_playback_enabled: 1; /* spdif switch enabled? */
460 int spdif_counter; /* for software AC3 */
461
462 unsigned int dig_status;
463 unsigned int dig_pcm_status;
464
465 snd_pcm_hardware_t *hw_info[3]; /* for playbacks */
466
467 int opened[2]; /* open mode */
468 struct semaphore open_mutex;
469
470 unsigned int mixer_insensitive: 1;
471 snd_kcontrol_t *mixer_res_ctl[CM_SAVED_MIXERS];
472 int mixer_res_status[CM_SAVED_MIXERS];
473
474 opl3_t *opl3;
475 snd_hwdep_t *opl3hwdep;
476
477 cmipci_pcm_t channel[2]; /* ch0 - DAC, ch1 - ADC or 2nd DAC */
478
479 /* external MIDI */
480 snd_rawmidi_t *rmidi;
481
482 #ifdef SUPPORT_JOYSTICK
483 struct gameport *gameport;
484 #endif
485
486 spinlock_t reg_lock;
487 };
488
489
490 /* read/write operations for dword register */
491 inline static void snd_cmipci_write(cmipci_t *cm, unsigned int cmd, unsigned int data)
492 {
493 outl(data, cm->iobase + cmd);
494 }
495 inline static unsigned int snd_cmipci_read(cmipci_t *cm, unsigned int cmd)
496 {
497 return inl(cm->iobase + cmd);
498 }
499
500 /* read/write operations for word register */
501 inline static void snd_cmipci_write_w(cmipci_t *cm, unsigned int cmd, unsigned short data)
502 {
503 outw(data, cm->iobase + cmd);
504 }
505 inline static unsigned short snd_cmipci_read_w(cmipci_t *cm, unsigned int cmd)
506 {
507 return inw(cm->iobase + cmd);
508 }
509
510 /* read/write operations for byte register */
511 inline static void snd_cmipci_write_b(cmipci_t *cm, unsigned int cmd, unsigned char data)
512 {
513 outb(data, cm->iobase + cmd);
514 }
515
516 inline static unsigned char snd_cmipci_read_b(cmipci_t *cm, unsigned int cmd)
517 {
518 return inb(cm->iobase + cmd);
519 }
520
521 /* bit operations for dword register */
522 static void snd_cmipci_set_bit(cmipci_t *cm, unsigned int cmd, unsigned int flag)
523 {
524 unsigned int val;
525 val = inl(cm->iobase + cmd);
526 val |= flag;
527 outl(val, cm->iobase + cmd);
528 }
529
530 static void snd_cmipci_clear_bit(cmipci_t *cm, unsigned int cmd, unsigned int flag)
531 {
532 unsigned int val;
533 val = inl(cm->iobase + cmd);
534 val &= ~flag;
535 outl(val, cm->iobase + cmd);
536 }
537
538 #if 0 // not used
539 /* bit operations for byte register */
540 static void snd_cmipci_set_bit_b(cmipci_t *cm, unsigned int cmd, unsigned char flag)
541 {
542 unsigned char val;
543 val = inb(cm->iobase + cmd);
544 val |= flag;
545 outb(val, cm->iobase + cmd);
546 }
547
548 static void snd_cmipci_clear_bit_b(cmipci_t *cm, unsigned int cmd, unsigned char flag)
549 {
550 unsigned char val;
551 val = inb(cm->iobase + cmd);
552 val &= ~flag;
553 outb(val, cm->iobase + cmd);
554 }
555 #endif
556
557
558 /*
559 * PCM interface
560 */
561
562 /*
563 * calculate frequency
564 */
565
566 static unsigned int rates[] = { 5512, 11025, 22050, 44100, 8000, 16000, 32000, 48000 };
567
568 static unsigned int snd_cmipci_rate_freq(unsigned int rate)
569 {
570 unsigned int i;
571 for (i = 0; i < ARRAY_SIZE(rates); i++) {
572 if (rates[i] == rate)
573 return i;
574 }
575 snd_BUG();
576 return 0;
577 }
578
579 #ifdef USE_VAR48KRATE
580 /*
581 * Determine PLL values for frequency setup, maybe the CMI8338 (CMI8738???)
582 * does it this way .. maybe not. Never get any information from C-Media about
583 * that <werner@suse.de>.
584 */
585 static int snd_cmipci_pll_rmn(unsigned int rate, unsigned int adcmult, int *r, int *m, int *n)
586 {
587 unsigned int delta, tolerance;
588 int xm, xn, xr;
589
590 for (*r = 0; rate < CM_MAXIMUM_RATE/adcmult; *r += (1<<5))
591 rate <<= 1;
592 *n = -1;
593 if (*r > 0xff)
594 goto out;
595 tolerance = rate*CM_TOLERANCE_RATE;
596
597 for (xn = (1+2); xn < (0x1f+2); xn++) {
598 for (xm = (1+2); xm < (0xff+2); xm++) {
599 xr = ((CM_REFFREQ_XIN/adcmult) * xm) / xn;
600
601 if (xr < rate)
602 delta = rate - xr;
603 else
604 delta = xr - rate;
605
606 /*
607 * If we found one, remember this,
608 * and try to find a closer one
609 */
610 if (delta < tolerance) {
611 tolerance = delta;
612 *m = xm - 2;
613 *n = xn - 2;
614 }
615 }
616 }
617 out:
618 return (*n > -1);
619 }
620
621 /*
622 * Program pll register bits, I assume that the 8 registers 0xf8 upto 0xff
623 * are mapped onto the 8 ADC/DAC sampling frequency which can be choosen
624 * at the register CM_REG_FUNCTRL1 (0x04).
625 * Problem: other ways are also possible (any information about that?)
626 */
627 static void snd_cmipci_set_pll(cmipci_t *cm, unsigned int rate, unsigned int slot)
628 {
629 unsigned int reg = CM_REG_PLL + slot;
630 /*
631 * Guess that this programs at reg. 0x04 the pos 15:13/12:10
632 * for DSFC/ASFC (000 upto 111).
633 */
634
635 /* FIXME: Init (Do we've to set an other register first before programming?) */
636
637 /* FIXME: Is this correct? Or shouldn't the m/n/r values be used for that? */
638 snd_cmipci_write_b(cm, reg, rate>>8);
639 snd_cmipci_write_b(cm, reg, rate&0xff);
640
641 /* FIXME: Setup (Do we've to set an other register first to enable this?) */
642 }
643 #endif /* USE_VAR48KRATE */
644
645 static int snd_cmipci_hw_params(snd_pcm_substream_t * substream,
646 snd_pcm_hw_params_t * hw_params)
647 {
648 return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
649 }
650
651 static int snd_cmipci_playback2_hw_params(snd_pcm_substream_t * substream,
652 snd_pcm_hw_params_t * hw_params)
653 {
654 cmipci_t *cm = snd_pcm_substream_chip(substream);
655 if (params_channels(hw_params) > 2) {
656 down(&cm->open_mutex);
657 if (cm->opened[CM_CH_PLAY]) {
658 up(&cm->open_mutex);
659 return -EBUSY;
660 }
661 /* reserve the channel A */
662 cm->opened[CM_CH_PLAY] = CM_OPEN_PLAYBACK_MULTI;
663 up(&cm->open_mutex);
664 }
665 return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
666 }
667
668 static void snd_cmipci_ch_reset(cmipci_t *cm, int ch)
669 {
670 int reset = CM_RST_CH0 << (cm->channel[ch].ch);
671 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | reset);
672 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~reset);
673 udelay(10);
674 }
675
676 static int snd_cmipci_hw_free(snd_pcm_substream_t * substream)
677 {
678 return snd_pcm_lib_free_pages(substream);
679 }
680
681
682 /*
683 */
684
685 static unsigned int hw_channels[] = {1, 2, 4, 5, 6, 8};
686 static snd_pcm_hw_constraint_list_t hw_constraints_channels_4 = {
687 .count = 3,
688 .list = hw_channels,
689 .mask = 0,
690 };
691 static snd_pcm_hw_constraint_list_t hw_constraints_channels_6 = {
692 .count = 5,
693 .list = hw_channels,
694 .mask = 0,
695 };
696 static snd_pcm_hw_constraint_list_t hw_constraints_channels_8 = {
697 .count = 6,
698 .list = hw_channels,
699 .mask = 0,
700 };
701
702 static int set_dac_channels(cmipci_t *cm, cmipci_pcm_t *rec, int channels)
703 {
704 if (channels > 2) {
705 if (! cm->can_multi_ch)
706 return -EINVAL;
707 if (rec->fmt != 0x03) /* stereo 16bit only */
708 return -EINVAL;
709
710 spin_lock_irq(&cm->reg_lock);
711 snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_NXCHG);
712 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
713 if (channels > 4) {
714 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D);
715 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_CHB3D5C);
716 } else {
717 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D5C);
718 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_CHB3D);
719 }
720 if (channels >= 6) {
721 snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_CHB3D6C);
722 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_ENCENTER);
723 } else {
724 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_CHB3D6C);
725 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_ENCENTER);
726 }
727 if (cm->chip_version == 68) {
728 if (channels == 8) {
729 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL_8768, CM_CHB3D8C);
730 } else {
731 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL_8768, CM_CHB3D8C);
732 }
733 }
734 spin_unlock_irq(&cm->reg_lock);
735
736 } else {
737 if (cm->can_multi_ch) {
738 spin_lock_irq(&cm->reg_lock);
739 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_NXCHG);
740 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D);
741 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D5C);
742 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_CHB3D6C);
743 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_ENCENTER);
744 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
745 spin_unlock_irq(&cm->reg_lock);
746 }
747 }
748 return 0;
749 }
750
751
752 /*
753 * prepare playback/capture channel
754 * channel to be used must have been set in rec->ch.
755 */
756 static int snd_cmipci_pcm_prepare(cmipci_t *cm, cmipci_pcm_t *rec,
757 snd_pcm_substream_t *substream)
758 {
759 unsigned int reg, freq, val;
760 snd_pcm_runtime_t *runtime = substream->runtime;
761
762 rec->fmt = 0;
763 rec->shift = 0;
764 if (snd_pcm_format_width(runtime->format) >= 16) {
765 rec->fmt |= 0x02;
766 if (snd_pcm_format_width(runtime->format) > 16)
767 rec->shift++; /* 24/32bit */
768 }
769 if (runtime->channels > 1)
770 rec->fmt |= 0x01;
771 if (rec->is_dac && set_dac_channels(cm, rec, runtime->channels) < 0) {
772 snd_printd("cannot set dac channels\n");
773 return -EINVAL;
774 }
775
776 rec->offset = runtime->dma_addr;
777 /* buffer and period sizes in frame */
778 rec->dma_size = runtime->buffer_size << rec->shift;
779 rec->period_size = runtime->period_size << rec->shift;
780 if (runtime->channels > 2) {
781 /* multi-channels */
782 rec->dma_size = (rec->dma_size * runtime->channels) / 2;
783 rec->period_size = (rec->period_size * runtime->channels) / 2;
784 }
785
786 spin_lock_irq(&cm->reg_lock);
787
788 /* set buffer address */
789 reg = rec->ch ? CM_REG_CH1_FRAME1 : CM_REG_CH0_FRAME1;
790 snd_cmipci_write(cm, reg, rec->offset);
791 /* program sample counts */
792 reg = rec->ch ? CM_REG_CH1_FRAME2 : CM_REG_CH0_FRAME2;
793 snd_cmipci_write_w(cm, reg, rec->dma_size - 1);
794 snd_cmipci_write_w(cm, reg + 2, rec->period_size - 1);
795
796 /* set adc/dac flag */
797 val = rec->ch ? CM_CHADC1 : CM_CHADC0;
798 if (rec->is_dac)
799 cm->ctrl &= ~val;
800 else
801 cm->ctrl |= val;
802 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
803 //snd_printd("cmipci: functrl0 = %08x\n", cm->ctrl);
804
805 /* set sample rate */
806 freq = snd_cmipci_rate_freq(runtime->rate);
807 val = snd_cmipci_read(cm, CM_REG_FUNCTRL1);
808 if (rec->ch) {
809 val &= ~CM_ASFC_MASK;
810 val |= (freq << CM_ASFC_SHIFT) & CM_ASFC_MASK;
811 } else {
812 val &= ~CM_DSFC_MASK;
813 val |= (freq << CM_DSFC_SHIFT) & CM_DSFC_MASK;
814 }
815 snd_cmipci_write(cm, CM_REG_FUNCTRL1, val);
816 //snd_printd("cmipci: functrl1 = %08x\n", val);
817
818 /* set format */
819 val = snd_cmipci_read(cm, CM_REG_CHFORMAT);
820 if (rec->ch) {
821 val &= ~CM_CH1FMT_MASK;
822 val |= rec->fmt << CM_CH1FMT_SHIFT;
823 } else {
824 val &= ~CM_CH0FMT_MASK;
825 val |= rec->fmt << CM_CH0FMT_SHIFT;
826 }
827 snd_cmipci_write(cm, CM_REG_CHFORMAT, val);
828 //snd_printd("cmipci: chformat = %08x\n", val);
829
830 rec->running = 0;
831 spin_unlock_irq(&cm->reg_lock);
832
833 return 0;
834 }
835
836 /*
837 * PCM trigger/stop
838 */
839 static int snd_cmipci_pcm_trigger(cmipci_t *cm, cmipci_pcm_t *rec,
840 snd_pcm_substream_t *substream, int cmd)
841 {
842 unsigned int inthld, chen, reset, pause;
843 int result = 0;
844
845 inthld = CM_CH0_INT_EN << rec->ch;
846 chen = CM_CHEN0 << rec->ch;
847 reset = CM_RST_CH0 << rec->ch;
848 pause = CM_PAUSE0 << rec->ch;
849
850 spin_lock(&cm->reg_lock);
851 switch (cmd) {
852 case SNDRV_PCM_TRIGGER_START:
853 rec->running = 1;
854 /* set interrupt */
855 snd_cmipci_set_bit(cm, CM_REG_INT_HLDCLR, inthld);
856 cm->ctrl |= chen;
857 /* enable channel */
858 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
859 //snd_printd("cmipci: functrl0 = %08x\n", cm->ctrl);
860 break;
861 case SNDRV_PCM_TRIGGER_STOP:
862 rec->running = 0;
863 /* disable interrupt */
864 snd_cmipci_clear_bit(cm, CM_REG_INT_HLDCLR, inthld);
865 /* reset */
866 cm->ctrl &= ~chen;
867 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | reset);
868 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~reset);
869 break;
870 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
871 cm->ctrl |= pause;
872 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
873 break;
874 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
875 cm->ctrl &= ~pause;
876 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
877 break;
878 default:
879 result = -EINVAL;
880 break;
881 }
882 spin_unlock(&cm->reg_lock);
883 return result;
884 }
885
886 /*
887 * return the current pointer
888 */
889 static snd_pcm_uframes_t snd_cmipci_pcm_pointer(cmipci_t *cm, cmipci_pcm_t *rec,
890 snd_pcm_substream_t *substream)
891 {
892 size_t ptr;
893 unsigned int reg;
894 if (!rec->running)
895 return 0;
896 #if 1 // this seems better..
897 reg = rec->ch ? CM_REG_CH1_FRAME2 : CM_REG_CH0_FRAME2;
898 ptr = rec->dma_size - (snd_cmipci_read_w(cm, reg) + 1);
899 ptr >>= rec->shift;
900 #else
901 reg = rec->ch ? CM_REG_CH1_FRAME1 : CM_REG_CH0_FRAME1;
902 ptr = snd_cmipci_read(cm, reg) - rec->offset;
903 ptr = bytes_to_frames(substream->runtime, ptr);
904 #endif
905 if (substream->runtime->channels > 2)
906 ptr = (ptr * 2) / substream->runtime->channels;
907 return ptr;
908 }
909
910 /*
911 * playback
912 */
913
914 static int snd_cmipci_playback_trigger(snd_pcm_substream_t *substream,
915 int cmd)
916 {
917 cmipci_t *cm = snd_pcm_substream_chip(substream);
918 return snd_cmipci_pcm_trigger(cm, &cm->channel[CM_CH_PLAY], substream, cmd);
919 }
920
921 static snd_pcm_uframes_t snd_cmipci_playback_pointer(snd_pcm_substream_t *substream)
922 {
923 cmipci_t *cm = snd_pcm_substream_chip(substream);
924 return snd_cmipci_pcm_pointer(cm, &cm->channel[CM_CH_PLAY], substream);
925 }
926
927
928
929 /*
930 * capture
931 */
932
933 static int snd_cmipci_capture_trigger(snd_pcm_substream_t *substream,
934 int cmd)
935 {
936 cmipci_t *cm = snd_pcm_substream_chip(substream);
937 return snd_cmipci_pcm_trigger(cm, &cm->channel[CM_CH_CAPT], substream, cmd);
938 }
939
940 static snd_pcm_uframes_t snd_cmipci_capture_pointer(snd_pcm_substream_t *substream)
941 {
942 cmipci_t *cm = snd_pcm_substream_chip(substream);
943 return snd_cmipci_pcm_pointer(cm, &cm->channel[CM_CH_CAPT], substream);
944 }
945
946
947 /*
948 * hw preparation for spdif
949 */
950
951 static int snd_cmipci_spdif_default_info(snd_kcontrol_t *kcontrol,
952 snd_ctl_elem_info_t *uinfo)
953 {
954 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
955 uinfo->count = 1;
956 return 0;
957 }
958
959 static int snd_cmipci_spdif_default_get(snd_kcontrol_t *kcontrol,
960 snd_ctl_elem_value_t *ucontrol)
961 {
962 cmipci_t *chip = snd_kcontrol_chip(kcontrol);
963 int i;
964
965 spin_lock_irq(&chip->reg_lock);
966 for (i = 0; i < 4; i++)
967 ucontrol->value.iec958.status[i] = (chip->dig_status >> (i * 8)) & 0xff;
968 spin_unlock_irq(&chip->reg_lock);
969 return 0;
970 }
971
972 static int snd_cmipci_spdif_default_put(snd_kcontrol_t * kcontrol,
973 snd_ctl_elem_value_t * ucontrol)
974 {
975 cmipci_t *chip = snd_kcontrol_chip(kcontrol);
976 int i, change;
977 unsigned int val;
978
979 val = 0;
980 spin_lock_irq(&chip->reg_lock);
981 for (i = 0; i < 4; i++)
982 val |= (unsigned int)ucontrol->value.iec958.status[i] << (i * 8);
983 change = val != chip->dig_status;
984 chip->dig_status = val;
985 spin_unlock_irq(&chip->reg_lock);
986 return change;
987 }
988
989 static snd_kcontrol_new_t snd_cmipci_spdif_default __devinitdata =
990 {
991 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
992 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
993 .info = snd_cmipci_spdif_default_info,
994 .get = snd_cmipci_spdif_default_get,
995 .put = snd_cmipci_spdif_default_put
996 };
997
998 static int snd_cmipci_spdif_mask_info(snd_kcontrol_t *kcontrol,
999 snd_ctl_elem_info_t *uinfo)
1000 {
1001 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1002 uinfo->count = 1;
1003 return 0;
1004 }
1005
1006 static int snd_cmipci_spdif_mask_get(snd_kcontrol_t * kcontrol,
1007 snd_ctl_elem_value_t *ucontrol)
1008 {
1009 ucontrol->value.iec958.status[0] = 0xff;
1010 ucontrol->value.iec958.status[1] = 0xff;
1011 ucontrol->value.iec958.status[2] = 0xff;
1012 ucontrol->value.iec958.status[3] = 0xff;
1013 return 0;
1014 }
1015
1016 static snd_kcontrol_new_t snd_cmipci_spdif_mask __devinitdata =
1017 {
1018 .access = SNDRV_CTL_ELEM_ACCESS_READ,
1019 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1020 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),
1021 .info = snd_cmipci_spdif_mask_info,
1022 .get = snd_cmipci_spdif_mask_get,
1023 };
1024
1025 static int snd_cmipci_spdif_stream_info(snd_kcontrol_t *kcontrol,
1026 snd_ctl_elem_info_t *uinfo)
1027 {
1028 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1029 uinfo->count = 1;
1030 return 0;
1031 }
1032
1033 static int snd_cmipci_spdif_stream_get(snd_kcontrol_t *kcontrol,
1034 snd_ctl_elem_value_t *ucontrol)
1035 {
1036 cmipci_t *chip = snd_kcontrol_chip(kcontrol);
1037 int i;
1038
1039 spin_lock_irq(&chip->reg_lock);
1040 for (i = 0; i < 4; i++)
1041 ucontrol->value.iec958.status[i] = (chip->dig_pcm_status >> (i * 8)) & 0xff;
1042 spin_unlock_irq(&chip->reg_lock);
1043 return 0;
1044 }
1045
1046 static int snd_cmipci_spdif_stream_put(snd_kcontrol_t *kcontrol,
1047 snd_ctl_elem_value_t *ucontrol)
1048 {
1049 cmipci_t *chip = snd_kcontrol_chip(kcontrol);
1050 int i, change;
1051 unsigned int val;
1052
1053 val = 0;
1054 spin_lock_irq(&chip->reg_lock);
1055 for (i = 0; i < 4; i++)
1056 val |= (unsigned int)ucontrol->value.iec958.status[i] << (i * 8);
1057 change = val != chip->dig_pcm_status;
1058 chip->dig_pcm_status = val;
1059 spin_unlock_irq(&chip->reg_lock);
1060 return change;
1061 }
1062
1063 static snd_kcontrol_new_t snd_cmipci_spdif_stream __devinitdata =
1064 {
1065 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
1066 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1067 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
1068 .info = snd_cmipci_spdif_stream_info,
1069 .get = snd_cmipci_spdif_stream_get,
1070 .put = snd_cmipci_spdif_stream_put
1071 };
1072
1073 /*
1074 */
1075
1076 /* save mixer setting and mute for AC3 playback */
1077 static int save_mixer_state(cmipci_t *cm)
1078 {
1079 if (! cm->mixer_insensitive) {
1080 snd_ctl_elem_value_t *val;
1081 unsigned int i;
1082
1083 val = kmalloc(sizeof(*val), GFP_ATOMIC);
1084 if (!val)
1085 return -ENOMEM;
1086 for (i = 0; i < CM_SAVED_MIXERS; i++) {
1087 snd_kcontrol_t *ctl = cm->mixer_res_ctl[i];
1088 if (ctl) {
1089 int event;
1090 memset(val, 0, sizeof(*val));
1091 ctl->get(ctl, val);
1092 cm->mixer_res_status[i] = val->value.integer.value[0];
1093 val->value.integer.value[0] = cm_saved_mixer[i].toggle_on;
1094 event = SNDRV_CTL_EVENT_MASK_INFO;
1095 if (cm->mixer_res_status[i] != val->value.integer.value[0]) {
1096 ctl->put(ctl, val); /* toggle */
1097 event |= SNDRV_CTL_EVENT_MASK_VALUE;
1098 }
1099 ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1100 snd_ctl_notify(cm->card, event, &ctl->id);
1101 }
1102 }
1103 kfree(val);
1104 cm->mixer_insensitive = 1;
1105 }
1106 return 0;
1107 }
1108
1109
1110 /* restore the previously saved mixer status */
1111 static void restore_mixer_state(cmipci_t *cm)
1112 {
1113 if (cm->mixer_insensitive) {
1114 snd_ctl_elem_value_t *val;
1115 unsigned int i;
1116
1117 val = kmalloc(sizeof(*val), GFP_KERNEL);
1118 if (!val)
1119 return;
1120 cm->mixer_insensitive = 0; /* at first clear this;
1121 otherwise the changes will be ignored */
1122 for (i = 0; i < CM_SAVED_MIXERS; i++) {
1123 snd_kcontrol_t *ctl = cm->mixer_res_ctl[i];
1124 if (ctl) {
1125 int event;
1126
1127 memset(val, 0, sizeof(*val));
1128 ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1129 ctl->get(ctl, val);
1130 event = SNDRV_CTL_EVENT_MASK_INFO;
1131 if (val->value.integer.value[0] != cm->mixer_res_status[i]) {
1132 val->value.integer.value[0] = cm->mixer_res_status[i];
1133 ctl->put(ctl, val);
1134 event |= SNDRV_CTL_EVENT_MASK_VALUE;
1135 }
1136 snd_ctl_notify(cm->card, event, &ctl->id);
1137 }
1138 }
1139 kfree(val);
1140 }
1141 }
1142
1143 /* spinlock held! */
1144 static void setup_ac3(cmipci_t *cm, snd_pcm_substream_t *subs, int do_ac3, int rate)
1145 {
1146 if (do_ac3) {
1147 /* AC3EN for 037 */
1148 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_AC3EN1);
1149 /* AC3EN for 039 */
1150 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_AC3EN2);
1151
1152 if (cm->can_ac3_hw) {
1153 /* SPD24SEL for 037, 0x02 */
1154 /* SPD24SEL for 039, 0x20, but cannot be set */
1155 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1156 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1157 } else { /* can_ac3_sw */
1158 /* SPD32SEL for 037 & 039, 0x20 */
1159 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1160 /* set 176K sample rate to fix 033 HW bug */
1161 if (cm->chip_version == 33) {
1162 if (rate >= 48000) {
1163 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K);
1164 } else {
1165 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K);
1166 }
1167 }
1168 }
1169
1170 } else {
1171 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_AC3EN1);
1172 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_AC3EN2);
1173
1174 if (cm->can_ac3_hw) {
1175 /* chip model >= 37 */
1176 if (snd_pcm_format_width(subs->runtime->format) > 16) {
1177 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1178 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1179 } else {
1180 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1181 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1182 }
1183 } else {
1184 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1185 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1186 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K);
1187 }
1188 }
1189 }
1190
1191 static int setup_spdif_playback(cmipci_t *cm, snd_pcm_substream_t *subs, int up, int do_ac3)
1192 {
1193 int rate, err;
1194
1195 rate = subs->runtime->rate;
1196
1197 if (up && do_ac3)
1198 if ((err = save_mixer_state(cm)) < 0)
1199 return err;
1200
1201 spin_lock_irq(&cm->reg_lock);
1202 cm->spdif_playback_avail = up;
1203 if (up) {
1204 /* they are controlled via "IEC958 Output Switch" */
1205 /* snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT); */
1206 /* snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_SPDO2DAC); */
1207 if (cm->spdif_playback_enabled)
1208 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
1209 setup_ac3(cm, subs, do_ac3, rate);
1210
1211 if (rate == 48000)
1212 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K | CM_SPDF_AC97);
1213 else
1214 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K | CM_SPDF_AC97);
1215
1216 } else {
1217 /* they are controlled via "IEC958 Output Switch" */
1218 /* snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT); */
1219 /* snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_SPDO2DAC); */
1220 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
1221 setup_ac3(cm, subs, 0, 0);
1222 }
1223 spin_unlock_irq(&cm->reg_lock);
1224 return 0;
1225 }
1226
1227
1228 /*
1229 * preparation
1230 */
1231
1232 /* playback - enable spdif only on the certain condition */
1233 static int snd_cmipci_playback_prepare(snd_pcm_substream_t *substream)
1234 {
1235 cmipci_t *cm = snd_pcm_substream_chip(substream);
1236 int rate = substream->runtime->rate;
1237 int err, do_spdif, do_ac3 = 0;
1238
1239 do_spdif = ((rate == 44100 || rate == 48000) &&
1240 substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE &&
1241 substream->runtime->channels == 2);
1242 if (do_spdif && cm->can_ac3_hw)
1243 do_ac3 = cm->dig_pcm_status & IEC958_AES0_NONAUDIO;
1244 if ((err = setup_spdif_playback(cm, substream, do_spdif, do_ac3)) < 0)
1245 return err;
1246 return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_PLAY], substream);
1247 }
1248
1249 /* playback (via device #2) - enable spdif always */
1250 static int snd_cmipci_playback_spdif_prepare(snd_pcm_substream_t *substream)
1251 {
1252 cmipci_t *cm = snd_pcm_substream_chip(substream);
1253 int err, do_ac3;
1254
1255 if (cm->can_ac3_hw)
1256 do_ac3 = cm->dig_pcm_status & IEC958_AES0_NONAUDIO;
1257 else
1258 do_ac3 = 1; /* doesn't matter */
1259 if ((err = setup_spdif_playback(cm, substream, 1, do_ac3)) < 0)
1260 return err;
1261 return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_PLAY], substream);
1262 }
1263
1264 static int snd_cmipci_playback_hw_free(snd_pcm_substream_t *substream)
1265 {
1266 cmipci_t *cm = snd_pcm_substream_chip(substream);
1267 setup_spdif_playback(cm, substream, 0, 0);
1268 restore_mixer_state(cm);
1269 return snd_cmipci_hw_free(substream);
1270 }
1271
1272 /* capture */
1273 static int snd_cmipci_capture_prepare(snd_pcm_substream_t *substream)
1274 {
1275 cmipci_t *cm = snd_pcm_substream_chip(substream);
1276 return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_CAPT], substream);
1277 }
1278
1279 /* capture with spdif (via device #2) */
1280 static int snd_cmipci_capture_spdif_prepare(snd_pcm_substream_t *substream)
1281 {
1282 cmipci_t *cm = snd_pcm_substream_chip(substream);
1283
1284 spin_lock_irq(&cm->reg_lock);
1285 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_CAPTURE_SPDF);
1286 spin_unlock_irq(&cm->reg_lock);
1287
1288 return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_CAPT], substream);
1289 }
1290
1291 static int snd_cmipci_capture_spdif_hw_free(snd_pcm_substream_t *subs)
1292 {
1293 cmipci_t *cm = snd_pcm_substream_chip(subs);
1294
1295 spin_lock_irq(&cm->reg_lock);
1296 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_CAPTURE_SPDF);
1297 spin_unlock_irq(&cm->reg_lock);
1298
1299 return snd_cmipci_hw_free(subs);
1300 }
1301
1302
1303 /*
1304 * interrupt handler
1305 */
1306 static irqreturn_t snd_cmipci_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1307 {
1308 cmipci_t *cm = dev_id;
1309 unsigned int status, mask = 0;
1310
1311 /* fastpath out, to ease interrupt sharing */
1312 status = snd_cmipci_read(cm, CM_REG_INT_STATUS);
1313 if (!(status & CM_INTR))
1314 return IRQ_NONE;
1315
1316 /* acknowledge interrupt */
1317 spin_lock(&cm->reg_lock);
1318 if (status & CM_CHINT0)
1319 mask |= CM_CH0_INT_EN;
1320 if (status & CM_CHINT1)
1321 mask |= CM_CH1_INT_EN;
1322 snd_cmipci_clear_bit(cm, CM_REG_INT_HLDCLR, mask);
1323 snd_cmipci_set_bit(cm, CM_REG_INT_HLDCLR, mask);
1324 spin_unlock(&cm->reg_lock);
1325
1326 if (cm->rmidi && (status & CM_UARTINT))
1327 snd_mpu401_uart_interrupt(irq, cm->rmidi->private_data, regs);
1328
1329 if (cm->pcm) {
1330 if ((status & CM_CHINT0) && cm->channel[0].running)
1331 snd_pcm_period_elapsed(cm->channel[0].substream);
1332 if ((status & CM_CHINT1) && cm->channel[1].running)
1333 snd_pcm_period_elapsed(cm->channel[1].substream);
1334 }
1335 return IRQ_HANDLED;
1336 }
1337
1338 /*
1339 * h/w infos
1340 */
1341
1342 /* playback on channel A */
1343 static snd_pcm_hardware_t snd_cmipci_playback =
1344 {
1345 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1346 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1347 SNDRV_PCM_INFO_MMAP_VALID),
1348 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1349 .rates = SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000,
1350 .rate_min = 5512,
1351 .rate_max = 48000,
1352 .channels_min = 1,
1353 .channels_max = 2,
1354 .buffer_bytes_max = (128*1024),
1355 .period_bytes_min = 64,
1356 .period_bytes_max = (128*1024),
1357 .periods_min = 2,
1358 .periods_max = 1024,
1359 .fifo_size = 0,
1360 };
1361
1362 /* capture on channel B */
1363 static snd_pcm_hardware_t snd_cmipci_capture =
1364 {
1365 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1366 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1367 SNDRV_PCM_INFO_MMAP_VALID),
1368 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1369 .rates = SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000,
1370 .rate_min = 5512,
1371 .rate_max = 48000,
1372 .channels_min = 1,
1373 .channels_max = 2,
1374 .buffer_bytes_max = (128*1024),
1375 .period_bytes_min = 64,
1376 .period_bytes_max = (128*1024),
1377 .periods_min = 2,
1378 .periods_max = 1024,
1379 .fifo_size = 0,
1380 };
1381
1382 /* playback on channel B - stereo 16bit only? */
1383 static snd_pcm_hardware_t snd_cmipci_playback2 =
1384 {
1385 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1386 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1387 SNDRV_PCM_INFO_MMAP_VALID),
1388 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1389 .rates = SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000,
1390 .rate_min = 5512,
1391 .rate_max = 48000,
1392 .channels_min = 2,
1393 .channels_max = 2,
1394 .buffer_bytes_max = (128*1024),
1395 .period_bytes_min = 64,
1396 .period_bytes_max = (128*1024),
1397 .periods_min = 2,
1398 .periods_max = 1024,
1399 .fifo_size = 0,
1400 };
1401
1402 /* spdif playback on channel A */
1403 static snd_pcm_hardware_t snd_cmipci_playback_spdif =
1404 {
1405 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1406 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1407 SNDRV_PCM_INFO_MMAP_VALID),
1408 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1409 .rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
1410 .rate_min = 44100,
1411 .rate_max = 48000,
1412 .channels_min = 2,
1413 .channels_max = 2,
1414 .buffer_bytes_max = (128*1024),
1415 .period_bytes_min = 64,
1416 .period_bytes_max = (128*1024),
1417 .periods_min = 2,
1418 .periods_max = 1024,
1419 .fifo_size = 0,
1420 };
1421
1422 /* spdif playback on channel A (32bit, IEC958 subframes) */
1423 static snd_pcm_hardware_t snd_cmipci_playback_iec958_subframe =
1424 {
1425 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1426 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1427 SNDRV_PCM_INFO_MMAP_VALID),
1428 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
1429 .rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
1430 .rate_min = 44100,
1431 .rate_max = 48000,
1432 .channels_min = 2,
1433 .channels_max = 2,
1434 .buffer_bytes_max = (128*1024),
1435 .period_bytes_min = 64,
1436 .period_bytes_max = (128*1024),
1437 .periods_min = 2,
1438 .periods_max = 1024,
1439 .fifo_size = 0,
1440 };
1441
1442 /* spdif capture on channel B */
1443 static snd_pcm_hardware_t snd_cmipci_capture_spdif =
1444 {
1445 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1446 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1447 SNDRV_PCM_INFO_MMAP_VALID),
1448 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1449 .rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
1450 .rate_min = 44100,
1451 .rate_max = 48000,
1452 .channels_min = 2,
1453 .channels_max = 2,
1454 .buffer_bytes_max = (128*1024),
1455 .period_bytes_min = 64,
1456 .period_bytes_max = (128*1024),
1457 .periods_min = 2,
1458 .periods_max = 1024,
1459 .fifo_size = 0,
1460 };
1461
1462 /*
1463 * check device open/close
1464 */
1465 static int open_device_check(cmipci_t *cm, int mode, snd_pcm_substream_t *subs)
1466 {
1467 int ch = mode & CM_OPEN_CH_MASK;
1468
1469 /* FIXME: a file should wait until the device becomes free
1470 * when it's opened on blocking mode. however, since the current
1471 * pcm framework doesn't pass file pointer before actually opened,
1472 * we can't know whether blocking mode or not in open callback..
1473 */
1474 down(&cm->open_mutex);
1475 if (cm->opened[ch]) {
1476 up(&cm->open_mutex);
1477 return -EBUSY;
1478 }
1479 cm->opened[ch] = mode;
1480 cm->channel[ch].substream = subs;
1481 if (! (mode & CM_OPEN_DAC)) {
1482 /* disable dual DAC mode */
1483 cm->channel[ch].is_dac = 0;
1484 spin_lock_irq(&cm->reg_lock);
1485 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC);
1486 spin_unlock_irq(&cm->reg_lock);
1487 }
1488 up(&cm->open_mutex);
1489 return 0;
1490 }
1491
1492 static void close_device_check(cmipci_t *cm, int mode)
1493 {
1494 int ch = mode & CM_OPEN_CH_MASK;
1495
1496 down(&cm->open_mutex);
1497 if (cm->opened[ch] == mode) {
1498 if (cm->channel[ch].substream) {
1499 snd_cmipci_ch_reset(cm, ch);
1500 cm->channel[ch].running = 0;
1501 cm->channel[ch].substream = NULL;
1502 }
1503 cm->opened[ch] = 0;
1504 if (! cm->channel[ch].is_dac) {
1505 /* enable dual DAC mode again */
1506 cm->channel[ch].is_dac = 1;
1507 spin_lock_irq(&cm->reg_lock);
1508 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC);
1509 spin_unlock_irq(&cm->reg_lock);
1510 }
1511 }
1512 up(&cm->open_mutex);
1513 }
1514
1515 /*
1516 */
1517
1518 static int snd_cmipci_playback_open(snd_pcm_substream_t *substream)
1519 {
1520 cmipci_t *cm = snd_pcm_substream_chip(substream);
1521 snd_pcm_runtime_t *runtime = substream->runtime;
1522 int err;
1523
1524 if ((err = open_device_check(cm, CM_OPEN_PLAYBACK, substream)) < 0)
1525 return err;
1526 runtime->hw = snd_cmipci_playback;
1527 runtime->hw.channels_max = cm->max_channels;
1528 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000);
1529 cm->dig_pcm_status = cm->dig_status;
1530 return 0;
1531 }
1532
1533 static int snd_cmipci_capture_open(snd_pcm_substream_t *substream)
1534 {
1535 cmipci_t *cm = snd_pcm_substream_chip(substream);
1536 snd_pcm_runtime_t *runtime = substream->runtime;
1537 int err;
1538
1539 if ((err = open_device_check(cm, CM_OPEN_CAPTURE, substream)) < 0)
1540 return err;
1541 runtime->hw = snd_cmipci_capture;
1542 if (cm->chip_version == 68) { // 8768 only supports 44k/48k recording
1543 runtime->hw.rate_min = 41000;
1544 runtime->hw.rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000;
1545 }
1546 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000);
1547 return 0;
1548 }
1549
1550 static int snd_cmipci_playback2_open(snd_pcm_substream_t *substream)
1551 {
1552 cmipci_t *cm = snd_pcm_substream_chip(substream);
1553 snd_pcm_runtime_t *runtime = substream->runtime;
1554 int err;
1555
1556 if ((err = open_device_check(cm, CM_OPEN_PLAYBACK2, substream)) < 0) /* use channel B */
1557 return err;
1558 runtime->hw = snd_cmipci_playback2;
1559 down(&cm->open_mutex);
1560 if (! cm->opened[CM_CH_PLAY]) {
1561 if (cm->can_multi_ch) {
1562 runtime->hw.channels_max = cm->max_channels;
1563 if (cm->max_channels == 4)
1564 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_4);
1565 else if (cm->max_channels == 6)
1566 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_6);
1567 else if (cm->max_channels == 8)
1568 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_8);
1569 }
1570 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000);
1571 }
1572 up(&cm->open_mutex);
1573 return 0;
1574 }
1575
1576 static int snd_cmipci_playback_spdif_open(snd_pcm_substream_t *substream)
1577 {
1578 cmipci_t *cm = snd_pcm_substream_chip(substream);
1579 snd_pcm_runtime_t *runtime = substream->runtime;
1580 int err;
1581
1582 if ((err = open_device_check(cm, CM_OPEN_SPDIF_PLAYBACK, substream)) < 0) /* use channel A */
1583 return err;
1584 if (cm->can_ac3_hw) {
1585 runtime->hw = snd_cmipci_playback_spdif;
1586 if (cm->chip_version >= 37)
1587 runtime->hw.formats |= SNDRV_PCM_FMTBIT_S32_LE;
1588 } else {
1589 runtime->hw = snd_cmipci_playback_iec958_subframe;
1590 }
1591 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x40000);
1592 cm->dig_pcm_status = cm->dig_status;
1593 return 0;
1594 }
1595
1596 static int snd_cmipci_capture_spdif_open(snd_pcm_substream_t * substream)
1597 {
1598 cmipci_t *cm = snd_pcm_substream_chip(substream);
1599 snd_pcm_runtime_t *runtime = substream->runtime;
1600 int err;
1601
1602 if ((err = open_device_check(cm, CM_OPEN_SPDIF_CAPTURE, substream)) < 0) /* use channel B */
1603 return err;
1604 runtime->hw = snd_cmipci_capture_spdif;
1605 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x40000);
1606 return 0;
1607 }
1608
1609
1610 /*
1611 */
1612
1613 static int snd_cmipci_playback_close(snd_pcm_substream_t * substream)
1614 {
1615 cmipci_t *cm = snd_pcm_substream_chip(substream);
1616 close_device_check(cm, CM_OPEN_PLAYBACK);
1617 return 0;
1618 }
1619
1620 static int snd_cmipci_capture_close(snd_pcm_substream_t * substream)
1621 {
1622 cmipci_t *cm = snd_pcm_substream_chip(substream);
1623 close_device_check(cm, CM_OPEN_CAPTURE);
1624 return 0;
1625 }
1626
1627 static int snd_cmipci_playback2_close(snd_pcm_substream_t * substream)
1628 {
1629 cmipci_t *cm = snd_pcm_substream_chip(substream);
1630 close_device_check(cm, CM_OPEN_PLAYBACK2);
1631 close_device_check(cm, CM_OPEN_PLAYBACK_MULTI);
1632 return 0;
1633 }
1634
1635 static int snd_cmipci_playback_spdif_close(snd_pcm_substream_t * substream)
1636 {
1637 cmipci_t *cm = snd_pcm_substream_chip(substream);
1638 close_device_check(cm, CM_OPEN_SPDIF_PLAYBACK);
1639 return 0;
1640 }
1641
1642 static int snd_cmipci_capture_spdif_close(snd_pcm_substream_t * substream)
1643 {
1644 cmipci_t *cm = snd_pcm_substream_chip(substream);
1645 close_device_check(cm, CM_OPEN_SPDIF_CAPTURE);
1646 return 0;
1647 }
1648
1649
1650 /*
1651 */
1652
1653 static snd_pcm_ops_t snd_cmipci_playback_ops = {
1654 .open = snd_cmipci_playback_open,
1655 .close = snd_cmipci_playback_close,
1656 .ioctl = snd_pcm_lib_ioctl,
1657 .hw_params = snd_cmipci_hw_params,
1658 .hw_free = snd_cmipci_playback_hw_free,
1659 .prepare = snd_cmipci_playback_prepare,
1660 .trigger = snd_cmipci_playback_trigger,
1661 .pointer = snd_cmipci_playback_pointer,
1662 };
1663
1664 static snd_pcm_ops_t snd_cmipci_capture_ops = {
1665 .open = snd_cmipci_capture_open,
1666 .close = snd_cmipci_capture_close,
1667 .ioctl = snd_pcm_lib_ioctl,
1668 .hw_params = snd_cmipci_hw_params,
1669 .hw_free = snd_cmipci_hw_free,
1670 .prepare = snd_cmipci_capture_prepare,
1671 .trigger = snd_cmipci_capture_trigger,
1672 .pointer = snd_cmipci_capture_pointer,
1673 };
1674
1675 static snd_pcm_ops_t snd_cmipci_playback2_ops = {
1676 .open = snd_cmipci_playback2_open,
1677 .close = snd_cmipci_playback2_close,
1678 .ioctl = snd_pcm_lib_ioctl,
1679 .hw_params = snd_cmipci_playback2_hw_params,
1680 .hw_free = snd_cmipci_hw_free,
1681 .prepare = snd_cmipci_capture_prepare, /* channel B */
1682 .trigger = snd_cmipci_capture_trigger, /* channel B */
1683 .pointer = snd_cmipci_capture_pointer, /* channel B */
1684 };
1685
1686 static snd_pcm_ops_t snd_cmipci_playback_spdif_ops = {
1687 .open = snd_cmipci_playback_spdif_open,
1688 .close = snd_cmipci_playback_spdif_close,
1689 .ioctl = snd_pcm_lib_ioctl,
1690 .hw_params = snd_cmipci_hw_params,
1691 .hw_free = snd_cmipci_playback_hw_free,
1692 .prepare = snd_cmipci_playback_spdif_prepare, /* set up rate */
1693 .trigger = snd_cmipci_playback_trigger,
1694 .pointer = snd_cmipci_playback_pointer,
1695 };
1696
1697 static snd_pcm_ops_t snd_cmipci_capture_spdif_ops = {
1698 .open = snd_cmipci_capture_spdif_open,
1699 .close = snd_cmipci_capture_spdif_close,
1700 .ioctl = snd_pcm_lib_ioctl,
1701 .hw_params = snd_cmipci_hw_params,
1702 .hw_free = snd_cmipci_capture_spdif_hw_free,
1703 .prepare = snd_cmipci_capture_spdif_prepare,
1704 .trigger = snd_cmipci_capture_trigger,
1705 .pointer = snd_cmipci_capture_pointer,
1706 };
1707
1708
1709 /*
1710 */
1711
1712 static void snd_cmipci_pcm_free(snd_pcm_t *pcm)
1713 {
1714 snd_pcm_lib_preallocate_free_for_all(pcm);
1715 }
1716
1717 static int __devinit snd_cmipci_pcm_new(cmipci_t *cm, int device)
1718 {
1719 snd_pcm_t *pcm;
1720 int err;
1721
1722 err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 1, &pcm);
1723 if (err < 0)
1724 return err;
1725
1726 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback_ops);
1727 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cmipci_capture_ops);
1728
1729 pcm->private_data = cm;
1730 pcm->private_free = snd_cmipci_pcm_free;
1731 pcm->info_flags = 0;
1732 strcpy(pcm->name, "C-Media PCI DAC/ADC");
1733 cm->pcm = pcm;
1734
1735 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1736 snd_dma_pci_data(cm->pci), 64*1024, 128*1024);
1737
1738 return 0;
1739 }
1740
1741 static int __devinit snd_cmipci_pcm2_new(cmipci_t *cm, int device)
1742 {
1743 snd_pcm_t *pcm;
1744 int err;
1745
1746 err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 0, &pcm);
1747 if (err < 0)
1748 return err;
1749
1750 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback2_ops);
1751
1752 pcm->private_data = cm;
1753 pcm->private_free = snd_cmipci_pcm_free;
1754 pcm->info_flags = 0;
1755 strcpy(pcm->name, "C-Media PCI 2nd DAC");
1756 cm->pcm2 = pcm;
1757
1758 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1759 snd_dma_pci_data(cm->pci), 64*1024, 128*1024);
1760
1761 return 0;
1762 }
1763
1764 static int __devinit snd_cmipci_pcm_spdif_new(cmipci_t *cm, int device)
1765 {
1766 snd_pcm_t *pcm;
1767 int err;
1768
1769 err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 1, &pcm);
1770 if (err < 0)
1771 return err;
1772
1773 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback_spdif_ops);
1774 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cmipci_capture_spdif_ops);
1775
1776 pcm->private_data = cm;
1777 pcm->private_free = snd_cmipci_pcm_free;
1778 pcm->info_flags = 0;
1779 strcpy(pcm->name, "C-Media PCI IEC958");
1780 cm->pcm_spdif = pcm;
1781
1782 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1783 snd_dma_pci_data(cm->pci), 64*1024, 128*1024);
1784
1785 return 0;
1786 }
1787
1788 /*
1789 * mixer interface:
1790 * - CM8338/8738 has a compatible mixer interface with SB16, but
1791 * lack of some elements like tone control, i/o gain and AGC.
1792 * - Access to native registers:
1793 * - A 3D switch
1794 * - Output mute switches
1795 */
1796
1797 static void snd_cmipci_mixer_write(cmipci_t *s, unsigned char idx, unsigned char data)
1798 {
1799 outb(idx, s->iobase + CM_REG_SB16_ADDR);
1800 outb(data, s->iobase + CM_REG_SB16_DATA);
1801 }
1802
1803 static unsigned char snd_cmipci_mixer_read(cmipci_t *s, unsigned char idx)
1804 {
1805 unsigned char v;
1806
1807 outb(idx, s->iobase + CM_REG_SB16_ADDR);
1808 v = inb(s->iobase + CM_REG_SB16_DATA);
1809 return v;
1810 }
1811
1812 /*
1813 * general mixer element
1814 */
1815 typedef struct cmipci_sb_reg {
1816 unsigned int left_reg, right_reg;
1817 unsigned int left_shift, right_shift;
1818 unsigned int mask;
1819 unsigned int invert: 1;
1820 unsigned int stereo: 1;
1821 } cmipci_sb_reg_t;
1822
1823 #define COMPOSE_SB_REG(lreg,rreg,lshift,rshift,mask,invert,stereo) \
1824 ((lreg) | ((rreg) << 8) | (lshift << 16) | (rshift << 19) | (mask << 24) | (invert << 22) | (stereo << 23))
1825
1826 #define CMIPCI_DOUBLE(xname, left_reg, right_reg, left_shift, right_shift, mask, invert, stereo) \
1827 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1828 .info = snd_cmipci_info_volume, \
1829 .get = snd_cmipci_get_volume, .put = snd_cmipci_put_volume, \
1830 .private_value = COMPOSE_SB_REG(left_reg, right_reg, left_shift, right_shift, mask, invert, stereo), \
1831 }
1832
1833 #define CMIPCI_SB_VOL_STEREO(xname,reg,shift,mask) CMIPCI_DOUBLE(xname, reg, reg+1, shift, shift, mask, 0, 1)
1834 #define CMIPCI_SB_VOL_MONO(xname,reg,shift,mask) CMIPCI_DOUBLE(xname, reg, reg, shift, shift, mask, 0, 0)
1835 #define CMIPCI_SB_SW_STEREO(xname,lshift,rshift) CMIPCI_DOUBLE(xname, SB_DSP4_OUTPUT_SW, SB_DSP4_OUTPUT_SW, lshift, rshift, 1, 0, 1)
1836 #define CMIPCI_SB_SW_MONO(xname,shift) CMIPCI_DOUBLE(xname, SB_DSP4_OUTPUT_SW, SB_DSP4_OUTPUT_SW, shift, shift, 1, 0, 0)
1837
1838 static void cmipci_sb_reg_decode(cmipci_sb_reg_t *r, unsigned long val)
1839 {
1840 r->left_reg = val & 0xff;
1841 r->right_reg = (val >> 8) & 0xff;
1842 r->left_shift = (val >> 16) & 0x07;
1843 r->right_shift = (val >> 19) & 0x07;
1844 r->invert = (val >> 22) & 1;
1845 r->stereo = (val >> 23) & 1;
1846 r->mask = (val >> 24) & 0xff;
1847 }
1848
1849 static int snd_cmipci_info_volume(snd_kcontrol_t * kcontrol, snd_ctl_elem_info_t * uinfo)
1850 {
1851 cmipci_sb_reg_t reg;
1852
1853 cmipci_sb_reg_decode(&reg, kcontrol->private_value);
1854 uinfo->type = reg.mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
1855 uinfo->count = reg.stereo + 1;
1856 uinfo->value.integer.min = 0;
1857 uinfo->value.integer.max = reg.mask;
1858 return 0;
1859 }
1860
1861 static int snd_cmipci_get_volume(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1862 {
1863 cmipci_t *cm = snd_kcontrol_chip(kcontrol);
1864 cmipci_sb_reg_t reg;
1865 int val;
1866
1867 cmipci_sb_reg_decode(&reg, kcontrol->private_value);
1868 spin_lock_irq(&cm->reg_lock);
1869 val = (snd_cmipci_mixer_read(cm, reg.left_reg) >> reg.left_shift) & reg.mask;
1870 if (reg.invert)
1871 val = reg.mask - val;
1872 ucontrol->value.integer.value[0] = val;
1873 if (reg.stereo) {
1874 val = (snd_cmipci_mixer_read(cm, reg.right_reg) >> reg.right_shift) & reg.mask;
1875 if (reg.invert)
1876 val = reg.mask - val;
1877 ucontrol->value.integer.value[1] = val;
1878 }
1879 spin_unlock_irq(&cm->reg_lock);
1880 return 0;
1881 }
1882
1883 static int snd_cmipci_put_volume(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1884 {
1885 cmipci_t *cm = snd_kcontrol_chip(kcontrol);
1886 cmipci_sb_reg_t reg;
1887 int change;
1888 int left, right, oleft, oright;
1889
1890 cmipci_sb_reg_decode(&reg, kcontrol->private_value);
1891 left = ucontrol->value.integer.value[0] & reg.mask;
1892 if (reg.invert)
1893 left = reg.mask - left;
1894 left <<= reg.left_shift;
1895 if (reg.stereo) {
1896 right = ucontrol->value.integer.value[1] & reg.mask;
1897 if (reg.invert)
1898 right = reg.mask - right;
1899 right <<= reg.right_shift;
1900 } else
1901 right = 0;
1902 spin_lock_irq(&cm->reg_lock);
1903 oleft = snd_cmipci_mixer_read(cm, reg.left_reg);
1904 left |= oleft & ~(reg.mask << reg.left_shift);
1905 change = left != oleft;
1906 if (reg.stereo) {
1907 if (reg.left_reg != reg.right_reg) {
1908 snd_cmipci_mixer_write(cm, reg.left_reg, left);
1909 oright = snd_cmipci_mixer_read(cm, reg.right_reg);
1910 } else
1911 oright = left;
1912 right |= oright & ~(reg.mask << reg.right_shift);
1913 change |= right != oright;
1914 snd_cmipci_mixer_write(cm, reg.right_reg, right);
1915 } else
1916 snd_cmipci_mixer_write(cm, reg.left_reg, left);
1917 spin_unlock_irq(&cm->reg_lock);
1918 return change;
1919 }
1920
1921 /*
1922 * input route (left,right) -> (left,right)
1923 */
1924 #define CMIPCI_SB_INPUT_SW(xname, left_shift, right_shift) \
1925 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1926 .info = snd_cmipci_info_input_sw, \
1927 .get = snd_cmipci_get_input_sw, .put = snd_cmipci_put_input_sw, \
1928 .private_value = COMPOSE_SB_REG(SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT, left_shift, right_shift, 1, 0, 1), \
1929 }
1930
1931 static int snd_cmipci_info_input_sw(snd_kcontrol_t * kcontrol, snd_ctl_elem_info_t * uinfo)
1932 {
1933 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1934 uinfo->count = 4;
1935 uinfo->value.integer.min = 0;
1936 uinfo->value.integer.max = 1;
1937 return 0;
1938 }
1939
1940 static int snd_cmipci_get_input_sw(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1941 {
1942 cmipci_t *cm = snd_kcontrol_chip(kcontrol);
1943 cmipci_sb_reg_t reg;
1944 int val1, val2;
1945
1946 cmipci_sb_reg_decode(&reg, kcontrol->private_value);
1947 spin_lock_irq(&cm->reg_lock);
1948 val1 = snd_cmipci_mixer_read(cm, reg.left_reg);
1949 val2 = snd_cmipci_mixer_read(cm, reg.right_reg);
1950 spin_unlock_irq(&cm->reg_lock);
1951 ucontrol->value.integer.value[0] = (val1 >> reg.left_shift) & 1;
1952 ucontrol->value.integer.value[1] = (val2 >> reg.left_shift) & 1;
1953 ucontrol->value.integer.value[2] = (val1 >> reg.right_shift) & 1;
1954 ucontrol->value.integer.value[3] = (val2 >> reg.right_shift) & 1;
1955 return 0;
1956 }
1957
1958 static int snd_cmipci_put_input_sw(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1959 {
1960 cmipci_t *cm = snd_kcontrol_chip(kcontrol);
1961 cmipci_sb_reg_t reg;
1962 int change;
1963 int val1, val2, oval1, oval2;
1964
1965 cmipci_sb_reg_decode(&reg, kcontrol->private_value);
1966 spin_lock_irq(&cm->reg_lock);
1967 oval1 = snd_cmipci_mixer_read(cm, reg.left_reg);
1968 oval2 = snd_cmipci_mixer_read(cm, reg.right_reg);
1969 val1 = oval1 & ~((1 << reg.left_shift) | (1 << reg.right_shift));
1970 val2 = oval2 & ~((1 << reg.left_shift) | (1 << reg.right_shift));
1971 val1 |= (ucontrol->value.integer.value[0] & 1) << reg.left_shift;
1972 val2 |= (ucontrol->value.integer.value[1] & 1) << reg.left_shift;
1973 val1 |= (ucontrol->value.integer.value[2] & 1) << reg.right_shift;
1974 val2 |= (ucontrol->value.integer.value[3] & 1) << reg.right_shift;
1975 change = val1 != oval1 || val2 != oval2;
1976 snd_cmipci_mixer_write(cm, reg.left_reg, val1);
1977 snd_cmipci_mixer_write(cm, reg.right_reg, val2);
1978 spin_unlock_irq(&cm->reg_lock);
1979 return change;
1980 }
1981
1982 /*
1983 * native mixer switches/volumes
1984 */
1985
1986 #define CMIPCI_MIXER_SW_STEREO(xname, reg, lshift, rshift, invert) \
1987 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1988 .info = snd_cmipci_info_native_mixer, \
1989 .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
1990 .private_value = COMPOSE_SB_REG(reg, reg, lshift, rshift, 1, invert, 1), \
1991 }
1992
1993 #define CMIPCI_MIXER_SW_MONO(xname, reg, shift, invert) \
1994 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1995 .info = snd_cmipci_info_native_mixer, \
1996 .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
1997 .private_value = COMPOSE_SB_REG(reg, reg, shift, shift, 1, invert, 0), \
1998 }
1999
2000 #define CMIPCI_MIXER_VOL_STEREO(xname, reg, lshift, rshift, mask) \
2001 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2002 .info = snd_cmipci_info_native_mixer, \
2003 .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
2004 .private_value = COMPOSE_SB_REG(reg, reg, lshift, rshift, mask, 0, 1), \
2005 }
2006
2007 #define CMIPCI_MIXER_VOL_MONO(xname, reg, shift, mask) \
2008 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2009 .info = snd_cmipci_info_native_mixer, \
2010 .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
2011 .private_value = COMPOSE_SB_REG(reg, reg, shift, shift, mask, 0, 0), \
2012 }
2013
2014 static int snd_cmipci_info_native_mixer(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t *uinfo)
2015 {
2016 cmipci_sb_reg_t reg;
2017
2018 cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2019 uinfo->type = reg.mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
2020 uinfo->count = reg.stereo + 1;
2021 uinfo->value.integer.min = 0;
2022 uinfo->value.integer.max = reg.mask;
2023 return 0;
2024
2025 }
2026
2027 static int snd_cmipci_get_native_mixer(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2028 {
2029 cmipci_t *cm = snd_kcontrol_chip(kcontrol);
2030 cmipci_sb_reg_t reg;
2031 unsigned char oreg, val;
2032
2033 cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2034 spin_lock_irq(&cm->reg_lock);
2035 oreg = inb(cm->iobase + reg.left_reg);
2036 val = (oreg >> reg.left_shift) & reg.mask;
2037 if (reg.invert)
2038 val = reg.mask - val;
2039 ucontrol->value.integer.value[0] = val;
2040 if (reg.stereo) {
2041 val = (oreg >> reg.right_shift) & reg.mask;
2042 if (reg.invert)
2043 val = reg.mask - val;
2044 ucontrol->value.integer.value[1] = val;
2045 }
2046 spin_unlock_irq(&cm->reg_lock);
2047 return 0;
2048 }
2049
2050 static int snd_cmipci_put_native_mixer(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2051 {
2052 cmipci_t *cm = snd_kcontrol_chip(kcontrol);
2053 cmipci_sb_reg_t reg;
2054 unsigned char oreg, nreg, val;
2055
2056 cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2057 spin_lock_irq(&cm->reg_lock);
2058 oreg = inb(cm->iobase + reg.left_reg);
2059 val = ucontrol->value.integer.value[0] & reg.mask;
2060 if (reg.invert)
2061 val = reg.mask - val;
2062 nreg = oreg & ~(reg.mask << reg.left_shift);
2063 nreg |= (val << reg.left_shift);
2064 if (reg.stereo) {
2065 val = ucontrol->value.integer.value[1] & reg.mask;
2066 if (reg.invert)
2067 val = reg.mask - val;
2068 nreg &= ~(reg.mask << reg.right_shift);
2069 nreg |= (val << reg.right_shift);
2070 }
2071 outb(nreg, cm->iobase + reg.left_reg);
2072 spin_unlock_irq(&cm->reg_lock);
2073 return (nreg != oreg);
2074 }
2075
2076 /*
2077 * special case - check mixer sensitivity
2078 */
2079 static int snd_cmipci_get_native_mixer_sensitive(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol)
2080 {
2081 //cmipci_t *cm = snd_kcontrol_chip(kcontrol);
2082 return snd_cmipci_get_native_mixer(kcontrol, ucontrol);
2083 }
2084
2085 static int snd_cmipci_put_native_mixer_sensitive(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol)
2086 {
2087 cmipci_t *cm = snd_kcontrol_chip(kcontrol);
2088 if (cm->mixer_insensitive) {
2089 /* ignored */
2090 return 0;
2091 }
2092 return snd_cmipci_put_native_mixer(kcontrol, ucontrol);
2093 }
2094
2095
2096 static snd_kcontrol_new_t snd_cmipci_mixers[] __devinitdata = {
2097 CMIPCI_SB_VOL_STEREO("Master Playback Volume", SB_DSP4_MASTER_DEV, 3, 31),
2098 CMIPCI_MIXER_SW_MONO("3D Control - Switch", CM_REG_MIXER1, CM_X3DEN_SHIFT, 0),
2099 CMIPCI_SB_VOL_STEREO("PCM Playback Volume", SB_DSP4_PCM_DEV, 3, 31),
2100 //CMIPCI_MIXER_SW_MONO("PCM Playback Switch", CM_REG_MIXER1, CM_WSMUTE_SHIFT, 1),
2101 { /* switch with sensitivity */
2102 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2103 .name = "PCM Playback Switch",
2104 .info = snd_cmipci_info_native_mixer,
2105 .get = snd_cmipci_get_native_mixer_sensitive,
2106 .put = snd_cmipci_put_native_mixer_sensitive,
2107 .private_value = COMPOSE_SB_REG(CM_REG_MIXER1, CM_REG_MIXER1, CM_WSMUTE_SHIFT, CM_WSMUTE_SHIFT, 1, 1, 0),
2108 },
2109 CMIPCI_MIXER_SW_STEREO("PCM Capture Switch", CM_REG_MIXER1, CM_WAVEINL_SHIFT, CM_WAVEINR_SHIFT, 0),
2110 CMIPCI_SB_VOL_STEREO("Synth Playback Volume", SB_DSP4_SYNTH_DEV, 3, 31),
2111 CMIPCI_MIXER_SW_MONO("Synth Playback Switch", CM_REG_MIXER1, CM_FMMUTE_SHIFT, 1),
2112 CMIPCI_SB_INPUT_SW("Synth Capture Route", 6, 5),
2113 CMIPCI_SB_VOL_STEREO("CD Playback Volume", SB_DSP4_CD_DEV, 3, 31),
2114 CMIPCI_SB_SW_STEREO("CD Playback Switch", 2, 1),
2115 CMIPCI_SB_INPUT_SW("CD Capture Route", 2, 1),
2116 CMIPCI_SB_VOL_STEREO("Line Playback Volume", SB_DSP4_LINE_DEV, 3, 31),
2117 CMIPCI_SB_SW_STEREO("Line Playback Switch", 4, 3),
2118 CMIPCI_SB_INPUT_SW("Line Capture Route", 4, 3),
2119 CMIPCI_SB_VOL_MONO("Mic Playback Volume", SB_DSP4_MIC_DEV, 3, 31),
2120 CMIPCI_SB_SW_MONO("Mic Playback Switch", 0),
2121 CMIPCI_DOUBLE("Mic Capture Switch", SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT, 0, 0, 1, 0, 0),
2122 CMIPCI_SB_VOL_MONO("PC Speaker Playback Volume", SB_DSP4_SPEAKER_DEV, 6, 3),
2123 CMIPCI_MIXER_VOL_STEREO("Aux Playback Volume", CM_REG_AUX_VOL, 4, 0, 15),
2124 CMIPCI_MIXER_SW_STEREO("Aux Playback Switch", CM_REG_MIXER2, CM_VAUXLM_SHIFT, CM_VAUXRM_SHIFT, 0),
2125 CMIPCI_MIXER_SW_STEREO("Aux Capture Switch", CM_REG_MIXER2, CM_RAUXLEN_SHIFT, CM_RAUXREN_SHIFT, 0),
2126 CMIPCI_MIXER_SW_MONO("Mic Boost", CM_REG_MIXER2, CM_MICGAINZ_SHIFT, 1),
2127 CMIPCI_MIXER_VOL_MONO("Mic Capture Volume", CM_REG_MIXER2, CM_VADMIC_SHIFT, 7),
2128 };
2129
2130 /*
2131 * other switches
2132 */
2133
2134 typedef struct snd_cmipci_switch_args {
2135 int reg; /* register index */
2136 unsigned int mask; /* mask bits */
2137 unsigned int mask_on; /* mask bits to turn on */
2138 unsigned int is_byte: 1; /* byte access? */
2139 unsigned int ac3_sensitive: 1; /* access forbidden during non-audio operation? */
2140 } snd_cmipci_switch_args_t;
2141
2142 static int snd_cmipci_uswitch_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t *uinfo)
2143 {
2144 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
2145 uinfo->count = 1;
2146 uinfo->value.integer.min = 0;
2147 uinfo->value.integer.max = 1;
2148 return 0;
2149 }
2150
2151 static int _snd_cmipci_uswitch_get(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol, snd_cmipci_switch_args_t *args)
2152 {
2153 unsigned int val;
2154 cmipci_t *cm = snd_kcontrol_chip(kcontrol);
2155
2156 spin_lock_irq(&cm->reg_lock);
2157 if (args->ac3_sensitive && cm->mixer_insensitive) {
2158 ucontrol->value.integer.value[0] = 0;
2159 spin_unlock_irq(&cm->reg_lock);
2160 return 0;
2161 }
2162 if (args->is_byte)
2163 val = inb(cm->iobase + args->reg);
2164 else
2165 val = snd_cmipci_read(cm, args->reg);
2166 ucontrol->value.integer.value[0] = ((val & args->mask) == args->mask_on) ? 1 : 0;
2167 spin_unlock_irq(&cm->reg_lock);
2168 return 0;
2169 }
2170
2171 static int snd_cmipci_uswitch_get(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol)
2172 {
2173 snd_cmipci_switch_args_t *args = (snd_cmipci_switch_args_t*)kcontrol->private_value;
2174 snd_assert(args != NULL, return -EINVAL);
2175 return _snd_cmipci_uswitch_get(kcontrol, ucontrol, args);
2176 }
2177
2178 static int _snd_cmipci_uswitch_put(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol, snd_cmipci_switch_args_t *args)
2179 {
2180 unsigned int val;
2181 int change;
2182 cmipci_t *cm = snd_kcontrol_chip(kcontrol);
2183
2184 spin_lock_irq(&cm->reg_lock);
2185 if (args->ac3_sensitive && cm->mixer_insensitive) {
2186 /* ignored */
2187 spin_unlock_irq(&cm->reg_lock);
2188 return 0;
2189 }
2190 if (args->is_byte)
2191 val = inb(cm->iobase + args->reg);
2192 else
2193 val = snd_cmipci_read(cm, args->reg);
2194 change = (val & args->mask) != (ucontrol->value.integer.value[0] ? args->mask : 0);
2195 if (change) {
2196 val &= ~args->mask;
2197 if (ucontrol->value.integer.value[0])
2198 val |= args->mask_on;
2199 else
2200 val |= (args->mask & ~args->mask_on);
2201 if (args->is_byte)
2202 outb((unsigned char)val, cm->iobase + args->reg);
2203 else
2204 snd_cmipci_write(cm, args->reg, val);
2205 }
2206 spin_unlock_irq(&cm->reg_lock);
2207 return change;
2208 }
2209
2210 static int snd_cmipci_uswitch_put(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol)
2211 {
2212 snd_cmipci_switch_args_t *args = (snd_cmipci_switch_args_t*)kcontrol->private_value;
2213 snd_assert(args != NULL, return -EINVAL);
2214 return _snd_cmipci_uswitch_put(kcontrol, ucontrol, args);
2215 }
2216
2217 #define DEFINE_SWITCH_ARG(sname, xreg, xmask, xmask_on, xis_byte, xac3) \
2218 static snd_cmipci_switch_args_t cmipci_switch_arg_##sname = { \
2219 .reg = xreg, \
2220 .mask = xmask, \
2221 .mask_on = xmask_on, \
2222 .is_byte = xis_byte, \
2223 .ac3_sensitive = xac3, \
2224 }
2225
2226 #define DEFINE_BIT_SWITCH_ARG(sname, xreg, xmask, xis_byte, xac3) \
2227 DEFINE_SWITCH_ARG(sname, xreg, xmask, xmask, xis_byte, xac3)
2228
2229 #if 0 /* these will be controlled in pcm device */
2230 DEFINE_BIT_SWITCH_ARG(spdif_in, CM_REG_FUNCTRL1, CM_SPDF_1, 0, 0);
2231 DEFINE_BIT_SWITCH_ARG(spdif_out, CM_REG_FUNCTRL1, CM_SPDF_0, 0, 0);
2232 #endif
2233 DEFINE_BIT_SWITCH_ARG(spdif_in_sel1, CM_REG_CHFORMAT, CM_SPDIF_SELECT1, 0, 0);
2234 DEFINE_BIT_SWITCH_ARG(spdif_in_sel2, CM_REG_MISC_CTRL, CM_SPDIF_SELECT2, 0, 0);
2235 DEFINE_BIT_SWITCH_ARG(spdif_enable, CM_REG_LEGACY_CTRL, CM_ENSPDOUT, 0, 0);
2236 DEFINE_BIT_SWITCH_ARG(spdo2dac, CM_REG_FUNCTRL1, CM_SPDO2DAC, 0, 1);
2237 DEFINE_BIT_SWITCH_ARG(spdi_valid, CM_REG_MISC, CM_SPDVALID, 1, 0);
2238 DEFINE_BIT_SWITCH_ARG(spdif_copyright, CM_REG_LEGACY_CTRL, CM_SPDCOPYRHT, 0, 0);
2239 DEFINE_BIT_SWITCH_ARG(spdif_dac_out, CM_REG_LEGACY_CTRL, CM_DAC2SPDO, 0, 1);
2240 DEFINE_SWITCH_ARG(spdo_5v, CM_REG_MISC_CTRL, CM_SPDO5V, 0, 0, 0); /* inverse: 0 = 5V */
2241 // DEFINE_BIT_SWITCH_ARG(spdo_48k, CM_REG_MISC_CTRL, CM_SPDF_AC97|CM_SPDIF48K, 0, 1);
2242 DEFINE_BIT_SWITCH_ARG(spdif_loop, CM_REG_FUNCTRL1, CM_SPDFLOOP, 0, 1);
2243 DEFINE_BIT_SWITCH_ARG(spdi_monitor, CM_REG_MIXER1, CM_CDPLAY, 1, 0);
2244 /* DEFINE_BIT_SWITCH_ARG(spdi_phase, CM_REG_CHFORMAT, CM_SPDIF_INVERSE, 0, 0); */
2245 DEFINE_BIT_SWITCH_ARG(spdi_phase, CM_REG_MISC, CM_SPDIF_INVERSE, 1, 0);
2246 DEFINE_BIT_SWITCH_ARG(spdi_phase2, CM_REG_CHFORMAT, CM_SPDIF_INVERSE2, 0, 0);
2247 #if CM_CH_PLAY == 1
2248 DEFINE_SWITCH_ARG(exchange_dac, CM_REG_MISC_CTRL, CM_XCHGDAC, 0, 0, 0); /* reversed */
2249 #else
2250 DEFINE_SWITCH_ARG(exchange_dac, CM_REG_MISC_CTRL, CM_XCHGDAC, CM_XCHGDAC, 0, 0);
2251 #endif
2252 DEFINE_BIT_SWITCH_ARG(fourch, CM_REG_MISC_CTRL, CM_N4SPK3D, 0, 0);
2253 DEFINE_BIT_SWITCH_ARG(line_rear, CM_REG_MIXER1, CM_SPK4, 1, 0);
2254 DEFINE_BIT_SWITCH_ARG(line_bass, CM_REG_LEGACY_CTRL, CM_LINE_AS_BASS, 0, 0);
2255 // DEFINE_BIT_SWITCH_ARG(joystick, CM_REG_FUNCTRL1, CM_JYSTK_EN, 0, 0); /* now module option */
2256 DEFINE_SWITCH_ARG(modem, CM_REG_MISC_CTRL, CM_FLINKON|CM_FLINKOFF, CM_FLINKON, 0, 0);
2257
2258 #define DEFINE_SWITCH(sname, stype, sarg) \
2259 { .name = sname, \
2260 .iface = stype, \
2261 .info = snd_cmipci_uswitch_info, \
2262 .get = snd_cmipci_uswitch_get, \
2263 .put = snd_cmipci_uswitch_put, \
2264 .private_value = (unsigned long)&cmipci_switch_arg_##sarg,\
2265 }
2266
2267 #define DEFINE_CARD_SWITCH(sname, sarg) DEFINE_SWITCH(sname, SNDRV_CTL_ELEM_IFACE_CARD, sarg)
2268 #define DEFINE_MIXER_SWITCH(sname, sarg) DEFINE_SWITCH(sname, SNDRV_CTL_ELEM_IFACE_MIXER, sarg)
2269
2270
2271 /*
2272 * callbacks for spdif output switch
2273 * needs toggle two registers..
2274 */
2275 static int snd_cmipci_spdout_enable_get(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol)
2276 {
2277 int changed;
2278 changed = _snd_cmipci_uswitch_get(kcontrol, ucontrol, &cmipci_switch_arg_spdif_enable);
2279 changed |= _snd_cmipci_uswitch_get(kcontrol, ucontrol, &cmipci_switch_arg_spdo2dac);
2280 return changed;
2281 }
2282
2283 static int snd_cmipci_spdout_enable_put(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol)
2284 {
2285 cmipci_t *chip = snd_kcontrol_chip(kcontrol);
2286 int changed;
2287 changed = _snd_cmipci_uswitch_put(kcontrol, ucontrol, &cmipci_switch_arg_spdif_enable);
2288 changed |= _snd_cmipci_uswitch_put(kcontrol, ucontrol, &cmipci_switch_arg_spdo2dac);
2289 if (changed) {
2290 if (ucontrol->value.integer.value[0]) {
2291 if (chip->spdif_playback_avail)
2292 snd_cmipci_set_bit(chip, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
2293 } else {
2294 if (chip->spdif_playback_avail)
2295 snd_cmipci_clear_bit(chip, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
2296 }
2297 }
2298 chip->spdif_playback_enabled = ucontrol->value.integer.value[0];
2299 return changed;
2300 }
2301
2302
2303 /* both for CM8338/8738 */
2304 static snd_kcontrol_new_t snd_cmipci_mixer_switches[] __devinitdata = {
2305 DEFINE_MIXER_SWITCH("Four Channel Mode", fourch),
2306 DEFINE_MIXER_SWITCH("Line-In As Rear", line_rear),
2307 };
2308
2309 /* for non-multichannel chips */
2310 static snd_kcontrol_new_t snd_cmipci_nomulti_switch __devinitdata =
2311 DEFINE_MIXER_SWITCH("Exchange DAC", exchange_dac);
2312
2313 /* only for CM8738 */
2314 static snd_kcontrol_new_t snd_cmipci_8738_mixer_switches[] __devinitdata = {
2315 #if 0 /* controlled in pcm device */
2316 DEFINE_MIXER_SWITCH("IEC958 In Record", spdif_in),
2317 DEFINE_MIXER_SWITCH("IEC958 Out", spdif_out),
2318 DEFINE_MIXER_SWITCH("IEC958 Out To DAC", spdo2dac),
2319 #endif
2320 // DEFINE_MIXER_SWITCH("IEC958 Output Switch", spdif_enable),
2321 { .name = "IEC958 Output Switch",
2322 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2323 .info = snd_cmipci_uswitch_info,
2324 .get = snd_cmipci_spdout_enable_get,
2325 .put = snd_cmipci_spdout_enable_put,
2326 },
2327 DEFINE_MIXER_SWITCH("IEC958 In Valid", spdi_valid),
2328 DEFINE_MIXER_SWITCH("IEC958 Copyright", spdif_copyright),
2329 DEFINE_MIXER_SWITCH("IEC958 5V", spdo_5v),
2330 // DEFINE_MIXER_SWITCH("IEC958 In/Out 48KHz", spdo_48k),
2331 DEFINE_MIXER_SWITCH("IEC958 Loop", spdif_loop),
2332 DEFINE_MIXER_SWITCH("IEC958 In Monitor", spdi_monitor),
2333 };
2334
2335 /* only for model 033/037 */
2336 static snd_kcontrol_new_t snd_cmipci_old_mixer_switches[] __devinitdata = {
2337 DEFINE_MIXER_SWITCH("IEC958 Mix Analog", spdif_dac_out),
2338 DEFINE_MIXER_SWITCH("IEC958 In Phase Inverse", spdi_phase),
2339 DEFINE_MIXER_SWITCH("IEC958 In Select", spdif_in_sel1),
2340 };
2341
2342 /* only for model 039 or later */
2343 static snd_kcontrol_new_t snd_cmipci_extra_mixer_switches[] __devinitdata = {
2344 DEFINE_MIXER_SWITCH("Line-In As Bass", line_bass),
2345 DEFINE_MIXER_SWITCH("IEC958 In Select", spdif_in_sel2),
2346 DEFINE_MIXER_SWITCH("IEC958 In Phase Inverse", spdi_phase2),
2347 DEFINE_MIXER_SWITCH("Mic As Center/LFE", spdi_phase), /* same bit as spdi_phase */
2348 };
2349
2350 /* card control switches */
2351 static snd_kcontrol_new_t snd_cmipci_control_switches[] __devinitdata = {
2352 // DEFINE_CARD_SWITCH("Joystick", joystick), /* now module option */
2353 DEFINE_CARD_SWITCH("Modem", modem),
2354 };
2355
2356
2357 static int __devinit snd_cmipci_mixer_new(cmipci_t *cm, int pcm_spdif_device)
2358 {
2359 snd_card_t *card;
2360 snd_kcontrol_new_t *sw;
2361 snd_kcontrol_t *kctl;
2362 unsigned int idx;
2363 int err;
2364
2365 snd_assert(cm != NULL && cm->card != NULL, return -EINVAL);
2366
2367 card = cm->card;
2368
2369 strcpy(card->mixername, "CMedia PCI");
2370
2371 spin_lock_irq(&cm->reg_lock);
2372 snd_cmipci_mixer_write(cm, 0x00, 0x00); /* mixer reset */
2373 spin_unlock_irq(&cm->reg_lock);
2374
2375 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_mixers); idx++) {
2376 if (cm->chip_version == 68) { // 8768 has no PCM volume
2377 if (!strcmp(snd_cmipci_mixers[idx].name,
2378 "PCM Playback Volume"))
2379 continue;
2380 }
2381 if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_cmipci_mixers[idx], cm))) < 0)
2382 return err;
2383 }
2384
2385 /* mixer switches */
2386 sw = snd_cmipci_mixer_switches;
2387 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_mixer_switches); idx++, sw++) {
2388 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2389 if (err < 0)
2390 return err;
2391 }
2392 if (! cm->can_multi_ch) {
2393 err = snd_ctl_add(cm->card, snd_ctl_new1(&snd_cmipci_nomulti_switch, cm));
2394 if (err < 0)
2395 return err;
2396 }
2397 if (cm->device == PCI_DEVICE_ID_CMEDIA_CM8738 ||
2398 cm->device == PCI_DEVICE_ID_CMEDIA_CM8738B) {
2399 sw = snd_cmipci_8738_mixer_switches;
2400 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_8738_mixer_switches); idx++, sw++) {
2401 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2402 if (err < 0)
2403 return err;
2404 }
2405 if (cm->can_ac3_hw) {
2406 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_cmipci_spdif_default, cm))) < 0)
2407 return err;
2408 kctl->id.device = pcm_spdif_device;
2409 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_cmipci_spdif_mask, cm))) < 0)
2410 return err;
2411 kctl->id.device = pcm_spdif_device;
2412 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_cmipci_spdif_stream, cm))) < 0)
2413 return err;
2414 kctl->id.device = pcm_spdif_device;
2415 }
2416 if (cm->chip_version <= 37) {
2417 sw = snd_cmipci_old_mixer_switches;
2418 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_old_mixer_switches); idx++, sw++) {
2419 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2420 if (err < 0)
2421 return err;
2422 }
2423 }
2424 }
2425 if (cm->chip_version >= 39) {
2426 sw = snd_cmipci_extra_mixer_switches;
2427 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_extra_mixer_switches); idx++, sw++) {
2428 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2429 if (err < 0)
2430 return err;
2431 }
2432 }
2433
2434 /* card switches */
2435 sw = snd_cmipci_control_switches;
2436 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_control_switches); idx++, sw++) {
2437 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2438 if (err < 0)
2439 return err;
2440 }
2441
2442 for (idx = 0; idx < CM_SAVED_MIXERS; idx++) {
2443 snd_ctl_elem_id_t id;
2444 snd_kcontrol_t *ctl;
2445 memset(&id, 0, sizeof(id));
2446 id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2447 strcpy(id.name, cm_saved_mixer[idx].name);
2448 if ((ctl = snd_ctl_find_id(cm->card, &id)) != NULL)
2449 cm->mixer_res_ctl[idx] = ctl;
2450 }
2451
2452 return 0;
2453 }
2454
2455
2456 /*
2457 * proc interface
2458 */
2459
2460 #ifdef CONFIG_PROC_FS
2461 static void snd_cmipci_proc_read(snd_info_entry_t *entry,
2462 snd_info_buffer_t *buffer)
2463 {
2464 cmipci_t *cm = entry->private_data;
2465 int i;
2466
2467 snd_iprintf(buffer, "%s\n\n", cm->card->longname);
2468 for (i = 0; i < 0x40; i++) {
2469 int v = inb(cm->iobase + i);
2470 if (i % 4 == 0)
2471 snd_iprintf(buffer, "%02x: ", i);
2472 snd_iprintf(buffer, "%02x", v);
2473 if (i % 4 == 3)
2474 snd_iprintf(buffer, "\n");
2475 else
2476 snd_iprintf(buffer, " ");
2477 }
2478 }
2479
2480 static void __devinit snd_cmipci_proc_init(cmipci_t *cm)
2481 {
2482 snd_info_entry_t *entry;
2483
2484 if (! snd_card_proc_new(cm->card, "cmipci", &entry))
2485 snd_info_set_text_ops(entry, cm, 1024, snd_cmipci_proc_read);
2486 }
2487 #else /* !CONFIG_PROC_FS */
2488 static inline void snd_cmipci_proc_init(cmipci_t *cm) {}
2489 #endif
2490
2491
2492 static struct pci_device_id snd_cmipci_ids[] = {
2493 {PCI_VENDOR_ID_CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8338A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
2494 {PCI_VENDOR_ID_CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8338B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
2495 {PCI_VENDOR_ID_CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8738, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
2496 {PCI_VENDOR_ID_CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8738B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
2497 {PCI_VENDOR_ID_AL, PCI_DEVICE_ID_CMEDIA_CM8738, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
2498 {0,},
2499 };
2500
2501
2502 /*
2503 * check chip version and capabilities
2504 * driver name is modified according to the chip model
2505 */
2506 static void __devinit query_chip(cmipci_t *cm)
2507 {
2508 unsigned int detect;
2509
2510 /* check reg 0Ch, bit 24-31 */
2511 detect = snd_cmipci_read(cm, CM_REG_INT_HLDCLR) & CM_CHIP_MASK2;
2512 if (! detect) {
2513 /* check reg 08h, bit 24-28 */
2514 detect = snd_cmipci_read(cm, CM_REG_CHFORMAT) & CM_CHIP_MASK1;
2515 if (! detect) {
2516 cm->chip_version = 33;
2517 cm->max_channels = 2;
2518 if (cm->do_soft_ac3)
2519 cm->can_ac3_sw = 1;
2520 else
2521 cm->can_ac3_hw = 1;
2522 cm->has_dual_dac = 1;
2523 } else {
2524 cm->chip_version = 37;
2525 cm->max_channels = 2;
2526 cm->can_ac3_hw = 1;
2527 cm->has_dual_dac = 1;
2528 }
2529 } else {
2530 /* check reg 0Ch, bit 26 */
2531 if (detect & CM_CHIP_8768) {
2532 cm->chip_version = 68;
2533 cm->max_channels = 8;
2534 cm->can_ac3_hw = 1;
2535 cm->has_dual_dac = 1;
2536 cm->can_multi_ch = 1;
2537 } else if (detect & CM_CHIP_055) {
2538 cm->chip_version = 55;
2539 cm->max_channels = 6;
2540 cm->can_ac3_hw = 1;
2541 cm->has_dual_dac = 1;
2542 cm->can_multi_ch = 1;
2543 } else if (detect & CM_CHIP_039) {
2544 cm->chip_version = 39;
2545 if (detect & CM_CHIP_039_6CH) /* 4 or 6 channels */
2546 cm->max_channels = 6;
2547 else
2548 cm->max_channels = 4;
2549 cm->can_ac3_hw = 1;
2550 cm->has_dual_dac = 1;
2551 cm->can_multi_ch = 1;
2552 } else {
2553 printk(KERN_ERR "chip %x version not supported\n", detect);
2554 }
2555 }
2556 }
2557
2558 #ifdef SUPPORT_JOYSTICK
2559 static int __devinit snd_cmipci_create_gameport(cmipci_t *cm, int dev)
2560 {
2561 static int ports[] = { 0x201, 0x200, 0 }; /* FIXME: majority is 0x201? */
2562 struct gameport *gp;
2563 struct resource *r = NULL;
2564 int i, io_port = 0;
2565
2566 if (joystick_port[dev] == 0)
2567 return -ENODEV;
2568
2569 if (joystick_port[dev] == 1) { /* auto-detect */
2570 for (i = 0; ports[i]; i++) {
2571 io_port = ports[i];
2572 r = request_region(io_port, 1, "CMIPCI gameport");
2573 if (r)
2574 break;
2575 }
2576 } else {
2577 io_port = joystick_port[dev];
2578 r = request_region(io_port, 1, "CMIPCI gameport");
2579 }
2580
2581 if (!r) {
2582 printk(KERN_WARNING "cmipci: cannot reserve joystick ports\n");
2583 return -EBUSY;
2584 }
2585
2586 cm->gameport = gp = gameport_allocate_port();
2587 if (!gp) {
2588 printk(KERN_ERR "cmipci: cannot allocate memory for gameport\n");
2589 release_resource(r);
2590 kfree_nocheck(r);
2591 return -ENOMEM;
2592 }
2593 gameport_set_name(gp, "C-Media Gameport");
2594 gameport_set_phys(gp, "pci%s/gameport0", pci_name(cm->pci));
2595 gameport_set_dev_parent(gp, &cm->pci->dev);
2596 gp->io = io_port;
2597 gameport_set_port_data(gp, r);
2598
2599 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);
2600
2601 gameport_register_port(cm->gameport);
2602
2603 return 0;
2604 }
2605
2606 static void snd_cmipci_free_gameport(cmipci_t *cm)
2607 {
2608 if (cm->gameport) {
2609 struct resource *r = gameport_get_port_data(cm->gameport);
2610
2611 gameport_unregister_port(cm->gameport);
2612 cm->gameport = NULL;
2613
2614 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);
2615 release_resource(r);
2616 kfree_nocheck(r);
2617 }
2618 }
2619 #else
2620 static inline int snd_cmipci_create_gameport(cmipci_t *cm, int dev) { return -ENOSYS; }
2621 static inline void snd_cmipci_free_gameport(cmipci_t *cm) { }
2622 #endif
2623
2624 static int snd_cmipci_free(cmipci_t *cm)
2625 {
2626 if (cm->irq >= 0) {
2627 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN);
2628 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT);
2629 snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0); /* disable ints */
2630 snd_cmipci_ch_reset(cm, CM_CH_PLAY);
2631 snd_cmipci_ch_reset(cm, CM_CH_CAPT);
2632 snd_cmipci_write(cm, CM_REG_FUNCTRL0, 0); /* disable channels */
2633 snd_cmipci_write(cm, CM_REG_FUNCTRL1, 0);
2634
2635 /* reset mixer */
2636 snd_cmipci_mixer_write(cm, 0, 0);
2637
2638 synchronize_irq(cm->irq);
2639
2640 free_irq(cm->irq, (void *)cm);
2641 }
2642
2643 snd_cmipci_free_gameport(cm);
2644 pci_release_regions(cm->pci);
2645 pci_disable_device(cm->pci);
2646 kfree(cm);
2647 return 0;
2648 }
2649
2650 static int snd_cmipci_dev_free(snd_device_t *device)
2651 {
2652 cmipci_t *cm = device->device_data;
2653 return snd_cmipci_free(cm);
2654 }
2655
2656 static int __devinit snd_cmipci_create(snd_card_t *card, struct pci_dev *pci,
2657 int dev, cmipci_t **rcmipci)
2658 {
2659 cmipci_t *cm;
2660 int err;
2661 static snd_device_ops_t ops = {
2662 .dev_free = snd_cmipci_dev_free,
2663 };
2664 unsigned int val = 0;
2665 long iomidi = mpu_port[dev];
2666 long iosynth = fm_port[dev];
2667 int pcm_index, pcm_spdif_index;
2668 static struct pci_device_id intel_82437vx[] = {
2669 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX) },
2670 { },
2671 };
2672
2673 *rcmipci = NULL;
2674
2675 if ((err = pci_enable_device(pci)) < 0)
2676 return err;
2677
2678 cm = kcalloc(1, sizeof(*cm), GFP_KERNEL);
2679 if (cm == NULL) {
2680 pci_disable_device(pci);
2681 return -ENOMEM;
2682 }
2683
2684 spin_lock_init(&cm->reg_lock);
2685 init_MUTEX(&cm->open_mutex);
2686 cm->device = pci->device;
2687 cm->card = card;
2688 cm->pci = pci;
2689 cm->irq = -1;
2690 cm->channel[0].ch = 0;
2691 cm->channel[1].ch = 1;
2692 cm->channel[0].is_dac = cm->channel[1].is_dac = 1; /* dual DAC mode */
2693
2694 if ((err = pci_request_regions(pci, card->driver)) < 0) {
2695 kfree(cm);
2696 pci_disable_device(pci);
2697 return err;
2698 }
2699 cm->iobase = pci_resource_start(pci, 0);
2700
2701 if (request_irq(pci->irq, snd_cmipci_interrupt, SA_INTERRUPT|SA_SHIRQ, card->driver, (void *)cm)) {
2702 snd_printk("unable to grab IRQ %d\n", pci->irq);
2703 snd_cmipci_free(cm);
2704 return -EBUSY;
2705 }
2706 cm->irq = pci->irq;
2707
2708 pci_set_master(cm->pci);
2709
2710 /*
2711 * check chip version, max channels and capabilities
2712 */
2713
2714 cm->chip_version = 0;
2715 cm->max_channels = 2;
2716 cm->do_soft_ac3 = soft_ac3[dev];
2717
2718 if (pci->device != PCI_DEVICE_ID_CMEDIA_CM8338A &&
2719 pci->device != PCI_DEVICE_ID_CMEDIA_CM8338B)
2720 query_chip(cm);
2721 /* added -MCx suffix for chip supporting multi-channels */
2722 if (cm->can_multi_ch)
2723 sprintf(cm->card->driver + strlen(cm->card->driver),
2724 "-MC%d", cm->max_channels);
2725 else if (cm->can_ac3_sw)
2726 strcpy(cm->card->driver + strlen(cm->card->driver), "-SWIEC");
2727
2728 cm->dig_status = SNDRV_PCM_DEFAULT_CON_SPDIF;
2729 cm->dig_pcm_status = SNDRV_PCM_DEFAULT_CON_SPDIF;
2730
2731 #if CM_CH_PLAY == 1
2732 cm->ctrl = CM_CHADC0; /* default FUNCNTRL0 */
2733 #else
2734 cm->ctrl = CM_CHADC1; /* default FUNCNTRL0 */
2735 #endif
2736
2737 /* initialize codec registers */
2738 snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0); /* disable ints */
2739 snd_cmipci_ch_reset(cm, CM_CH_PLAY);
2740 snd_cmipci_ch_reset(cm, CM_CH_CAPT);
2741 snd_cmipci_write(cm, CM_REG_FUNCTRL0, 0); /* disable channels */
2742 snd_cmipci_write(cm, CM_REG_FUNCTRL1, 0);
2743
2744 snd_cmipci_write(cm, CM_REG_CHFORMAT, 0);
2745 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC|CM_N4SPK3D);
2746 #if CM_CH_PLAY == 1
2747 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
2748 #else
2749 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
2750 #endif
2751 /* Set Bus Master Request */
2752 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_BREQ);
2753
2754 /* Assume TX and compatible chip set (Autodetection required for VX chip sets) */
2755 switch (pci->device) {
2756 case PCI_DEVICE_ID_CMEDIA_CM8738:
2757 case PCI_DEVICE_ID_CMEDIA_CM8738B:
2758 if (!pci_dev_present(intel_82437vx))
2759 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_TXVX);
2760 break;
2761 default:
2762 break;
2763 }
2764
2765 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, cm, &ops)) < 0) {
2766 snd_cmipci_free(cm);
2767 return err;
2768 }
2769
2770 /* set MPU address */
2771 switch (iomidi) {
2772 case 0x320: val = CM_VMPU_320; break;
2773 case 0x310: val = CM_VMPU_310; break;
2774 case 0x300: val = CM_VMPU_300; break;
2775 case 0x330: val = CM_VMPU_330; break;
2776 default:
2777 iomidi = 0; break;
2778 }
2779 if (iomidi > 0) {
2780 snd_cmipci_write(cm, CM_REG_LEGACY_CTRL, val);
2781 /* enable UART */
2782 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_UART_EN);
2783 }
2784
2785 /* set FM address */
2786 val = snd_cmipci_read(cm, CM_REG_LEGACY_CTRL) & ~CM_FMSEL_MASK;
2787 switch (iosynth) {
2788 case 0x3E8: val |= CM_FMSEL_3E8; break;
2789 case 0x3E0: val |= CM_FMSEL_3E0; break;
2790 case 0x3C8: val |= CM_FMSEL_3C8; break;
2791 case 0x388: val |= CM_FMSEL_388; break;
2792 default:
2793 iosynth = 0; break;
2794 }
2795 if (iosynth > 0) {
2796 snd_cmipci_write(cm, CM_REG_LEGACY_CTRL, val);
2797 /* enable FM */
2798 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN);
2799
2800 if (snd_opl3_create(card, iosynth, iosynth + 2,
2801 OPL3_HW_OPL3, 0, &cm->opl3) < 0) {
2802 printk(KERN_ERR "cmipci: no OPL device at 0x%lx, skipping...\n", iosynth);
2803 iosynth = 0;
2804 } else {
2805 if ((err = snd_opl3_hwdep_new(cm->opl3, 0, 1, &cm->opl3hwdep)) < 0) {
2806 printk(KERN_ERR "cmipci: cannot create OPL3 hwdep\n");
2807 return err;
2808 }
2809 }
2810 }
2811 if (! iosynth) {
2812 /* disable FM */
2813 snd_cmipci_write(cm, CM_REG_LEGACY_CTRL, val & ~CM_FMSEL_MASK);
2814 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN);
2815 }
2816
2817 /* reset mixer */
2818 snd_cmipci_mixer_write(cm, 0, 0);
2819
2820 snd_cmipci_proc_init(cm);
2821
2822 /* create pcm devices */
2823 pcm_index = pcm_spdif_index = 0;
2824 if ((err = snd_cmipci_pcm_new(cm, pcm_index)) < 0)
2825 return err;
2826 pcm_index++;
2827 if (cm->has_dual_dac) {
2828 if ((err = snd_cmipci_pcm2_new(cm, pcm_index)) < 0)
2829 return err;
2830 pcm_index++;
2831 }
2832 if (cm->can_ac3_hw || cm->can_ac3_sw) {
2833 pcm_spdif_index = pcm_index;
2834 if ((err = snd_cmipci_pcm_spdif_new(cm, pcm_index)) < 0)
2835 return err;
2836 }
2837
2838 /* create mixer interface & switches */
2839 if ((err = snd_cmipci_mixer_new(cm, pcm_spdif_index)) < 0)
2840 return err;
2841
2842 if (iomidi > 0) {
2843 if ((err = snd_mpu401_uart_new(card, 0, MPU401_HW_CMIPCI,
2844 iomidi, 0,
2845 cm->irq, 0, &cm->rmidi)) < 0) {
2846 printk(KERN_ERR "cmipci: no UART401 device at 0x%lx\n", iomidi);
2847 }
2848 }
2849
2850 #ifdef USE_VAR48KRATE
2851 for (val = 0; val < ARRAY_SIZE(rates); val++)
2852 snd_cmipci_set_pll(cm, rates[val], val);
2853
2854 /*
2855 * (Re-)Enable external switch spdo_48k
2856 */
2857 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K|CM_SPDF_AC97);
2858 #endif /* USE_VAR48KRATE */
2859
2860 if (snd_cmipci_create_gameport(cm, dev) < 0)
2861 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);
2862
2863 snd_card_set_dev(card, &pci->dev);
2864
2865 *rcmipci = cm;
2866 return 0;
2867 }
2868
2869 /*
2870 */
2871
2872 MODULE_DEVICE_TABLE(pci, snd_cmipci_ids);
2873
2874 static int __devinit snd_cmipci_probe(struct pci_dev *pci,
2875 const struct pci_device_id *pci_id)
2876 {
2877 static int dev;
2878 snd_card_t *card;
2879 cmipci_t *cm;
2880 int err;
2881
2882 if (dev >= SNDRV_CARDS)
2883 return -ENODEV;
2884 if (! enable[dev]) {
2885 dev++;
2886 return -ENOENT;
2887 }
2888
2889 card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
2890 if (card == NULL)
2891 return -ENOMEM;
2892
2893 switch (pci->device) {
2894 case PCI_DEVICE_ID_CMEDIA_CM8738:
2895 case PCI_DEVICE_ID_CMEDIA_CM8738B:
2896 strcpy(card->driver, "CMI8738");
2897 break;
2898 case PCI_DEVICE_ID_CMEDIA_CM8338A:
2899 case PCI_DEVICE_ID_CMEDIA_CM8338B:
2900 strcpy(card->driver, "CMI8338");
2901 break;
2902 default:
2903 strcpy(card->driver, "CMIPCI");
2904 break;
2905 }
2906
2907 if ((err = snd_cmipci_create(card, pci, dev, &cm)) < 0) {
2908 snd_card_free(card);
2909 return err;
2910 }
2911
2912 sprintf(card->shortname, "C-Media PCI %s", card->driver);
2913 sprintf(card->longname, "%s (model %d) at 0x%lx, irq %i",
2914 card->shortname,
2915 cm->chip_version,
2916 cm->iobase,
2917 cm->irq);
2918
2919 //snd_printd("%s is detected\n", card->longname);
2920
2921 if ((err = snd_card_register(card)) < 0) {
2922 snd_card_free(card);
2923 return err;
2924 }
2925 pci_set_drvdata(pci, card);
2926 dev++;
2927 return 0;
2928
2929 }
2930
2931 static void __devexit snd_cmipci_remove(struct pci_dev *pci)
2932 {
2933 snd_card_free(pci_get_drvdata(pci));
2934 pci_set_drvdata(pci, NULL);
2935 }
2936
2937
2938 static struct pci_driver driver = {
2939 .name = "C-Media PCI",
2940 .id_table = snd_cmipci_ids,
2941 .probe = snd_cmipci_probe,
2942 .remove = __devexit_p(snd_cmipci_remove),
2943 };
2944
2945 static int __init alsa_card_cmipci_init(void)
2946 {
2947 return pci_module_init(&driver);
2948 }
2949
2950 static void __exit alsa_card_cmipci_exit(void)
2951 {
2952 pci_unregister_driver(&driver);
2953 }
2954
2955 module_init(alsa_card_cmipci_init)
2956 module_exit(alsa_card_cmipci_exit)
Verdex Pro support