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[TG3]: Set minimal hw interrupt mitigation.
[linux-2.6/verdex.git] / sound / pci / rme9652 / hdsp.c
blob12efbf0fab549241de4fdfb32f129a1d87eefb4b
1 /*
2 * ALSA driver for RME Hammerfall DSP audio interface(s)
3 *
4 * Copyright (c) 2002 Paul Davis
5 * Marcus Andersson
6 * Thomas Charbonnel
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 *
22 */
23
24 #include <sound/driver.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/interrupt.h>
28 #include <linux/slab.h>
29 #include <linux/pci.h>
30 #include <linux/firmware.h>
31 #include <linux/moduleparam.h>
32
33 #include <sound/core.h>
34 #include <sound/control.h>
35 #include <sound/pcm.h>
36 #include <sound/info.h>
37 #include <sound/asoundef.h>
38 #include <sound/rawmidi.h>
39 #include <sound/hwdep.h>
40 #include <sound/initval.h>
41 #include <sound/hdsp.h>
42
43 #include <asm/byteorder.h>
44 #include <asm/current.h>
45 #include <asm/io.h>
46
47 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
48 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
49 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
50
51 module_param_array(index, int, NULL, 0444);
52 MODULE_PARM_DESC(index, "Index value for RME Hammerfall DSP interface.");
53 module_param_array(id, charp, NULL, 0444);
54 MODULE_PARM_DESC(id, "ID string for RME Hammerfall DSP interface.");
55 module_param_array(enable, bool, NULL, 0444);
56 MODULE_PARM_DESC(enable, "Enable/disable specific Hammerfall DSP soundcards.");
57 MODULE_AUTHOR("Paul Davis <paul@linuxaudiosystems.com>, Marcus Andersson, Thomas Charbonnel <thomas@undata.org>");
58 MODULE_DESCRIPTION("RME Hammerfall DSP");
59 MODULE_LICENSE("GPL");
60 MODULE_SUPPORTED_DEVICE("{{RME Hammerfall-DSP},"
61 "{RME HDSP-9652},"
62 "{RME HDSP-9632}}");
63
64 #define HDSP_MAX_CHANNELS 26
65 #define HDSP_MAX_DS_CHANNELS 14
66 #define HDSP_MAX_QS_CHANNELS 8
67 #define DIGIFACE_SS_CHANNELS 26
68 #define DIGIFACE_DS_CHANNELS 14
69 #define MULTIFACE_SS_CHANNELS 18
70 #define MULTIFACE_DS_CHANNELS 14
71 #define H9652_SS_CHANNELS 26
72 #define H9652_DS_CHANNELS 14
73 /* This does not include possible Analog Extension Boards
74 AEBs are detected at card initialization
75 */
76 #define H9632_SS_CHANNELS 12
77 #define H9632_DS_CHANNELS 8
78 #define H9632_QS_CHANNELS 4
79
80 /* Write registers. These are defined as byte-offsets from the iobase value.
81 */
82 #define HDSP_resetPointer 0
83 #define HDSP_outputBufferAddress 32
84 #define HDSP_inputBufferAddress 36
85 #define HDSP_controlRegister 64
86 #define HDSP_interruptConfirmation 96
87 #define HDSP_outputEnable 128
88 #define HDSP_control2Reg 256
89 #define HDSP_midiDataOut0 352
90 #define HDSP_midiDataOut1 356
91 #define HDSP_fifoData 368
92 #define HDSP_inputEnable 384
93
94 /* Read registers. These are defined as byte-offsets from the iobase value
95 */
96
97 #define HDSP_statusRegister 0
98 #define HDSP_timecode 128
99 #define HDSP_status2Register 192
100 #define HDSP_midiDataOut0 352
101 #define HDSP_midiDataOut1 356
102 #define HDSP_midiDataIn0 360
103 #define HDSP_midiDataIn1 364
104 #define HDSP_midiStatusOut0 384
105 #define HDSP_midiStatusOut1 388
106 #define HDSP_midiStatusIn0 392
107 #define HDSP_midiStatusIn1 396
108 #define HDSP_fifoStatus 400
109
110 /* the meters are regular i/o-mapped registers, but offset
111 considerably from the rest. the peak registers are reset
112 when read; the least-significant 4 bits are full-scale counters;
113 the actual peak value is in the most-significant 24 bits.
114 */
115
116 #define HDSP_playbackPeakLevel 4096 /* 26 * 32 bit values */
117 #define HDSP_inputPeakLevel 4224 /* 26 * 32 bit values */
118 #define HDSP_outputPeakLevel 4352 /* (26+2) * 32 bit values */
119 #define HDSP_playbackRmsLevel 4612 /* 26 * 64 bit values */
120 #define HDSP_inputRmsLevel 4868 /* 26 * 64 bit values */
121
122
123 /* This is for H9652 cards
124 Peak values are read downward from the base
125 Rms values are read upward
126 There are rms values for the outputs too
127 26*3 values are read in ss mode
128 14*3 in ds mode, with no gap between values
129 */
130 #define HDSP_9652_peakBase 7164
131 #define HDSP_9652_rmsBase 4096
132
133 /* c.f. the hdsp_9632_meters_t struct */
134 #define HDSP_9632_metersBase 4096
135
136 #define HDSP_IO_EXTENT 7168
137
138 /* control2 register bits */
139
140 #define HDSP_TMS 0x01
141 #define HDSP_TCK 0x02
142 #define HDSP_TDI 0x04
143 #define HDSP_JTAG 0x08
144 #define HDSP_PWDN 0x10
145 #define HDSP_PROGRAM 0x020
146 #define HDSP_CONFIG_MODE_0 0x040
147 #define HDSP_CONFIG_MODE_1 0x080
148 #define HDSP_VERSION_BIT 0x100
149 #define HDSP_BIGENDIAN_MODE 0x200
150 #define HDSP_RD_MULTIPLE 0x400
151 #define HDSP_9652_ENABLE_MIXER 0x800
152 #define HDSP_TDO 0x10000000
153
154 #define HDSP_S_PROGRAM (HDSP_PROGRAM|HDSP_CONFIG_MODE_0)
155 #define HDSP_S_LOAD (HDSP_PROGRAM|HDSP_CONFIG_MODE_1)
156
157 /* Control Register bits */
158
159 #define HDSP_Start (1<<0) /* start engine */
160 #define HDSP_Latency0 (1<<1) /* buffer size = 2^n where n is defined by Latency{2,1,0} */
161 #define HDSP_Latency1 (1<<2) /* [ see above ] */
162 #define HDSP_Latency2 (1<<3) /* [ see above ] */
163 #define HDSP_ClockModeMaster (1<<4) /* 1=Master, 0=Slave/Autosync */
164 #define HDSP_AudioInterruptEnable (1<<5) /* what do you think ? */
165 #define HDSP_Frequency0 (1<<6) /* 0=44.1kHz/88.2kHz/176.4kHz 1=48kHz/96kHz/192kHz */
166 #define HDSP_Frequency1 (1<<7) /* 0=32kHz/64kHz/128kHz */
167 #define HDSP_DoubleSpeed (1<<8) /* 0=normal speed, 1=double speed */
168 #define HDSP_SPDIFProfessional (1<<9) /* 0=consumer, 1=professional */
169 #define HDSP_SPDIFEmphasis (1<<10) /* 0=none, 1=on */
170 #define HDSP_SPDIFNonAudio (1<<11) /* 0=off, 1=on */
171 #define HDSP_SPDIFOpticalOut (1<<12) /* 1=use 1st ADAT connector for SPDIF, 0=do not */
172 #define HDSP_SyncRef2 (1<<13)
173 #define HDSP_SPDIFInputSelect0 (1<<14)
174 #define HDSP_SPDIFInputSelect1 (1<<15)
175 #define HDSP_SyncRef0 (1<<16)
176 #define HDSP_SyncRef1 (1<<17)
177 #define HDSP_AnalogExtensionBoard (1<<18) /* For H9632 cards */
178 #define HDSP_XLRBreakoutCable (1<<20) /* For H9632 cards */
179 #define HDSP_Midi0InterruptEnable (1<<22)
180 #define HDSP_Midi1InterruptEnable (1<<23)
181 #define HDSP_LineOut (1<<24)
182 #define HDSP_ADGain0 (1<<25) /* From here : H9632 specific */
183 #define HDSP_ADGain1 (1<<26)
184 #define HDSP_DAGain0 (1<<27)
185 #define HDSP_DAGain1 (1<<28)
186 #define HDSP_PhoneGain0 (1<<29)
187 #define HDSP_PhoneGain1 (1<<30)
188 #define HDSP_QuadSpeed (1<<31)
189
190 #define HDSP_ADGainMask (HDSP_ADGain0|HDSP_ADGain1)
191 #define HDSP_ADGainMinus10dBV HDSP_ADGainMask
192 #define HDSP_ADGainPlus4dBu (HDSP_ADGain0)
193 #define HDSP_ADGainLowGain 0
194
195 #define HDSP_DAGainMask (HDSP_DAGain0|HDSP_DAGain1)
196 #define HDSP_DAGainHighGain HDSP_DAGainMask
197 #define HDSP_DAGainPlus4dBu (HDSP_DAGain0)
198 #define HDSP_DAGainMinus10dBV 0
199
200 #define HDSP_PhoneGainMask (HDSP_PhoneGain0|HDSP_PhoneGain1)
201 #define HDSP_PhoneGain0dB HDSP_PhoneGainMask
202 #define HDSP_PhoneGainMinus6dB (HDSP_PhoneGain0)
203 #define HDSP_PhoneGainMinus12dB 0
204
205 #define HDSP_LatencyMask (HDSP_Latency0|HDSP_Latency1|HDSP_Latency2)
206 #define HDSP_FrequencyMask (HDSP_Frequency0|HDSP_Frequency1|HDSP_DoubleSpeed|HDSP_QuadSpeed)
207
208 #define HDSP_SPDIFInputMask (HDSP_SPDIFInputSelect0|HDSP_SPDIFInputSelect1)
209 #define HDSP_SPDIFInputADAT1 0
210 #define HDSP_SPDIFInputCoaxial (HDSP_SPDIFInputSelect0)
211 #define HDSP_SPDIFInputCdrom (HDSP_SPDIFInputSelect1)
212 #define HDSP_SPDIFInputAES (HDSP_SPDIFInputSelect0|HDSP_SPDIFInputSelect1)
213
214 #define HDSP_SyncRefMask (HDSP_SyncRef0|HDSP_SyncRef1|HDSP_SyncRef2)
215 #define HDSP_SyncRef_ADAT1 0
216 #define HDSP_SyncRef_ADAT2 (HDSP_SyncRef0)
217 #define HDSP_SyncRef_ADAT3 (HDSP_SyncRef1)
218 #define HDSP_SyncRef_SPDIF (HDSP_SyncRef0|HDSP_SyncRef1)
219 #define HDSP_SyncRef_WORD (HDSP_SyncRef2)
220 #define HDSP_SyncRef_ADAT_SYNC (HDSP_SyncRef0|HDSP_SyncRef2)
221
222 /* Sample Clock Sources */
223
224 #define HDSP_CLOCK_SOURCE_AUTOSYNC 0
225 #define HDSP_CLOCK_SOURCE_INTERNAL_32KHZ 1
226 #define HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ 2
227 #define HDSP_CLOCK_SOURCE_INTERNAL_48KHZ 3
228 #define HDSP_CLOCK_SOURCE_INTERNAL_64KHZ 4
229 #define HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ 5
230 #define HDSP_CLOCK_SOURCE_INTERNAL_96KHZ 6
231 #define HDSP_CLOCK_SOURCE_INTERNAL_128KHZ 7
232 #define HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ 8
233 #define HDSP_CLOCK_SOURCE_INTERNAL_192KHZ 9
234
235 /* Preferred sync reference choices - used by "pref_sync_ref" control switch */
236
237 #define HDSP_SYNC_FROM_WORD 0
238 #define HDSP_SYNC_FROM_SPDIF 1
239 #define HDSP_SYNC_FROM_ADAT1 2
240 #define HDSP_SYNC_FROM_ADAT_SYNC 3
241 #define HDSP_SYNC_FROM_ADAT2 4
242 #define HDSP_SYNC_FROM_ADAT3 5
243
244 /* SyncCheck status */
245
246 #define HDSP_SYNC_CHECK_NO_LOCK 0
247 #define HDSP_SYNC_CHECK_LOCK 1
248 #define HDSP_SYNC_CHECK_SYNC 2
249
250 /* AutoSync references - used by "autosync_ref" control switch */
251
252 #define HDSP_AUTOSYNC_FROM_WORD 0
253 #define HDSP_AUTOSYNC_FROM_ADAT_SYNC 1
254 #define HDSP_AUTOSYNC_FROM_SPDIF 2
255 #define HDSP_AUTOSYNC_FROM_NONE 3
256 #define HDSP_AUTOSYNC_FROM_ADAT1 4
257 #define HDSP_AUTOSYNC_FROM_ADAT2 5
258 #define HDSP_AUTOSYNC_FROM_ADAT3 6
259
260 /* Possible sources of S/PDIF input */
261
262 #define HDSP_SPDIFIN_OPTICAL 0 /* optical (ADAT1) */
263 #define HDSP_SPDIFIN_COAXIAL 1 /* coaxial (RCA) */
264 #define HDSP_SPDIFIN_INTERNAL 2 /* internal (CDROM) */
265 #define HDSP_SPDIFIN_AES 3 /* xlr for H9632 (AES)*/
266
267 #define HDSP_Frequency32KHz HDSP_Frequency0
268 #define HDSP_Frequency44_1KHz HDSP_Frequency1
269 #define HDSP_Frequency48KHz (HDSP_Frequency1|HDSP_Frequency0)
270 #define HDSP_Frequency64KHz (HDSP_DoubleSpeed|HDSP_Frequency0)
271 #define HDSP_Frequency88_2KHz (HDSP_DoubleSpeed|HDSP_Frequency1)
272 #define HDSP_Frequency96KHz (HDSP_DoubleSpeed|HDSP_Frequency1|HDSP_Frequency0)
273 /* For H9632 cards */
274 #define HDSP_Frequency128KHz (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency0)
275 #define HDSP_Frequency176_4KHz (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency1)
276 #define HDSP_Frequency192KHz (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency1|HDSP_Frequency0)
277
278 #define hdsp_encode_latency(x) (((x)<<1) & HDSP_LatencyMask)
279 #define hdsp_decode_latency(x) (((x) & HDSP_LatencyMask)>>1)
280
281 #define hdsp_encode_spdif_in(x) (((x)&0x3)<<14)
282 #define hdsp_decode_spdif_in(x) (((x)>>14)&0x3)
283
284 /* Status Register bits */
285
286 #define HDSP_audioIRQPending (1<<0)
287 #define HDSP_Lock2 (1<<1) /* this is for Digiface and H9652 */
288 #define HDSP_spdifFrequency3 HDSP_Lock2 /* this is for H9632 only */
289 #define HDSP_Lock1 (1<<2)
290 #define HDSP_Lock0 (1<<3)
291 #define HDSP_SPDIFSync (1<<4)
292 #define HDSP_TimecodeLock (1<<5)
293 #define HDSP_BufferPositionMask 0x000FFC0 /* Bit 6..15 : h/w buffer pointer */
294 #define HDSP_Sync2 (1<<16)
295 #define HDSP_Sync1 (1<<17)
296 #define HDSP_Sync0 (1<<18)
297 #define HDSP_DoubleSpeedStatus (1<<19)
298 #define HDSP_ConfigError (1<<20)
299 #define HDSP_DllError (1<<21)
300 #define HDSP_spdifFrequency0 (1<<22)
301 #define HDSP_spdifFrequency1 (1<<23)
302 #define HDSP_spdifFrequency2 (1<<24)
303 #define HDSP_SPDIFErrorFlag (1<<25)
304 #define HDSP_BufferID (1<<26)
305 #define HDSP_TimecodeSync (1<<27)
306 #define HDSP_AEBO (1<<28) /* H9632 specific Analog Extension Boards */
307 #define HDSP_AEBI (1<<29) /* 0 = present, 1 = absent */
308 #define HDSP_midi0IRQPending (1<<30)
309 #define HDSP_midi1IRQPending (1<<31)
310
311 #define HDSP_spdifFrequencyMask (HDSP_spdifFrequency0|HDSP_spdifFrequency1|HDSP_spdifFrequency2)
312
313 #define HDSP_spdifFrequency32KHz (HDSP_spdifFrequency0)
314 #define HDSP_spdifFrequency44_1KHz (HDSP_spdifFrequency1)
315 #define HDSP_spdifFrequency48KHz (HDSP_spdifFrequency0|HDSP_spdifFrequency1)
316
317 #define HDSP_spdifFrequency64KHz (HDSP_spdifFrequency2)
318 #define HDSP_spdifFrequency88_2KHz (HDSP_spdifFrequency0|HDSP_spdifFrequency2)
319 #define HDSP_spdifFrequency96KHz (HDSP_spdifFrequency2|HDSP_spdifFrequency1)
320
321 /* This is for H9632 cards */
322 #define HDSP_spdifFrequency128KHz HDSP_spdifFrequencyMask
323 #define HDSP_spdifFrequency176_4KHz HDSP_spdifFrequency3
324 #define HDSP_spdifFrequency192KHz (HDSP_spdifFrequency3|HDSP_spdifFrequency0)
325
326 /* Status2 Register bits */
327
328 #define HDSP_version0 (1<<0)
329 #define HDSP_version1 (1<<1)
330 #define HDSP_version2 (1<<2)
331 #define HDSP_wc_lock (1<<3)
332 #define HDSP_wc_sync (1<<4)
333 #define HDSP_inp_freq0 (1<<5)
334 #define HDSP_inp_freq1 (1<<6)
335 #define HDSP_inp_freq2 (1<<7)
336 #define HDSP_SelSyncRef0 (1<<8)
337 #define HDSP_SelSyncRef1 (1<<9)
338 #define HDSP_SelSyncRef2 (1<<10)
339
340 #define HDSP_wc_valid (HDSP_wc_lock|HDSP_wc_sync)
341
342 #define HDSP_systemFrequencyMask (HDSP_inp_freq0|HDSP_inp_freq1|HDSP_inp_freq2)
343 #define HDSP_systemFrequency32 (HDSP_inp_freq0)
344 #define HDSP_systemFrequency44_1 (HDSP_inp_freq1)
345 #define HDSP_systemFrequency48 (HDSP_inp_freq0|HDSP_inp_freq1)
346 #define HDSP_systemFrequency64 (HDSP_inp_freq2)
347 #define HDSP_systemFrequency88_2 (HDSP_inp_freq0|HDSP_inp_freq2)
348 #define HDSP_systemFrequency96 (HDSP_inp_freq1|HDSP_inp_freq2)
349 /* FIXME : more values for 9632 cards ? */
350
351 #define HDSP_SelSyncRefMask (HDSP_SelSyncRef0|HDSP_SelSyncRef1|HDSP_SelSyncRef2)
352 #define HDSP_SelSyncRef_ADAT1 0
353 #define HDSP_SelSyncRef_ADAT2 (HDSP_SelSyncRef0)
354 #define HDSP_SelSyncRef_ADAT3 (HDSP_SelSyncRef1)
355 #define HDSP_SelSyncRef_SPDIF (HDSP_SelSyncRef0|HDSP_SelSyncRef1)
356 #define HDSP_SelSyncRef_WORD (HDSP_SelSyncRef2)
357 #define HDSP_SelSyncRef_ADAT_SYNC (HDSP_SelSyncRef0|HDSP_SelSyncRef2)
358
359 /* Card state flags */
360
361 #define HDSP_InitializationComplete (1<<0)
362 #define HDSP_FirmwareLoaded (1<<1)
363 #define HDSP_FirmwareCached (1<<2)
364
365 /* FIFO wait times, defined in terms of 1/10ths of msecs */
366
367 #define HDSP_LONG_WAIT 5000
368 #define HDSP_SHORT_WAIT 30
369
370 #define UNITY_GAIN 32768
371 #define MINUS_INFINITY_GAIN 0
372
373 #ifndef PCI_VENDOR_ID_XILINX
374 #define PCI_VENDOR_ID_XILINX 0x10ee
375 #endif
376 #ifndef PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP
377 #define PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP 0x3fc5
378 #endif
379
380 /* the size of a substream (1 mono data stream) */
381
382 #define HDSP_CHANNEL_BUFFER_SAMPLES (16*1024)
383 #define HDSP_CHANNEL_BUFFER_BYTES (4*HDSP_CHANNEL_BUFFER_SAMPLES)
384
385 /* the size of the area we need to allocate for DMA transfers. the
386 size is the same regardless of the number of channels - the
387 Multiface still uses the same memory area.
388
389 Note that we allocate 1 more channel than is apparently needed
390 because the h/w seems to write 1 byte beyond the end of the last
391 page. Sigh.
392 */
393
394 #define HDSP_DMA_AREA_BYTES ((HDSP_MAX_CHANNELS+1) * HDSP_CHANNEL_BUFFER_BYTES)
395 #define HDSP_DMA_AREA_KILOBYTES (HDSP_DMA_AREA_BYTES/1024)
396
397 /* use hotplug firmeare loader? */
398 #if defined(CONFIG_FW_LOADER) || defined(CONFIG_FW_LOADER_MODULE)
399 #ifndef HDSP_USE_HWDEP_LOADER
400 #define HDSP_FW_LOADER
401 #endif
402 #endif
403
404 typedef struct _hdsp hdsp_t;
405 typedef struct _hdsp_midi hdsp_midi_t;
406 typedef struct _hdsp_9632_meters hdsp_9632_meters_t;
407
408 struct _hdsp_9632_meters {
409 u32 input_peak[16];
410 u32 playback_peak[16];
411 u32 output_peak[16];
412 u32 xxx_peak[16];
413 u32 padding[64];
414 u32 input_rms_low[16];
415 u32 playback_rms_low[16];
416 u32 output_rms_low[16];
417 u32 xxx_rms_low[16];
418 u32 input_rms_high[16];
419 u32 playback_rms_high[16];
420 u32 output_rms_high[16];
421 u32 xxx_rms_high[16];
422 };
423
424 struct _hdsp_midi {
425 hdsp_t *hdsp;
426 int id;
427 snd_rawmidi_t *rmidi;
428 snd_rawmidi_substream_t *input;
429 snd_rawmidi_substream_t *output;
430 char istimer; /* timer in use */
431 struct timer_list timer;
432 spinlock_t lock;
433 int pending;
434 };
435
436 struct _hdsp {
437 spinlock_t lock;
438 snd_pcm_substream_t *capture_substream;
439 snd_pcm_substream_t *playback_substream;
440 hdsp_midi_t midi[2];
441 struct tasklet_struct midi_tasklet;
442 int use_midi_tasklet;
443 int precise_ptr;
444 u32 control_register; /* cached value */
445 u32 control2_register; /* cached value */
446 u32 creg_spdif;
447 u32 creg_spdif_stream;
448 char *card_name; /* digiface/multiface */
449 HDSP_IO_Type io_type; /* ditto, but for code use */
450 unsigned short firmware_rev;
451 unsigned short state; /* stores state bits */
452 u32 firmware_cache[24413]; /* this helps recover from accidental iobox power failure */
453 size_t period_bytes; /* guess what this is */
454 unsigned char max_channels;
455 unsigned char qs_in_channels; /* quad speed mode for H9632 */
456 unsigned char ds_in_channels;
457 unsigned char ss_in_channels; /* different for multiface/digiface */
458 unsigned char qs_out_channels;
459 unsigned char ds_out_channels;
460 unsigned char ss_out_channels;
461
462 struct snd_dma_buffer capture_dma_buf;
463 struct snd_dma_buffer playback_dma_buf;
464 unsigned char *capture_buffer; /* suitably aligned address */
465 unsigned char *playback_buffer; /* suitably aligned address */
466
467 pid_t capture_pid;
468 pid_t playback_pid;
469 int running;
470 int system_sample_rate;
471 char *channel_map;
472 int dev;
473 int irq;
474 unsigned long port;
475 void __iomem *iobase;
476 snd_card_t *card;
477 snd_pcm_t *pcm;
478 snd_hwdep_t *hwdep;
479 struct pci_dev *pci;
480 snd_kcontrol_t *spdif_ctl;
481 unsigned short mixer_matrix[HDSP_MATRIX_MIXER_SIZE];
482 };
483
484 /* These tables map the ALSA channels 1..N to the channels that we
485 need to use in order to find the relevant channel buffer. RME
486 refer to this kind of mapping as between "the ADAT channel and
487 the DMA channel." We index it using the logical audio channel,
488 and the value is the DMA channel (i.e. channel buffer number)
489 where the data for that channel can be read/written from/to.
490 */
491
492 static char channel_map_df_ss[HDSP_MAX_CHANNELS] = {
493 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,
494 18, 19, 20, 21, 22, 23, 24, 25
495 };
496
497 static char channel_map_mf_ss[HDSP_MAX_CHANNELS] = { /* Multiface */
498 /* Analog */
499 0, 1, 2, 3, 4, 5, 6, 7,
500 /* ADAT 2 */
501 16, 17, 18, 19, 20, 21, 22, 23,
502 /* SPDIF */
503 24, 25,
504 -1, -1, -1, -1, -1, -1, -1, -1
505 };
506
507 static char channel_map_ds[HDSP_MAX_CHANNELS] = {
508 /* ADAT channels are remapped */
509 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23,
510 /* channels 12 and 13 are S/PDIF */
511 24, 25,
512 /* others don't exist */
513 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
514 };
515
516 static char channel_map_H9632_ss[HDSP_MAX_CHANNELS] = {
517 /* ADAT channels */
518 0, 1, 2, 3, 4, 5, 6, 7,
519 /* SPDIF */
520 8, 9,
521 /* Analog */
522 10, 11,
523 /* AO4S-192 and AI4S-192 extension boards */
524 12, 13, 14, 15,
525 /* others don't exist */
526 -1, -1, -1, -1, -1, -1, -1, -1,
527 -1, -1
528 };
529
530 static char channel_map_H9632_ds[HDSP_MAX_CHANNELS] = {
531 /* ADAT */
532 1, 3, 5, 7,
533 /* SPDIF */
534 8, 9,
535 /* Analog */
536 10, 11,
537 /* AO4S-192 and AI4S-192 extension boards */
538 12, 13, 14, 15,
539 /* others don't exist */
540 -1, -1, -1, -1, -1, -1, -1, -1,
541 -1, -1, -1, -1, -1, -1
542 };
543
544 static char channel_map_H9632_qs[HDSP_MAX_CHANNELS] = {
545 /* ADAT is disabled in this mode */
546 /* SPDIF */
547 8, 9,
548 /* Analog */
549 10, 11,
550 /* AO4S-192 and AI4S-192 extension boards */
551 12, 13, 14, 15,
552 /* others don't exist */
553 -1, -1, -1, -1, -1, -1, -1, -1,
554 -1, -1, -1, -1, -1, -1, -1, -1,
555 -1, -1
556 };
557
558 static int snd_hammerfall_get_buffer(struct pci_dev *pci, struct snd_dma_buffer *dmab, size_t size)
559 {
560 dmab->dev.type = SNDRV_DMA_TYPE_DEV;
561 dmab->dev.dev = snd_dma_pci_data(pci);
562 if (! snd_dma_get_reserved_buf(dmab, snd_dma_pci_buf_id(pci))) {
563 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci),
564 size, dmab) < 0)
565 return -ENOMEM;
566 }
567 return 0;
568 }
569
570 static void snd_hammerfall_free_buffer(struct snd_dma_buffer *dmab, struct pci_dev *pci)
571 {
572 if (dmab->area)
573 snd_dma_reserve_buf(dmab, snd_dma_pci_buf_id(pci));
574 }
575
576
577 static struct pci_device_id snd_hdsp_ids[] = {
578 {
579 .vendor = PCI_VENDOR_ID_XILINX,
580 .device = PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP,
581 .subvendor = PCI_ANY_ID,
582 .subdevice = PCI_ANY_ID,
583 }, /* RME Hammerfall-DSP */
584 { 0, },
585 };
586
587 MODULE_DEVICE_TABLE(pci, snd_hdsp_ids);
588
589 /* prototypes */
590 static int snd_hdsp_create_alsa_devices(snd_card_t *card, hdsp_t *hdsp);
591 static int snd_hdsp_create_pcm(snd_card_t *card, hdsp_t *hdsp);
592 static int snd_hdsp_enable_io (hdsp_t *hdsp);
593 static void snd_hdsp_initialize_midi_flush (hdsp_t *hdsp);
594 static void snd_hdsp_initialize_channels (hdsp_t *hdsp);
595 static int hdsp_fifo_wait(hdsp_t *hdsp, int count, int timeout);
596 static int hdsp_autosync_ref(hdsp_t *hdsp);
597 static int snd_hdsp_set_defaults(hdsp_t *hdsp);
598 static void snd_hdsp_9652_enable_mixer (hdsp_t *hdsp);
599
600 static int hdsp_playback_to_output_key (hdsp_t *hdsp, int in, int out)
601 {
602 switch (hdsp->firmware_rev) {
603 case 0xa:
604 return (64 * out) + (32 + (in));
605 case 0x96:
606 case 0x97:
607 return (32 * out) + (16 + (in));
608 default:
609 return (52 * out) + (26 + (in));
610 }
611 }
612
613 static int hdsp_input_to_output_key (hdsp_t *hdsp, int in, int out)
614 {
615 switch (hdsp->firmware_rev) {
616 case 0xa:
617 return (64 * out) + in;
618 case 0x96:
619 case 0x97:
620 return (32 * out) + in;
621 default:
622 return (52 * out) + in;
623 }
624 }
625
626 static void hdsp_write(hdsp_t *hdsp, int reg, int val)
627 {
628 writel(val, hdsp->iobase + reg);
629 }
630
631 static unsigned int hdsp_read(hdsp_t *hdsp, int reg)
632 {
633 return readl (hdsp->iobase + reg);
634 }
635
636 static int hdsp_check_for_iobox (hdsp_t *hdsp)
637 {
638
639 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return 0;
640 if (hdsp_read (hdsp, HDSP_statusRegister) & HDSP_ConfigError) {
641 snd_printk ("Hammerfall-DSP: no Digiface or Multiface connected!\n");
642 hdsp->state &= ~HDSP_FirmwareLoaded;
643 return -EIO;
644 }
645 return 0;
646
647 }
648
649 static int snd_hdsp_load_firmware_from_cache(hdsp_t *hdsp) {
650
651 int i;
652 unsigned long flags;
653
654 if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
655
656 snd_printk ("Hammerfall-DSP: loading firmware\n");
657
658 hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_PROGRAM);
659 hdsp_write (hdsp, HDSP_fifoData, 0);
660
661 if (hdsp_fifo_wait (hdsp, 0, HDSP_LONG_WAIT)) {
662 snd_printk ("Hammerfall-DSP: timeout waiting for download preparation\n");
663 return -EIO;
664 }
665
666 hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_LOAD);
667
668 for (i = 0; i < 24413; ++i) {
669 hdsp_write(hdsp, HDSP_fifoData, hdsp->firmware_cache[i]);
670 if (hdsp_fifo_wait (hdsp, 127, HDSP_LONG_WAIT)) {
671 snd_printk ("Hammerfall-DSP: timeout during firmware loading\n");
672 return -EIO;
673 }
674 }
675
676 if ((1000 / HZ) < 3000) {
677 set_current_state(TASK_UNINTERRUPTIBLE);
678 schedule_timeout((3000 * HZ + 999) / 1000);
679 } else {
680 mdelay(3000);
681 }
682
683 if (hdsp_fifo_wait (hdsp, 0, HDSP_LONG_WAIT)) {
684 snd_printk ("Hammerfall-DSP: timeout at end of firmware loading\n");
685 return -EIO;
686 }
687
688 #ifdef SNDRV_BIG_ENDIAN
689 hdsp->control2_register = HDSP_BIGENDIAN_MODE;
690 #else
691 hdsp->control2_register = 0;
692 #endif
693 hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register);
694 snd_printk ("Hammerfall-DSP: finished firmware loading\n");
695
696 }
697 if (hdsp->state & HDSP_InitializationComplete) {
698 snd_printk("Hammerfall-DSP: firmware loaded from cache, restoring defaults\n");
699 spin_lock_irqsave(&hdsp->lock, flags);
700 snd_hdsp_set_defaults(hdsp);
701 spin_unlock_irqrestore(&hdsp->lock, flags);
702 }
703
704 hdsp->state |= HDSP_FirmwareLoaded;
705
706 return 0;
707 }
708
709 static int hdsp_get_iobox_version (hdsp_t *hdsp)
710 {
711 if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
712
713 hdsp_write (hdsp, HDSP_control2Reg, HDSP_PROGRAM);
714 hdsp_write (hdsp, HDSP_fifoData, 0);
715 if (hdsp_fifo_wait (hdsp, 0, HDSP_SHORT_WAIT) < 0) {
716 return -EIO;
717 }
718
719 hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_LOAD);
720 hdsp_write (hdsp, HDSP_fifoData, 0);
721
722 if (hdsp_fifo_wait (hdsp, 0, HDSP_SHORT_WAIT)) {
723 hdsp->io_type = Multiface;
724 hdsp_write (hdsp, HDSP_control2Reg, HDSP_VERSION_BIT);
725 hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_LOAD);
726 hdsp_fifo_wait (hdsp, 0, HDSP_SHORT_WAIT);
727 } else {
728 hdsp->io_type = Digiface;
729 }
730 } else {
731 /* firmware was already loaded, get iobox type */
732 if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version1) {
733 hdsp->io_type = Multiface;
734 } else {
735 hdsp->io_type = Digiface;
736 }
737 }
738 return 0;
739 }
740
741
742 static int hdsp_check_for_firmware (hdsp_t *hdsp)
743 {
744 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return 0;
745 if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
746 snd_printk("Hammerfall-DSP: firmware not present.\n");
747 hdsp->state &= ~HDSP_FirmwareLoaded;
748 return -EIO;
749 }
750 return 0;
751 }
752
753
754 static int hdsp_fifo_wait(hdsp_t *hdsp, int count, int timeout)
755 {
756 int i;
757
758 /* the fifoStatus registers reports on how many words
759 are available in the command FIFO.
760 */
761
762 for (i = 0; i < timeout; i++) {
763
764 if ((int)(hdsp_read (hdsp, HDSP_fifoStatus) & 0xff) <= count)
765 return 0;
766
767 /* not very friendly, but we only do this during a firmware
768 load and changing the mixer, so we just put up with it.
769 */
770
771 udelay (100);
772 }
773
774 snd_printk ("Hammerfall-DSP: wait for FIFO status <= %d failed after %d iterations\n",
775 count, timeout);
776 return -1;
777 }
778
779 static int hdsp_read_gain (hdsp_t *hdsp, unsigned int addr)
780 {
781 if (addr >= HDSP_MATRIX_MIXER_SIZE) {
782 return 0;
783 }
784 return hdsp->mixer_matrix[addr];
785 }
786
787 static int hdsp_write_gain(hdsp_t *hdsp, unsigned int addr, unsigned short data)
788 {
789 unsigned int ad;
790
791 if (addr >= HDSP_MATRIX_MIXER_SIZE)
792 return -1;
793
794 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) {
795
796 /* from martin bjornsen:
797
798 "You can only write dwords to the
799 mixer memory which contain two
800 mixer values in the low and high
801 word. So if you want to change
802 value 0 you have to read value 1
803 from the cache and write both to
804 the first dword in the mixer
805 memory."
806 */
807
808 if (hdsp->io_type == H9632 && addr >= 512) {
809 return 0;
810 }
811
812 if (hdsp->io_type == H9652 && addr >= 1352) {
813 return 0;
814 }
815
816 hdsp->mixer_matrix[addr] = data;
817
818
819 /* `addr' addresses a 16-bit wide address, but
820 the address space accessed via hdsp_write
821 uses byte offsets. put another way, addr
822 varies from 0 to 1351, but to access the
823 corresponding memory location, we need
824 to access 0 to 2703 ...
825 */
826 ad = addr/2;
827
828 hdsp_write (hdsp, 4096 + (ad*4),
829 (hdsp->mixer_matrix[(addr&0x7fe)+1] << 16) +
830 hdsp->mixer_matrix[addr&0x7fe]);
831
832 return 0;
833
834 } else {
835
836 ad = (addr << 16) + data;
837
838 if (hdsp_fifo_wait(hdsp, 127, HDSP_LONG_WAIT)) {
839 return -1;
840 }
841
842 hdsp_write (hdsp, HDSP_fifoData, ad);
843 hdsp->mixer_matrix[addr] = data;
844
845 }
846
847 return 0;
848 }
849
850 static int snd_hdsp_use_is_exclusive(hdsp_t *hdsp)
851 {
852 unsigned long flags;
853 int ret = 1;
854
855 spin_lock_irqsave(&hdsp->lock, flags);
856 if ((hdsp->playback_pid != hdsp->capture_pid) &&
857 (hdsp->playback_pid >= 0) && (hdsp->capture_pid >= 0)) {
858 ret = 0;
859 }
860 spin_unlock_irqrestore(&hdsp->lock, flags);
861 return ret;
862 }
863
864 static int hdsp_external_sample_rate (hdsp_t *hdsp)
865 {
866 unsigned int status2 = hdsp_read(hdsp, HDSP_status2Register);
867 unsigned int rate_bits = status2 & HDSP_systemFrequencyMask;
868
869 switch (rate_bits) {
870 case HDSP_systemFrequency32: return 32000;
871 case HDSP_systemFrequency44_1: return 44100;
872 case HDSP_systemFrequency48: return 48000;
873 case HDSP_systemFrequency64: return 64000;
874 case HDSP_systemFrequency88_2: return 88200;
875 case HDSP_systemFrequency96: return 96000;
876 default:
877 return 0;
878 }
879 }
880
881 static int hdsp_spdif_sample_rate(hdsp_t *hdsp)
882 {
883 unsigned int status = hdsp_read(hdsp, HDSP_statusRegister);
884 unsigned int rate_bits = (status & HDSP_spdifFrequencyMask);
885
886 if (status & HDSP_SPDIFErrorFlag) {
887 return 0;
888 }
889
890 switch (rate_bits) {
891 case HDSP_spdifFrequency32KHz: return 32000;
892 case HDSP_spdifFrequency44_1KHz: return 44100;
893 case HDSP_spdifFrequency48KHz: return 48000;
894 case HDSP_spdifFrequency64KHz: return 64000;
895 case HDSP_spdifFrequency88_2KHz: return 88200;
896 case HDSP_spdifFrequency96KHz: return 96000;
897 case HDSP_spdifFrequency128KHz:
898 if (hdsp->io_type == H9632) return 128000;
899 break;
900 case HDSP_spdifFrequency176_4KHz:
901 if (hdsp->io_type == H9632) return 176400;
902 break;
903 case HDSP_spdifFrequency192KHz:
904 if (hdsp->io_type == H9632) return 192000;
905 break;
906 default:
907 break;
908 }
909 snd_printk ("Hammerfall-DSP: unknown spdif frequency status; bits = 0x%x, status = 0x%x\n", rate_bits, status);
910 return 0;
911 }
912
913 static void hdsp_compute_period_size(hdsp_t *hdsp)
914 {
915 hdsp->period_bytes = 1 << ((hdsp_decode_latency(hdsp->control_register) + 8));
916 }
917
918 static snd_pcm_uframes_t hdsp_hw_pointer(hdsp_t *hdsp)
919 {
920 int position;
921
922 position = hdsp_read(hdsp, HDSP_statusRegister);
923
924 if (!hdsp->precise_ptr) {
925 return (position & HDSP_BufferID) ? (hdsp->period_bytes / 4) : 0;
926 }
927
928 position &= HDSP_BufferPositionMask;
929 position /= 4;
930 position &= (hdsp->period_bytes/2) - 1;
931 return position;
932 }
933
934 static void hdsp_reset_hw_pointer(hdsp_t *hdsp)
935 {
936 hdsp_write (hdsp, HDSP_resetPointer, 0);
937 }
938
939 static void hdsp_start_audio(hdsp_t *s)
940 {
941 s->control_register |= (HDSP_AudioInterruptEnable | HDSP_Start);
942 hdsp_write(s, HDSP_controlRegister, s->control_register);
943 }
944
945 static void hdsp_stop_audio(hdsp_t *s)
946 {
947 s->control_register &= ~(HDSP_Start | HDSP_AudioInterruptEnable);
948 hdsp_write(s, HDSP_controlRegister, s->control_register);
949 }
950
951 static void hdsp_silence_playback(hdsp_t *hdsp)
952 {
953 memset(hdsp->playback_buffer, 0, HDSP_DMA_AREA_BYTES);
954 }
955
956 static int hdsp_set_interrupt_interval(hdsp_t *s, unsigned int frames)
957 {
958 int n;
959
960 spin_lock_irq(&s->lock);
961
962 frames >>= 7;
963 n = 0;
964 while (frames) {
965 n++;
966 frames >>= 1;
967 }
968
969 s->control_register &= ~HDSP_LatencyMask;
970 s->control_register |= hdsp_encode_latency(n);
971
972 hdsp_write(s, HDSP_controlRegister, s->control_register);
973
974 hdsp_compute_period_size(s);
975
976 spin_unlock_irq(&s->lock);
977
978 return 0;
979 }
980
981 static int hdsp_set_rate(hdsp_t *hdsp, int rate, int called_internally)
982 {
983 int reject_if_open = 0;
984 int current_rate;
985 int rate_bits;
986
987 /* ASSUMPTION: hdsp->lock is either held, or
988 there is no need for it (e.g. during module
989 initialization).
990 */
991
992 if (!(hdsp->control_register & HDSP_ClockModeMaster)) {
993 if (called_internally) {
994 /* request from ctl or card initialization */
995 snd_printk("Hammerfall-DSP: device is not running as a clock master: cannot set sample rate.\n");
996 return -1;
997 } else {
998 /* hw_param request while in AutoSync mode */
999 int external_freq = hdsp_external_sample_rate(hdsp);
1000 int spdif_freq = hdsp_spdif_sample_rate(hdsp);
1001
1002 if ((spdif_freq == external_freq*2) && (hdsp_autosync_ref(hdsp) >= HDSP_AUTOSYNC_FROM_ADAT1)) {
1003 snd_printk("Hammerfall-DSP: Detected ADAT in double speed mode\n");
1004 } else if (hdsp->io_type == H9632 && (spdif_freq == external_freq*4) && (hdsp_autosync_ref(hdsp) >= HDSP_AUTOSYNC_FROM_ADAT1)) {
1005 snd_printk("Hammerfall-DSP: Detected ADAT in quad speed mode\n");
1006 } else if (rate != external_freq) {
1007 snd_printk("Hammerfall-DSP: No AutoSync source for requested rate\n");
1008 return -1;
1009 }
1010 }
1011 }
1012
1013 current_rate = hdsp->system_sample_rate;
1014
1015 /* Changing from a "single speed" to a "double speed" rate is
1016 not allowed if any substreams are open. This is because
1017 such a change causes a shift in the location of
1018 the DMA buffers and a reduction in the number of available
1019 buffers.
1020
1021 Note that a similar but essentially insoluble problem
1022 exists for externally-driven rate changes. All we can do
1023 is to flag rate changes in the read/write routines. */
1024
1025 if (rate > 96000 && hdsp->io_type != H9632) {
1026 return -EINVAL;
1027 }
1028
1029 switch (rate) {
1030 case 32000:
1031 if (current_rate > 48000) {
1032 reject_if_open = 1;
1033 }
1034 rate_bits = HDSP_Frequency32KHz;
1035 break;
1036 case 44100:
1037 if (current_rate > 48000) {
1038 reject_if_open = 1;
1039 }
1040 rate_bits = HDSP_Frequency44_1KHz;
1041 break;
1042 case 48000:
1043 if (current_rate > 48000) {
1044 reject_if_open = 1;
1045 }
1046 rate_bits = HDSP_Frequency48KHz;
1047 break;
1048 case 64000:
1049 if (current_rate <= 48000 || current_rate > 96000) {
1050 reject_if_open = 1;
1051 }
1052 rate_bits = HDSP_Frequency64KHz;
1053 break;
1054 case 88200:
1055 if (current_rate <= 48000 || current_rate > 96000) {
1056 reject_if_open = 1;
1057 }
1058 rate_bits = HDSP_Frequency88_2KHz;
1059 break;
1060 case 96000:
1061 if (current_rate <= 48000 || current_rate > 96000) {
1062 reject_if_open = 1;
1063 }
1064 rate_bits = HDSP_Frequency96KHz;
1065 break;
1066 case 128000:
1067 if (current_rate < 128000) {
1068 reject_if_open = 1;
1069 }
1070 rate_bits = HDSP_Frequency128KHz;
1071 break;
1072 case 176400:
1073 if (current_rate < 128000) {
1074 reject_if_open = 1;
1075 }
1076 rate_bits = HDSP_Frequency176_4KHz;
1077 break;
1078 case 192000:
1079 if (current_rate < 128000) {
1080 reject_if_open = 1;
1081 }
1082 rate_bits = HDSP_Frequency192KHz;
1083 break;
1084 default:
1085 return -EINVAL;
1086 }
1087
1088 if (reject_if_open && (hdsp->capture_pid >= 0 || hdsp->playback_pid >= 0)) {
1089 snd_printk ("Hammerfall-DSP: cannot change speed mode (capture PID = %d, playback PID = %d)\n",
1090 hdsp->capture_pid,
1091 hdsp->playback_pid);
1092 return -EBUSY;
1093 }
1094
1095 hdsp->control_register &= ~HDSP_FrequencyMask;
1096 hdsp->control_register |= rate_bits;
1097 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1098
1099 if (rate >= 128000) {
1100 hdsp->channel_map = channel_map_H9632_qs;
1101 } else if (rate > 48000) {
1102 if (hdsp->io_type == H9632) {
1103 hdsp->channel_map = channel_map_H9632_ds;
1104 } else {
1105 hdsp->channel_map = channel_map_ds;
1106 }
1107 } else {
1108 switch (hdsp->io_type) {
1109 case Multiface:
1110 hdsp->channel_map = channel_map_mf_ss;
1111 break;
1112 case Digiface:
1113 case H9652:
1114 hdsp->channel_map = channel_map_df_ss;
1115 break;
1116 case H9632:
1117 hdsp->channel_map = channel_map_H9632_ss;
1118 break;
1119 default:
1120 /* should never happen */
1121 break;
1122 }
1123 }
1124
1125 hdsp->system_sample_rate = rate;
1126
1127 return 0;
1128 }
1129
1130 /*----------------------------------------------------------------------------
1131 MIDI
1132 ----------------------------------------------------------------------------*/
1133
1134 static unsigned char snd_hdsp_midi_read_byte (hdsp_t *hdsp, int id)
1135 {
1136 /* the hardware already does the relevant bit-mask with 0xff */
1137 if (id) {
1138 return hdsp_read(hdsp, HDSP_midiDataIn1);
1139 } else {
1140 return hdsp_read(hdsp, HDSP_midiDataIn0);
1141 }
1142 }
1143
1144 static void snd_hdsp_midi_write_byte (hdsp_t *hdsp, int id, int val)
1145 {
1146 /* the hardware already does the relevant bit-mask with 0xff */
1147 if (id) {
1148 hdsp_write(hdsp, HDSP_midiDataOut1, val);
1149 } else {
1150 hdsp_write(hdsp, HDSP_midiDataOut0, val);
1151 }
1152 }
1153
1154 static int snd_hdsp_midi_input_available (hdsp_t *hdsp, int id)
1155 {
1156 if (id) {
1157 return (hdsp_read(hdsp, HDSP_midiStatusIn1) & 0xff);
1158 } else {
1159 return (hdsp_read(hdsp, HDSP_midiStatusIn0) & 0xff);
1160 }
1161 }
1162
1163 static int snd_hdsp_midi_output_possible (hdsp_t *hdsp, int id)
1164 {
1165 int fifo_bytes_used;
1166
1167 if (id) {
1168 fifo_bytes_used = hdsp_read(hdsp, HDSP_midiStatusOut1) & 0xff;
1169 } else {
1170 fifo_bytes_used = hdsp_read(hdsp, HDSP_midiStatusOut0) & 0xff;
1171 }
1172
1173 if (fifo_bytes_used < 128) {
1174 return 128 - fifo_bytes_used;
1175 } else {
1176 return 0;
1177 }
1178 }
1179
1180 static void snd_hdsp_flush_midi_input (hdsp_t *hdsp, int id)
1181 {
1182 while (snd_hdsp_midi_input_available (hdsp, id)) {
1183 snd_hdsp_midi_read_byte (hdsp, id);
1184 }
1185 }
1186
1187 static int snd_hdsp_midi_output_write (hdsp_midi_t *hmidi)
1188 {
1189 unsigned long flags;
1190 int n_pending;
1191 int to_write;
1192 int i;
1193 unsigned char buf[128];
1194
1195 /* Output is not interrupt driven */
1196
1197 spin_lock_irqsave (&hmidi->lock, flags);
1198 if (hmidi->output) {
1199 if (!snd_rawmidi_transmit_empty (hmidi->output)) {
1200 if ((n_pending = snd_hdsp_midi_output_possible (hmidi->hdsp, hmidi->id)) > 0) {
1201 if (n_pending > (int)sizeof (buf))
1202 n_pending = sizeof (buf);
1203
1204 if ((to_write = snd_rawmidi_transmit (hmidi->output, buf, n_pending)) > 0) {
1205 for (i = 0; i < to_write; ++i)
1206 snd_hdsp_midi_write_byte (hmidi->hdsp, hmidi->id, buf[i]);
1207 }
1208 }
1209 }
1210 }
1211 spin_unlock_irqrestore (&hmidi->lock, flags);
1212 return 0;
1213 }
1214
1215 static int snd_hdsp_midi_input_read (hdsp_midi_t *hmidi)
1216 {
1217 unsigned char buf[128]; /* this buffer is designed to match the MIDI input FIFO size */
1218 unsigned long flags;
1219 int n_pending;
1220 int i;
1221
1222 spin_lock_irqsave (&hmidi->lock, flags);
1223 if ((n_pending = snd_hdsp_midi_input_available (hmidi->hdsp, hmidi->id)) > 0) {
1224 if (hmidi->input) {
1225 if (n_pending > (int)sizeof (buf)) {
1226 n_pending = sizeof (buf);
1227 }
1228 for (i = 0; i < n_pending; ++i) {
1229 buf[i] = snd_hdsp_midi_read_byte (hmidi->hdsp, hmidi->id);
1230 }
1231 if (n_pending) {
1232 snd_rawmidi_receive (hmidi->input, buf, n_pending);
1233 }
1234 } else {
1235 /* flush the MIDI input FIFO */
1236 while (--n_pending) {
1237 snd_hdsp_midi_read_byte (hmidi->hdsp, hmidi->id);
1238 }
1239 }
1240 }
1241 hmidi->pending = 0;
1242 if (hmidi->id) {
1243 hmidi->hdsp->control_register |= HDSP_Midi1InterruptEnable;
1244 } else {
1245 hmidi->hdsp->control_register |= HDSP_Midi0InterruptEnable;
1246 }
1247 hdsp_write(hmidi->hdsp, HDSP_controlRegister, hmidi->hdsp->control_register);
1248 spin_unlock_irqrestore (&hmidi->lock, flags);
1249 return snd_hdsp_midi_output_write (hmidi);
1250 }
1251
1252 static void snd_hdsp_midi_input_trigger(snd_rawmidi_substream_t * substream, int up)
1253 {
1254 hdsp_t *hdsp;
1255 hdsp_midi_t *hmidi;
1256 unsigned long flags;
1257 u32 ie;
1258
1259 hmidi = (hdsp_midi_t *) substream->rmidi->private_data;
1260 hdsp = hmidi->hdsp;
1261 ie = hmidi->id ? HDSP_Midi1InterruptEnable : HDSP_Midi0InterruptEnable;
1262 spin_lock_irqsave (&hdsp->lock, flags);
1263 if (up) {
1264 if (!(hdsp->control_register & ie)) {
1265 snd_hdsp_flush_midi_input (hdsp, hmidi->id);
1266 hdsp->control_register |= ie;
1267 }
1268 } else {
1269 hdsp->control_register &= ~ie;
1270 tasklet_kill(&hdsp->midi_tasklet);
1271 }
1272
1273 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1274 spin_unlock_irqrestore (&hdsp->lock, flags);
1275 }
1276
1277 static void snd_hdsp_midi_output_timer(unsigned long data)
1278 {
1279 hdsp_midi_t *hmidi = (hdsp_midi_t *) data;
1280 unsigned long flags;
1281
1282 snd_hdsp_midi_output_write(hmidi);
1283 spin_lock_irqsave (&hmidi->lock, flags);
1284
1285 /* this does not bump hmidi->istimer, because the
1286 kernel automatically removed the timer when it
1287 expired, and we are now adding it back, thus
1288 leaving istimer wherever it was set before.
1289 */
1290
1291 if (hmidi->istimer) {
1292 hmidi->timer.expires = 1 + jiffies;
1293 add_timer(&hmidi->timer);
1294 }
1295
1296 spin_unlock_irqrestore (&hmidi->lock, flags);
1297 }
1298
1299 static void snd_hdsp_midi_output_trigger(snd_rawmidi_substream_t * substream, int up)
1300 {
1301 hdsp_midi_t *hmidi;
1302 unsigned long flags;
1303
1304 hmidi = (hdsp_midi_t *) substream->rmidi->private_data;
1305 spin_lock_irqsave (&hmidi->lock, flags);
1306 if (up) {
1307 if (!hmidi->istimer) {
1308 init_timer(&hmidi->timer);
1309 hmidi->timer.function = snd_hdsp_midi_output_timer;
1310 hmidi->timer.data = (unsigned long) hmidi;
1311 hmidi->timer.expires = 1 + jiffies;
1312 add_timer(&hmidi->timer);
1313 hmidi->istimer++;
1314 }
1315 } else {
1316 if (hmidi->istimer && --hmidi->istimer <= 0) {
1317 del_timer (&hmidi->timer);
1318 }
1319 }
1320 spin_unlock_irqrestore (&hmidi->lock, flags);
1321 if (up)
1322 snd_hdsp_midi_output_write(hmidi);
1323 }
1324
1325 static int snd_hdsp_midi_input_open(snd_rawmidi_substream_t * substream)
1326 {
1327 hdsp_midi_t *hmidi;
1328
1329 hmidi = (hdsp_midi_t *) substream->rmidi->private_data;
1330 spin_lock_irq (&hmidi->lock);
1331 snd_hdsp_flush_midi_input (hmidi->hdsp, hmidi->id);
1332 hmidi->input = substream;
1333 spin_unlock_irq (&hmidi->lock);
1334
1335 return 0;
1336 }
1337
1338 static int snd_hdsp_midi_output_open(snd_rawmidi_substream_t * substream)
1339 {
1340 hdsp_midi_t *hmidi;
1341
1342 hmidi = (hdsp_midi_t *) substream->rmidi->private_data;
1343 spin_lock_irq (&hmidi->lock);
1344 hmidi->output = substream;
1345 spin_unlock_irq (&hmidi->lock);
1346
1347 return 0;
1348 }
1349
1350 static int snd_hdsp_midi_input_close(snd_rawmidi_substream_t * substream)
1351 {
1352 hdsp_midi_t *hmidi;
1353
1354 snd_hdsp_midi_input_trigger (substream, 0);
1355
1356 hmidi = (hdsp_midi_t *) substream->rmidi->private_data;
1357 spin_lock_irq (&hmidi->lock);
1358 hmidi->input = NULL;
1359 spin_unlock_irq (&hmidi->lock);
1360
1361 return 0;
1362 }
1363
1364 static int snd_hdsp_midi_output_close(snd_rawmidi_substream_t * substream)
1365 {
1366 hdsp_midi_t *hmidi;
1367
1368 snd_hdsp_midi_output_trigger (substream, 0);
1369
1370 hmidi = (hdsp_midi_t *) substream->rmidi->private_data;
1371 spin_lock_irq (&hmidi->lock);
1372 hmidi->output = NULL;
1373 spin_unlock_irq (&hmidi->lock);
1374
1375 return 0;
1376 }
1377
1378 static snd_rawmidi_ops_t snd_hdsp_midi_output =
1379 {
1380 .open = snd_hdsp_midi_output_open,
1381 .close = snd_hdsp_midi_output_close,
1382 .trigger = snd_hdsp_midi_output_trigger,
1383 };
1384
1385 static snd_rawmidi_ops_t snd_hdsp_midi_input =
1386 {
1387 .open = snd_hdsp_midi_input_open,
1388 .close = snd_hdsp_midi_input_close,
1389 .trigger = snd_hdsp_midi_input_trigger,
1390 };
1391
1392 static int __devinit snd_hdsp_create_midi (snd_card_t *card, hdsp_t *hdsp, int id)
1393 {
1394 char buf[32];
1395
1396 hdsp->midi[id].id = id;
1397 hdsp->midi[id].rmidi = NULL;
1398 hdsp->midi[id].input = NULL;
1399 hdsp->midi[id].output = NULL;
1400 hdsp->midi[id].hdsp = hdsp;
1401 hdsp->midi[id].istimer = 0;
1402 hdsp->midi[id].pending = 0;
1403 spin_lock_init (&hdsp->midi[id].lock);
1404
1405 sprintf (buf, "%s MIDI %d", card->shortname, id+1);
1406 if (snd_rawmidi_new (card, buf, id, 1, 1, &hdsp->midi[id].rmidi) < 0) {
1407 return -1;
1408 }
1409
1410 sprintf (hdsp->midi[id].rmidi->name, "%s MIDI %d", card->id, id+1);
1411 hdsp->midi[id].rmidi->private_data = &hdsp->midi[id];
1412
1413 snd_rawmidi_set_ops (hdsp->midi[id].rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_hdsp_midi_output);
1414 snd_rawmidi_set_ops (hdsp->midi[id].rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_hdsp_midi_input);
1415
1416 hdsp->midi[id].rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT |
1417 SNDRV_RAWMIDI_INFO_INPUT |
1418 SNDRV_RAWMIDI_INFO_DUPLEX;
1419
1420 return 0;
1421 }
1422
1423 /*-----------------------------------------------------------------------------
1424 Control Interface
1425 ----------------------------------------------------------------------------*/
1426
1427 static u32 snd_hdsp_convert_from_aes(snd_aes_iec958_t *aes)
1428 {
1429 u32 val = 0;
1430 val |= (aes->status[0] & IEC958_AES0_PROFESSIONAL) ? HDSP_SPDIFProfessional : 0;
1431 val |= (aes->status[0] & IEC958_AES0_NONAUDIO) ? HDSP_SPDIFNonAudio : 0;
1432 if (val & HDSP_SPDIFProfessional)
1433 val |= (aes->status[0] & IEC958_AES0_PRO_EMPHASIS_5015) ? HDSP_SPDIFEmphasis : 0;
1434 else
1435 val |= (aes->status[0] & IEC958_AES0_CON_EMPHASIS_5015) ? HDSP_SPDIFEmphasis : 0;
1436 return val;
1437 }
1438
1439 static void snd_hdsp_convert_to_aes(snd_aes_iec958_t *aes, u32 val)
1440 {
1441 aes->status[0] = ((val & HDSP_SPDIFProfessional) ? IEC958_AES0_PROFESSIONAL : 0) |
1442 ((val & HDSP_SPDIFNonAudio) ? IEC958_AES0_NONAUDIO : 0);
1443 if (val & HDSP_SPDIFProfessional)
1444 aes->status[0] |= (val & HDSP_SPDIFEmphasis) ? IEC958_AES0_PRO_EMPHASIS_5015 : 0;
1445 else
1446 aes->status[0] |= (val & HDSP_SPDIFEmphasis) ? IEC958_AES0_CON_EMPHASIS_5015 : 0;
1447 }
1448
1449 static int snd_hdsp_control_spdif_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1450 {
1451 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1452 uinfo->count = 1;
1453 return 0;
1454 }
1455
1456 static int snd_hdsp_control_spdif_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1457 {
1458 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1459
1460 snd_hdsp_convert_to_aes(&ucontrol->value.iec958, hdsp->creg_spdif);
1461 return 0;
1462 }
1463
1464 static int snd_hdsp_control_spdif_put(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1465 {
1466 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1467 int change;
1468 u32 val;
1469
1470 val = snd_hdsp_convert_from_aes(&ucontrol->value.iec958);
1471 spin_lock_irq(&hdsp->lock);
1472 change = val != hdsp->creg_spdif;
1473 hdsp->creg_spdif = val;
1474 spin_unlock_irq(&hdsp->lock);
1475 return change;
1476 }
1477
1478 static int snd_hdsp_control_spdif_stream_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1479 {
1480 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1481 uinfo->count = 1;
1482 return 0;
1483 }
1484
1485 static int snd_hdsp_control_spdif_stream_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1486 {
1487 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1488
1489 snd_hdsp_convert_to_aes(&ucontrol->value.iec958, hdsp->creg_spdif_stream);
1490 return 0;
1491 }
1492
1493 static int snd_hdsp_control_spdif_stream_put(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1494 {
1495 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1496 int change;
1497 u32 val;
1498
1499 val = snd_hdsp_convert_from_aes(&ucontrol->value.iec958);
1500 spin_lock_irq(&hdsp->lock);
1501 change = val != hdsp->creg_spdif_stream;
1502 hdsp->creg_spdif_stream = val;
1503 hdsp->control_register &= ~(HDSP_SPDIFProfessional | HDSP_SPDIFNonAudio | HDSP_SPDIFEmphasis);
1504 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register |= val);
1505 spin_unlock_irq(&hdsp->lock);
1506 return change;
1507 }
1508
1509 static int snd_hdsp_control_spdif_mask_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1510 {
1511 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1512 uinfo->count = 1;
1513 return 0;
1514 }
1515
1516 static int snd_hdsp_control_spdif_mask_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1517 {
1518 ucontrol->value.iec958.status[0] = kcontrol->private_value;
1519 return 0;
1520 }
1521
1522 #define HDSP_SPDIF_IN(xname, xindex) \
1523 { .iface = SNDRV_CTL_ELEM_IFACE_PCM, \
1524 .name = xname, \
1525 .index = xindex, \
1526 .info = snd_hdsp_info_spdif_in, \
1527 .get = snd_hdsp_get_spdif_in, \
1528 .put = snd_hdsp_put_spdif_in }
1529
1530 static unsigned int hdsp_spdif_in(hdsp_t *hdsp)
1531 {
1532 return hdsp_decode_spdif_in(hdsp->control_register & HDSP_SPDIFInputMask);
1533 }
1534
1535 static int hdsp_set_spdif_input(hdsp_t *hdsp, int in)
1536 {
1537 hdsp->control_register &= ~HDSP_SPDIFInputMask;
1538 hdsp->control_register |= hdsp_encode_spdif_in(in);
1539 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1540 return 0;
1541 }
1542
1543 static int snd_hdsp_info_spdif_in(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1544 {
1545 static char *texts[4] = {"Optical", "Coaxial", "Internal", "AES"};
1546 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1547
1548 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1549 uinfo->count = 1;
1550 uinfo->value.enumerated.items = ((hdsp->io_type == H9632) ? 4 : 3);
1551 if (uinfo->value.enumerated.item > ((hdsp->io_type == H9632) ? 3 : 2))
1552 uinfo->value.enumerated.item = ((hdsp->io_type == H9632) ? 3 : 2);
1553 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
1554 return 0;
1555 }
1556
1557 static int snd_hdsp_get_spdif_in(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1558 {
1559 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1560
1561 ucontrol->value.enumerated.item[0] = hdsp_spdif_in(hdsp);
1562 return 0;
1563 }
1564
1565 static int snd_hdsp_put_spdif_in(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1566 {
1567 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1568 int change;
1569 unsigned int val;
1570
1571 if (!snd_hdsp_use_is_exclusive(hdsp))
1572 return -EBUSY;
1573 val = ucontrol->value.enumerated.item[0] % ((hdsp->io_type == H9632) ? 4 : 3);
1574 spin_lock_irq(&hdsp->lock);
1575 change = val != hdsp_spdif_in(hdsp);
1576 if (change)
1577 hdsp_set_spdif_input(hdsp, val);
1578 spin_unlock_irq(&hdsp->lock);
1579 return change;
1580 }
1581
1582 #define HDSP_SPDIF_OUT(xname, xindex) \
1583 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, .name = xname, .index = xindex, \
1584 .info = snd_hdsp_info_spdif_bits, \
1585 .get = snd_hdsp_get_spdif_out, .put = snd_hdsp_put_spdif_out }
1586
1587 static int hdsp_spdif_out(hdsp_t *hdsp)
1588 {
1589 return (hdsp->control_register & HDSP_SPDIFOpticalOut) ? 1 : 0;
1590 }
1591
1592 static int hdsp_set_spdif_output(hdsp_t *hdsp, int out)
1593 {
1594 if (out) {
1595 hdsp->control_register |= HDSP_SPDIFOpticalOut;
1596 } else {
1597 hdsp->control_register &= ~HDSP_SPDIFOpticalOut;
1598 }
1599 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1600 return 0;
1601 }
1602
1603 static int snd_hdsp_info_spdif_bits(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1604 {
1605 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1606 uinfo->count = 1;
1607 uinfo->value.integer.min = 0;
1608 uinfo->value.integer.max = 1;
1609 return 0;
1610 }
1611
1612 static int snd_hdsp_get_spdif_out(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1613 {
1614 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1615
1616 ucontrol->value.integer.value[0] = hdsp_spdif_out(hdsp);
1617 return 0;
1618 }
1619
1620 static int snd_hdsp_put_spdif_out(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1621 {
1622 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1623 int change;
1624 unsigned int val;
1625
1626 if (!snd_hdsp_use_is_exclusive(hdsp))
1627 return -EBUSY;
1628 val = ucontrol->value.integer.value[0] & 1;
1629 spin_lock_irq(&hdsp->lock);
1630 change = (int)val != hdsp_spdif_out(hdsp);
1631 hdsp_set_spdif_output(hdsp, val);
1632 spin_unlock_irq(&hdsp->lock);
1633 return change;
1634 }
1635
1636 #define HDSP_SPDIF_PROFESSIONAL(xname, xindex) \
1637 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, .name = xname, .index = xindex, \
1638 .info = snd_hdsp_info_spdif_bits, \
1639 .get = snd_hdsp_get_spdif_professional, .put = snd_hdsp_put_spdif_professional }
1640
1641 static int hdsp_spdif_professional(hdsp_t *hdsp)
1642 {
1643 return (hdsp->control_register & HDSP_SPDIFProfessional) ? 1 : 0;
1644 }
1645
1646 static int hdsp_set_spdif_professional(hdsp_t *hdsp, int val)
1647 {
1648 if (val) {
1649 hdsp->control_register |= HDSP_SPDIFProfessional;
1650 } else {
1651 hdsp->control_register &= ~HDSP_SPDIFProfessional;
1652 }
1653 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1654 return 0;
1655 }
1656
1657 static int snd_hdsp_get_spdif_professional(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1658 {
1659 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1660
1661 ucontrol->value.integer.value[0] = hdsp_spdif_professional(hdsp);
1662 return 0;
1663 }
1664
1665 static int snd_hdsp_put_spdif_professional(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1666 {
1667 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1668 int change;
1669 unsigned int val;
1670
1671 if (!snd_hdsp_use_is_exclusive(hdsp))
1672 return -EBUSY;
1673 val = ucontrol->value.integer.value[0] & 1;
1674 spin_lock_irq(&hdsp->lock);
1675 change = (int)val != hdsp_spdif_professional(hdsp);
1676 hdsp_set_spdif_professional(hdsp, val);
1677 spin_unlock_irq(&hdsp->lock);
1678 return change;
1679 }
1680
1681 #define HDSP_SPDIF_EMPHASIS(xname, xindex) \
1682 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, .name = xname, .index = xindex, \
1683 .info = snd_hdsp_info_spdif_bits, \
1684 .get = snd_hdsp_get_spdif_emphasis, .put = snd_hdsp_put_spdif_emphasis }
1685
1686 static int hdsp_spdif_emphasis(hdsp_t *hdsp)
1687 {
1688 return (hdsp->control_register & HDSP_SPDIFEmphasis) ? 1 : 0;
1689 }
1690
1691 static int hdsp_set_spdif_emphasis(hdsp_t *hdsp, int val)
1692 {
1693 if (val) {
1694 hdsp->control_register |= HDSP_SPDIFEmphasis;
1695 } else {
1696 hdsp->control_register &= ~HDSP_SPDIFEmphasis;
1697 }
1698 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1699 return 0;
1700 }
1701
1702 static int snd_hdsp_get_spdif_emphasis(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1703 {
1704 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1705
1706 ucontrol->value.integer.value[0] = hdsp_spdif_emphasis(hdsp);
1707 return 0;
1708 }
1709
1710 static int snd_hdsp_put_spdif_emphasis(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1711 {
1712 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1713 int change;
1714 unsigned int val;
1715
1716 if (!snd_hdsp_use_is_exclusive(hdsp))
1717 return -EBUSY;
1718 val = ucontrol->value.integer.value[0] & 1;
1719 spin_lock_irq(&hdsp->lock);
1720 change = (int)val != hdsp_spdif_emphasis(hdsp);
1721 hdsp_set_spdif_emphasis(hdsp, val);
1722 spin_unlock_irq(&hdsp->lock);
1723 return change;
1724 }
1725
1726 #define HDSP_SPDIF_NON_AUDIO(xname, xindex) \
1727 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, .name = xname, .index = xindex, \
1728 .info = snd_hdsp_info_spdif_bits, \
1729 .get = snd_hdsp_get_spdif_nonaudio, .put = snd_hdsp_put_spdif_nonaudio }
1730
1731 static int hdsp_spdif_nonaudio(hdsp_t *hdsp)
1732 {
1733 return (hdsp->control_register & HDSP_SPDIFNonAudio) ? 1 : 0;
1734 }
1735
1736 static int hdsp_set_spdif_nonaudio(hdsp_t *hdsp, int val)
1737 {
1738 if (val) {
1739 hdsp->control_register |= HDSP_SPDIFNonAudio;
1740 } else {
1741 hdsp->control_register &= ~HDSP_SPDIFNonAudio;
1742 }
1743 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1744 return 0;
1745 }
1746
1747 static int snd_hdsp_get_spdif_nonaudio(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1748 {
1749 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1750
1751 ucontrol->value.integer.value[0] = hdsp_spdif_nonaudio(hdsp);
1752 return 0;
1753 }
1754
1755 static int snd_hdsp_put_spdif_nonaudio(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1756 {
1757 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1758 int change;
1759 unsigned int val;
1760
1761 if (!snd_hdsp_use_is_exclusive(hdsp))
1762 return -EBUSY;
1763 val = ucontrol->value.integer.value[0] & 1;
1764 spin_lock_irq(&hdsp->lock);
1765 change = (int)val != hdsp_spdif_nonaudio(hdsp);
1766 hdsp_set_spdif_nonaudio(hdsp, val);
1767 spin_unlock_irq(&hdsp->lock);
1768 return change;
1769 }
1770
1771 #define HDSP_SPDIF_SAMPLE_RATE(xname, xindex) \
1772 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
1773 .name = xname, \
1774 .index = xindex, \
1775 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1776 .info = snd_hdsp_info_spdif_sample_rate, \
1777 .get = snd_hdsp_get_spdif_sample_rate \
1778 }
1779
1780 static int snd_hdsp_info_spdif_sample_rate(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1781 {
1782 static char *texts[] = {"32000", "44100", "48000", "64000", "88200", "96000", "None", "128000", "176400", "192000"};
1783 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1784
1785 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1786 uinfo->count = 1;
1787 uinfo->value.enumerated.items = (hdsp->io_type == H9632) ? 10 : 7;
1788 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
1789 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
1790 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
1791 return 0;
1792 }
1793
1794 static int snd_hdsp_get_spdif_sample_rate(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1795 {
1796 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1797
1798 switch (hdsp_spdif_sample_rate(hdsp)) {
1799 case 32000:
1800 ucontrol->value.enumerated.item[0] = 0;
1801 break;
1802 case 44100:
1803 ucontrol->value.enumerated.item[0] = 1;
1804 break;
1805 case 48000:
1806 ucontrol->value.enumerated.item[0] = 2;
1807 break;
1808 case 64000:
1809 ucontrol->value.enumerated.item[0] = 3;
1810 break;
1811 case 88200:
1812 ucontrol->value.enumerated.item[0] = 4;
1813 break;
1814 case 96000:
1815 ucontrol->value.enumerated.item[0] = 5;
1816 break;
1817 case 128000:
1818 ucontrol->value.enumerated.item[0] = 7;
1819 break;
1820 case 176400:
1821 ucontrol->value.enumerated.item[0] = 8;
1822 break;
1823 case 192000:
1824 ucontrol->value.enumerated.item[0] = 9;
1825 break;
1826 default:
1827 ucontrol->value.enumerated.item[0] = 6;
1828 }
1829 return 0;
1830 }
1831
1832 #define HDSP_SYSTEM_SAMPLE_RATE(xname, xindex) \
1833 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
1834 .name = xname, \
1835 .index = xindex, \
1836 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1837 .info = snd_hdsp_info_system_sample_rate, \
1838 .get = snd_hdsp_get_system_sample_rate \
1839 }
1840
1841 static int snd_hdsp_info_system_sample_rate(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1842 {
1843 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1844 uinfo->count = 1;
1845 return 0;
1846 }
1847
1848 static int snd_hdsp_get_system_sample_rate(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1849 {
1850 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1851
1852 ucontrol->value.enumerated.item[0] = hdsp->system_sample_rate;
1853 return 0;
1854 }
1855
1856 #define HDSP_AUTOSYNC_SAMPLE_RATE(xname, xindex) \
1857 { .iface = SNDRV_CTL_ELEM_IFACE_PCM, \
1858 .name = xname, \
1859 .index = xindex, \
1860 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1861 .info = snd_hdsp_info_autosync_sample_rate, \
1862 .get = snd_hdsp_get_autosync_sample_rate \
1863 }
1864
1865 static int snd_hdsp_info_autosync_sample_rate(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1866 {
1867 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1868 static char *texts[] = {"32000", "44100", "48000", "64000", "88200", "96000", "None", "128000", "176400", "192000"};
1869 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1870 uinfo->count = 1;
1871 uinfo->value.enumerated.items = (hdsp->io_type == H9632) ? 10 : 7 ;
1872 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
1873 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
1874 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
1875 return 0;
1876 }
1877
1878 static int snd_hdsp_get_autosync_sample_rate(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1879 {
1880 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1881
1882 switch (hdsp_external_sample_rate(hdsp)) {
1883 case 32000:
1884 ucontrol->value.enumerated.item[0] = 0;
1885 break;
1886 case 44100:
1887 ucontrol->value.enumerated.item[0] = 1;
1888 break;
1889 case 48000:
1890 ucontrol->value.enumerated.item[0] = 2;
1891 break;
1892 case 64000:
1893 ucontrol->value.enumerated.item[0] = 3;
1894 break;
1895 case 88200:
1896 ucontrol->value.enumerated.item[0] = 4;
1897 break;
1898 case 96000:
1899 ucontrol->value.enumerated.item[0] = 5;
1900 break;
1901 case 128000:
1902 ucontrol->value.enumerated.item[0] = 7;
1903 break;
1904 case 176400:
1905 ucontrol->value.enumerated.item[0] = 8;
1906 break;
1907 case 192000:
1908 ucontrol->value.enumerated.item[0] = 9;
1909 break;
1910 default:
1911 ucontrol->value.enumerated.item[0] = 6;
1912 }
1913 return 0;
1914 }
1915
1916 #define HDSP_SYSTEM_CLOCK_MODE(xname, xindex) \
1917 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
1918 .name = xname, \
1919 .index = xindex, \
1920 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1921 .info = snd_hdsp_info_system_clock_mode, \
1922 .get = snd_hdsp_get_system_clock_mode \
1923 }
1924
1925 static int hdsp_system_clock_mode(hdsp_t *hdsp)
1926 {
1927 if (hdsp->control_register & HDSP_ClockModeMaster) {
1928 return 0;
1929 } else if (hdsp_external_sample_rate(hdsp) != hdsp->system_sample_rate) {
1930 return 0;
1931 }
1932 return 1;
1933 }
1934
1935 static int snd_hdsp_info_system_clock_mode(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1936 {
1937 static char *texts[] = {"Master", "Slave" };
1938
1939 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1940 uinfo->count = 1;
1941 uinfo->value.enumerated.items = 2;
1942 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
1943 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
1944 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
1945 return 0;
1946 }
1947
1948 static int snd_hdsp_get_system_clock_mode(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1949 {
1950 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1951
1952 ucontrol->value.enumerated.item[0] = hdsp_system_clock_mode(hdsp);
1953 return 0;
1954 }
1955
1956 #define HDSP_CLOCK_SOURCE(xname, xindex) \
1957 { .iface = SNDRV_CTL_ELEM_IFACE_PCM, \
1958 .name = xname, \
1959 .index = xindex, \
1960 .info = snd_hdsp_info_clock_source, \
1961 .get = snd_hdsp_get_clock_source, \
1962 .put = snd_hdsp_put_clock_source \
1963 }
1964
1965 static int hdsp_clock_source(hdsp_t *hdsp)
1966 {
1967 if (hdsp->control_register & HDSP_ClockModeMaster) {
1968 switch (hdsp->system_sample_rate) {
1969 case 32000:
1970 return 1;
1971 case 44100:
1972 return 2;
1973 case 48000:
1974 return 3;
1975 case 64000:
1976 return 4;
1977 case 88200:
1978 return 5;
1979 case 96000:
1980 return 6;
1981 case 128000:
1982 return 7;
1983 case 176400:
1984 return 8;
1985 case 192000:
1986 return 9;
1987 default:
1988 return 3;
1989 }
1990 } else {
1991 return 0;
1992 }
1993 }
1994
1995 static int hdsp_set_clock_source(hdsp_t *hdsp, int mode)
1996 {
1997 int rate;
1998 switch (mode) {
1999 case HDSP_CLOCK_SOURCE_AUTOSYNC:
2000 if (hdsp_external_sample_rate(hdsp) != 0) {
2001 if (!hdsp_set_rate(hdsp, hdsp_external_sample_rate(hdsp), 1)) {
2002 hdsp->control_register &= ~HDSP_ClockModeMaster;
2003 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2004 return 0;
2005 }
2006 }
2007 return -1;
2008 case HDSP_CLOCK_SOURCE_INTERNAL_32KHZ:
2009 rate = 32000;
2010 break;
2011 case HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ:
2012 rate = 44100;
2013 break;
2014 case HDSP_CLOCK_SOURCE_INTERNAL_48KHZ:
2015 rate = 48000;
2016 break;
2017 case HDSP_CLOCK_SOURCE_INTERNAL_64KHZ:
2018 rate = 64000;
2019 break;
2020 case HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ:
2021 rate = 88200;
2022 break;
2023 case HDSP_CLOCK_SOURCE_INTERNAL_96KHZ:
2024 rate = 96000;
2025 break;
2026 case HDSP_CLOCK_SOURCE_INTERNAL_128KHZ:
2027 rate = 128000;
2028 break;
2029 case HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ:
2030 rate = 176400;
2031 break;
2032 case HDSP_CLOCK_SOURCE_INTERNAL_192KHZ:
2033 rate = 192000;
2034 break;
2035 default:
2036 rate = 48000;
2037 }
2038 hdsp->control_register |= HDSP_ClockModeMaster;
2039 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2040 hdsp_set_rate(hdsp, rate, 1);
2041 return 0;
2042 }
2043
2044 static int snd_hdsp_info_clock_source(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2045 {
2046 static char *texts[] = {"AutoSync", "Internal 32.0 kHz", "Internal 44.1 kHz", "Internal 48.0 kHz", "Internal 64.0 kHz", "Internal 88.2 kHz", "Internal 96.0 kHz", "Internal 128 kHz", "Internal 176.4 kHz", "Internal 192.0 KHz" };
2047 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2048
2049 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2050 uinfo->count = 1;
2051 if (hdsp->io_type == H9632)
2052 uinfo->value.enumerated.items = 10;
2053 else
2054 uinfo->value.enumerated.items = 7;
2055 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2056 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2057 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2058 return 0;
2059 }
2060
2061 static int snd_hdsp_get_clock_source(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2062 {
2063 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2064
2065 ucontrol->value.enumerated.item[0] = hdsp_clock_source(hdsp);
2066 return 0;
2067 }
2068
2069 static int snd_hdsp_put_clock_source(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2070 {
2071 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2072 int change;
2073 int val;
2074
2075 if (!snd_hdsp_use_is_exclusive(hdsp))
2076 return -EBUSY;
2077 val = ucontrol->value.enumerated.item[0];
2078 if (val < 0) val = 0;
2079 if (hdsp->io_type == H9632) {
2080 if (val > 9) val = 9;
2081 } else {
2082 if (val > 6) val = 6;
2083 }
2084 spin_lock_irq(&hdsp->lock);
2085 if (val != hdsp_clock_source(hdsp)) {
2086 change = (hdsp_set_clock_source(hdsp, val) == 0) ? 1 : 0;
2087 } else {
2088 change = 0;
2089 }
2090 spin_unlock_irq(&hdsp->lock);
2091 return change;
2092 }
2093
2094 #define HDSP_DA_GAIN(xname, xindex) \
2095 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2096 .name = xname, \
2097 .index = xindex, \
2098 .info = snd_hdsp_info_da_gain, \
2099 .get = snd_hdsp_get_da_gain, \
2100 .put = snd_hdsp_put_da_gain \
2101 }
2102
2103 static int hdsp_da_gain(hdsp_t *hdsp)
2104 {
2105 switch (hdsp->control_register & HDSP_DAGainMask) {
2106 case HDSP_DAGainHighGain:
2107 return 0;
2108 case HDSP_DAGainPlus4dBu:
2109 return 1;
2110 case HDSP_DAGainMinus10dBV:
2111 return 2;
2112 default:
2113 return 1;
2114 }
2115 }
2116
2117 static int hdsp_set_da_gain(hdsp_t *hdsp, int mode)
2118 {
2119 hdsp->control_register &= ~HDSP_DAGainMask;
2120 switch (mode) {
2121 case 0:
2122 hdsp->control_register |= HDSP_DAGainHighGain;
2123 break;
2124 case 1:
2125 hdsp->control_register |= HDSP_DAGainPlus4dBu;
2126 break;
2127 case 2:
2128 hdsp->control_register |= HDSP_DAGainMinus10dBV;
2129 break;
2130 default:
2131 return -1;
2132
2133 }
2134 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2135 return 0;
2136 }
2137
2138 static int snd_hdsp_info_da_gain(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2139 {
2140 static char *texts[] = {"Hi Gain", "+4 dBu", "-10 dbV"};
2141
2142 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2143 uinfo->count = 1;
2144 uinfo->value.enumerated.items = 3;
2145 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2146 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2147 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2148 return 0;
2149 }
2150
2151 static int snd_hdsp_get_da_gain(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2152 {
2153 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2154
2155 ucontrol->value.enumerated.item[0] = hdsp_da_gain(hdsp);
2156 return 0;
2157 }
2158
2159 static int snd_hdsp_put_da_gain(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2160 {
2161 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2162 int change;
2163 int val;
2164
2165 if (!snd_hdsp_use_is_exclusive(hdsp))
2166 return -EBUSY;
2167 val = ucontrol->value.enumerated.item[0];
2168 if (val < 0) val = 0;
2169 if (val > 2) val = 2;
2170 spin_lock_irq(&hdsp->lock);
2171 if (val != hdsp_da_gain(hdsp)) {
2172 change = (hdsp_set_da_gain(hdsp, val) == 0) ? 1 : 0;
2173 } else {
2174 change = 0;
2175 }
2176 spin_unlock_irq(&hdsp->lock);
2177 return change;
2178 }
2179
2180 #define HDSP_AD_GAIN(xname, xindex) \
2181 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2182 .name = xname, \
2183 .index = xindex, \
2184 .info = snd_hdsp_info_ad_gain, \
2185 .get = snd_hdsp_get_ad_gain, \
2186 .put = snd_hdsp_put_ad_gain \
2187 }
2188
2189 static int hdsp_ad_gain(hdsp_t *hdsp)
2190 {
2191 switch (hdsp->control_register & HDSP_ADGainMask) {
2192 case HDSP_ADGainMinus10dBV:
2193 return 0;
2194 case HDSP_ADGainPlus4dBu:
2195 return 1;
2196 case HDSP_ADGainLowGain:
2197 return 2;
2198 default:
2199 return 1;
2200 }
2201 }
2202
2203 static int hdsp_set_ad_gain(hdsp_t *hdsp, int mode)
2204 {
2205 hdsp->control_register &= ~HDSP_ADGainMask;
2206 switch (mode) {
2207 case 0:
2208 hdsp->control_register |= HDSP_ADGainMinus10dBV;
2209 break;
2210 case 1:
2211 hdsp->control_register |= HDSP_ADGainPlus4dBu;
2212 break;
2213 case 2:
2214 hdsp->control_register |= HDSP_ADGainLowGain;
2215 break;
2216 default:
2217 return -1;
2218
2219 }
2220 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2221 return 0;
2222 }
2223
2224 static int snd_hdsp_info_ad_gain(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2225 {
2226 static char *texts[] = {"-10 dBV", "+4 dBu", "Lo Gain"};
2227
2228 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2229 uinfo->count = 1;
2230 uinfo->value.enumerated.items = 3;
2231 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2232 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2233 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2234 return 0;
2235 }
2236
2237 static int snd_hdsp_get_ad_gain(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2238 {
2239 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2240
2241 ucontrol->value.enumerated.item[0] = hdsp_ad_gain(hdsp);
2242 return 0;
2243 }
2244
2245 static int snd_hdsp_put_ad_gain(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2246 {
2247 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2248 int change;
2249 int val;
2250
2251 if (!snd_hdsp_use_is_exclusive(hdsp))
2252 return -EBUSY;
2253 val = ucontrol->value.enumerated.item[0];
2254 if (val < 0) val = 0;
2255 if (val > 2) val = 2;
2256 spin_lock_irq(&hdsp->lock);
2257 if (val != hdsp_ad_gain(hdsp)) {
2258 change = (hdsp_set_ad_gain(hdsp, val) == 0) ? 1 : 0;
2259 } else {
2260 change = 0;
2261 }
2262 spin_unlock_irq(&hdsp->lock);
2263 return change;
2264 }
2265
2266 #define HDSP_PHONE_GAIN(xname, xindex) \
2267 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2268 .name = xname, \
2269 .index = xindex, \
2270 .info = snd_hdsp_info_phone_gain, \
2271 .get = snd_hdsp_get_phone_gain, \
2272 .put = snd_hdsp_put_phone_gain \
2273 }
2274
2275 static int hdsp_phone_gain(hdsp_t *hdsp)
2276 {
2277 switch (hdsp->control_register & HDSP_PhoneGainMask) {
2278 case HDSP_PhoneGain0dB:
2279 return 0;
2280 case HDSP_PhoneGainMinus6dB:
2281 return 1;
2282 case HDSP_PhoneGainMinus12dB:
2283 return 2;
2284 default:
2285 return 0;
2286 }
2287 }
2288
2289 static int hdsp_set_phone_gain(hdsp_t *hdsp, int mode)
2290 {
2291 hdsp->control_register &= ~HDSP_PhoneGainMask;
2292 switch (mode) {
2293 case 0:
2294 hdsp->control_register |= HDSP_PhoneGain0dB;
2295 break;
2296 case 1:
2297 hdsp->control_register |= HDSP_PhoneGainMinus6dB;
2298 break;
2299 case 2:
2300 hdsp->control_register |= HDSP_PhoneGainMinus12dB;
2301 break;
2302 default:
2303 return -1;
2304
2305 }
2306 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2307 return 0;
2308 }
2309
2310 static int snd_hdsp_info_phone_gain(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2311 {
2312 static char *texts[] = {"0 dB", "-6 dB", "-12 dB"};
2313
2314 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2315 uinfo->count = 1;
2316 uinfo->value.enumerated.items = 3;
2317 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2318 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2319 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2320 return 0;
2321 }
2322
2323 static int snd_hdsp_get_phone_gain(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2324 {
2325 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2326
2327 ucontrol->value.enumerated.item[0] = hdsp_phone_gain(hdsp);
2328 return 0;
2329 }
2330
2331 static int snd_hdsp_put_phone_gain(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2332 {
2333 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2334 int change;
2335 int val;
2336
2337 if (!snd_hdsp_use_is_exclusive(hdsp))
2338 return -EBUSY;
2339 val = ucontrol->value.enumerated.item[0];
2340 if (val < 0) val = 0;
2341 if (val > 2) val = 2;
2342 spin_lock_irq(&hdsp->lock);
2343 if (val != hdsp_phone_gain(hdsp)) {
2344 change = (hdsp_set_phone_gain(hdsp, val) == 0) ? 1 : 0;
2345 } else {
2346 change = 0;
2347 }
2348 spin_unlock_irq(&hdsp->lock);
2349 return change;
2350 }
2351
2352 #define HDSP_XLR_BREAKOUT_CABLE(xname, xindex) \
2353 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2354 .name = xname, \
2355 .index = xindex, \
2356 .info = snd_hdsp_info_xlr_breakout_cable, \
2357 .get = snd_hdsp_get_xlr_breakout_cable, \
2358 .put = snd_hdsp_put_xlr_breakout_cable \
2359 }
2360
2361 static int hdsp_xlr_breakout_cable(hdsp_t *hdsp)
2362 {
2363 if (hdsp->control_register & HDSP_XLRBreakoutCable) {
2364 return 1;
2365 }
2366 return 0;
2367 }
2368
2369 static int hdsp_set_xlr_breakout_cable(hdsp_t *hdsp, int mode)
2370 {
2371 if (mode) {
2372 hdsp->control_register |= HDSP_XLRBreakoutCable;
2373 } else {
2374 hdsp->control_register &= ~HDSP_XLRBreakoutCable;
2375 }
2376 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2377 return 0;
2378 }
2379
2380 static int snd_hdsp_info_xlr_breakout_cable(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2381 {
2382 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
2383 uinfo->count = 1;
2384 uinfo->value.integer.min = 0;
2385 uinfo->value.integer.max = 1;
2386 return 0;
2387 }
2388
2389 static int snd_hdsp_get_xlr_breakout_cable(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2390 {
2391 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2392
2393 ucontrol->value.enumerated.item[0] = hdsp_xlr_breakout_cable(hdsp);
2394 return 0;
2395 }
2396
2397 static int snd_hdsp_put_xlr_breakout_cable(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2398 {
2399 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2400 int change;
2401 int val;
2402
2403 if (!snd_hdsp_use_is_exclusive(hdsp))
2404 return -EBUSY;
2405 val = ucontrol->value.integer.value[0] & 1;
2406 spin_lock_irq(&hdsp->lock);
2407 change = (int)val != hdsp_xlr_breakout_cable(hdsp);
2408 hdsp_set_xlr_breakout_cable(hdsp, val);
2409 spin_unlock_irq(&hdsp->lock);
2410 return change;
2411 }
2412
2413 /* (De)activates old RME Analog Extension Board
2414 These are connected to the internal ADAT connector
2415 Switching this on desactivates external ADAT
2416 */
2417 #define HDSP_AEB(xname, xindex) \
2418 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2419 .name = xname, \
2420 .index = xindex, \
2421 .info = snd_hdsp_info_aeb, \
2422 .get = snd_hdsp_get_aeb, \
2423 .put = snd_hdsp_put_aeb \
2424 }
2425
2426 static int hdsp_aeb(hdsp_t *hdsp)
2427 {
2428 if (hdsp->control_register & HDSP_AnalogExtensionBoard) {
2429 return 1;
2430 }
2431 return 0;
2432 }
2433
2434 static int hdsp_set_aeb(hdsp_t *hdsp, int mode)
2435 {
2436 if (mode) {
2437 hdsp->control_register |= HDSP_AnalogExtensionBoard;
2438 } else {
2439 hdsp->control_register &= ~HDSP_AnalogExtensionBoard;
2440 }
2441 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2442 return 0;
2443 }
2444
2445 static int snd_hdsp_info_aeb(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2446 {
2447 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
2448 uinfo->count = 1;
2449 uinfo->value.integer.min = 0;
2450 uinfo->value.integer.max = 1;
2451 return 0;
2452 }
2453
2454 static int snd_hdsp_get_aeb(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2455 {
2456 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2457
2458 ucontrol->value.enumerated.item[0] = hdsp_aeb(hdsp);
2459 return 0;
2460 }
2461
2462 static int snd_hdsp_put_aeb(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2463 {
2464 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2465 int change;
2466 int val;
2467
2468 if (!snd_hdsp_use_is_exclusive(hdsp))
2469 return -EBUSY;
2470 val = ucontrol->value.integer.value[0] & 1;
2471 spin_lock_irq(&hdsp->lock);
2472 change = (int)val != hdsp_aeb(hdsp);
2473 hdsp_set_aeb(hdsp, val);
2474 spin_unlock_irq(&hdsp->lock);
2475 return change;
2476 }
2477
2478 #define HDSP_PREF_SYNC_REF(xname, xindex) \
2479 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2480 .name = xname, \
2481 .index = xindex, \
2482 .info = snd_hdsp_info_pref_sync_ref, \
2483 .get = snd_hdsp_get_pref_sync_ref, \
2484 .put = snd_hdsp_put_pref_sync_ref \
2485 }
2486
2487 static int hdsp_pref_sync_ref(hdsp_t *hdsp)
2488 {
2489 /* Notice that this looks at the requested sync source,
2490 not the one actually in use.
2491 */
2492
2493 switch (hdsp->control_register & HDSP_SyncRefMask) {
2494 case HDSP_SyncRef_ADAT1:
2495 return HDSP_SYNC_FROM_ADAT1;
2496 case HDSP_SyncRef_ADAT2:
2497 return HDSP_SYNC_FROM_ADAT2;
2498 case HDSP_SyncRef_ADAT3:
2499 return HDSP_SYNC_FROM_ADAT3;
2500 case HDSP_SyncRef_SPDIF:
2501 return HDSP_SYNC_FROM_SPDIF;
2502 case HDSP_SyncRef_WORD:
2503 return HDSP_SYNC_FROM_WORD;
2504 case HDSP_SyncRef_ADAT_SYNC:
2505 return HDSP_SYNC_FROM_ADAT_SYNC;
2506 default:
2507 return HDSP_SYNC_FROM_WORD;
2508 }
2509 return 0;
2510 }
2511
2512 static int hdsp_set_pref_sync_ref(hdsp_t *hdsp, int pref)
2513 {
2514 hdsp->control_register &= ~HDSP_SyncRefMask;
2515 switch (pref) {
2516 case HDSP_SYNC_FROM_ADAT1:
2517 hdsp->control_register &= ~HDSP_SyncRefMask; /* clear SyncRef bits */
2518 break;
2519 case HDSP_SYNC_FROM_ADAT2:
2520 hdsp->control_register |= HDSP_SyncRef_ADAT2;
2521 break;
2522 case HDSP_SYNC_FROM_ADAT3:
2523 hdsp->control_register |= HDSP_SyncRef_ADAT3;
2524 break;
2525 case HDSP_SYNC_FROM_SPDIF:
2526 hdsp->control_register |= HDSP_SyncRef_SPDIF;
2527 break;
2528 case HDSP_SYNC_FROM_WORD:
2529 hdsp->control_register |= HDSP_SyncRef_WORD;
2530 break;
2531 case HDSP_SYNC_FROM_ADAT_SYNC:
2532 hdsp->control_register |= HDSP_SyncRef_ADAT_SYNC;
2533 break;
2534 default:
2535 return -1;
2536 }
2537 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2538 return 0;
2539 }
2540
2541 static int snd_hdsp_info_pref_sync_ref(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2542 {
2543 static char *texts[] = {"Word", "IEC958", "ADAT1", "ADAT Sync", "ADAT2", "ADAT3" };
2544 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2545
2546 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2547 uinfo->count = 1;
2548
2549 switch (hdsp->io_type) {
2550 case Digiface:
2551 case H9652:
2552 uinfo->value.enumerated.items = 6;
2553 break;
2554 case Multiface:
2555 uinfo->value.enumerated.items = 4;
2556 break;
2557 case H9632:
2558 uinfo->value.enumerated.items = 3;
2559 break;
2560 default:
2561 uinfo->value.enumerated.items = 0;
2562 break;
2563 }
2564
2565 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2566 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2567 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2568 return 0;
2569 }
2570
2571 static int snd_hdsp_get_pref_sync_ref(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2572 {
2573 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2574
2575 ucontrol->value.enumerated.item[0] = hdsp_pref_sync_ref(hdsp);
2576 return 0;
2577 }
2578
2579 static int snd_hdsp_put_pref_sync_ref(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2580 {
2581 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2582 int change, max;
2583 unsigned int val;
2584
2585 if (!snd_hdsp_use_is_exclusive(hdsp))
2586 return -EBUSY;
2587
2588 switch (hdsp->io_type) {
2589 case Digiface:
2590 case H9652:
2591 max = 6;
2592 break;
2593 case Multiface:
2594 max = 4;
2595 break;
2596 case H9632:
2597 max = 3;
2598 break;
2599 default:
2600 return -EIO;
2601 }
2602
2603 val = ucontrol->value.enumerated.item[0] % max;
2604 spin_lock_irq(&hdsp->lock);
2605 change = (int)val != hdsp_pref_sync_ref(hdsp);
2606 hdsp_set_pref_sync_ref(hdsp, val);
2607 spin_unlock_irq(&hdsp->lock);
2608 return change;
2609 }
2610
2611 #define HDSP_AUTOSYNC_REF(xname, xindex) \
2612 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2613 .name = xname, \
2614 .index = xindex, \
2615 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
2616 .info = snd_hdsp_info_autosync_ref, \
2617 .get = snd_hdsp_get_autosync_ref, \
2618 }
2619
2620 static int hdsp_autosync_ref(hdsp_t *hdsp)
2621 {
2622 /* This looks at the autosync selected sync reference */
2623 unsigned int status2 = hdsp_read(hdsp, HDSP_status2Register);
2624
2625 switch (status2 & HDSP_SelSyncRefMask) {
2626 case HDSP_SelSyncRef_WORD:
2627 return HDSP_AUTOSYNC_FROM_WORD;
2628 case HDSP_SelSyncRef_ADAT_SYNC:
2629 return HDSP_AUTOSYNC_FROM_ADAT_SYNC;
2630 case HDSP_SelSyncRef_SPDIF:
2631 return HDSP_AUTOSYNC_FROM_SPDIF;
2632 case HDSP_SelSyncRefMask:
2633 return HDSP_AUTOSYNC_FROM_NONE;
2634 case HDSP_SelSyncRef_ADAT1:
2635 return HDSP_AUTOSYNC_FROM_ADAT1;
2636 case HDSP_SelSyncRef_ADAT2:
2637 return HDSP_AUTOSYNC_FROM_ADAT2;
2638 case HDSP_SelSyncRef_ADAT3:
2639 return HDSP_AUTOSYNC_FROM_ADAT3;
2640 default:
2641 return HDSP_AUTOSYNC_FROM_WORD;
2642 }
2643 return 0;
2644 }
2645
2646 static int snd_hdsp_info_autosync_ref(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2647 {
2648 static char *texts[] = {"Word", "ADAT Sync", "IEC958", "None", "ADAT1", "ADAT2", "ADAT3" };
2649
2650 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2651 uinfo->count = 1;
2652 uinfo->value.enumerated.items = 7;
2653 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2654 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2655 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2656 return 0;
2657 }
2658
2659 static int snd_hdsp_get_autosync_ref(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2660 {
2661 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2662
2663 ucontrol->value.enumerated.item[0] = hdsp_autosync_ref(hdsp);
2664 return 0;
2665 }
2666
2667 #define HDSP_LINE_OUT(xname, xindex) \
2668 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2669 .name = xname, \
2670 .index = xindex, \
2671 .info = snd_hdsp_info_line_out, \
2672 .get = snd_hdsp_get_line_out, \
2673 .put = snd_hdsp_put_line_out \
2674 }
2675
2676 static int hdsp_line_out(hdsp_t *hdsp)
2677 {
2678 return (hdsp->control_register & HDSP_LineOut) ? 1 : 0;
2679 }
2680
2681 static int hdsp_set_line_output(hdsp_t *hdsp, int out)
2682 {
2683 if (out) {
2684 hdsp->control_register |= HDSP_LineOut;
2685 } else {
2686 hdsp->control_register &= ~HDSP_LineOut;
2687 }
2688 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2689 return 0;
2690 }
2691
2692 static int snd_hdsp_info_line_out(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2693 {
2694 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
2695 uinfo->count = 1;
2696 uinfo->value.integer.min = 0;
2697 uinfo->value.integer.max = 1;
2698 return 0;
2699 }
2700
2701 static int snd_hdsp_get_line_out(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2702 {
2703 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2704
2705 spin_lock_irq(&hdsp->lock);
2706 ucontrol->value.integer.value[0] = hdsp_line_out(hdsp);
2707 spin_unlock_irq(&hdsp->lock);
2708 return 0;
2709 }
2710
2711 static int snd_hdsp_put_line_out(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2712 {
2713 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2714 int change;
2715 unsigned int val;
2716
2717 if (!snd_hdsp_use_is_exclusive(hdsp))
2718 return -EBUSY;
2719 val = ucontrol->value.integer.value[0] & 1;
2720 spin_lock_irq(&hdsp->lock);
2721 change = (int)val != hdsp_line_out(hdsp);
2722 hdsp_set_line_output(hdsp, val);
2723 spin_unlock_irq(&hdsp->lock);
2724 return change;
2725 }
2726
2727 #define HDSP_PRECISE_POINTER(xname, xindex) \
2728 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2729 .name = xname, \
2730 .index = xindex, \
2731 .info = snd_hdsp_info_precise_pointer, \
2732 .get = snd_hdsp_get_precise_pointer, \
2733 .put = snd_hdsp_put_precise_pointer \
2734 }
2735
2736 static int hdsp_set_precise_pointer(hdsp_t *hdsp, int precise)
2737 {
2738 if (precise) {
2739 hdsp->precise_ptr = 1;
2740 } else {
2741 hdsp->precise_ptr = 0;
2742 }
2743 return 0;
2744 }
2745
2746 static int snd_hdsp_info_precise_pointer(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2747 {
2748 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
2749 uinfo->count = 1;
2750 uinfo->value.integer.min = 0;
2751 uinfo->value.integer.max = 1;
2752 return 0;
2753 }
2754
2755 static int snd_hdsp_get_precise_pointer(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2756 {
2757 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2758
2759 spin_lock_irq(&hdsp->lock);
2760 ucontrol->value.integer.value[0] = hdsp->precise_ptr;
2761 spin_unlock_irq(&hdsp->lock);
2762 return 0;
2763 }
2764
2765 static int snd_hdsp_put_precise_pointer(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2766 {
2767 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2768 int change;
2769 unsigned int val;
2770
2771 if (!snd_hdsp_use_is_exclusive(hdsp))
2772 return -EBUSY;
2773 val = ucontrol->value.integer.value[0] & 1;
2774 spin_lock_irq(&hdsp->lock);
2775 change = (int)val != hdsp->precise_ptr;
2776 hdsp_set_precise_pointer(hdsp, val);
2777 spin_unlock_irq(&hdsp->lock);
2778 return change;
2779 }
2780
2781 #define HDSP_USE_MIDI_TASKLET(xname, xindex) \
2782 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2783 .name = xname, \
2784 .index = xindex, \
2785 .info = snd_hdsp_info_use_midi_tasklet, \
2786 .get = snd_hdsp_get_use_midi_tasklet, \
2787 .put = snd_hdsp_put_use_midi_tasklet \
2788 }
2789
2790 static int hdsp_set_use_midi_tasklet(hdsp_t *hdsp, int use_tasklet)
2791 {
2792 if (use_tasklet) {
2793 hdsp->use_midi_tasklet = 1;
2794 } else {
2795 hdsp->use_midi_tasklet = 0;
2796 }
2797 return 0;
2798 }
2799
2800 static int snd_hdsp_info_use_midi_tasklet(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2801 {
2802 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
2803 uinfo->count = 1;
2804 uinfo->value.integer.min = 0;
2805 uinfo->value.integer.max = 1;
2806 return 0;
2807 }
2808
2809 static int snd_hdsp_get_use_midi_tasklet(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2810 {
2811 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2812
2813 spin_lock_irq(&hdsp->lock);
2814 ucontrol->value.integer.value[0] = hdsp->use_midi_tasklet;
2815 spin_unlock_irq(&hdsp->lock);
2816 return 0;
2817 }
2818
2819 static int snd_hdsp_put_use_midi_tasklet(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2820 {
2821 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2822 int change;
2823 unsigned int val;
2824
2825 if (!snd_hdsp_use_is_exclusive(hdsp))
2826 return -EBUSY;
2827 val = ucontrol->value.integer.value[0] & 1;
2828 spin_lock_irq(&hdsp->lock);
2829 change = (int)val != hdsp->use_midi_tasklet;
2830 hdsp_set_use_midi_tasklet(hdsp, val);
2831 spin_unlock_irq(&hdsp->lock);
2832 return change;
2833 }
2834
2835 #define HDSP_MIXER(xname, xindex) \
2836 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2837 .name = xname, \
2838 .index = xindex, \
2839 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
2840 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2841 .info = snd_hdsp_info_mixer, \
2842 .get = snd_hdsp_get_mixer, \
2843 .put = snd_hdsp_put_mixer \
2844 }
2845
2846 static int snd_hdsp_info_mixer(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2847 {
2848 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2849 uinfo->count = 3;
2850 uinfo->value.integer.min = 0;
2851 uinfo->value.integer.max = 65536;
2852 uinfo->value.integer.step = 1;
2853 return 0;
2854 }
2855
2856 static int snd_hdsp_get_mixer(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2857 {
2858 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2859 int source;
2860 int destination;
2861 int addr;
2862
2863 source = ucontrol->value.integer.value[0];
2864 destination = ucontrol->value.integer.value[1];
2865
2866 if (source >= hdsp->max_channels) {
2867 addr = hdsp_playback_to_output_key(hdsp,source-hdsp->max_channels,destination);
2868 } else {
2869 addr = hdsp_input_to_output_key(hdsp,source, destination);
2870 }
2871
2872 spin_lock_irq(&hdsp->lock);
2873 ucontrol->value.integer.value[2] = hdsp_read_gain (hdsp, addr);
2874 spin_unlock_irq(&hdsp->lock);
2875 return 0;
2876 }
2877
2878 static int snd_hdsp_put_mixer(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2879 {
2880 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2881 int change;
2882 int source;
2883 int destination;
2884 int gain;
2885 int addr;
2886
2887 if (!snd_hdsp_use_is_exclusive(hdsp))
2888 return -EBUSY;
2889
2890 source = ucontrol->value.integer.value[0];
2891 destination = ucontrol->value.integer.value[1];
2892
2893 if (source >= hdsp->max_channels) {
2894 addr = hdsp_playback_to_output_key(hdsp,source-hdsp->max_channels, destination);
2895 } else {
2896 addr = hdsp_input_to_output_key(hdsp,source, destination);
2897 }
2898
2899 gain = ucontrol->value.integer.value[2];
2900
2901 spin_lock_irq(&hdsp->lock);
2902 change = gain != hdsp_read_gain(hdsp, addr);
2903 if (change)
2904 hdsp_write_gain(hdsp, addr, gain);
2905 spin_unlock_irq(&hdsp->lock);
2906 return change;
2907 }
2908
2909 #define HDSP_WC_SYNC_CHECK(xname, xindex) \
2910 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2911 .name = xname, \
2912 .index = xindex, \
2913 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2914 .info = snd_hdsp_info_sync_check, \
2915 .get = snd_hdsp_get_wc_sync_check \
2916 }
2917
2918 static int snd_hdsp_info_sync_check(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2919 {
2920 static char *texts[] = {"No Lock", "Lock", "Sync" };
2921 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2922 uinfo->count = 1;
2923 uinfo->value.enumerated.items = 3;
2924 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2925 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2926 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2927 return 0;
2928 }
2929
2930 static int hdsp_wc_sync_check(hdsp_t *hdsp)
2931 {
2932 int status2 = hdsp_read(hdsp, HDSP_status2Register);
2933 if (status2 & HDSP_wc_lock) {
2934 if (status2 & HDSP_wc_sync) {
2935 return 2;
2936 } else {
2937 return 1;
2938 }
2939 } else {
2940 return 0;
2941 }
2942 return 0;
2943 }
2944
2945 static int snd_hdsp_get_wc_sync_check(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2946 {
2947 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2948
2949 ucontrol->value.enumerated.item[0] = hdsp_wc_sync_check(hdsp);
2950 return 0;
2951 }
2952
2953 #define HDSP_SPDIF_SYNC_CHECK(xname, xindex) \
2954 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2955 .name = xname, \
2956 .index = xindex, \
2957 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2958 .info = snd_hdsp_info_sync_check, \
2959 .get = snd_hdsp_get_spdif_sync_check \
2960 }
2961
2962 static int hdsp_spdif_sync_check(hdsp_t *hdsp)
2963 {
2964 int status = hdsp_read(hdsp, HDSP_statusRegister);
2965 if (status & HDSP_SPDIFErrorFlag) {
2966 return 0;
2967 } else {
2968 if (status & HDSP_SPDIFSync) {
2969 return 2;
2970 } else {
2971 return 1;
2972 }
2973 }
2974 return 0;
2975 }
2976
2977 static int snd_hdsp_get_spdif_sync_check(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2978 {
2979 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2980
2981 ucontrol->value.enumerated.item[0] = hdsp_spdif_sync_check(hdsp);
2982 return 0;
2983 }
2984
2985 #define HDSP_ADATSYNC_SYNC_CHECK(xname, xindex) \
2986 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2987 .name = xname, \
2988 .index = xindex, \
2989 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2990 .info = snd_hdsp_info_sync_check, \
2991 .get = snd_hdsp_get_adatsync_sync_check \
2992 }
2993
2994 static int hdsp_adatsync_sync_check(hdsp_t *hdsp)
2995 {
2996 int status = hdsp_read(hdsp, HDSP_statusRegister);
2997 if (status & HDSP_TimecodeLock) {
2998 if (status & HDSP_TimecodeSync) {
2999 return 2;
3000 } else {
3001 return 1;
3002 }
3003 } else {
3004 return 0;
3005 }
3006 }
3007
3008 static int snd_hdsp_get_adatsync_sync_check(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
3009 {
3010 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
3011
3012 ucontrol->value.enumerated.item[0] = hdsp_adatsync_sync_check(hdsp);
3013 return 0;
3014 }
3015
3016 #define HDSP_ADAT_SYNC_CHECK \
3017 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
3018 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3019 .info = snd_hdsp_info_sync_check, \
3020 .get = snd_hdsp_get_adat_sync_check \
3021 }
3022
3023 static int hdsp_adat_sync_check(hdsp_t *hdsp, int idx)
3024 {
3025 int status = hdsp_read(hdsp, HDSP_statusRegister);
3026
3027 if (status & (HDSP_Lock0>>idx)) {
3028 if (status & (HDSP_Sync0>>idx)) {
3029 return 2;
3030 } else {
3031 return 1;
3032 }
3033 } else {
3034 return 0;
3035 }
3036 }
3037
3038 static int snd_hdsp_get_adat_sync_check(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
3039 {
3040 int offset;
3041 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
3042
3043 offset = ucontrol->id.index - 1;
3044 snd_assert(offset >= 0);
3045
3046 switch (hdsp->io_type) {
3047 case Digiface:
3048 case H9652:
3049 if (offset >= 3)
3050 return -EINVAL;
3051 break;
3052 case Multiface:
3053 case H9632:
3054 if (offset >= 1)
3055 return -EINVAL;
3056 break;
3057 default:
3058 return -EIO;
3059 }
3060
3061 ucontrol->value.enumerated.item[0] = hdsp_adat_sync_check(hdsp, offset);
3062 return 0;
3063 }
3064
3065 static snd_kcontrol_new_t snd_hdsp_9632_controls[] = {
3066 HDSP_DA_GAIN("DA Gain", 0),
3067 HDSP_AD_GAIN("AD Gain", 0),
3068 HDSP_PHONE_GAIN("Phones Gain", 0),
3069 HDSP_XLR_BREAKOUT_CABLE("XLR Breakout Cable", 0)
3070 };
3071
3072 static snd_kcontrol_new_t snd_hdsp_controls[] = {
3073 {
3074 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
3075 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
3076 .info = snd_hdsp_control_spdif_info,
3077 .get = snd_hdsp_control_spdif_get,
3078 .put = snd_hdsp_control_spdif_put,
3079 },
3080 {
3081 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
3082 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
3083 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
3084 .info = snd_hdsp_control_spdif_stream_info,
3085 .get = snd_hdsp_control_spdif_stream_get,
3086 .put = snd_hdsp_control_spdif_stream_put,
3087 },
3088 {
3089 .access = SNDRV_CTL_ELEM_ACCESS_READ,
3090 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
3091 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),
3092 .info = snd_hdsp_control_spdif_mask_info,
3093 .get = snd_hdsp_control_spdif_mask_get,
3094 .private_value = IEC958_AES0_NONAUDIO |
3095 IEC958_AES0_PROFESSIONAL |
3096 IEC958_AES0_CON_EMPHASIS,
3097 },
3098 {
3099 .access = SNDRV_CTL_ELEM_ACCESS_READ,
3100 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
3101 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PRO_MASK),
3102 .info = snd_hdsp_control_spdif_mask_info,
3103 .get = snd_hdsp_control_spdif_mask_get,
3104 .private_value = IEC958_AES0_NONAUDIO |
3105 IEC958_AES0_PROFESSIONAL |
3106 IEC958_AES0_PRO_EMPHASIS,
3107 },
3108 HDSP_MIXER("Mixer", 0),
3109 HDSP_SPDIF_IN("IEC958 Input Connector", 0),
3110 HDSP_SPDIF_OUT("IEC958 Output also on ADAT1", 0),
3111 HDSP_SPDIF_PROFESSIONAL("IEC958 Professional Bit", 0),
3112 HDSP_SPDIF_EMPHASIS("IEC958 Emphasis Bit", 0),
3113 HDSP_SPDIF_NON_AUDIO("IEC958 Non-audio Bit", 0),
3114 /* 'Sample Clock Source' complies with the alsa control naming scheme */
3115 HDSP_CLOCK_SOURCE("Sample Clock Source", 0),
3116 HDSP_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
3117 HDSP_PREF_SYNC_REF("Preferred Sync Reference", 0),
3118 HDSP_AUTOSYNC_REF("AutoSync Reference", 0),
3119 HDSP_SPDIF_SAMPLE_RATE("SPDIF Sample Rate", 0),
3120 HDSP_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
3121 /* 'External Rate' complies with the alsa control naming scheme */
3122 HDSP_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
3123 HDSP_WC_SYNC_CHECK("Word Clock Lock Status", 0),
3124 HDSP_SPDIF_SYNC_CHECK("SPDIF Lock Status", 0),
3125 HDSP_ADATSYNC_SYNC_CHECK("ADAT Sync Lock Status", 0),
3126 HDSP_LINE_OUT("Line Out", 0),
3127 HDSP_PRECISE_POINTER("Precise Pointer", 0),
3128 HDSP_USE_MIDI_TASKLET("Use Midi Tasklet", 0),
3129 };
3130
3131 static snd_kcontrol_new_t snd_hdsp_96xx_aeb = HDSP_AEB("Analog Extension Board", 0);
3132 static snd_kcontrol_new_t snd_hdsp_adat_sync_check = HDSP_ADAT_SYNC_CHECK;
3133
3134 static int snd_hdsp_create_controls(snd_card_t *card, hdsp_t *hdsp)
3135 {
3136 unsigned int idx;
3137 int err;
3138 snd_kcontrol_t *kctl;
3139
3140 for (idx = 0; idx < ARRAY_SIZE(snd_hdsp_controls); idx++) {
3141 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_controls[idx], hdsp))) < 0) {
3142 return err;
3143 }
3144 if (idx == 1) /* IEC958 (S/PDIF) Stream */
3145 hdsp->spdif_ctl = kctl;
3146 }
3147
3148 /* ADAT SyncCheck status */
3149 snd_hdsp_adat_sync_check.name = "ADAT Lock Status";
3150 snd_hdsp_adat_sync_check.index = 1;
3151 if ((err = snd_ctl_add (card, kctl = snd_ctl_new1(&snd_hdsp_adat_sync_check, hdsp)))) {
3152 return err;
3153 }
3154 if (hdsp->io_type == Digiface || hdsp->io_type == H9652) {
3155 for (idx = 1; idx < 3; ++idx) {
3156 snd_hdsp_adat_sync_check.index = idx+1;
3157 if ((err = snd_ctl_add (card, kctl = snd_ctl_new1(&snd_hdsp_adat_sync_check, hdsp)))) {
3158 return err;
3159 }
3160 }
3161 }
3162
3163 /* DA, AD and Phone gain and XLR breakout cable controls for H9632 cards */
3164 if (hdsp->io_type == H9632) {
3165 for (idx = 0; idx < ARRAY_SIZE(snd_hdsp_9632_controls); idx++) {
3166 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_9632_controls[idx], hdsp))) < 0) {
3167 return err;
3168 }
3169 }
3170 }
3171
3172 /* AEB control for H96xx card */
3173 if (hdsp->io_type == H9632 || hdsp->io_type == H9652) {
3174 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_96xx_aeb, hdsp))) < 0) {
3175 return err;
3176 }
3177 }
3178
3179 return 0;
3180 }
3181
3182 /*------------------------------------------------------------
3183 /proc interface
3184 ------------------------------------------------------------*/
3185
3186 static void
3187 snd_hdsp_proc_read(snd_info_entry_t *entry, snd_info_buffer_t *buffer)
3188 {
3189 hdsp_t *hdsp = (hdsp_t *) entry->private_data;
3190 unsigned int status;
3191 unsigned int status2;
3192 char *pref_sync_ref;
3193 char *autosync_ref;
3194 char *system_clock_mode;
3195 char *clock_source;
3196 int x;
3197
3198 if (hdsp_check_for_iobox (hdsp)) {
3199 snd_iprintf(buffer, "No I/O box connected.\nPlease connect one and upload firmware.\n");
3200 return;
3201 }
3202
3203 if (hdsp_check_for_firmware(hdsp)) {
3204 if (hdsp->state & HDSP_FirmwareCached) {
3205 if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) {
3206 snd_iprintf(buffer, "Firmware loading from cache failed, please upload manually.\n");
3207 return;
3208 }
3209 } else {
3210 snd_iprintf(buffer, "No firmware loaded nor cached, please upload firmware.\n");
3211 return;
3212 }
3213 }
3214
3215 status = hdsp_read(hdsp, HDSP_statusRegister);
3216 status2 = hdsp_read(hdsp, HDSP_status2Register);
3217
3218 snd_iprintf(buffer, "%s (Card #%d)\n", hdsp->card_name, hdsp->card->number + 1);
3219 snd_iprintf(buffer, "Buffers: capture %p playback %p\n",
3220 hdsp->capture_buffer, hdsp->playback_buffer);
3221 snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n",
3222 hdsp->irq, hdsp->port, (unsigned long)hdsp->iobase);
3223 snd_iprintf(buffer, "Control register: 0x%x\n", hdsp->control_register);
3224 snd_iprintf(buffer, "Control2 register: 0x%x\n", hdsp->control2_register);
3225 snd_iprintf(buffer, "Status register: 0x%x\n", status);
3226 snd_iprintf(buffer, "Status2 register: 0x%x\n", status2);
3227 snd_iprintf(buffer, "FIFO status: %d\n", hdsp_read(hdsp, HDSP_fifoStatus) & 0xff);
3228 snd_iprintf(buffer, "MIDI1 Output status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusOut0));
3229 snd_iprintf(buffer, "MIDI1 Input status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusIn0));
3230 snd_iprintf(buffer, "MIDI2 Output status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusOut1));
3231 snd_iprintf(buffer, "MIDI2 Input status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusIn1));
3232 snd_iprintf(buffer, "Use Midi Tasklet: %s\n", hdsp->use_midi_tasklet ? "on" : "off");
3233
3234 snd_iprintf(buffer, "\n");
3235
3236 x = 1 << (6 + hdsp_decode_latency(hdsp->control_register & HDSP_LatencyMask));
3237
3238 snd_iprintf(buffer, "Buffer Size (Latency): %d samples (2 periods of %lu bytes)\n", x, (unsigned long) hdsp->period_bytes);
3239 snd_iprintf(buffer, "Hardware pointer (frames): %ld\n", hdsp_hw_pointer(hdsp));
3240 snd_iprintf(buffer, "Precise pointer: %s\n", hdsp->precise_ptr ? "on" : "off");
3241 snd_iprintf(buffer, "Line out: %s\n", (hdsp->control_register & HDSP_LineOut) ? "on" : "off");
3242
3243 snd_iprintf(buffer, "Firmware version: %d\n", (status2&HDSP_version0)|(status2&HDSP_version1)<<1|(status2&HDSP_version2)<<2);
3244
3245 snd_iprintf(buffer, "\n");
3246
3247
3248 switch (hdsp_clock_source(hdsp)) {
3249 case HDSP_CLOCK_SOURCE_AUTOSYNC:
3250 clock_source = "AutoSync";
3251 break;
3252 case HDSP_CLOCK_SOURCE_INTERNAL_32KHZ:
3253 clock_source = "Internal 32 kHz";
3254 break;
3255 case HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ:
3256 clock_source = "Internal 44.1 kHz";
3257 break;
3258 case HDSP_CLOCK_SOURCE_INTERNAL_48KHZ:
3259 clock_source = "Internal 48 kHz";
3260 break;
3261 case HDSP_CLOCK_SOURCE_INTERNAL_64KHZ:
3262 clock_source = "Internal 64 kHz";
3263 break;
3264 case HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ:
3265 clock_source = "Internal 88.2 kHz";
3266 break;
3267 case HDSP_CLOCK_SOURCE_INTERNAL_96KHZ:
3268 clock_source = "Internal 96 kHz";
3269 break;
3270 case HDSP_CLOCK_SOURCE_INTERNAL_128KHZ:
3271 clock_source = "Internal 128 kHz";
3272 break;
3273 case HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ:
3274 clock_source = "Internal 176.4 kHz";
3275 break;
3276 case HDSP_CLOCK_SOURCE_INTERNAL_192KHZ:
3277 clock_source = "Internal 192 kHz";
3278 break;
3279 default:
3280 clock_source = "Error";
3281 }
3282 snd_iprintf (buffer, "Sample Clock Source: %s\n", clock_source);
3283
3284 if (hdsp_system_clock_mode(hdsp)) {
3285 system_clock_mode = "Slave";
3286 } else {
3287 system_clock_mode = "Master";
3288 }
3289
3290 switch (hdsp_pref_sync_ref (hdsp)) {
3291 case HDSP_SYNC_FROM_WORD:
3292 pref_sync_ref = "Word Clock";
3293 break;
3294 case HDSP_SYNC_FROM_ADAT_SYNC:
3295 pref_sync_ref = "ADAT Sync";
3296 break;
3297 case HDSP_SYNC_FROM_SPDIF:
3298 pref_sync_ref = "SPDIF";
3299 break;
3300 case HDSP_SYNC_FROM_ADAT1:
3301 pref_sync_ref = "ADAT1";
3302 break;
3303 case HDSP_SYNC_FROM_ADAT2:
3304 pref_sync_ref = "ADAT2";
3305 break;
3306 case HDSP_SYNC_FROM_ADAT3:
3307 pref_sync_ref = "ADAT3";
3308 break;
3309 default:
3310 pref_sync_ref = "Word Clock";
3311 break;
3312 }
3313 snd_iprintf (buffer, "Preferred Sync Reference: %s\n", pref_sync_ref);
3314
3315 switch (hdsp_autosync_ref (hdsp)) {
3316 case HDSP_AUTOSYNC_FROM_WORD:
3317 autosync_ref = "Word Clock";
3318 break;
3319 case HDSP_AUTOSYNC_FROM_ADAT_SYNC:
3320 autosync_ref = "ADAT Sync";
3321 break;
3322 case HDSP_AUTOSYNC_FROM_SPDIF:
3323 autosync_ref = "SPDIF";
3324 break;
3325 case HDSP_AUTOSYNC_FROM_NONE:
3326 autosync_ref = "None";
3327 break;
3328 case HDSP_AUTOSYNC_FROM_ADAT1:
3329 autosync_ref = "ADAT1";
3330 break;
3331 case HDSP_AUTOSYNC_FROM_ADAT2:
3332 autosync_ref = "ADAT2";
3333 break;
3334 case HDSP_AUTOSYNC_FROM_ADAT3:
3335 autosync_ref = "ADAT3";
3336 break;
3337 default:
3338 autosync_ref = "---";
3339 break;
3340 }
3341 snd_iprintf (buffer, "AutoSync Reference: %s\n", autosync_ref);
3342
3343 snd_iprintf (buffer, "AutoSync Frequency: %d\n", hdsp_external_sample_rate(hdsp));
3344
3345 snd_iprintf (buffer, "System Clock Mode: %s\n", system_clock_mode);
3346
3347 snd_iprintf (buffer, "System Clock Frequency: %d\n", hdsp->system_sample_rate);
3348
3349 snd_iprintf(buffer, "\n");
3350
3351 switch (hdsp_spdif_in(hdsp)) {
3352 case HDSP_SPDIFIN_OPTICAL:
3353 snd_iprintf(buffer, "IEC958 input: Optical\n");
3354 break;
3355 case HDSP_SPDIFIN_COAXIAL:
3356 snd_iprintf(buffer, "IEC958 input: Coaxial\n");
3357 break;
3358 case HDSP_SPDIFIN_INTERNAL:
3359 snd_iprintf(buffer, "IEC958 input: Internal\n");
3360 break;
3361 case HDSP_SPDIFIN_AES:
3362 snd_iprintf(buffer, "IEC958 input: AES\n");
3363 break;
3364 default:
3365 snd_iprintf(buffer, "IEC958 input: ???\n");
3366 break;
3367 }
3368
3369 if (hdsp->control_register & HDSP_SPDIFOpticalOut) {
3370 snd_iprintf(buffer, "IEC958 output: Coaxial & ADAT1\n");
3371 } else {
3372 snd_iprintf(buffer, "IEC958 output: Coaxial only\n");
3373 }
3374
3375 if (hdsp->control_register & HDSP_SPDIFProfessional) {
3376 snd_iprintf(buffer, "IEC958 quality: Professional\n");
3377 } else {
3378 snd_iprintf(buffer, "IEC958 quality: Consumer\n");
3379 }
3380
3381 if (hdsp->control_register & HDSP_SPDIFEmphasis) {
3382 snd_iprintf(buffer, "IEC958 emphasis: on\n");
3383 } else {
3384 snd_iprintf(buffer, "IEC958 emphasis: off\n");
3385 }
3386
3387 if (hdsp->control_register & HDSP_SPDIFNonAudio) {
3388 snd_iprintf(buffer, "IEC958 NonAudio: on\n");
3389 } else {
3390 snd_iprintf(buffer, "IEC958 NonAudio: off\n");
3391 }
3392 if ((x = hdsp_spdif_sample_rate (hdsp)) != 0) {
3393 snd_iprintf (buffer, "IEC958 sample rate: %d\n", x);
3394 } else {
3395 snd_iprintf (buffer, "IEC958 sample rate: Error flag set\n");
3396 }
3397
3398 snd_iprintf(buffer, "\n");
3399
3400 /* Sync Check */
3401 x = status & HDSP_Sync0;
3402 if (status & HDSP_Lock0) {
3403 snd_iprintf(buffer, "ADAT1: %s\n", x ? "Sync" : "Lock");
3404 } else {
3405 snd_iprintf(buffer, "ADAT1: No Lock\n");
3406 }
3407
3408 switch (hdsp->io_type) {
3409 case Digiface:
3410 case H9652:
3411 x = status & HDSP_Sync1;
3412 if (status & HDSP_Lock1) {
3413 snd_iprintf(buffer, "ADAT2: %s\n", x ? "Sync" : "Lock");
3414 } else {
3415 snd_iprintf(buffer, "ADAT2: No Lock\n");
3416 }
3417 x = status & HDSP_Sync2;
3418 if (status & HDSP_Lock2) {
3419 snd_iprintf(buffer, "ADAT3: %s\n", x ? "Sync" : "Lock");
3420 } else {
3421 snd_iprintf(buffer, "ADAT3: No Lock\n");
3422 }
3423 default:
3424 /* relax */
3425 break;
3426 }
3427
3428 x = status & HDSP_SPDIFSync;
3429 if (status & HDSP_SPDIFErrorFlag) {
3430 snd_iprintf (buffer, "SPDIF: No Lock\n");
3431 } else {
3432 snd_iprintf (buffer, "SPDIF: %s\n", x ? "Sync" : "Lock");
3433 }
3434
3435 x = status2 & HDSP_wc_sync;
3436 if (status2 & HDSP_wc_lock) {
3437 snd_iprintf (buffer, "Word Clock: %s\n", x ? "Sync" : "Lock");
3438 } else {
3439 snd_iprintf (buffer, "Word Clock: No Lock\n");
3440 }
3441
3442 x = status & HDSP_TimecodeSync;
3443 if (status & HDSP_TimecodeLock) {
3444 snd_iprintf(buffer, "ADAT Sync: %s\n", x ? "Sync" : "Lock");
3445 } else {
3446 snd_iprintf(buffer, "ADAT Sync: No Lock\n");
3447 }
3448
3449 snd_iprintf(buffer, "\n");
3450
3451 /* Informations about H9632 specific controls */
3452 if (hdsp->io_type == H9632) {
3453 char *tmp;
3454
3455 switch (hdsp_ad_gain(hdsp)) {
3456 case 0:
3457 tmp = "-10 dBV";
3458 break;
3459 case 1:
3460 tmp = "+4 dBu";
3461 break;
3462 default:
3463 tmp = "Lo Gain";
3464 break;
3465 }
3466 snd_iprintf(buffer, "AD Gain : %s\n", tmp);
3467
3468 switch (hdsp_da_gain(hdsp)) {
3469 case 0:
3470 tmp = "Hi Gain";
3471 break;
3472 case 1:
3473 tmp = "+4 dBu";
3474 break;
3475 default:
3476 tmp = "-10 dBV";
3477 break;
3478 }
3479 snd_iprintf(buffer, "DA Gain : %s\n", tmp);
3480
3481 switch (hdsp_phone_gain(hdsp)) {
3482 case 0:
3483 tmp = "0 dB";
3484 break;
3485 case 1:
3486 tmp = "-6 dB";
3487 break;
3488 default:
3489 tmp = "-12 dB";
3490 break;
3491 }
3492 snd_iprintf(buffer, "Phones Gain : %s\n", tmp);
3493
3494 snd_iprintf(buffer, "XLR Breakout Cable : %s\n", hdsp_xlr_breakout_cable(hdsp) ? "yes" : "no");
3495
3496 if (hdsp->control_register & HDSP_AnalogExtensionBoard) {
3497 snd_iprintf(buffer, "AEB : on (ADAT1 internal)\n");
3498 } else {
3499 snd_iprintf(buffer, "AEB : off (ADAT1 external)\n");
3500 }
3501 snd_iprintf(buffer, "\n");
3502 }
3503
3504 }
3505
3506 static void __devinit snd_hdsp_proc_init(hdsp_t *hdsp)
3507 {
3508 snd_info_entry_t *entry;
3509
3510 if (! snd_card_proc_new(hdsp->card, "hdsp", &entry))
3511 snd_info_set_text_ops(entry, hdsp, 1024, snd_hdsp_proc_read);
3512 }
3513
3514 static void snd_hdsp_free_buffers(hdsp_t *hdsp)
3515 {
3516 snd_hammerfall_free_buffer(&hdsp->capture_dma_buf, hdsp->pci);
3517 snd_hammerfall_free_buffer(&hdsp->playback_dma_buf, hdsp->pci);
3518 }
3519
3520 static int __devinit snd_hdsp_initialize_memory(hdsp_t *hdsp)
3521 {
3522 unsigned long pb_bus, cb_bus;
3523
3524 if (snd_hammerfall_get_buffer(hdsp->pci, &hdsp->capture_dma_buf, HDSP_DMA_AREA_BYTES) < 0 ||
3525 snd_hammerfall_get_buffer(hdsp->pci, &hdsp->playback_dma_buf, HDSP_DMA_AREA_BYTES) < 0) {
3526 if (hdsp->capture_dma_buf.area)
3527 snd_dma_free_pages(&hdsp->capture_dma_buf);
3528 printk(KERN_ERR "%s: no buffers available\n", hdsp->card_name);
3529 return -ENOMEM;
3530 }
3531
3532 /* Align to bus-space 64K boundary */
3533
3534 cb_bus = (hdsp->capture_dma_buf.addr + 0xFFFF) & ~0xFFFFl;
3535 pb_bus = (hdsp->playback_dma_buf.addr + 0xFFFF) & ~0xFFFFl;
3536
3537 /* Tell the card where it is */
3538
3539 hdsp_write(hdsp, HDSP_inputBufferAddress, cb_bus);
3540 hdsp_write(hdsp, HDSP_outputBufferAddress, pb_bus);
3541
3542 hdsp->capture_buffer = hdsp->capture_dma_buf.area + (cb_bus - hdsp->capture_dma_buf.addr);
3543 hdsp->playback_buffer = hdsp->playback_dma_buf.area + (pb_bus - hdsp->playback_dma_buf.addr);
3544
3545 return 0;
3546 }
3547
3548 static int snd_hdsp_set_defaults(hdsp_t *hdsp)
3549 {
3550 unsigned int i;
3551
3552 /* ASSUMPTION: hdsp->lock is either held, or
3553 there is no need to hold it (e.g. during module
3554 initalization).
3555 */
3556
3557 /* set defaults:
3558
3559 SPDIF Input via Coax
3560 Master clock mode
3561 maximum latency (7 => 2^7 = 8192 samples, 64Kbyte buffer,
3562 which implies 2 4096 sample, 32Kbyte periods).
3563 Enable line out.
3564 */
3565
3566 hdsp->control_register = HDSP_ClockModeMaster |
3567 HDSP_SPDIFInputCoaxial |
3568 hdsp_encode_latency(7) |
3569 HDSP_LineOut;
3570
3571
3572 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3573
3574 #ifdef SNDRV_BIG_ENDIAN
3575 hdsp->control2_register = HDSP_BIGENDIAN_MODE;
3576 #else
3577 hdsp->control2_register = 0;
3578 #endif
3579 if (hdsp->io_type == H9652) {
3580 snd_hdsp_9652_enable_mixer (hdsp);
3581 } else {
3582 hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register);
3583 }
3584
3585 hdsp_reset_hw_pointer(hdsp);
3586 hdsp_compute_period_size(hdsp);
3587
3588 /* silence everything */
3589
3590 for (i = 0; i < HDSP_MATRIX_MIXER_SIZE; ++i) {
3591 hdsp->mixer_matrix[i] = MINUS_INFINITY_GAIN;
3592 }
3593
3594 for (i = 0; i < ((hdsp->io_type == H9652 || hdsp->io_type == H9632) ? 1352 : HDSP_MATRIX_MIXER_SIZE); ++i) {
3595 if (hdsp_write_gain (hdsp, i, MINUS_INFINITY_GAIN)) {
3596 return -EIO;
3597 }
3598 }
3599
3600 /* H9632 specific defaults */
3601 if (hdsp->io_type == H9632) {
3602 hdsp->control_register |= (HDSP_DAGainPlus4dBu | HDSP_ADGainPlus4dBu | HDSP_PhoneGain0dB);
3603 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3604 }
3605
3606 /* set a default rate so that the channel map is set up.
3607 */
3608
3609 hdsp_set_rate(hdsp, 48000, 1);
3610
3611 return 0;
3612 }
3613
3614 static void hdsp_midi_tasklet(unsigned long arg)
3615 {
3616 hdsp_t *hdsp = (hdsp_t *)arg;
3617
3618 if (hdsp->midi[0].pending) {
3619 snd_hdsp_midi_input_read (&hdsp->midi[0]);
3620 }
3621 if (hdsp->midi[1].pending) {
3622 snd_hdsp_midi_input_read (&hdsp->midi[1]);
3623 }
3624 }
3625
3626 static irqreturn_t snd_hdsp_interrupt(int irq, void *dev_id, struct pt_regs *regs)
3627 {
3628 hdsp_t *hdsp = (hdsp_t *) dev_id;
3629 unsigned int status;
3630 int audio;
3631 int midi0;
3632 int midi1;
3633 unsigned int midi0status;
3634 unsigned int midi1status;
3635 int schedule = 0;
3636
3637 status = hdsp_read(hdsp, HDSP_statusRegister);
3638
3639 audio = status & HDSP_audioIRQPending;
3640 midi0 = status & HDSP_midi0IRQPending;
3641 midi1 = status & HDSP_midi1IRQPending;
3642
3643 if (!audio && !midi0 && !midi1) {
3644 return IRQ_NONE;
3645 }
3646
3647 hdsp_write(hdsp, HDSP_interruptConfirmation, 0);
3648
3649 midi0status = hdsp_read (hdsp, HDSP_midiStatusIn0) & 0xff;
3650 midi1status = hdsp_read (hdsp, HDSP_midiStatusIn1) & 0xff;
3651
3652 if (audio) {
3653 if (hdsp->capture_substream) {
3654 snd_pcm_period_elapsed(hdsp->pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream);
3655 }
3656
3657 if (hdsp->playback_substream) {
3658 snd_pcm_period_elapsed(hdsp->pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream);
3659 }
3660 }
3661
3662 if (midi0 && midi0status) {
3663 if (hdsp->use_midi_tasklet) {
3664 /* we disable interrupts for this input until processing is done */
3665 hdsp->control_register &= ~HDSP_Midi0InterruptEnable;
3666 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3667 hdsp->midi[0].pending = 1;
3668 schedule = 1;
3669 } else {
3670 snd_hdsp_midi_input_read (&hdsp->midi[0]);
3671 }
3672 }
3673 if (hdsp->io_type != Multiface && hdsp->io_type != H9632 && midi1 && midi1status) {
3674 if (hdsp->use_midi_tasklet) {
3675 /* we disable interrupts for this input until processing is done */
3676 hdsp->control_register &= ~HDSP_Midi1InterruptEnable;
3677 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3678 hdsp->midi[1].pending = 1;
3679 schedule = 1;
3680 } else {
3681 snd_hdsp_midi_input_read (&hdsp->midi[1]);
3682 }
3683 }
3684 if (hdsp->use_midi_tasklet && schedule)
3685 tasklet_hi_schedule(&hdsp->midi_tasklet);
3686 return IRQ_HANDLED;
3687 }
3688
3689 static snd_pcm_uframes_t snd_hdsp_hw_pointer(snd_pcm_substream_t *substream)
3690 {
3691 hdsp_t *hdsp = snd_pcm_substream_chip(substream);
3692 return hdsp_hw_pointer(hdsp);
3693 }
3694
3695 static char *hdsp_channel_buffer_location(hdsp_t *hdsp,
3696 int stream,
3697 int channel)
3698
3699 {
3700 int mapped_channel;
3701
3702 snd_assert(channel >= 0 && channel < hdsp->max_channels, return NULL);
3703
3704 if ((mapped_channel = hdsp->channel_map[channel]) < 0) {
3705 return NULL;
3706 }
3707
3708 if (stream == SNDRV_PCM_STREAM_CAPTURE) {
3709 return hdsp->capture_buffer + (mapped_channel * HDSP_CHANNEL_BUFFER_BYTES);
3710 } else {
3711 return hdsp->playback_buffer + (mapped_channel * HDSP_CHANNEL_BUFFER_BYTES);
3712 }
3713 }
3714
3715 static int snd_hdsp_playback_copy(snd_pcm_substream_t *substream, int channel,
3716 snd_pcm_uframes_t pos, void __user *src, snd_pcm_uframes_t count)
3717 {
3718 hdsp_t *hdsp = snd_pcm_substream_chip(substream);
3719 char *channel_buf;
3720
3721 snd_assert(pos + count <= HDSP_CHANNEL_BUFFER_BYTES / 4, return -EINVAL);
3722
3723 channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel);
3724 snd_assert(channel_buf != NULL, return -EIO);
3725 if (copy_from_user(channel_buf + pos * 4, src, count * 4))
3726 return -EFAULT;
3727 return count;
3728 }
3729
3730 static int snd_hdsp_capture_copy(snd_pcm_substream_t *substream, int channel,
3731 snd_pcm_uframes_t pos, void __user *dst, snd_pcm_uframes_t count)
3732 {
3733 hdsp_t *hdsp = snd_pcm_substream_chip(substream);
3734 char *channel_buf;
3735
3736 snd_assert(pos + count <= HDSP_CHANNEL_BUFFER_BYTES / 4, return -EINVAL);
3737
3738 channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel);
3739 snd_assert(channel_buf != NULL, return -EIO);
3740 if (copy_to_user(dst, channel_buf + pos * 4, count * 4))
3741 return -EFAULT;
3742 return count;
3743 }
3744
3745 static int snd_hdsp_hw_silence(snd_pcm_substream_t *substream, int channel,
3746 snd_pcm_uframes_t pos, snd_pcm_uframes_t count)
3747 {
3748 hdsp_t *hdsp = snd_pcm_substream_chip(substream);
3749 char *channel_buf;
3750
3751 channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel);
3752 snd_assert(channel_buf != NULL, return -EIO);
3753 memset(channel_buf + pos * 4, 0, count * 4);
3754 return count;
3755 }
3756
3757 static int snd_hdsp_reset(snd_pcm_substream_t *substream)
3758 {
3759 snd_pcm_runtime_t *runtime = substream->runtime;
3760 hdsp_t *hdsp = snd_pcm_substream_chip(substream);
3761 snd_pcm_substream_t *other;
3762 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
3763 other = hdsp->capture_substream;
3764 else
3765 other = hdsp->playback_substream;
3766 if (hdsp->running)
3767 runtime->status->hw_ptr = hdsp_hw_pointer(hdsp);
3768 else
3769 runtime->status->hw_ptr = 0;
3770 if (other) {
3771 struct list_head *pos;
3772 snd_pcm_substream_t *s;
3773 snd_pcm_runtime_t *oruntime = other->runtime;
3774 snd_pcm_group_for_each(pos, substream) {
3775 s = snd_pcm_group_substream_entry(pos);
3776 if (s == other) {
3777 oruntime->status->hw_ptr = runtime->status->hw_ptr;
3778 break;
3779 }
3780 }
3781 }
3782 return 0;
3783 }
3784
3785 static int snd_hdsp_hw_params(snd_pcm_substream_t *substream,
3786 snd_pcm_hw_params_t *params)
3787 {
3788 hdsp_t *hdsp = snd_pcm_substream_chip(substream);
3789 int err;
3790 pid_t this_pid;
3791 pid_t other_pid;
3792
3793 if (hdsp_check_for_iobox (hdsp)) {
3794 return -EIO;
3795 }
3796
3797 if (hdsp_check_for_firmware(hdsp)) {
3798 if (hdsp->state & HDSP_FirmwareCached) {
3799 if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) {
3800 snd_printk("Hammerfall-DSP: Firmware loading from cache failed, please upload manually.\n");
3801 }
3802 } else {
3803 snd_printk("Hammerfall-DSP: No firmware loaded nor cached, please upload firmware.\n");
3804 }
3805 return -EIO;
3806 }
3807
3808 spin_lock_irq(&hdsp->lock);
3809
3810 if (substream->pstr->stream == SNDRV_PCM_STREAM_PLAYBACK) {
3811 hdsp->control_register &= ~(HDSP_SPDIFProfessional | HDSP_SPDIFNonAudio | HDSP_SPDIFEmphasis);
3812 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register |= hdsp->creg_spdif_stream);
3813 this_pid = hdsp->playback_pid;
3814 other_pid = hdsp->capture_pid;
3815 } else {
3816 this_pid = hdsp->capture_pid;
3817 other_pid = hdsp->playback_pid;
3818 }
3819
3820 if ((other_pid > 0) && (this_pid != other_pid)) {
3821
3822 /* The other stream is open, and not by the same
3823 task as this one. Make sure that the parameters
3824 that matter are the same.
3825 */
3826
3827 if (params_rate(params) != hdsp->system_sample_rate) {
3828 spin_unlock_irq(&hdsp->lock);
3829 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_RATE);
3830 return -EBUSY;
3831 }
3832
3833 if (params_period_size(params) != hdsp->period_bytes / 4) {
3834 spin_unlock_irq(&hdsp->lock);
3835 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
3836 return -EBUSY;
3837 }
3838
3839 /* We're fine. */
3840
3841 spin_unlock_irq(&hdsp->lock);
3842 return 0;
3843
3844 } else {
3845 spin_unlock_irq(&hdsp->lock);
3846 }
3847
3848 /* how to make sure that the rate matches an externally-set one ?
3849 */
3850
3851 spin_lock_irq(&hdsp->lock);
3852 if ((err = hdsp_set_rate(hdsp, params_rate(params), 0)) < 0) {
3853 spin_unlock_irq(&hdsp->lock);
3854 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_RATE);
3855 return err;
3856 } else {
3857 spin_unlock_irq(&hdsp->lock);
3858 }
3859
3860 if ((err = hdsp_set_interrupt_interval(hdsp, params_period_size(params))) < 0) {
3861 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
3862 return err;
3863 }
3864
3865 return 0;
3866 }
3867
3868 static int snd_hdsp_channel_info(snd_pcm_substream_t *substream,
3869 snd_pcm_channel_info_t *info)
3870 {
3871 hdsp_t *hdsp = snd_pcm_substream_chip(substream);
3872 int mapped_channel;
3873
3874 snd_assert(info->channel < hdsp->max_channels, return -EINVAL);
3875
3876 if ((mapped_channel = hdsp->channel_map[info->channel]) < 0) {
3877 return -EINVAL;
3878 }
3879
3880 info->offset = mapped_channel * HDSP_CHANNEL_BUFFER_BYTES;
3881 info->first = 0;
3882 info->step = 32;
3883 return 0;
3884 }
3885
3886 static int snd_hdsp_ioctl(snd_pcm_substream_t *substream,
3887 unsigned int cmd, void *arg)
3888 {
3889 switch (cmd) {
3890 case SNDRV_PCM_IOCTL1_RESET:
3891 {
3892 return snd_hdsp_reset(substream);
3893 }
3894 case SNDRV_PCM_IOCTL1_CHANNEL_INFO:
3895 {
3896 snd_pcm_channel_info_t *info = arg;
3897 return snd_hdsp_channel_info(substream, info);
3898 }
3899 default:
3900 break;
3901 }
3902
3903 return snd_pcm_lib_ioctl(substream, cmd, arg);
3904 }
3905
3906 static int snd_hdsp_trigger(snd_pcm_substream_t *substream, int cmd)
3907 {
3908 hdsp_t *hdsp = snd_pcm_substream_chip(substream);
3909 snd_pcm_substream_t *other;
3910 int running;
3911
3912 if (hdsp_check_for_iobox (hdsp)) {
3913 return -EIO;
3914 }
3915
3916 if (hdsp_check_for_firmware(hdsp)) {
3917 if (hdsp->state & HDSP_FirmwareCached) {
3918 if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) {
3919 snd_printk("Hammerfall-DSP: Firmware loading from cache failed, please upload manually.\n");
3920 }
3921 } else {
3922 snd_printk("Hammerfall-DSP: No firmware loaded nor cached, please upload firmware.\n");
3923 }
3924 return -EIO;
3925 }
3926
3927 spin_lock(&hdsp->lock);
3928 running = hdsp->running;
3929 switch (cmd) {
3930 case SNDRV_PCM_TRIGGER_START:
3931 running |= 1 << substream->stream;
3932 break;
3933 case SNDRV_PCM_TRIGGER_STOP:
3934 running &= ~(1 << substream->stream);
3935 break;
3936 default:
3937 snd_BUG();
3938 spin_unlock(&hdsp->lock);
3939 return -EINVAL;
3940 }
3941 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
3942 other = hdsp->capture_substream;
3943 else
3944 other = hdsp->playback_substream;
3945
3946 if (other) {
3947 struct list_head *pos;
3948 snd_pcm_substream_t *s;
3949 snd_pcm_group_for_each(pos, substream) {
3950 s = snd_pcm_group_substream_entry(pos);
3951 if (s == other) {
3952 snd_pcm_trigger_done(s, substream);
3953 if (cmd == SNDRV_PCM_TRIGGER_START)
3954 running |= 1 << s->stream;
3955 else
3956 running &= ~(1 << s->stream);
3957 goto _ok;
3958 }
3959 }
3960 if (cmd == SNDRV_PCM_TRIGGER_START) {
3961 if (!(running & (1 << SNDRV_PCM_STREAM_PLAYBACK)) &&
3962 substream->stream == SNDRV_PCM_STREAM_CAPTURE)
3963 hdsp_silence_playback(hdsp);
3964 } else {
3965 if (running &&
3966 substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
3967 hdsp_silence_playback(hdsp);
3968 }
3969 } else {
3970 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
3971 hdsp_silence_playback(hdsp);
3972 }
3973 _ok:
3974 snd_pcm_trigger_done(substream, substream);
3975 if (!hdsp->running && running)
3976 hdsp_start_audio(hdsp);
3977 else if (hdsp->running && !running)
3978 hdsp_stop_audio(hdsp);
3979 hdsp->running = running;
3980 spin_unlock(&hdsp->lock);
3981
3982 return 0;
3983 }
3984
3985 static int snd_hdsp_prepare(snd_pcm_substream_t *substream)
3986 {
3987 hdsp_t *hdsp = snd_pcm_substream_chip(substream);
3988 int result = 0;
3989
3990 if (hdsp_check_for_iobox (hdsp)) {
3991 return -EIO;
3992 }
3993
3994 if (hdsp_check_for_firmware(hdsp)) {
3995 if (hdsp->state & HDSP_FirmwareCached) {
3996 if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) {
3997 snd_printk("Hammerfall-DSP: Firmware loading from cache failed, please upload manually.\n");
3998 }
3999 } else {
4000 snd_printk("Hammerfall-DSP: No firmware loaded nor cached, please upload firmware.\n");
4001 }
4002 return -EIO;
4003 }
4004
4005 spin_lock_irq(&hdsp->lock);
4006 if (!hdsp->running)
4007 hdsp_reset_hw_pointer(hdsp);
4008 spin_unlock_irq(&hdsp->lock);
4009 return result;
4010 }
4011
4012 static snd_pcm_hardware_t snd_hdsp_playback_subinfo =
4013 {
4014 .info = (SNDRV_PCM_INFO_MMAP |
4015 SNDRV_PCM_INFO_MMAP_VALID |
4016 SNDRV_PCM_INFO_NONINTERLEAVED |
4017 SNDRV_PCM_INFO_SYNC_START |
4018 SNDRV_PCM_INFO_DOUBLE),
4019 #ifdef SNDRV_BIG_ENDIAN
4020 .formats = SNDRV_PCM_FMTBIT_S32_BE,
4021 #else
4022 .formats = SNDRV_PCM_FMTBIT_S32_LE,
4023 #endif
4024 .rates = (SNDRV_PCM_RATE_32000 |
4025 SNDRV_PCM_RATE_44100 |
4026 SNDRV_PCM_RATE_48000 |
4027 SNDRV_PCM_RATE_64000 |
4028 SNDRV_PCM_RATE_88200 |
4029 SNDRV_PCM_RATE_96000),
4030 .rate_min = 32000,
4031 .rate_max = 96000,
4032 .channels_min = 14,
4033 .channels_max = HDSP_MAX_CHANNELS,
4034 .buffer_bytes_max = HDSP_CHANNEL_BUFFER_BYTES * HDSP_MAX_CHANNELS,
4035 .period_bytes_min = (64 * 4) * 10,
4036 .period_bytes_max = (8192 * 4) * HDSP_MAX_CHANNELS,
4037 .periods_min = 2,
4038 .periods_max = 2,
4039 .fifo_size = 0
4040 };
4041
4042 static snd_pcm_hardware_t snd_hdsp_capture_subinfo =
4043 {
4044 .info = (SNDRV_PCM_INFO_MMAP |
4045 SNDRV_PCM_INFO_MMAP_VALID |
4046 SNDRV_PCM_INFO_NONINTERLEAVED |
4047 SNDRV_PCM_INFO_SYNC_START),
4048 #ifdef SNDRV_BIG_ENDIAN
4049 .formats = SNDRV_PCM_FMTBIT_S32_BE,
4050 #else
4051 .formats = SNDRV_PCM_FMTBIT_S32_LE,
4052 #endif
4053 .rates = (SNDRV_PCM_RATE_32000 |
4054 SNDRV_PCM_RATE_44100 |
4055 SNDRV_PCM_RATE_48000 |
4056 SNDRV_PCM_RATE_64000 |
4057 SNDRV_PCM_RATE_88200 |
4058 SNDRV_PCM_RATE_96000),
4059 .rate_min = 32000,
4060 .rate_max = 96000,
4061 .channels_min = 14,
4062 .channels_max = HDSP_MAX_CHANNELS,
4063 .buffer_bytes_max = HDSP_CHANNEL_BUFFER_BYTES * HDSP_MAX_CHANNELS,
4064 .period_bytes_min = (64 * 4) * 10,
4065 .period_bytes_max = (8192 * 4) * HDSP_MAX_CHANNELS,
4066 .periods_min = 2,
4067 .periods_max = 2,
4068 .fifo_size = 0
4069 };
4070
4071 static unsigned int hdsp_period_sizes[] = { 64, 128, 256, 512, 1024, 2048, 4096, 8192 };
4072
4073 static snd_pcm_hw_constraint_list_t hdsp_hw_constraints_period_sizes = {
4074 .count = ARRAY_SIZE(hdsp_period_sizes),
4075 .list = hdsp_period_sizes,
4076 .mask = 0
4077 };
4078
4079 static unsigned int hdsp_9632_sample_rates[] = { 32000, 44100, 48000, 64000, 88200, 96000, 128000, 176400, 192000 };
4080
4081 static snd_pcm_hw_constraint_list_t hdsp_hw_constraints_9632_sample_rates = {
4082 .count = ARRAY_SIZE(hdsp_9632_sample_rates),
4083 .list = hdsp_9632_sample_rates,
4084 .mask = 0
4085 };
4086
4087 static int snd_hdsp_hw_rule_in_channels(snd_pcm_hw_params_t *params,
4088 snd_pcm_hw_rule_t *rule)
4089 {
4090 hdsp_t *hdsp = rule->private;
4091 snd_interval_t *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4092 if (hdsp->io_type == H9632) {
4093 unsigned int list[3];
4094 list[0] = hdsp->qs_in_channels;
4095 list[1] = hdsp->ds_in_channels;
4096 list[2] = hdsp->ss_in_channels;
4097 return snd_interval_list(c, 3, list, 0);
4098 } else {
4099 unsigned int list[2];
4100 list[0] = hdsp->ds_in_channels;
4101 list[1] = hdsp->ss_in_channels;
4102 return snd_interval_list(c, 2, list, 0);
4103 }
4104 }
4105
4106 static int snd_hdsp_hw_rule_out_channels(snd_pcm_hw_params_t *params,
4107 snd_pcm_hw_rule_t *rule)
4108 {
4109 unsigned int list[3];
4110 hdsp_t *hdsp = rule->private;
4111 snd_interval_t *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4112 if (hdsp->io_type == H9632) {
4113 list[0] = hdsp->qs_out_channels;
4114 list[1] = hdsp->ds_out_channels;
4115 list[2] = hdsp->ss_out_channels;
4116 return snd_interval_list(c, 3, list, 0);
4117 } else {
4118 list[0] = hdsp->ds_out_channels;
4119 list[1] = hdsp->ss_out_channels;
4120 }
4121 return snd_interval_list(c, 2, list, 0);
4122 }
4123
4124 static int snd_hdsp_hw_rule_in_channels_rate(snd_pcm_hw_params_t *params,
4125 snd_pcm_hw_rule_t *rule)
4126 {
4127 hdsp_t *hdsp = rule->private;
4128 snd_interval_t *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4129 snd_interval_t *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4130 if (r->min > 96000 && hdsp->io_type == H9632) {
4131 snd_interval_t t = {
4132 .min = hdsp->qs_in_channels,
4133 .max = hdsp->qs_in_channels,
4134 .integer = 1,
4135 };
4136 return snd_interval_refine(c, &t);
4137 } else if (r->min > 48000 && r->max <= 96000) {
4138 snd_interval_t t = {
4139 .min = hdsp->ds_in_channels,
4140 .max = hdsp->ds_in_channels,
4141 .integer = 1,
4142 };
4143 return snd_interval_refine(c, &t);
4144 } else if (r->max < 64000) {
4145 snd_interval_t t = {
4146 .min = hdsp->ss_in_channels,
4147 .max = hdsp->ss_in_channels,
4148 .integer = 1,
4149 };
4150 return snd_interval_refine(c, &t);
4151 }
4152 return 0;
4153 }
4154
4155 static int snd_hdsp_hw_rule_out_channels_rate(snd_pcm_hw_params_t *params,
4156 snd_pcm_hw_rule_t *rule)
4157 {
4158 hdsp_t *hdsp = rule->private;
4159 snd_interval_t *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4160 snd_interval_t *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4161 if (r->min > 96000 && hdsp->io_type == H9632) {
4162 snd_interval_t t = {
4163 .min = hdsp->qs_out_channels,
4164 .max = hdsp->qs_out_channels,
4165 .integer = 1,
4166 };
4167 return snd_interval_refine(c, &t);
4168 } else if (r->min > 48000 && r->max <= 96000) {
4169 snd_interval_t t = {
4170 .min = hdsp->ds_out_channels,
4171 .max = hdsp->ds_out_channels,
4172 .integer = 1,
4173 };
4174 return snd_interval_refine(c, &t);
4175 } else if (r->max < 64000) {
4176 snd_interval_t t = {
4177 .min = hdsp->ss_out_channels,
4178 .max = hdsp->ss_out_channels,
4179 .integer = 1,
4180 };
4181 return snd_interval_refine(c, &t);
4182 }
4183 return 0;
4184 }
4185
4186 static int snd_hdsp_hw_rule_rate_out_channels(snd_pcm_hw_params_t *params,
4187 snd_pcm_hw_rule_t *rule)
4188 {
4189 hdsp_t *hdsp = rule->private;
4190 snd_interval_t *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4191 snd_interval_t *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4192 if (c->min >= hdsp->ss_out_channels) {
4193 snd_interval_t t = {
4194 .min = 32000,
4195 .max = 48000,
4196 .integer = 1,
4197 };
4198 return snd_interval_refine(r, &t);
4199 } else if (c->max <= hdsp->qs_out_channels && hdsp->io_type == H9632) {
4200 snd_interval_t t = {
4201 .min = 128000,
4202 .max = 192000,
4203 .integer = 1,
4204 };
4205 return snd_interval_refine(r, &t);
4206 } else if (c->max <= hdsp->ds_out_channels) {
4207 snd_interval_t t = {
4208 .min = 64000,
4209 .max = 96000,
4210 .integer = 1,
4211 };
4212 return snd_interval_refine(r, &t);
4213 }
4214 return 0;
4215 }
4216
4217 static int snd_hdsp_hw_rule_rate_in_channels(snd_pcm_hw_params_t *params,
4218 snd_pcm_hw_rule_t *rule)
4219 {
4220 hdsp_t *hdsp = rule->private;
4221 snd_interval_t *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4222 snd_interval_t *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4223 if (c->min >= hdsp->ss_in_channels) {
4224 snd_interval_t t = {
4225 .min = 32000,
4226 .max = 48000,
4227 .integer = 1,
4228 };
4229 return snd_interval_refine(r, &t);
4230 } else if (c->max <= hdsp->qs_in_channels && hdsp->io_type == H9632) {
4231 snd_interval_t t = {
4232 .min = 128000,
4233 .max = 192000,
4234 .integer = 1,
4235 };
4236 return snd_interval_refine(r, &t);
4237 } else if (c->max <= hdsp->ds_in_channels) {
4238 snd_interval_t t = {
4239 .min = 64000,
4240 .max = 96000,
4241 .integer = 1,
4242 };
4243 return snd_interval_refine(r, &t);
4244 }
4245 return 0;
4246 }
4247
4248 static int snd_hdsp_playback_open(snd_pcm_substream_t *substream)
4249 {
4250 hdsp_t *hdsp = snd_pcm_substream_chip(substream);
4251 snd_pcm_runtime_t *runtime = substream->runtime;
4252
4253 if (hdsp_check_for_iobox (hdsp)) {
4254 return -EIO;
4255 }
4256
4257 if (hdsp_check_for_firmware(hdsp)) {
4258 if (hdsp->state & HDSP_FirmwareCached) {
4259 if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) {
4260 snd_printk("Hammerfall-DSP: Firmware loading from cache failed, please upload manually.\n");
4261 }
4262 } else {
4263 snd_printk("Hammerfall-DSP: No firmware loaded nor cached, please upload firmware.\n");
4264 }
4265 return -EIO;
4266 }
4267
4268 spin_lock_irq(&hdsp->lock);
4269
4270 snd_pcm_set_sync(substream);
4271
4272 runtime->hw = snd_hdsp_playback_subinfo;
4273 runtime->dma_area = hdsp->playback_buffer;
4274 runtime->dma_bytes = HDSP_DMA_AREA_BYTES;
4275
4276 hdsp->playback_pid = current->pid;
4277 hdsp->playback_substream = substream;
4278
4279 spin_unlock_irq(&hdsp->lock);
4280
4281 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
4282 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, &hdsp_hw_constraints_period_sizes);
4283 if (hdsp->io_type == H9632) {
4284 runtime->hw.channels_min = hdsp->qs_out_channels;
4285 runtime->hw.channels_max = hdsp->ss_out_channels;
4286 runtime->hw.rate_max = 192000;
4287 runtime->hw.rates = SNDRV_PCM_RATE_KNOT;
4288 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hdsp_hw_constraints_9632_sample_rates);
4289 }
4290
4291 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4292 snd_hdsp_hw_rule_out_channels, hdsp,
4293 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4294 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4295 snd_hdsp_hw_rule_out_channels_rate, hdsp,
4296 SNDRV_PCM_HW_PARAM_RATE, -1);
4297 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
4298 snd_hdsp_hw_rule_rate_out_channels, hdsp,
4299 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4300
4301 hdsp->creg_spdif_stream = hdsp->creg_spdif;
4302 hdsp->spdif_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
4303 snd_ctl_notify(hdsp->card, SNDRV_CTL_EVENT_MASK_VALUE |
4304 SNDRV_CTL_EVENT_MASK_INFO, &hdsp->spdif_ctl->id);
4305 return 0;
4306 }
4307
4308 static int snd_hdsp_playback_release(snd_pcm_substream_t *substream)
4309 {
4310 hdsp_t *hdsp = snd_pcm_substream_chip(substream);
4311
4312 spin_lock_irq(&hdsp->lock);
4313
4314 hdsp->playback_pid = -1;
4315 hdsp->playback_substream = NULL;
4316
4317 spin_unlock_irq(&hdsp->lock);
4318
4319 hdsp->spdif_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
4320 snd_ctl_notify(hdsp->card, SNDRV_CTL_EVENT_MASK_VALUE |
4321 SNDRV_CTL_EVENT_MASK_INFO, &hdsp->spdif_ctl->id);
4322 return 0;
4323 }
4324
4325
4326 static int snd_hdsp_capture_open(snd_pcm_substream_t *substream)
4327 {
4328 hdsp_t *hdsp = snd_pcm_substream_chip(substream);
4329 snd_pcm_runtime_t *runtime = substream->runtime;
4330
4331 if (hdsp_check_for_iobox (hdsp)) {
4332 return -EIO;
4333 }
4334
4335 if (hdsp_check_for_firmware(hdsp)) {
4336 if (hdsp->state & HDSP_FirmwareCached) {
4337 if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) {
4338 snd_printk("Hammerfall-DSP: Firmware loading from cache failed, please upload manually.\n");
4339 }
4340 } else {
4341 snd_printk("Hammerfall-DSP: No firmware loaded nor cached, please upload firmware.\n");
4342 }
4343 return -EIO;
4344 }
4345
4346 spin_lock_irq(&hdsp->lock);
4347
4348 snd_pcm_set_sync(substream);
4349
4350 runtime->hw = snd_hdsp_capture_subinfo;
4351 runtime->dma_area = hdsp->capture_buffer;
4352 runtime->dma_bytes = HDSP_DMA_AREA_BYTES;
4353
4354 hdsp->capture_pid = current->pid;
4355 hdsp->capture_substream = substream;
4356
4357 spin_unlock_irq(&hdsp->lock);
4358
4359 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
4360 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, &hdsp_hw_constraints_period_sizes);
4361 if (hdsp->io_type == H9632) {
4362 runtime->hw.channels_min = hdsp->qs_in_channels;
4363 runtime->hw.channels_max = hdsp->ss_in_channels;
4364 runtime->hw.rate_max = 192000;
4365 runtime->hw.rates = SNDRV_PCM_RATE_KNOT;
4366 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hdsp_hw_constraints_9632_sample_rates);
4367 }
4368 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4369 snd_hdsp_hw_rule_in_channels, hdsp,
4370 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4371 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4372 snd_hdsp_hw_rule_in_channels_rate, hdsp,
4373 SNDRV_PCM_HW_PARAM_RATE, -1);
4374 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
4375 snd_hdsp_hw_rule_rate_in_channels, hdsp,
4376 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4377 return 0;
4378 }
4379
4380 static int snd_hdsp_capture_release(snd_pcm_substream_t *substream)
4381 {
4382 hdsp_t *hdsp = snd_pcm_substream_chip(substream);
4383
4384 spin_lock_irq(&hdsp->lock);
4385
4386 hdsp->capture_pid = -1;
4387 hdsp->capture_substream = NULL;
4388
4389 spin_unlock_irq(&hdsp->lock);
4390 return 0;
4391 }
4392
4393 static int snd_hdsp_hwdep_dummy_op(snd_hwdep_t *hw, struct file *file)
4394 {
4395 /* we have nothing to initialize but the call is required */
4396 return 0;
4397 }
4398
4399
4400 /* helper functions for copying meter values */
4401 static inline int copy_u32_le(void __user *dest, void __iomem *src)
4402 {
4403 u32 val = readl(src);
4404 return copy_to_user(dest, &val, 4);
4405 }
4406
4407 static inline int copy_u64_le(void __user *dest, void __iomem *src_low, void __iomem *src_high)
4408 {
4409 u32 rms_low, rms_high;
4410 u64 rms;
4411 rms_low = readl(src_low);
4412 rms_high = readl(src_high);
4413 rms = ((u64)rms_high << 32) | rms_low;
4414 return copy_to_user(dest, &rms, 8);
4415 }
4416
4417 static inline int copy_u48_le(void __user *dest, void __iomem *src_low, void __iomem *src_high)
4418 {
4419 u32 rms_low, rms_high;
4420 u64 rms;
4421 rms_low = readl(src_low) & 0xffffff00;
4422 rms_high = readl(src_high) & 0xffffff00;
4423 rms = ((u64)rms_high << 32) | rms_low;
4424 return copy_to_user(dest, &rms, 8);
4425 }
4426
4427 static int hdsp_9652_get_peak(hdsp_t *hdsp, hdsp_peak_rms_t __user *peak_rms)
4428 {
4429 int doublespeed = 0;
4430 int i, j, channels, ofs;
4431
4432 if (hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DoubleSpeedStatus)
4433 doublespeed = 1;
4434 channels = doublespeed ? 14 : 26;
4435 for (i = 0, j = 0; i < 26; ++i) {
4436 if (doublespeed && (i & 4))
4437 continue;
4438 ofs = HDSP_9652_peakBase - j * 4;
4439 if (copy_u32_le(&peak_rms->input_peaks[i], hdsp->iobase + ofs))
4440 return -EFAULT;
4441 ofs -= channels * 4;
4442 if (copy_u32_le(&peak_rms->playback_peaks[i], hdsp->iobase + ofs))
4443 return -EFAULT;
4444 ofs -= channels * 4;
4445 if (copy_u32_le(&peak_rms->output_peaks[i], hdsp->iobase + ofs))
4446 return -EFAULT;
4447 ofs = HDSP_9652_rmsBase + j * 8;
4448 if (copy_u48_le(&peak_rms->input_rms[i], hdsp->iobase + ofs,
4449 hdsp->iobase + ofs + 4))
4450 return -EFAULT;
4451 ofs += channels * 8;
4452 if (copy_u48_le(&peak_rms->playback_rms[i], hdsp->iobase + ofs,
4453 hdsp->iobase + ofs + 4))
4454 return -EFAULT;
4455 ofs += channels * 8;
4456 if (copy_u48_le(&peak_rms->output_rms[i], hdsp->iobase + ofs,
4457 hdsp->iobase + ofs + 4))
4458 return -EFAULT;
4459 j++;
4460 }
4461 return 0;
4462 }
4463
4464 static int hdsp_9632_get_peak(hdsp_t *hdsp, hdsp_peak_rms_t __user *peak_rms)
4465 {
4466 int i, j;
4467 hdsp_9632_meters_t __iomem *m;
4468 int doublespeed = 0;
4469
4470 if (hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DoubleSpeedStatus)
4471 doublespeed = 1;
4472 m = (hdsp_9632_meters_t __iomem *)(hdsp->iobase+HDSP_9632_metersBase);
4473 for (i = 0, j = 0; i < 16; ++i, ++j) {
4474 if (copy_u32_le(&peak_rms->input_peaks[i], &m->input_peak[j]))
4475 return -EFAULT;
4476 if (copy_u32_le(&peak_rms->playback_peaks[i], &m->playback_peak[j]))
4477 return -EFAULT;
4478 if (copy_u32_le(&peak_rms->output_peaks[i], &m->output_peak[j]))
4479 return -EFAULT;
4480 if (copy_u64_le(&peak_rms->input_rms[i], &m->input_rms_low[j],
4481 &m->input_rms_high[j]))
4482 return -EFAULT;
4483 if (copy_u64_le(&peak_rms->playback_rms[i], &m->playback_rms_low[j],
4484 &m->playback_rms_high[j]))
4485 return -EFAULT;
4486 if (copy_u64_le(&peak_rms->output_rms[i], &m->output_rms_low[j],
4487 &m->output_rms_high[j]))
4488 return -EFAULT;
4489 if (doublespeed && i == 3) i += 4;
4490 }
4491 return 0;
4492 }
4493
4494 static int hdsp_get_peak(hdsp_t *hdsp, hdsp_peak_rms_t __user *peak_rms)
4495 {
4496 int i;
4497
4498 for (i = 0; i < 26; i++) {
4499 if (copy_u32_le(&peak_rms->playback_peaks[i],
4500 hdsp->iobase + HDSP_playbackPeakLevel + i * 4))
4501 return -EFAULT;
4502 if (copy_u32_le(&peak_rms->input_peaks[i],
4503 hdsp->iobase + HDSP_inputPeakLevel + i * 4))
4504 return -EFAULT;
4505 }
4506 for (i = 0; i < 28; i++) {
4507 if (copy_u32_le(&peak_rms->output_peaks[i],
4508 hdsp->iobase + HDSP_outputPeakLevel + i * 4))
4509 return -EFAULT;
4510 }
4511 for (i = 0; i < 26; ++i) {
4512 if (copy_u64_le(&peak_rms->playback_rms[i],
4513 hdsp->iobase + HDSP_playbackRmsLevel + i * 8 + 4,
4514 hdsp->iobase + HDSP_playbackRmsLevel + i * 8))
4515 return -EFAULT;
4516 if (copy_u64_le(&peak_rms->input_rms[i],
4517 hdsp->iobase + HDSP_inputRmsLevel + i * 8 + 4,
4518 hdsp->iobase + HDSP_inputRmsLevel + i * 8))
4519 return -EFAULT;
4520 }
4521 return 0;
4522 }
4523
4524 static int snd_hdsp_hwdep_ioctl(snd_hwdep_t *hw, struct file *file, unsigned int cmd, unsigned long arg)
4525 {
4526 hdsp_t *hdsp = (hdsp_t *)hw->private_data;
4527 void __user *argp = (void __user *)arg;
4528
4529 switch (cmd) {
4530 case SNDRV_HDSP_IOCTL_GET_PEAK_RMS: {
4531 hdsp_peak_rms_t __user *peak_rms = (hdsp_peak_rms_t __user *)arg;
4532
4533 if (!(hdsp->state & HDSP_FirmwareLoaded)) {
4534 snd_printk(KERN_ERR "Hammerfall-DSP: firmware needs to be uploaded to the card.\n");
4535 return -EINVAL;
4536 }
4537
4538 switch (hdsp->io_type) {
4539 case H9652:
4540 return hdsp_9652_get_peak(hdsp, peak_rms);
4541 case H9632:
4542 return hdsp_9632_get_peak(hdsp, peak_rms);
4543 default:
4544 return hdsp_get_peak(hdsp, peak_rms);
4545 }
4546 }
4547 case SNDRV_HDSP_IOCTL_GET_CONFIG_INFO: {
4548 hdsp_config_info_t info;
4549 unsigned long flags;
4550 int i;
4551
4552 if (!(hdsp->state & HDSP_FirmwareLoaded)) {
4553 snd_printk("Hammerfall-DSP: Firmware needs to be uploaded to the card.\n");
4554 return -EINVAL;
4555 }
4556 spin_lock_irqsave(&hdsp->lock, flags);
4557 info.pref_sync_ref = (unsigned char)hdsp_pref_sync_ref(hdsp);
4558 info.wordclock_sync_check = (unsigned char)hdsp_wc_sync_check(hdsp);
4559 if (hdsp->io_type != H9632) {
4560 info.adatsync_sync_check = (unsigned char)hdsp_adatsync_sync_check(hdsp);
4561 }
4562 info.spdif_sync_check = (unsigned char)hdsp_spdif_sync_check(hdsp);
4563 for (i = 0; i < ((hdsp->io_type != Multiface && hdsp->io_type != H9632) ? 3 : 1); ++i) {
4564 info.adat_sync_check[i] = (unsigned char)hdsp_adat_sync_check(hdsp, i);
4565 }
4566 info.spdif_in = (unsigned char)hdsp_spdif_in(hdsp);
4567 info.spdif_out = (unsigned char)hdsp_spdif_out(hdsp);
4568 info.spdif_professional = (unsigned char)hdsp_spdif_professional(hdsp);
4569 info.spdif_emphasis = (unsigned char)hdsp_spdif_emphasis(hdsp);
4570 info.spdif_nonaudio = (unsigned char)hdsp_spdif_nonaudio(hdsp);
4571 info.spdif_sample_rate = hdsp_spdif_sample_rate(hdsp);
4572 info.system_sample_rate = hdsp->system_sample_rate;
4573 info.autosync_sample_rate = hdsp_external_sample_rate(hdsp);
4574 info.system_clock_mode = (unsigned char)hdsp_system_clock_mode(hdsp);
4575 info.clock_source = (unsigned char)hdsp_clock_source(hdsp);
4576 info.autosync_ref = (unsigned char)hdsp_autosync_ref(hdsp);
4577 info.line_out = (unsigned char)hdsp_line_out(hdsp);
4578 if (hdsp->io_type == H9632) {
4579 info.da_gain = (unsigned char)hdsp_da_gain(hdsp);
4580 info.ad_gain = (unsigned char)hdsp_ad_gain(hdsp);
4581 info.phone_gain = (unsigned char)hdsp_phone_gain(hdsp);
4582 info.xlr_breakout_cable = (unsigned char)hdsp_xlr_breakout_cable(hdsp);
4583
4584 }
4585 if (hdsp->io_type == H9632 || hdsp->io_type == H9652) {
4586 info.analog_extension_board = (unsigned char)hdsp_aeb(hdsp);
4587 }
4588 spin_unlock_irqrestore(&hdsp->lock, flags);
4589 if (copy_to_user(argp, &info, sizeof(info)))
4590 return -EFAULT;
4591 break;
4592 }
4593 case SNDRV_HDSP_IOCTL_GET_9632_AEB: {
4594 hdsp_9632_aeb_t h9632_aeb;
4595
4596 if (hdsp->io_type != H9632) return -EINVAL;
4597 h9632_aeb.aebi = hdsp->ss_in_channels - H9632_SS_CHANNELS;
4598 h9632_aeb.aebo = hdsp->ss_out_channels - H9632_SS_CHANNELS;
4599 if (copy_to_user(argp, &h9632_aeb, sizeof(h9632_aeb)))
4600 return -EFAULT;
4601 break;
4602 }
4603 case SNDRV_HDSP_IOCTL_GET_VERSION: {
4604 hdsp_version_t hdsp_version;
4605 int err;
4606
4607 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return -EINVAL;
4608 if (hdsp->io_type == Undefined) {
4609 if ((err = hdsp_get_iobox_version(hdsp)) < 0) {
4610 return err;
4611 }
4612 }
4613 hdsp_version.io_type = hdsp->io_type;
4614 hdsp_version.firmware_rev = hdsp->firmware_rev;
4615 if ((err = copy_to_user(argp, &hdsp_version, sizeof(hdsp_version)))) {
4616 return -EFAULT;
4617 }
4618 break;
4619 }
4620 case SNDRV_HDSP_IOCTL_UPLOAD_FIRMWARE: {
4621 hdsp_firmware_t __user *firmware;
4622 u32 __user *firmware_data;
4623 int err;
4624
4625 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return -EINVAL;
4626 /* SNDRV_HDSP_IOCTL_GET_VERSION must have been called */
4627 if (hdsp->io_type == Undefined) return -EINVAL;
4628
4629 if (hdsp->state & (HDSP_FirmwareCached | HDSP_FirmwareLoaded))
4630 return -EBUSY;
4631
4632 snd_printk("Hammerfall-DSP: initializing firmware upload\n");
4633 firmware = (hdsp_firmware_t __user *)argp;
4634
4635 if (get_user(firmware_data, &firmware->firmware_data)) {
4636 return -EFAULT;
4637 }
4638
4639 if (hdsp_check_for_iobox (hdsp)) {
4640 return -EIO;
4641 }
4642
4643 if (copy_from_user(hdsp->firmware_cache, firmware_data, sizeof(hdsp->firmware_cache)) != 0) {
4644 return -EFAULT;
4645 }
4646
4647 hdsp->state |= HDSP_FirmwareCached;
4648
4649 if ((err = snd_hdsp_load_firmware_from_cache(hdsp)) < 0) {
4650 return err;
4651 }
4652
4653 if (!(hdsp->state & HDSP_InitializationComplete)) {
4654 if ((err = snd_hdsp_enable_io(hdsp)) < 0) {
4655 return err;
4656 }
4657
4658 snd_hdsp_initialize_channels(hdsp);
4659 snd_hdsp_initialize_midi_flush(hdsp);
4660
4661 if ((err = snd_hdsp_create_alsa_devices(hdsp->card, hdsp)) < 0) {
4662 snd_printk("Hammerfall-DSP: error creating alsa devices\n");
4663 return err;
4664 }
4665 }
4666 break;
4667 }
4668 case SNDRV_HDSP_IOCTL_GET_MIXER: {
4669 hdsp_mixer_t __user *mixer = (hdsp_mixer_t __user *)argp;
4670 if (copy_to_user(mixer->matrix, hdsp->mixer_matrix, sizeof(unsigned short)*HDSP_MATRIX_MIXER_SIZE))
4671 return -EFAULT;
4672 break;
4673 }
4674 default:
4675 return -EINVAL;
4676 }
4677 return 0;
4678 }
4679
4680 static snd_pcm_ops_t snd_hdsp_playback_ops = {
4681 .open = snd_hdsp_playback_open,
4682 .close = snd_hdsp_playback_release,
4683 .ioctl = snd_hdsp_ioctl,
4684 .hw_params = snd_hdsp_hw_params,
4685 .prepare = snd_hdsp_prepare,
4686 .trigger = snd_hdsp_trigger,
4687 .pointer = snd_hdsp_hw_pointer,
4688 .copy = snd_hdsp_playback_copy,
4689 .silence = snd_hdsp_hw_silence,
4690 };
4691
4692 static snd_pcm_ops_t snd_hdsp_capture_ops = {
4693 .open = snd_hdsp_capture_open,
4694 .close = snd_hdsp_capture_release,
4695 .ioctl = snd_hdsp_ioctl,
4696 .hw_params = snd_hdsp_hw_params,
4697 .prepare = snd_hdsp_prepare,
4698 .trigger = snd_hdsp_trigger,
4699 .pointer = snd_hdsp_hw_pointer,
4700 .copy = snd_hdsp_capture_copy,
4701 };
4702
4703 static int __devinit snd_hdsp_create_hwdep(snd_card_t *card,
4704 hdsp_t *hdsp)
4705 {
4706 snd_hwdep_t *hw;
4707 int err;
4708
4709 if ((err = snd_hwdep_new(card, "HDSP hwdep", 0, &hw)) < 0)
4710 return err;
4711
4712 hdsp->hwdep = hw;
4713 hw->private_data = hdsp;
4714 strcpy(hw->name, "HDSP hwdep interface");
4715
4716 hw->ops.open = snd_hdsp_hwdep_dummy_op;
4717 hw->ops.ioctl = snd_hdsp_hwdep_ioctl;
4718 hw->ops.release = snd_hdsp_hwdep_dummy_op;
4719
4720 return 0;
4721 }
4722
4723 static int snd_hdsp_create_pcm(snd_card_t *card, hdsp_t *hdsp)
4724 {
4725 snd_pcm_t *pcm;
4726 int err;
4727
4728 if ((err = snd_pcm_new(card, hdsp->card_name, 0, 1, 1, &pcm)) < 0)
4729 return err;
4730
4731 hdsp->pcm = pcm;
4732 pcm->private_data = hdsp;
4733 strcpy(pcm->name, hdsp->card_name);
4734
4735 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_hdsp_playback_ops);
4736 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_hdsp_capture_ops);
4737
4738 pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;
4739
4740 return 0;
4741 }
4742
4743 static void snd_hdsp_9652_enable_mixer (hdsp_t *hdsp)
4744 {
4745 hdsp->control2_register |= HDSP_9652_ENABLE_MIXER;
4746 hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register);
4747 }
4748
4749 static int snd_hdsp_enable_io (hdsp_t *hdsp)
4750 {
4751 int i;
4752
4753 if (hdsp_fifo_wait (hdsp, 0, 100)) {
4754 snd_printk("Hammerfall-DSP: enable_io fifo_wait failed\n");
4755 return -EIO;
4756 }
4757
4758 for (i = 0; i < hdsp->max_channels; ++i) {
4759 hdsp_write (hdsp, HDSP_inputEnable + (4 * i), 1);
4760 hdsp_write (hdsp, HDSP_outputEnable + (4 * i), 1);
4761 }
4762
4763 return 0;
4764 }
4765
4766 static void snd_hdsp_initialize_channels(hdsp_t *hdsp)
4767 {
4768 int status, aebi_channels, aebo_channels;
4769
4770 switch (hdsp->io_type) {
4771 case Digiface:
4772 hdsp->card_name = "RME Hammerfall DSP + Digiface";
4773 hdsp->ss_in_channels = hdsp->ss_out_channels = DIGIFACE_SS_CHANNELS;
4774 hdsp->ds_in_channels = hdsp->ds_out_channels = DIGIFACE_DS_CHANNELS;
4775 break;
4776
4777 case H9652:
4778 hdsp->card_name = "RME Hammerfall HDSP 9652";
4779 hdsp->ss_in_channels = hdsp->ss_out_channels = H9652_SS_CHANNELS;
4780 hdsp->ds_in_channels = hdsp->ds_out_channels = H9652_DS_CHANNELS;
4781 break;
4782
4783 case H9632:
4784 status = hdsp_read(hdsp, HDSP_statusRegister);
4785 /* HDSP_AEBx bits are low when AEB are connected */
4786 aebi_channels = (status & HDSP_AEBI) ? 0 : 4;
4787 aebo_channels = (status & HDSP_AEBO) ? 0 : 4;
4788 hdsp->card_name = "RME Hammerfall HDSP 9632";
4789 hdsp->ss_in_channels = H9632_SS_CHANNELS+aebi_channels;
4790 hdsp->ds_in_channels = H9632_DS_CHANNELS+aebi_channels;
4791 hdsp->qs_in_channels = H9632_QS_CHANNELS+aebi_channels;
4792 hdsp->ss_out_channels = H9632_SS_CHANNELS+aebo_channels;
4793 hdsp->ds_out_channels = H9632_DS_CHANNELS+aebo_channels;
4794 hdsp->qs_out_channels = H9632_QS_CHANNELS+aebo_channels;
4795 break;
4796
4797 case Multiface:
4798 hdsp->card_name = "RME Hammerfall DSP + Multiface";
4799 hdsp->ss_in_channels = hdsp->ss_out_channels = MULTIFACE_SS_CHANNELS;
4800 hdsp->ds_in_channels = hdsp->ds_out_channels = MULTIFACE_DS_CHANNELS;
4801 break;
4802
4803 default:
4804 /* should never get here */
4805 break;
4806 }
4807 }
4808
4809 static void snd_hdsp_initialize_midi_flush (hdsp_t *hdsp)
4810 {
4811 snd_hdsp_flush_midi_input (hdsp, 0);
4812 snd_hdsp_flush_midi_input (hdsp, 1);
4813 }
4814
4815 static int snd_hdsp_create_alsa_devices(snd_card_t *card, hdsp_t *hdsp)
4816 {
4817 int err;
4818
4819 if ((err = snd_hdsp_create_pcm(card, hdsp)) < 0) {
4820 snd_printk("Hammerfall-DSP: Error creating pcm interface\n");
4821 return err;
4822 }
4823
4824
4825 if ((err = snd_hdsp_create_midi(card, hdsp, 0)) < 0) {
4826 snd_printk("Hammerfall-DSP: Error creating first midi interface\n");
4827 return err;
4828 }
4829
4830 if (hdsp->io_type == Digiface || hdsp->io_type == H9652) {
4831 if ((err = snd_hdsp_create_midi(card, hdsp, 1)) < 0) {
4832 snd_printk("Hammerfall-DSP: Error creating second midi interface\n");
4833 return err;
4834 }
4835 }
4836
4837 if ((err = snd_hdsp_create_controls(card, hdsp)) < 0) {
4838 snd_printk("Hammerfall-DSP: Error creating ctl interface\n");
4839 return err;
4840 }
4841
4842 snd_hdsp_proc_init(hdsp);
4843
4844 hdsp->system_sample_rate = -1;
4845 hdsp->playback_pid = -1;
4846 hdsp->capture_pid = -1;
4847 hdsp->capture_substream = NULL;
4848 hdsp->playback_substream = NULL;
4849
4850 if ((err = snd_hdsp_set_defaults(hdsp)) < 0) {
4851 snd_printk("Hammerfall-DSP: Error setting default values\n");
4852 return err;
4853 }
4854
4855 if (!(hdsp->state & HDSP_InitializationComplete)) {
4856 sprintf(card->longname, "%s at 0x%lx, irq %d", hdsp->card_name,
4857 hdsp->port, hdsp->irq);
4858
4859 if ((err = snd_card_register(card)) < 0) {
4860 snd_printk("Hammerfall-DSP: error registering card\n");
4861 return err;
4862 }
4863 hdsp->state |= HDSP_InitializationComplete;
4864 }
4865
4866 return 0;
4867 }
4868
4869 #ifdef HDSP_FW_LOADER
4870 /* load firmware via hotplug fw loader */
4871 static int __devinit hdsp_request_fw_loader(hdsp_t *hdsp)
4872 {
4873 const char *fwfile;
4874 const struct firmware *fw;
4875 int err;
4876
4877 if (hdsp->io_type == H9652 || hdsp->io_type == H9632)
4878 return 0;
4879 if (hdsp->io_type == Undefined) {
4880 if ((err = hdsp_get_iobox_version(hdsp)) < 0)
4881 return err;
4882 if (hdsp->io_type == H9652 || hdsp->io_type == H9632)
4883 return 0;
4884 }
4885
4886 /* caution: max length of firmware filename is 30! */
4887 switch (hdsp->io_type) {
4888 case Multiface:
4889 if (hdsp->firmware_rev == 0xa)
4890 fwfile = "multiface_firmware.bin";
4891 else
4892 fwfile = "multiface_firmware_rev11.bin";
4893 break;
4894 case Digiface:
4895 if (hdsp->firmware_rev == 0xa)
4896 fwfile = "digiface_firmware.bin";
4897 else
4898 fwfile = "digiface_firmware_rev11.bin";
4899 break;
4900 default:
4901 snd_printk(KERN_ERR "Hammerfall-DSP: invalid io_type %d\n", hdsp->io_type);
4902 return -EINVAL;
4903 }
4904
4905 if (request_firmware(&fw, fwfile, &hdsp->pci->dev)) {
4906 snd_printk(KERN_ERR "Hammerfall-DSP: cannot load firmware %s\n", fwfile);
4907 return -ENOENT;
4908 }
4909 if (fw->size < sizeof(hdsp->firmware_cache)) {
4910 snd_printk(KERN_ERR "Hammerfall-DSP: too short firmware size %d (expected %d)\n",
4911 (int)fw->size, (int)sizeof(hdsp->firmware_cache));
4912 release_firmware(fw);
4913 return -EINVAL;
4914 }
4915 #ifdef SNDRV_BIG_ENDIAN
4916 {
4917 int i;
4918 u32 *src = (u32*)fw->data;
4919 for (i = 0; i < ARRAY_SIZE(hdsp->firmware_cache); i++, src++)
4920 hdsp->firmware_cache[i] = ((*src & 0x000000ff) << 16) |
4921 ((*src & 0x0000ff00) << 8) |
4922 ((*src & 0x00ff0000) >> 8) |
4923 ((*src & 0xff000000) >> 16);
4924 }
4925 #else
4926 memcpy(hdsp->firmware_cache, fw->data, sizeof(hdsp->firmware_cache));
4927 #endif
4928 release_firmware(fw);
4929
4930 hdsp->state |= HDSP_FirmwareCached;
4931
4932 if ((err = snd_hdsp_load_firmware_from_cache(hdsp)) < 0)
4933 return err;
4934
4935 if (!(hdsp->state & HDSP_InitializationComplete)) {
4936 if ((err = snd_hdsp_enable_io(hdsp)) < 0) {
4937 return err;
4938 }
4939
4940 if ((err = snd_hdsp_create_hwdep(hdsp->card, hdsp)) < 0) {
4941 snd_printk("Hammerfall-DSP: error creating hwdep device\n");
4942 return err;
4943 }
4944 snd_hdsp_initialize_channels(hdsp);
4945 snd_hdsp_initialize_midi_flush(hdsp);
4946 if ((err = snd_hdsp_create_alsa_devices(hdsp->card, hdsp)) < 0) {
4947 snd_printk("Hammerfall-DSP: error creating alsa devices\n");
4948 return err;
4949 }
4950 }
4951 return 0;
4952 }
4953 #endif
4954
4955 static int __devinit snd_hdsp_create(snd_card_t *card,
4956 hdsp_t *hdsp)
4957 {
4958 struct pci_dev *pci = hdsp->pci;
4959 int err;
4960 int is_9652 = 0;
4961 int is_9632 = 0;
4962
4963 hdsp->irq = -1;
4964 hdsp->state = 0;
4965 hdsp->midi[0].rmidi = NULL;
4966 hdsp->midi[1].rmidi = NULL;
4967 hdsp->midi[0].input = NULL;
4968 hdsp->midi[1].input = NULL;
4969 hdsp->midi[0].output = NULL;
4970 hdsp->midi[1].output = NULL;
4971 hdsp->midi[0].pending = 0;
4972 hdsp->midi[1].pending = 0;
4973 spin_lock_init(&hdsp->midi[0].lock);
4974 spin_lock_init(&hdsp->midi[1].lock);
4975 hdsp->iobase = NULL;
4976 hdsp->control_register = 0;
4977 hdsp->control2_register = 0;
4978 hdsp->io_type = Undefined;
4979 hdsp->max_channels = 26;
4980
4981 hdsp->card = card;
4982
4983 spin_lock_init(&hdsp->lock);
4984
4985 tasklet_init(&hdsp->midi_tasklet, hdsp_midi_tasklet, (unsigned long)hdsp);
4986
4987 pci_read_config_word(hdsp->pci, PCI_CLASS_REVISION, &hdsp->firmware_rev);
4988 hdsp->firmware_rev &= 0xff;
4989
4990 /* From Martin Bjoernsen :
4991 "It is important that the card's latency timer register in
4992 the PCI configuration space is set to a value much larger
4993 than 0 by the computer's BIOS or the driver.
4994 The windows driver always sets this 8 bit register [...]
4995 to its maximum 255 to avoid problems with some computers."
4996 */
4997 pci_write_config_byte(hdsp->pci, PCI_LATENCY_TIMER, 0xFF);
4998
4999 strcpy(card->driver, "H-DSP");
5000 strcpy(card->mixername, "Xilinx FPGA");
5001
5002 if (hdsp->firmware_rev < 0xa) {
5003 return -ENODEV;
5004 } else if (hdsp->firmware_rev < 0x64) {
5005 hdsp->card_name = "RME Hammerfall DSP";
5006 } else if (hdsp->firmware_rev < 0x96) {
5007 hdsp->card_name = "RME HDSP 9652";
5008 is_9652 = 1;
5009 } else {
5010 hdsp->card_name = "RME HDSP 9632";
5011 hdsp->max_channels = 16;
5012 is_9632 = 1;
5013 }
5014
5015 if ((err = pci_enable_device(pci)) < 0) {
5016 return err;
5017 }
5018
5019 pci_set_master(hdsp->pci);
5020
5021 if ((err = pci_request_regions(pci, "hdsp")) < 0)
5022 return err;
5023 hdsp->port = pci_resource_start(pci, 0);
5024 if ((hdsp->iobase = ioremap_nocache(hdsp->port, HDSP_IO_EXTENT)) == NULL) {
5025 snd_printk("Hammerfall-DSP: unable to remap region 0x%lx-0x%lx\n", hdsp->port, hdsp->port + HDSP_IO_EXTENT - 1);
5026 return -EBUSY;
5027 }
5028
5029 if (request_irq(pci->irq, snd_hdsp_interrupt, SA_INTERRUPT|SA_SHIRQ, "hdsp", (void *)hdsp)) {
5030 snd_printk("Hammerfall-DSP: unable to use IRQ %d\n", pci->irq);
5031 return -EBUSY;
5032 }
5033
5034 hdsp->irq = pci->irq;
5035 hdsp->precise_ptr = 1;
5036 hdsp->use_midi_tasklet = 1;
5037
5038 if ((err = snd_hdsp_initialize_memory(hdsp)) < 0) {
5039 return err;
5040 }
5041
5042 if (!is_9652 && !is_9632) {
5043 /* we wait 2 seconds to let freshly inserted cardbus cards do their hardware init */
5044 if ((1000 / HZ) < 2000) {
5045 set_current_state(TASK_UNINTERRUPTIBLE);
5046 schedule_timeout((2000 * HZ + 999) / 1000);
5047 } else {
5048 mdelay(2000);
5049 }
5050
5051 if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
5052 #ifdef HDSP_FW_LOADER
5053 if ((err = hdsp_request_fw_loader(hdsp)) < 0) {
5054 /* we don't fail as this can happen
5055 if userspace is not ready for
5056 firmware upload
5057 */
5058 snd_printk("Hammerfall-DSP: couldn't get firmware from userspace. try using hdsploader\n");
5059 } else {
5060 /* init is complete, we return */
5061 return 0;
5062 }
5063 #endif
5064 /* no iobox connected, we defer initialization */
5065 snd_printk("Hammerfall-DSP: card initialization pending : waiting for firmware\n");
5066 if ((err = snd_hdsp_create_hwdep(card, hdsp)) < 0) {
5067 return err;
5068 }
5069 return 0;
5070 } else {
5071 snd_printk("Hammerfall-DSP: Firmware already present, initializing card.\n");
5072 if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version1) {
5073 hdsp->io_type = Multiface;
5074 } else {
5075 hdsp->io_type = Digiface;
5076 }
5077 }
5078 }
5079
5080 if ((err = snd_hdsp_enable_io(hdsp)) != 0) {
5081 return err;
5082 }
5083
5084 if (is_9652) {
5085 hdsp->io_type = H9652;
5086 }
5087
5088 if (is_9632) {
5089 hdsp->io_type = H9632;
5090 }
5091
5092 if ((err = snd_hdsp_create_hwdep(card, hdsp)) < 0) {
5093 return err;
5094 }
5095
5096 snd_hdsp_initialize_channels(hdsp);
5097 snd_hdsp_initialize_midi_flush(hdsp);
5098
5099 hdsp->state |= HDSP_FirmwareLoaded;
5100
5101 if ((err = snd_hdsp_create_alsa_devices(card, hdsp)) < 0) {
5102 return err;
5103 }
5104
5105 return 0;
5106 }
5107
5108 static int snd_hdsp_free(hdsp_t *hdsp)
5109 {
5110 if (hdsp->port) {
5111 /* stop the audio, and cancel all interrupts */
5112 tasklet_kill(&hdsp->midi_tasklet);
5113 hdsp->control_register &= ~(HDSP_Start|HDSP_AudioInterruptEnable|HDSP_Midi0InterruptEnable|HDSP_Midi1InterruptEnable);
5114 hdsp_write (hdsp, HDSP_controlRegister, hdsp->control_register);
5115 }
5116
5117 if (hdsp->irq >= 0)
5118 free_irq(hdsp->irq, (void *)hdsp);
5119
5120 snd_hdsp_free_buffers(hdsp);
5121
5122 if (hdsp->iobase)
5123 iounmap(hdsp->iobase);
5124
5125 if (hdsp->port)
5126 pci_release_regions(hdsp->pci);
5127
5128 pci_disable_device(hdsp->pci);
5129 return 0;
5130 }
5131
5132 static void snd_hdsp_card_free(snd_card_t *card)
5133 {
5134 hdsp_t *hdsp = (hdsp_t *) card->private_data;
5135
5136 if (hdsp)
5137 snd_hdsp_free(hdsp);
5138 }
5139
5140 static int __devinit snd_hdsp_probe(struct pci_dev *pci,
5141 const struct pci_device_id *pci_id)
5142 {
5143 static int dev;
5144 hdsp_t *hdsp;
5145 snd_card_t *card;
5146 int err;
5147
5148 if (dev >= SNDRV_CARDS)
5149 return -ENODEV;
5150 if (!enable[dev]) {
5151 dev++;
5152 return -ENOENT;
5153 }
5154
5155 if (!(card = snd_card_new(index[dev], id[dev], THIS_MODULE, sizeof(hdsp_t))))
5156 return -ENOMEM;
5157
5158 hdsp = (hdsp_t *) card->private_data;
5159 card->private_free = snd_hdsp_card_free;
5160 hdsp->dev = dev;
5161 hdsp->pci = pci;
5162 snd_card_set_dev(card, &pci->dev);
5163
5164 if ((err = snd_hdsp_create(card, hdsp)) < 0) {
5165 snd_card_free(card);
5166 return err;
5167 }
5168
5169 strcpy(card->shortname, "Hammerfall DSP");
5170 sprintf(card->longname, "%s at 0x%lx, irq %d", hdsp->card_name,
5171 hdsp->port, hdsp->irq);
5172
5173 if ((err = snd_card_register(card)) < 0) {
5174 snd_card_free(card);
5175 return err;
5176 }
5177 pci_set_drvdata(pci, card);
5178 dev++;
5179 return 0;
5180 }
5181
5182 static void __devexit snd_hdsp_remove(struct pci_dev *pci)
5183 {
5184 snd_card_free(pci_get_drvdata(pci));
5185 pci_set_drvdata(pci, NULL);
5186 }
5187
5188 static struct pci_driver driver = {
5189 .name = "RME Hammerfall DSP",
5190 .id_table = snd_hdsp_ids,
5191 .probe = snd_hdsp_probe,
5192 .remove = __devexit_p(snd_hdsp_remove),
5193 };
5194
5195 static int __init alsa_card_hdsp_init(void)
5196 {
5197 return pci_module_init(&driver);
5198 }
5199
5200 static void __exit alsa_card_hdsp_exit(void)
5201 {
5202 pci_unregister_driver(&driver);
5203 }
5204
5205 module_init(alsa_card_hdsp_init)
5206 module_exit(alsa_card_hdsp_exit)
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