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[TG3]: Set minimal hw interrupt mitigation.
[linux-2.6/verdex.git] / sound / pci / ymfpci / ymfpci_main.c
blob05f1629760bc7cc38ca1bd71daa6c1e42979b7d3
1 /*
2 * Copyright (c) by Jaroslav Kysela <perex@suse.cz>
3 * Routines for control of YMF724/740/744/754 chips
4 *
5 * BUGS:
6 * --
7 *
8 * TODO:
9 * --
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 *
25 */
26
27 #include <sound/driver.h>
28 #include <linux/delay.h>
29 #include <linux/init.h>
30 #include <linux/interrupt.h>
31 #include <linux/pci.h>
32 #include <linux/sched.h>
33 #include <linux/slab.h>
34 #include <linux/vmalloc.h>
35
36 #include <sound/core.h>
37 #include <sound/control.h>
38 #include <sound/info.h>
39 #include <sound/ymfpci.h>
40 #include <sound/asoundef.h>
41 #include <sound/mpu401.h>
42
43 #include <asm/io.h>
44
45 /*
46 * constants
47 */
48
49 /*
50 * common I/O routines
51 */
52
53 static void snd_ymfpci_irq_wait(ymfpci_t *chip);
54
55 static inline u8 snd_ymfpci_readb(ymfpci_t *chip, u32 offset)
56 {
57 return readb(chip->reg_area_virt + offset);
58 }
59
60 static inline void snd_ymfpci_writeb(ymfpci_t *chip, u32 offset, u8 val)
61 {
62 writeb(val, chip->reg_area_virt + offset);
63 }
64
65 static inline u16 snd_ymfpci_readw(ymfpci_t *chip, u32 offset)
66 {
67 return readw(chip->reg_area_virt + offset);
68 }
69
70 static inline void snd_ymfpci_writew(ymfpci_t *chip, u32 offset, u16 val)
71 {
72 writew(val, chip->reg_area_virt + offset);
73 }
74
75 static inline u32 snd_ymfpci_readl(ymfpci_t *chip, u32 offset)
76 {
77 return readl(chip->reg_area_virt + offset);
78 }
79
80 static inline void snd_ymfpci_writel(ymfpci_t *chip, u32 offset, u32 val)
81 {
82 writel(val, chip->reg_area_virt + offset);
83 }
84
85 static int snd_ymfpci_codec_ready(ymfpci_t *chip, int secondary)
86 {
87 signed long end_time;
88 u32 reg = secondary ? YDSXGR_SECSTATUSADR : YDSXGR_PRISTATUSADR;
89
90 end_time = (jiffies + ((3 * HZ) / 4)) + 1;
91 do {
92 if ((snd_ymfpci_readw(chip, reg) & 0x8000) == 0)
93 return 0;
94 set_current_state(TASK_UNINTERRUPTIBLE);
95 schedule_timeout(1);
96 } while (end_time - (signed long)jiffies >= 0);
97 snd_printk("codec_ready: codec %i is not ready [0x%x]\n", secondary, snd_ymfpci_readw(chip, reg));
98 return -EBUSY;
99 }
100
101 static void snd_ymfpci_codec_write(ac97_t *ac97, u16 reg, u16 val)
102 {
103 ymfpci_t *chip = ac97->private_data;
104 u32 cmd;
105
106 snd_ymfpci_codec_ready(chip, 0);
107 cmd = ((YDSXG_AC97WRITECMD | reg) << 16) | val;
108 snd_ymfpci_writel(chip, YDSXGR_AC97CMDDATA, cmd);
109 }
110
111 static u16 snd_ymfpci_codec_read(ac97_t *ac97, u16 reg)
112 {
113 ymfpci_t *chip = ac97->private_data;
114
115 if (snd_ymfpci_codec_ready(chip, 0))
116 return ~0;
117 snd_ymfpci_writew(chip, YDSXGR_AC97CMDADR, YDSXG_AC97READCMD | reg);
118 if (snd_ymfpci_codec_ready(chip, 0))
119 return ~0;
120 if (chip->device_id == PCI_DEVICE_ID_YAMAHA_744 && chip->rev < 2) {
121 int i;
122 for (i = 0; i < 600; i++)
123 snd_ymfpci_readw(chip, YDSXGR_PRISTATUSDATA);
124 }
125 return snd_ymfpci_readw(chip, YDSXGR_PRISTATUSDATA);
126 }
127
128 /*
129 * Misc routines
130 */
131
132 static u32 snd_ymfpci_calc_delta(u32 rate)
133 {
134 switch (rate) {
135 case 8000: return 0x02aaab00;
136 case 11025: return 0x03accd00;
137 case 16000: return 0x05555500;
138 case 22050: return 0x07599a00;
139 case 32000: return 0x0aaaab00;
140 case 44100: return 0x0eb33300;
141 default: return ((rate << 16) / 375) << 5;
142 }
143 }
144
145 static u32 def_rate[8] = {
146 100, 2000, 8000, 11025, 16000, 22050, 32000, 48000
147 };
148
149 static u32 snd_ymfpci_calc_lpfK(u32 rate)
150 {
151 u32 i;
152 static u32 val[8] = {
153 0x00570000, 0x06AA0000, 0x18B20000, 0x20930000,
154 0x2B9A0000, 0x35A10000, 0x3EAA0000, 0x40000000
155 };
156
157 if (rate == 44100)
158 return 0x40000000; /* FIXME: What's the right value? */
159 for (i = 0; i < 8; i++)
160 if (rate <= def_rate[i])
161 return val[i];
162 return val[0];
163 }
164
165 static u32 snd_ymfpci_calc_lpfQ(u32 rate)
166 {
167 u32 i;
168 static u32 val[8] = {
169 0x35280000, 0x34A70000, 0x32020000, 0x31770000,
170 0x31390000, 0x31C90000, 0x33D00000, 0x40000000
171 };
172
173 if (rate == 44100)
174 return 0x370A0000;
175 for (i = 0; i < 8; i++)
176 if (rate <= def_rate[i])
177 return val[i];
178 return val[0];
179 }
180
181 /*
182 * Hardware start management
183 */
184
185 static void snd_ymfpci_hw_start(ymfpci_t *chip)
186 {
187 unsigned long flags;
188
189 spin_lock_irqsave(&chip->reg_lock, flags);
190 if (chip->start_count++ > 0)
191 goto __end;
192 snd_ymfpci_writel(chip, YDSXGR_MODE,
193 snd_ymfpci_readl(chip, YDSXGR_MODE) | 3);
194 chip->active_bank = snd_ymfpci_readl(chip, YDSXGR_CTRLSELECT) & 1;
195 __end:
196 spin_unlock_irqrestore(&chip->reg_lock, flags);
197 }
198
199 static void snd_ymfpci_hw_stop(ymfpci_t *chip)
200 {
201 unsigned long flags;
202 long timeout = 1000;
203
204 spin_lock_irqsave(&chip->reg_lock, flags);
205 if (--chip->start_count > 0)
206 goto __end;
207 snd_ymfpci_writel(chip, YDSXGR_MODE,
208 snd_ymfpci_readl(chip, YDSXGR_MODE) & ~3);
209 while (timeout-- > 0) {
210 if ((snd_ymfpci_readl(chip, YDSXGR_STATUS) & 2) == 0)
211 break;
212 }
213 if (atomic_read(&chip->interrupt_sleep_count)) {
214 atomic_set(&chip->interrupt_sleep_count, 0);
215 wake_up(&chip->interrupt_sleep);
216 }
217 __end:
218 spin_unlock_irqrestore(&chip->reg_lock, flags);
219 }
220
221 /*
222 * Playback voice management
223 */
224
225 static int voice_alloc(ymfpci_t *chip, ymfpci_voice_type_t type, int pair, ymfpci_voice_t **rvoice)
226 {
227 ymfpci_voice_t *voice, *voice2;
228 int idx;
229
230 *rvoice = NULL;
231 for (idx = 0; idx < YDSXG_PLAYBACK_VOICES; idx += pair ? 2 : 1) {
232 voice = &chip->voices[idx];
233 voice2 = pair ? &chip->voices[idx+1] : NULL;
234 if (voice->use || (voice2 && voice2->use))
235 continue;
236 voice->use = 1;
237 if (voice2)
238 voice2->use = 1;
239 switch (type) {
240 case YMFPCI_PCM:
241 voice->pcm = 1;
242 if (voice2)
243 voice2->pcm = 1;
244 break;
245 case YMFPCI_SYNTH:
246 voice->synth = 1;
247 break;
248 case YMFPCI_MIDI:
249 voice->midi = 1;
250 break;
251 }
252 snd_ymfpci_hw_start(chip);
253 if (voice2)
254 snd_ymfpci_hw_start(chip);
255 *rvoice = voice;
256 return 0;
257 }
258 return -ENOMEM;
259 }
260
261 static int snd_ymfpci_voice_alloc(ymfpci_t *chip, ymfpci_voice_type_t type, int pair, ymfpci_voice_t **rvoice)
262 {
263 unsigned long flags;
264 int result;
265
266 snd_assert(rvoice != NULL, return -EINVAL);
267 snd_assert(!pair || type == YMFPCI_PCM, return -EINVAL);
268
269 spin_lock_irqsave(&chip->voice_lock, flags);
270 for (;;) {
271 result = voice_alloc(chip, type, pair, rvoice);
272 if (result == 0 || type != YMFPCI_PCM)
273 break;
274 /* TODO: synth/midi voice deallocation */
275 break;
276 }
277 spin_unlock_irqrestore(&chip->voice_lock, flags);
278 return result;
279 }
280
281 static int snd_ymfpci_voice_free(ymfpci_t *chip, ymfpci_voice_t *pvoice)
282 {
283 unsigned long flags;
284
285 snd_assert(pvoice != NULL, return -EINVAL);
286 snd_ymfpci_hw_stop(chip);
287 spin_lock_irqsave(&chip->voice_lock, flags);
288 pvoice->use = pvoice->pcm = pvoice->synth = pvoice->midi = 0;
289 pvoice->ypcm = NULL;
290 pvoice->interrupt = NULL;
291 spin_unlock_irqrestore(&chip->voice_lock, flags);
292 return 0;
293 }
294
295 /*
296 * PCM part
297 */
298
299 static void snd_ymfpci_pcm_interrupt(ymfpci_t *chip, ymfpci_voice_t *voice)
300 {
301 ymfpci_pcm_t *ypcm;
302 u32 pos, delta;
303
304 if ((ypcm = voice->ypcm) == NULL)
305 return;
306 if (ypcm->substream == NULL)
307 return;
308 spin_lock(&chip->reg_lock);
309 if (ypcm->running) {
310 pos = le32_to_cpu(voice->bank[chip->active_bank].start);
311 if (pos < ypcm->last_pos)
312 delta = pos + (ypcm->buffer_size - ypcm->last_pos);
313 else
314 delta = pos - ypcm->last_pos;
315 ypcm->period_pos += delta;
316 ypcm->last_pos = pos;
317 if (ypcm->period_pos >= ypcm->period_size) {
318 // printk("done - active_bank = 0x%x, start = 0x%x\n", chip->active_bank, voice->bank[chip->active_bank].start);
319 ypcm->period_pos %= ypcm->period_size;
320 spin_unlock(&chip->reg_lock);
321 snd_pcm_period_elapsed(ypcm->substream);
322 spin_lock(&chip->reg_lock);
323 }
324 }
325 spin_unlock(&chip->reg_lock);
326 }
327
328 static void snd_ymfpci_pcm_capture_interrupt(snd_pcm_substream_t *substream)
329 {
330 snd_pcm_runtime_t *runtime = substream->runtime;
331 ymfpci_pcm_t *ypcm = runtime->private_data;
332 ymfpci_t *chip = ypcm->chip;
333 u32 pos, delta;
334
335 spin_lock(&chip->reg_lock);
336 if (ypcm->running) {
337 pos = le32_to_cpu(chip->bank_capture[ypcm->capture_bank_number][chip->active_bank]->start) >> ypcm->shift;
338 if (pos < ypcm->last_pos)
339 delta = pos + (ypcm->buffer_size - ypcm->last_pos);
340 else
341 delta = pos - ypcm->last_pos;
342 ypcm->period_pos += delta;
343 ypcm->last_pos = pos;
344 if (ypcm->period_pos >= ypcm->period_size) {
345 ypcm->period_pos %= ypcm->period_size;
346 // printk("done - active_bank = 0x%x, start = 0x%x\n", chip->active_bank, voice->bank[chip->active_bank].start);
347 spin_unlock(&chip->reg_lock);
348 snd_pcm_period_elapsed(substream);
349 spin_lock(&chip->reg_lock);
350 }
351 }
352 spin_unlock(&chip->reg_lock);
353 }
354
355 static int snd_ymfpci_playback_trigger(snd_pcm_substream_t * substream,
356 int cmd)
357 {
358 ymfpci_t *chip = snd_pcm_substream_chip(substream);
359 ymfpci_pcm_t *ypcm = substream->runtime->private_data;
360 int result = 0;
361
362 spin_lock(&chip->reg_lock);
363 if (ypcm->voices[0] == NULL) {
364 result = -EINVAL;
365 goto __unlock;
366 }
367 switch (cmd) {
368 case SNDRV_PCM_TRIGGER_START:
369 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
370 case SNDRV_PCM_TRIGGER_RESUME:
371 chip->ctrl_playback[ypcm->voices[0]->number + 1] = cpu_to_le32(ypcm->voices[0]->bank_addr);
372 if (ypcm->voices[1] != NULL)
373 chip->ctrl_playback[ypcm->voices[1]->number + 1] = cpu_to_le32(ypcm->voices[1]->bank_addr);
374 ypcm->running = 1;
375 break;
376 case SNDRV_PCM_TRIGGER_STOP:
377 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
378 case SNDRV_PCM_TRIGGER_SUSPEND:
379 chip->ctrl_playback[ypcm->voices[0]->number + 1] = 0;
380 if (ypcm->voices[1] != NULL)
381 chip->ctrl_playback[ypcm->voices[1]->number + 1] = 0;
382 ypcm->running = 0;
383 break;
384 default:
385 result = -EINVAL;
386 break;
387 }
388 __unlock:
389 spin_unlock(&chip->reg_lock);
390 return result;
391 }
392 static int snd_ymfpci_capture_trigger(snd_pcm_substream_t * substream,
393 int cmd)
394 {
395 ymfpci_t *chip = snd_pcm_substream_chip(substream);
396 ymfpci_pcm_t *ypcm = substream->runtime->private_data;
397 int result = 0;
398 u32 tmp;
399
400 spin_lock(&chip->reg_lock);
401 switch (cmd) {
402 case SNDRV_PCM_TRIGGER_START:
403 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
404 case SNDRV_PCM_TRIGGER_RESUME:
405 tmp = snd_ymfpci_readl(chip, YDSXGR_MAPOFREC) | (1 << ypcm->capture_bank_number);
406 snd_ymfpci_writel(chip, YDSXGR_MAPOFREC, tmp);
407 ypcm->running = 1;
408 break;
409 case SNDRV_PCM_TRIGGER_STOP:
410 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
411 case SNDRV_PCM_TRIGGER_SUSPEND:
412 tmp = snd_ymfpci_readl(chip, YDSXGR_MAPOFREC) & ~(1 << ypcm->capture_bank_number);
413 snd_ymfpci_writel(chip, YDSXGR_MAPOFREC, tmp);
414 ypcm->running = 0;
415 break;
416 default:
417 result = -EINVAL;
418 break;
419 }
420 spin_unlock(&chip->reg_lock);
421 return result;
422 }
423
424 static int snd_ymfpci_pcm_voice_alloc(ymfpci_pcm_t *ypcm, int voices)
425 {
426 int err;
427
428 if (ypcm->voices[1] != NULL && voices < 2) {
429 snd_ymfpci_voice_free(ypcm->chip, ypcm->voices[1]);
430 ypcm->voices[1] = NULL;
431 }
432 if (voices == 1 && ypcm->voices[0] != NULL)
433 return 0; /* already allocated */
434 if (voices == 2 && ypcm->voices[0] != NULL && ypcm->voices[1] != NULL)
435 return 0; /* already allocated */
436 if (voices > 1) {
437 if (ypcm->voices[0] != NULL && ypcm->voices[1] == NULL) {
438 snd_ymfpci_voice_free(ypcm->chip, ypcm->voices[0]);
439 ypcm->voices[0] = NULL;
440 }
441 }
442 err = snd_ymfpci_voice_alloc(ypcm->chip, YMFPCI_PCM, voices > 1, &ypcm->voices[0]);
443 if (err < 0)
444 return err;
445 ypcm->voices[0]->ypcm = ypcm;
446 ypcm->voices[0]->interrupt = snd_ymfpci_pcm_interrupt;
447 if (voices > 1) {
448 ypcm->voices[1] = &ypcm->chip->voices[ypcm->voices[0]->number + 1];
449 ypcm->voices[1]->ypcm = ypcm;
450 }
451 return 0;
452 }
453
454 static void snd_ymfpci_pcm_init_voice(ymfpci_voice_t *voice, int stereo,
455 int rate, int w_16, unsigned long addr,
456 unsigned int end,
457 int output_front, int output_rear)
458 {
459 u32 format;
460 u32 delta = snd_ymfpci_calc_delta(rate);
461 u32 lpfQ = snd_ymfpci_calc_lpfQ(rate);
462 u32 lpfK = snd_ymfpci_calc_lpfK(rate);
463 snd_ymfpci_playback_bank_t *bank;
464 unsigned int nbank;
465
466 snd_assert(voice != NULL, return);
467 format = (stereo ? 0x00010000 : 0) | (w_16 ? 0 : 0x80000000);
468 for (nbank = 0; nbank < 2; nbank++) {
469 bank = &voice->bank[nbank];
470 bank->format = cpu_to_le32(format);
471 bank->loop_default = 0;
472 bank->base = cpu_to_le32(addr);
473 bank->loop_start = 0;
474 bank->loop_end = cpu_to_le32(end);
475 bank->loop_frac = 0;
476 bank->eg_gain_end = cpu_to_le32(0x40000000);
477 bank->lpfQ = cpu_to_le32(lpfQ);
478 bank->status = 0;
479 bank->num_of_frames = 0;
480 bank->loop_count = 0;
481 bank->start = 0;
482 bank->start_frac = 0;
483 bank->delta =
484 bank->delta_end = cpu_to_le32(delta);
485 bank->lpfK =
486 bank->lpfK_end = cpu_to_le32(lpfK);
487 bank->eg_gain = cpu_to_le32(0x40000000);
488 bank->lpfD1 =
489 bank->lpfD2 = 0;
490
491 bank->left_gain =
492 bank->right_gain =
493 bank->left_gain_end =
494 bank->right_gain_end =
495 bank->eff1_gain =
496 bank->eff2_gain =
497 bank->eff3_gain =
498 bank->eff1_gain_end =
499 bank->eff2_gain_end =
500 bank->eff3_gain_end = 0;
501
502 if (!stereo) {
503 if (output_front) {
504 bank->left_gain =
505 bank->right_gain =
506 bank->left_gain_end =
507 bank->right_gain_end = cpu_to_le32(0x40000000);
508 }
509 if (output_rear) {
510 bank->eff2_gain =
511 bank->eff2_gain_end =
512 bank->eff3_gain =
513 bank->eff3_gain_end = cpu_to_le32(0x40000000);
514 }
515 } else {
516 if (output_front) {
517 if ((voice->number & 1) == 0) {
518 bank->left_gain =
519 bank->left_gain_end = cpu_to_le32(0x40000000);
520 } else {
521 bank->format |= cpu_to_le32(1);
522 bank->right_gain =
523 bank->right_gain_end = cpu_to_le32(0x40000000);
524 }
525 }
526 if (output_rear) {
527 if ((voice->number & 1) == 0) {
528 bank->eff3_gain =
529 bank->eff3_gain_end = cpu_to_le32(0x40000000);
530 } else {
531 bank->format |= cpu_to_le32(1);
532 bank->eff2_gain =
533 bank->eff2_gain_end = cpu_to_le32(0x40000000);
534 }
535 }
536 }
537 }
538 }
539
540 static int __devinit snd_ymfpci_ac3_init(ymfpci_t *chip)
541 {
542 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci),
543 4096, &chip->ac3_tmp_base) < 0)
544 return -ENOMEM;
545
546 chip->bank_effect[3][0]->base =
547 chip->bank_effect[3][1]->base = cpu_to_le32(chip->ac3_tmp_base.addr);
548 chip->bank_effect[3][0]->loop_end =
549 chip->bank_effect[3][1]->loop_end = cpu_to_le32(1024);
550 chip->bank_effect[4][0]->base =
551 chip->bank_effect[4][1]->base = cpu_to_le32(chip->ac3_tmp_base.addr + 2048);
552 chip->bank_effect[4][0]->loop_end =
553 chip->bank_effect[4][1]->loop_end = cpu_to_le32(1024);
554
555 spin_lock_irq(&chip->reg_lock);
556 snd_ymfpci_writel(chip, YDSXGR_MAPOFEFFECT,
557 snd_ymfpci_readl(chip, YDSXGR_MAPOFEFFECT) | 3 << 3);
558 spin_unlock_irq(&chip->reg_lock);
559 return 0;
560 }
561
562 static int snd_ymfpci_ac3_done(ymfpci_t *chip)
563 {
564 spin_lock_irq(&chip->reg_lock);
565 snd_ymfpci_writel(chip, YDSXGR_MAPOFEFFECT,
566 snd_ymfpci_readl(chip, YDSXGR_MAPOFEFFECT) & ~(3 << 3));
567 spin_unlock_irq(&chip->reg_lock);
568 // snd_ymfpci_irq_wait(chip);
569 if (chip->ac3_tmp_base.area) {
570 snd_dma_free_pages(&chip->ac3_tmp_base);
571 chip->ac3_tmp_base.area = NULL;
572 }
573 return 0;
574 }
575
576 static int snd_ymfpci_playback_hw_params(snd_pcm_substream_t * substream,
577 snd_pcm_hw_params_t * hw_params)
578 {
579 snd_pcm_runtime_t *runtime = substream->runtime;
580 ymfpci_pcm_t *ypcm = runtime->private_data;
581 int err;
582
583 if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0)
584 return err;
585 if ((err = snd_ymfpci_pcm_voice_alloc(ypcm, params_channels(hw_params))) < 0)
586 return err;
587 return 0;
588 }
589
590 static int snd_ymfpci_playback_hw_free(snd_pcm_substream_t * substream)
591 {
592 ymfpci_t *chip = snd_pcm_substream_chip(substream);
593 snd_pcm_runtime_t *runtime = substream->runtime;
594 ymfpci_pcm_t *ypcm;
595
596 if (runtime->private_data == NULL)
597 return 0;
598 ypcm = runtime->private_data;
599
600 /* wait, until the PCI operations are not finished */
601 snd_ymfpci_irq_wait(chip);
602 snd_pcm_lib_free_pages(substream);
603 if (ypcm->voices[1]) {
604 snd_ymfpci_voice_free(chip, ypcm->voices[1]);
605 ypcm->voices[1] = NULL;
606 }
607 if (ypcm->voices[0]) {
608 snd_ymfpci_voice_free(chip, ypcm->voices[0]);
609 ypcm->voices[0] = NULL;
610 }
611 return 0;
612 }
613
614 static int snd_ymfpci_playback_prepare(snd_pcm_substream_t * substream)
615 {
616 // ymfpci_t *chip = snd_pcm_substream_chip(substream);
617 snd_pcm_runtime_t *runtime = substream->runtime;
618 ymfpci_pcm_t *ypcm = runtime->private_data;
619 unsigned int nvoice;
620
621 ypcm->period_size = runtime->period_size;
622 ypcm->buffer_size = runtime->buffer_size;
623 ypcm->period_pos = 0;
624 ypcm->last_pos = 0;
625 for (nvoice = 0; nvoice < runtime->channels; nvoice++)
626 snd_ymfpci_pcm_init_voice(ypcm->voices[nvoice],
627 runtime->channels == 2,
628 runtime->rate,
629 snd_pcm_format_width(runtime->format) == 16,
630 runtime->dma_addr,
631 ypcm->buffer_size,
632 ypcm->output_front,
633 ypcm->output_rear);
634 return 0;
635 }
636
637 static int snd_ymfpci_capture_hw_params(snd_pcm_substream_t * substream,
638 snd_pcm_hw_params_t * hw_params)
639 {
640 return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
641 }
642
643 static int snd_ymfpci_capture_hw_free(snd_pcm_substream_t * substream)
644 {
645 ymfpci_t *chip = snd_pcm_substream_chip(substream);
646
647 /* wait, until the PCI operations are not finished */
648 snd_ymfpci_irq_wait(chip);
649 return snd_pcm_lib_free_pages(substream);
650 }
651
652 static int snd_ymfpci_capture_prepare(snd_pcm_substream_t * substream)
653 {
654 ymfpci_t *chip = snd_pcm_substream_chip(substream);
655 snd_pcm_runtime_t *runtime = substream->runtime;
656 ymfpci_pcm_t *ypcm = runtime->private_data;
657 snd_ymfpci_capture_bank_t * bank;
658 int nbank;
659 u32 rate, format;
660
661 ypcm->period_size = runtime->period_size;
662 ypcm->buffer_size = runtime->buffer_size;
663 ypcm->period_pos = 0;
664 ypcm->last_pos = 0;
665 ypcm->shift = 0;
666 rate = ((48000 * 4096) / runtime->rate) - 1;
667 format = 0;
668 if (runtime->channels == 2) {
669 format |= 2;
670 ypcm->shift++;
671 }
672 if (snd_pcm_format_width(runtime->format) == 8)
673 format |= 1;
674 else
675 ypcm->shift++;
676 switch (ypcm->capture_bank_number) {
677 case 0:
678 snd_ymfpci_writel(chip, YDSXGR_RECFORMAT, format);
679 snd_ymfpci_writel(chip, YDSXGR_RECSLOTSR, rate);
680 break;
681 case 1:
682 snd_ymfpci_writel(chip, YDSXGR_ADCFORMAT, format);
683 snd_ymfpci_writel(chip, YDSXGR_ADCSLOTSR, rate);
684 break;
685 }
686 for (nbank = 0; nbank < 2; nbank++) {
687 bank = chip->bank_capture[ypcm->capture_bank_number][nbank];
688 bank->base = cpu_to_le32(runtime->dma_addr);
689 bank->loop_end = cpu_to_le32(ypcm->buffer_size << ypcm->shift);
690 bank->start = 0;
691 bank->num_of_loops = 0;
692 }
693 return 0;
694 }
695
696 static snd_pcm_uframes_t snd_ymfpci_playback_pointer(snd_pcm_substream_t * substream)
697 {
698 ymfpci_t *chip = snd_pcm_substream_chip(substream);
699 snd_pcm_runtime_t *runtime = substream->runtime;
700 ymfpci_pcm_t *ypcm = runtime->private_data;
701 ymfpci_voice_t *voice = ypcm->voices[0];
702
703 if (!(ypcm->running && voice))
704 return 0;
705 return le32_to_cpu(voice->bank[chip->active_bank].start);
706 }
707
708 static snd_pcm_uframes_t snd_ymfpci_capture_pointer(snd_pcm_substream_t * substream)
709 {
710 ymfpci_t *chip = snd_pcm_substream_chip(substream);
711 snd_pcm_runtime_t *runtime = substream->runtime;
712 ymfpci_pcm_t *ypcm = runtime->private_data;
713
714 if (!ypcm->running)
715 return 0;
716 return le32_to_cpu(chip->bank_capture[ypcm->capture_bank_number][chip->active_bank]->start) >> ypcm->shift;
717 }
718
719 static void snd_ymfpci_irq_wait(ymfpci_t *chip)
720 {
721 wait_queue_t wait;
722 int loops = 4;
723
724 while (loops-- > 0) {
725 if ((snd_ymfpci_readl(chip, YDSXGR_MODE) & 3) == 0)
726 continue;
727 init_waitqueue_entry(&wait, current);
728 add_wait_queue(&chip->interrupt_sleep, &wait);
729 atomic_inc(&chip->interrupt_sleep_count);
730 set_current_state(TASK_UNINTERRUPTIBLE);
731 schedule_timeout(HZ/20);
732 remove_wait_queue(&chip->interrupt_sleep, &wait);
733 }
734 }
735
736 static irqreturn_t snd_ymfpci_interrupt(int irq, void *dev_id, struct pt_regs *regs)
737 {
738 ymfpci_t *chip = dev_id;
739 u32 status, nvoice, mode;
740 ymfpci_voice_t *voice;
741
742 status = snd_ymfpci_readl(chip, YDSXGR_STATUS);
743 if (status & 0x80000000) {
744 chip->active_bank = snd_ymfpci_readl(chip, YDSXGR_CTRLSELECT) & 1;
745 spin_lock(&chip->voice_lock);
746 for (nvoice = 0; nvoice < YDSXG_PLAYBACK_VOICES; nvoice++) {
747 voice = &chip->voices[nvoice];
748 if (voice->interrupt)
749 voice->interrupt(chip, voice);
750 }
751 for (nvoice = 0; nvoice < YDSXG_CAPTURE_VOICES; nvoice++) {
752 if (chip->capture_substream[nvoice])
753 snd_ymfpci_pcm_capture_interrupt(chip->capture_substream[nvoice]);
754 }
755 #if 0
756 for (nvoice = 0; nvoice < YDSXG_EFFECT_VOICES; nvoice++) {
757 if (chip->effect_substream[nvoice])
758 snd_ymfpci_pcm_effect_interrupt(chip->effect_substream[nvoice]);
759 }
760 #endif
761 spin_unlock(&chip->voice_lock);
762 spin_lock(&chip->reg_lock);
763 snd_ymfpci_writel(chip, YDSXGR_STATUS, 0x80000000);
764 mode = snd_ymfpci_readl(chip, YDSXGR_MODE) | 2;
765 snd_ymfpci_writel(chip, YDSXGR_MODE, mode);
766 spin_unlock(&chip->reg_lock);
767
768 if (atomic_read(&chip->interrupt_sleep_count)) {
769 atomic_set(&chip->interrupt_sleep_count, 0);
770 wake_up(&chip->interrupt_sleep);
771 }
772 }
773
774 status = snd_ymfpci_readw(chip, YDSXGR_INTFLAG);
775 if (status & 1) {
776 if (chip->timer)
777 snd_timer_interrupt(chip->timer, chip->timer->sticks);
778 }
779 snd_ymfpci_writew(chip, YDSXGR_INTFLAG, status);
780
781 if (chip->rawmidi)
782 snd_mpu401_uart_interrupt(irq, chip->rawmidi->private_data, regs);
783 return IRQ_HANDLED;
784 }
785
786 static snd_pcm_hardware_t snd_ymfpci_playback =
787 {
788 .info = (SNDRV_PCM_INFO_MMAP |
789 SNDRV_PCM_INFO_MMAP_VALID |
790 SNDRV_PCM_INFO_INTERLEAVED |
791 SNDRV_PCM_INFO_BLOCK_TRANSFER |
792 SNDRV_PCM_INFO_PAUSE |
793 SNDRV_PCM_INFO_RESUME),
794 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
795 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
796 .rate_min = 8000,
797 .rate_max = 48000,
798 .channels_min = 1,
799 .channels_max = 2,
800 .buffer_bytes_max = 256 * 1024, /* FIXME: enough? */
801 .period_bytes_min = 64,
802 .period_bytes_max = 256 * 1024, /* FIXME: enough? */
803 .periods_min = 3,
804 .periods_max = 1024,
805 .fifo_size = 0,
806 };
807
808 static snd_pcm_hardware_t snd_ymfpci_capture =
809 {
810 .info = (SNDRV_PCM_INFO_MMAP |
811 SNDRV_PCM_INFO_MMAP_VALID |
812 SNDRV_PCM_INFO_INTERLEAVED |
813 SNDRV_PCM_INFO_BLOCK_TRANSFER |
814 SNDRV_PCM_INFO_PAUSE |
815 SNDRV_PCM_INFO_RESUME),
816 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
817 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
818 .rate_min = 8000,
819 .rate_max = 48000,
820 .channels_min = 1,
821 .channels_max = 2,
822 .buffer_bytes_max = 256 * 1024, /* FIXME: enough? */
823 .period_bytes_min = 64,
824 .period_bytes_max = 256 * 1024, /* FIXME: enough? */
825 .periods_min = 3,
826 .periods_max = 1024,
827 .fifo_size = 0,
828 };
829
830 static void snd_ymfpci_pcm_free_substream(snd_pcm_runtime_t *runtime)
831 {
832 ymfpci_pcm_t *ypcm = runtime->private_data;
833
834 kfree(ypcm);
835 }
836
837 static int snd_ymfpci_playback_open_1(snd_pcm_substream_t * substream)
838 {
839 ymfpci_t *chip = snd_pcm_substream_chip(substream);
840 snd_pcm_runtime_t *runtime = substream->runtime;
841 ymfpci_pcm_t *ypcm;
842
843 ypcm = kcalloc(1, sizeof(*ypcm), GFP_KERNEL);
844 if (ypcm == NULL)
845 return -ENOMEM;
846 ypcm->chip = chip;
847 ypcm->type = PLAYBACK_VOICE;
848 ypcm->substream = substream;
849 runtime->hw = snd_ymfpci_playback;
850 runtime->private_data = ypcm;
851 runtime->private_free = snd_ymfpci_pcm_free_substream;
852 /* FIXME? True value is 256/48 = 5.33333 ms */
853 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_PERIOD_TIME, 5333, UINT_MAX);
854 return 0;
855 }
856
857 /* call with spinlock held */
858 static void ymfpci_open_extension(ymfpci_t *chip)
859 {
860 if (! chip->rear_opened) {
861 if (! chip->spdif_opened) /* set AC3 */
862 snd_ymfpci_writel(chip, YDSXGR_MODE,
863 snd_ymfpci_readl(chip, YDSXGR_MODE) | (1 << 30));
864 /* enable second codec (4CHEN) */
865 snd_ymfpci_writew(chip, YDSXGR_SECCONFIG,
866 (snd_ymfpci_readw(chip, YDSXGR_SECCONFIG) & ~0x0330) | 0x0010);
867 }
868 }
869
870 /* call with spinlock held */
871 static void ymfpci_close_extension(ymfpci_t *chip)
872 {
873 if (! chip->rear_opened) {
874 if (! chip->spdif_opened)
875 snd_ymfpci_writel(chip, YDSXGR_MODE,
876 snd_ymfpci_readl(chip, YDSXGR_MODE) & ~(1 << 30));
877 snd_ymfpci_writew(chip, YDSXGR_SECCONFIG,
878 (snd_ymfpci_readw(chip, YDSXGR_SECCONFIG) & ~0x0330) & ~0x0010);
879 }
880 }
881
882 static int snd_ymfpci_playback_open(snd_pcm_substream_t * substream)
883 {
884 ymfpci_t *chip = snd_pcm_substream_chip(substream);
885 snd_pcm_runtime_t *runtime = substream->runtime;
886 ymfpci_pcm_t *ypcm;
887 int err;
888
889 if ((err = snd_ymfpci_playback_open_1(substream)) < 0)
890 return err;
891 ypcm = runtime->private_data;
892 ypcm->output_front = 1;
893 ypcm->output_rear = chip->mode_dup4ch ? 1 : 0;
894 spin_lock_irq(&chip->reg_lock);
895 if (ypcm->output_rear) {
896 ymfpci_open_extension(chip);
897 chip->rear_opened++;
898 }
899 spin_unlock_irq(&chip->reg_lock);
900 return 0;
901 }
902
903 static int snd_ymfpci_playback_spdif_open(snd_pcm_substream_t * substream)
904 {
905 ymfpci_t *chip = snd_pcm_substream_chip(substream);
906 snd_pcm_runtime_t *runtime = substream->runtime;
907 ymfpci_pcm_t *ypcm;
908 int err;
909
910 if ((err = snd_ymfpci_playback_open_1(substream)) < 0)
911 return err;
912 ypcm = runtime->private_data;
913 ypcm->output_front = 0;
914 ypcm->output_rear = 1;
915 spin_lock_irq(&chip->reg_lock);
916 snd_ymfpci_writew(chip, YDSXGR_SPDIFOUTCTRL,
917 snd_ymfpci_readw(chip, YDSXGR_SPDIFOUTCTRL) | 2);
918 ymfpci_open_extension(chip);
919 chip->spdif_pcm_bits = chip->spdif_bits;
920 snd_ymfpci_writew(chip, YDSXGR_SPDIFOUTSTATUS, chip->spdif_pcm_bits);
921 chip->spdif_opened++;
922 spin_unlock_irq(&chip->reg_lock);
923
924 chip->spdif_pcm_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
925 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE |
926 SNDRV_CTL_EVENT_MASK_INFO, &chip->spdif_pcm_ctl->id);
927 return 0;
928 }
929
930 static int snd_ymfpci_playback_4ch_open(snd_pcm_substream_t * substream)
931 {
932 ymfpci_t *chip = snd_pcm_substream_chip(substream);
933 snd_pcm_runtime_t *runtime = substream->runtime;
934 ymfpci_pcm_t *ypcm;
935 int err;
936
937 if ((err = snd_ymfpci_playback_open_1(substream)) < 0)
938 return err;
939 ypcm = runtime->private_data;
940 ypcm->output_front = 0;
941 ypcm->output_rear = 1;
942 spin_lock_irq(&chip->reg_lock);
943 ymfpci_open_extension(chip);
944 chip->rear_opened++;
945 spin_unlock_irq(&chip->reg_lock);
946 return 0;
947 }
948
949 static int snd_ymfpci_capture_open(snd_pcm_substream_t * substream,
950 u32 capture_bank_number)
951 {
952 ymfpci_t *chip = snd_pcm_substream_chip(substream);
953 snd_pcm_runtime_t *runtime = substream->runtime;
954 ymfpci_pcm_t *ypcm;
955
956 ypcm = kcalloc(1, sizeof(*ypcm), GFP_KERNEL);
957 if (ypcm == NULL)
958 return -ENOMEM;
959 ypcm->chip = chip;
960 ypcm->type = capture_bank_number + CAPTURE_REC;
961 ypcm->substream = substream;
962 ypcm->capture_bank_number = capture_bank_number;
963 chip->capture_substream[capture_bank_number] = substream;
964 runtime->hw = snd_ymfpci_capture;
965 /* FIXME? True value is 256/48 = 5.33333 ms */
966 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_PERIOD_TIME, 5333, UINT_MAX);
967 runtime->private_data = ypcm;
968 runtime->private_free = snd_ymfpci_pcm_free_substream;
969 snd_ymfpci_hw_start(chip);
970 return 0;
971 }
972
973 static int snd_ymfpci_capture_rec_open(snd_pcm_substream_t * substream)
974 {
975 return snd_ymfpci_capture_open(substream, 0);
976 }
977
978 static int snd_ymfpci_capture_ac97_open(snd_pcm_substream_t * substream)
979 {
980 return snd_ymfpci_capture_open(substream, 1);
981 }
982
983 static int snd_ymfpci_playback_close_1(snd_pcm_substream_t * substream)
984 {
985 return 0;
986 }
987
988 static int snd_ymfpci_playback_close(snd_pcm_substream_t * substream)
989 {
990 ymfpci_t *chip = snd_pcm_substream_chip(substream);
991 ymfpci_pcm_t *ypcm = substream->runtime->private_data;
992
993 spin_lock_irq(&chip->reg_lock);
994 if (ypcm->output_rear && chip->rear_opened > 0) {
995 chip->rear_opened--;
996 ymfpci_close_extension(chip);
997 }
998 spin_unlock_irq(&chip->reg_lock);
999 return snd_ymfpci_playback_close_1(substream);
1000 }
1001
1002 static int snd_ymfpci_playback_spdif_close(snd_pcm_substream_t * substream)
1003 {
1004 ymfpci_t *chip = snd_pcm_substream_chip(substream);
1005
1006 spin_lock_irq(&chip->reg_lock);
1007 chip->spdif_opened = 0;
1008 ymfpci_close_extension(chip);
1009 snd_ymfpci_writew(chip, YDSXGR_SPDIFOUTCTRL,
1010 snd_ymfpci_readw(chip, YDSXGR_SPDIFOUTCTRL) & ~2);
1011 snd_ymfpci_writew(chip, YDSXGR_SPDIFOUTSTATUS, chip->spdif_bits);
1012 spin_unlock_irq(&chip->reg_lock);
1013 chip->spdif_pcm_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1014 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE |
1015 SNDRV_CTL_EVENT_MASK_INFO, &chip->spdif_pcm_ctl->id);
1016 return snd_ymfpci_playback_close_1(substream);
1017 }
1018
1019 static int snd_ymfpci_playback_4ch_close(snd_pcm_substream_t * substream)
1020 {
1021 ymfpci_t *chip = snd_pcm_substream_chip(substream);
1022
1023 spin_lock_irq(&chip->reg_lock);
1024 if (chip->rear_opened > 0) {
1025 chip->rear_opened--;
1026 ymfpci_close_extension(chip);
1027 }
1028 spin_unlock_irq(&chip->reg_lock);
1029 return snd_ymfpci_playback_close_1(substream);
1030 }
1031
1032 static int snd_ymfpci_capture_close(snd_pcm_substream_t * substream)
1033 {
1034 ymfpci_t *chip = snd_pcm_substream_chip(substream);
1035 snd_pcm_runtime_t *runtime = substream->runtime;
1036 ymfpci_pcm_t *ypcm = runtime->private_data;
1037
1038 if (ypcm != NULL) {
1039 chip->capture_substream[ypcm->capture_bank_number] = NULL;
1040 snd_ymfpci_hw_stop(chip);
1041 }
1042 return 0;
1043 }
1044
1045 static snd_pcm_ops_t snd_ymfpci_playback_ops = {
1046 .open = snd_ymfpci_playback_open,
1047 .close = snd_ymfpci_playback_close,
1048 .ioctl = snd_pcm_lib_ioctl,
1049 .hw_params = snd_ymfpci_playback_hw_params,
1050 .hw_free = snd_ymfpci_playback_hw_free,
1051 .prepare = snd_ymfpci_playback_prepare,
1052 .trigger = snd_ymfpci_playback_trigger,
1053 .pointer = snd_ymfpci_playback_pointer,
1054 };
1055
1056 static snd_pcm_ops_t snd_ymfpci_capture_rec_ops = {
1057 .open = snd_ymfpci_capture_rec_open,
1058 .close = snd_ymfpci_capture_close,
1059 .ioctl = snd_pcm_lib_ioctl,
1060 .hw_params = snd_ymfpci_capture_hw_params,
1061 .hw_free = snd_ymfpci_capture_hw_free,
1062 .prepare = snd_ymfpci_capture_prepare,
1063 .trigger = snd_ymfpci_capture_trigger,
1064 .pointer = snd_ymfpci_capture_pointer,
1065 };
1066
1067 static void snd_ymfpci_pcm_free(snd_pcm_t *pcm)
1068 {
1069 ymfpci_t *chip = pcm->private_data;
1070 chip->pcm = NULL;
1071 snd_pcm_lib_preallocate_free_for_all(pcm);
1072 }
1073
1074 int __devinit snd_ymfpci_pcm(ymfpci_t *chip, int device, snd_pcm_t ** rpcm)
1075 {
1076 snd_pcm_t *pcm;
1077 int err;
1078
1079 if (rpcm)
1080 *rpcm = NULL;
1081 if ((err = snd_pcm_new(chip->card, "YMFPCI", device, 32, 1, &pcm)) < 0)
1082 return err;
1083 pcm->private_data = chip;
1084 pcm->private_free = snd_ymfpci_pcm_free;
1085
1086 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ymfpci_playback_ops);
1087 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_ymfpci_capture_rec_ops);
1088
1089 /* global setup */
1090 pcm->info_flags = 0;
1091 strcpy(pcm->name, "YMFPCI");
1092 chip->pcm = pcm;
1093
1094 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1095 snd_dma_pci_data(chip->pci), 64*1024, 256*1024);
1096
1097 if (rpcm)
1098 *rpcm = pcm;
1099 return 0;
1100 }
1101
1102 static snd_pcm_ops_t snd_ymfpci_capture_ac97_ops = {
1103 .open = snd_ymfpci_capture_ac97_open,
1104 .close = snd_ymfpci_capture_close,
1105 .ioctl = snd_pcm_lib_ioctl,
1106 .hw_params = snd_ymfpci_capture_hw_params,
1107 .hw_free = snd_ymfpci_capture_hw_free,
1108 .prepare = snd_ymfpci_capture_prepare,
1109 .trigger = snd_ymfpci_capture_trigger,
1110 .pointer = snd_ymfpci_capture_pointer,
1111 };
1112
1113 static void snd_ymfpci_pcm2_free(snd_pcm_t *pcm)
1114 {
1115 ymfpci_t *chip = pcm->private_data;
1116 chip->pcm2 = NULL;
1117 snd_pcm_lib_preallocate_free_for_all(pcm);
1118 }
1119
1120 int __devinit snd_ymfpci_pcm2(ymfpci_t *chip, int device, snd_pcm_t ** rpcm)
1121 {
1122 snd_pcm_t *pcm;
1123 int err;
1124
1125 if (rpcm)
1126 *rpcm = NULL;
1127 if ((err = snd_pcm_new(chip->card, "YMFPCI - PCM2", device, 0, 1, &pcm)) < 0)
1128 return err;
1129 pcm->private_data = chip;
1130 pcm->private_free = snd_ymfpci_pcm2_free;
1131
1132 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_ymfpci_capture_ac97_ops);
1133
1134 /* global setup */
1135 pcm->info_flags = 0;
1136 sprintf(pcm->name, "YMFPCI - %s",
1137 chip->device_id == PCI_DEVICE_ID_YAMAHA_754 ? "Direct Recording" : "AC'97");
1138 chip->pcm2 = pcm;
1139
1140 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1141 snd_dma_pci_data(chip->pci), 64*1024, 256*1024);
1142
1143 if (rpcm)
1144 *rpcm = pcm;
1145 return 0;
1146 }
1147
1148 static snd_pcm_ops_t snd_ymfpci_playback_spdif_ops = {
1149 .open = snd_ymfpci_playback_spdif_open,
1150 .close = snd_ymfpci_playback_spdif_close,
1151 .ioctl = snd_pcm_lib_ioctl,
1152 .hw_params = snd_ymfpci_playback_hw_params,
1153 .hw_free = snd_ymfpci_playback_hw_free,
1154 .prepare = snd_ymfpci_playback_prepare,
1155 .trigger = snd_ymfpci_playback_trigger,
1156 .pointer = snd_ymfpci_playback_pointer,
1157 };
1158
1159 static void snd_ymfpci_pcm_spdif_free(snd_pcm_t *pcm)
1160 {
1161 ymfpci_t *chip = pcm->private_data;
1162 chip->pcm_spdif = NULL;
1163 snd_pcm_lib_preallocate_free_for_all(pcm);
1164 }
1165
1166 int __devinit snd_ymfpci_pcm_spdif(ymfpci_t *chip, int device, snd_pcm_t ** rpcm)
1167 {
1168 snd_pcm_t *pcm;
1169 int err;
1170
1171 if (rpcm)
1172 *rpcm = NULL;
1173 if ((err = snd_pcm_new(chip->card, "YMFPCI - IEC958", device, 1, 0, &pcm)) < 0)
1174 return err;
1175 pcm->private_data = chip;
1176 pcm->private_free = snd_ymfpci_pcm_spdif_free;
1177
1178 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ymfpci_playback_spdif_ops);
1179
1180 /* global setup */
1181 pcm->info_flags = 0;
1182 strcpy(pcm->name, "YMFPCI - IEC958");
1183 chip->pcm_spdif = pcm;
1184
1185 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1186 snd_dma_pci_data(chip->pci), 64*1024, 256*1024);
1187
1188 if (rpcm)
1189 *rpcm = pcm;
1190 return 0;
1191 }
1192
1193 static snd_pcm_ops_t snd_ymfpci_playback_4ch_ops = {
1194 .open = snd_ymfpci_playback_4ch_open,
1195 .close = snd_ymfpci_playback_4ch_close,
1196 .ioctl = snd_pcm_lib_ioctl,
1197 .hw_params = snd_ymfpci_playback_hw_params,
1198 .hw_free = snd_ymfpci_playback_hw_free,
1199 .prepare = snd_ymfpci_playback_prepare,
1200 .trigger = snd_ymfpci_playback_trigger,
1201 .pointer = snd_ymfpci_playback_pointer,
1202 };
1203
1204 static void snd_ymfpci_pcm_4ch_free(snd_pcm_t *pcm)
1205 {
1206 ymfpci_t *chip = pcm->private_data;
1207 chip->pcm_4ch = NULL;
1208 snd_pcm_lib_preallocate_free_for_all(pcm);
1209 }
1210
1211 int __devinit snd_ymfpci_pcm_4ch(ymfpci_t *chip, int device, snd_pcm_t ** rpcm)
1212 {
1213 snd_pcm_t *pcm;
1214 int err;
1215
1216 if (rpcm)
1217 *rpcm = NULL;
1218 if ((err = snd_pcm_new(chip->card, "YMFPCI - Rear", device, 1, 0, &pcm)) < 0)
1219 return err;
1220 pcm->private_data = chip;
1221 pcm->private_free = snd_ymfpci_pcm_4ch_free;
1222
1223 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ymfpci_playback_4ch_ops);
1224
1225 /* global setup */
1226 pcm->info_flags = 0;
1227 strcpy(pcm->name, "YMFPCI - Rear PCM");
1228 chip->pcm_4ch = pcm;
1229
1230 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1231 snd_dma_pci_data(chip->pci), 64*1024, 256*1024);
1232
1233 if (rpcm)
1234 *rpcm = pcm;
1235 return 0;
1236 }
1237
1238 static int snd_ymfpci_spdif_default_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1239 {
1240 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1241 uinfo->count = 1;
1242 return 0;
1243 }
1244
1245 static int snd_ymfpci_spdif_default_get(snd_kcontrol_t * kcontrol,
1246 snd_ctl_elem_value_t * ucontrol)
1247 {
1248 ymfpci_t *chip = snd_kcontrol_chip(kcontrol);
1249
1250 spin_lock_irq(&chip->reg_lock);
1251 ucontrol->value.iec958.status[0] = (chip->spdif_bits >> 0) & 0xff;
1252 ucontrol->value.iec958.status[1] = (chip->spdif_bits >> 8) & 0xff;
1253 spin_unlock_irq(&chip->reg_lock);
1254 return 0;
1255 }
1256
1257 static int snd_ymfpci_spdif_default_put(snd_kcontrol_t * kcontrol,
1258 snd_ctl_elem_value_t * ucontrol)
1259 {
1260 ymfpci_t *chip = snd_kcontrol_chip(kcontrol);
1261 unsigned int val;
1262 int change;
1263
1264 val = ((ucontrol->value.iec958.status[0] & 0x3e) << 0) |
1265 (ucontrol->value.iec958.status[1] << 8);
1266 spin_lock_irq(&chip->reg_lock);
1267 change = chip->spdif_bits != val;
1268 chip->spdif_bits = val;
1269 if ((snd_ymfpci_readw(chip, YDSXGR_SPDIFOUTCTRL) & 1) && chip->pcm_spdif == NULL)
1270 snd_ymfpci_writew(chip, YDSXGR_SPDIFOUTSTATUS, chip->spdif_bits);
1271 spin_unlock_irq(&chip->reg_lock);
1272 return change;
1273 }
1274
1275 static snd_kcontrol_new_t snd_ymfpci_spdif_default __devinitdata =
1276 {
1277 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1278 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
1279 .info = snd_ymfpci_spdif_default_info,
1280 .get = snd_ymfpci_spdif_default_get,
1281 .put = snd_ymfpci_spdif_default_put
1282 };
1283
1284 static int snd_ymfpci_spdif_mask_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1285 {
1286 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1287 uinfo->count = 1;
1288 return 0;
1289 }
1290
1291 static int snd_ymfpci_spdif_mask_get(snd_kcontrol_t * kcontrol,
1292 snd_ctl_elem_value_t * ucontrol)
1293 {
1294 ymfpci_t *chip = snd_kcontrol_chip(kcontrol);
1295
1296 spin_lock_irq(&chip->reg_lock);
1297 ucontrol->value.iec958.status[0] = 0x3e;
1298 ucontrol->value.iec958.status[1] = 0xff;
1299 spin_unlock_irq(&chip->reg_lock);
1300 return 0;
1301 }
1302
1303 static snd_kcontrol_new_t snd_ymfpci_spdif_mask __devinitdata =
1304 {
1305 .access = SNDRV_CTL_ELEM_ACCESS_READ,
1306 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1307 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),
1308 .info = snd_ymfpci_spdif_mask_info,
1309 .get = snd_ymfpci_spdif_mask_get,
1310 };
1311
1312 static int snd_ymfpci_spdif_stream_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1313 {
1314 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1315 uinfo->count = 1;
1316 return 0;
1317 }
1318
1319 static int snd_ymfpci_spdif_stream_get(snd_kcontrol_t * kcontrol,
1320 snd_ctl_elem_value_t * ucontrol)
1321 {
1322 ymfpci_t *chip = snd_kcontrol_chip(kcontrol);
1323
1324 spin_lock_irq(&chip->reg_lock);
1325 ucontrol->value.iec958.status[0] = (chip->spdif_pcm_bits >> 0) & 0xff;
1326 ucontrol->value.iec958.status[1] = (chip->spdif_pcm_bits >> 8) & 0xff;
1327 spin_unlock_irq(&chip->reg_lock);
1328 return 0;
1329 }
1330
1331 static int snd_ymfpci_spdif_stream_put(snd_kcontrol_t * kcontrol,
1332 snd_ctl_elem_value_t * ucontrol)
1333 {
1334 ymfpci_t *chip = snd_kcontrol_chip(kcontrol);
1335 unsigned int val;
1336 int change;
1337
1338 val = ((ucontrol->value.iec958.status[0] & 0x3e) << 0) |
1339 (ucontrol->value.iec958.status[1] << 8);
1340 spin_lock_irq(&chip->reg_lock);
1341 change = chip->spdif_pcm_bits != val;
1342 chip->spdif_pcm_bits = val;
1343 if ((snd_ymfpci_readw(chip, YDSXGR_SPDIFOUTCTRL) & 2))
1344 snd_ymfpci_writew(chip, YDSXGR_SPDIFOUTSTATUS, chip->spdif_pcm_bits);
1345 spin_unlock_irq(&chip->reg_lock);
1346 return change;
1347 }
1348
1349 static snd_kcontrol_new_t snd_ymfpci_spdif_stream __devinitdata =
1350 {
1351 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
1352 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1353 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
1354 .info = snd_ymfpci_spdif_stream_info,
1355 .get = snd_ymfpci_spdif_stream_get,
1356 .put = snd_ymfpci_spdif_stream_put
1357 };
1358
1359 static int snd_ymfpci_drec_source_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t *info)
1360 {
1361 static char *texts[3] = {"AC'97", "IEC958", "ZV Port"};
1362
1363 info->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1364 info->count = 1;
1365 info->value.enumerated.items = 3;
1366 if (info->value.enumerated.item > 2)
1367 info->value.enumerated.item = 2;
1368 strcpy(info->value.enumerated.name, texts[info->value.enumerated.item]);
1369 return 0;
1370 }
1371
1372 static int snd_ymfpci_drec_source_get(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *value)
1373 {
1374 ymfpci_t *chip = snd_kcontrol_chip(kcontrol);
1375 u16 reg;
1376
1377 spin_lock_irq(&chip->reg_lock);
1378 reg = snd_ymfpci_readw(chip, YDSXGR_GLOBALCTRL);
1379 spin_unlock_irq(&chip->reg_lock);
1380 if (!(reg & 0x100))
1381 value->value.enumerated.item[0] = 0;
1382 else
1383 value->value.enumerated.item[0] = 1 + ((reg & 0x200) != 0);
1384 return 0;
1385 }
1386
1387 static int snd_ymfpci_drec_source_put(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *value)
1388 {
1389 ymfpci_t *chip = snd_kcontrol_chip(kcontrol);
1390 u16 reg, old_reg;
1391
1392 spin_lock_irq(&chip->reg_lock);
1393 old_reg = snd_ymfpci_readw(chip, YDSXGR_GLOBALCTRL);
1394 if (value->value.enumerated.item[0] == 0)
1395 reg = old_reg & ~0x100;
1396 else
1397 reg = (old_reg & ~0x300) | 0x100 | ((value->value.enumerated.item[0] == 2) << 9);
1398 snd_ymfpci_writew(chip, YDSXGR_GLOBALCTRL, reg);
1399 spin_unlock_irq(&chip->reg_lock);
1400 return reg != old_reg;
1401 }
1402
1403 static snd_kcontrol_new_t snd_ymfpci_drec_source __devinitdata = {
1404 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,
1405 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1406 .name = "Direct Recording Source",
1407 .info = snd_ymfpci_drec_source_info,
1408 .get = snd_ymfpci_drec_source_get,
1409 .put = snd_ymfpci_drec_source_put
1410 };
1411
1412 /*
1413 * Mixer controls
1414 */
1415
1416 #define YMFPCI_SINGLE(xname, xindex, reg) \
1417 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
1418 .info = snd_ymfpci_info_single, \
1419 .get = snd_ymfpci_get_single, .put = snd_ymfpci_put_single, \
1420 .private_value = reg }
1421
1422 static int snd_ymfpci_info_single(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1423 {
1424 unsigned int mask = 1;
1425
1426 switch (kcontrol->private_value) {
1427 case YDSXGR_SPDIFOUTCTRL: break;
1428 case YDSXGR_SPDIFINCTRL: break;
1429 default: return -EINVAL;
1430 }
1431 uinfo->type = mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
1432 uinfo->count = 1;
1433 uinfo->value.integer.min = 0;
1434 uinfo->value.integer.max = mask;
1435 return 0;
1436 }
1437
1438 static int snd_ymfpci_get_single(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1439 {
1440 ymfpci_t *chip = snd_kcontrol_chip(kcontrol);
1441 int reg = kcontrol->private_value;
1442 unsigned int shift = 0, mask = 1, invert = 0;
1443
1444 switch (kcontrol->private_value) {
1445 case YDSXGR_SPDIFOUTCTRL: break;
1446 case YDSXGR_SPDIFINCTRL: break;
1447 default: return -EINVAL;
1448 }
1449 ucontrol->value.integer.value[0] = (snd_ymfpci_readl(chip, reg) >> shift) & mask;
1450 if (invert)
1451 ucontrol->value.integer.value[0] = mask - ucontrol->value.integer.value[0];
1452 return 0;
1453 }
1454
1455 static int snd_ymfpci_put_single(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1456 {
1457 ymfpci_t *chip = snd_kcontrol_chip(kcontrol);
1458 int reg = kcontrol->private_value;
1459 unsigned int shift = 0, mask = 1, invert = 0;
1460 int change;
1461 unsigned int val, oval;
1462
1463 switch (kcontrol->private_value) {
1464 case YDSXGR_SPDIFOUTCTRL: break;
1465 case YDSXGR_SPDIFINCTRL: break;
1466 default: return -EINVAL;
1467 }
1468 val = (ucontrol->value.integer.value[0] & mask);
1469 if (invert)
1470 val = mask - val;
1471 val <<= shift;
1472 spin_lock_irq(&chip->reg_lock);
1473 oval = snd_ymfpci_readl(chip, reg);
1474 val = (oval & ~(mask << shift)) | val;
1475 change = val != oval;
1476 snd_ymfpci_writel(chip, reg, val);
1477 spin_unlock_irq(&chip->reg_lock);
1478 return change;
1479 }
1480
1481 #define YMFPCI_DOUBLE(xname, xindex, reg) \
1482 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
1483 .info = snd_ymfpci_info_double, \
1484 .get = snd_ymfpci_get_double, .put = snd_ymfpci_put_double, \
1485 .private_value = reg }
1486
1487 static int snd_ymfpci_info_double(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1488 {
1489 unsigned int reg = kcontrol->private_value;
1490 unsigned int mask = 16383;
1491
1492 if (reg < 0x80 || reg >= 0xc0)
1493 return -EINVAL;
1494 uinfo->type = mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
1495 uinfo->count = 2;
1496 uinfo->value.integer.min = 0;
1497 uinfo->value.integer.max = mask;
1498 return 0;
1499 }
1500
1501 static int snd_ymfpci_get_double(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1502 {
1503 ymfpci_t *chip = snd_kcontrol_chip(kcontrol);
1504 unsigned int reg = kcontrol->private_value;
1505 unsigned int shift_left = 0, shift_right = 16, mask = 16383, invert = 0;
1506 unsigned int val;
1507
1508 if (reg < 0x80 || reg >= 0xc0)
1509 return -EINVAL;
1510 spin_lock_irq(&chip->reg_lock);
1511 val = snd_ymfpci_readl(chip, reg);
1512 spin_unlock_irq(&chip->reg_lock);
1513 ucontrol->value.integer.value[0] = (val >> shift_left) & mask;
1514 ucontrol->value.integer.value[1] = (val >> shift_right) & mask;
1515 if (invert) {
1516 ucontrol->value.integer.value[0] = mask - ucontrol->value.integer.value[0];
1517 ucontrol->value.integer.value[1] = mask - ucontrol->value.integer.value[1];
1518 }
1519 return 0;
1520 }
1521
1522 static int snd_ymfpci_put_double(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1523 {
1524 ymfpci_t *chip = snd_kcontrol_chip(kcontrol);
1525 unsigned int reg = kcontrol->private_value;
1526 unsigned int shift_left = 0, shift_right = 16, mask = 16383, invert = 0;
1527 int change;
1528 unsigned int val1, val2, oval;
1529
1530 if (reg < 0x80 || reg >= 0xc0)
1531 return -EINVAL;
1532 val1 = ucontrol->value.integer.value[0] & mask;
1533 val2 = ucontrol->value.integer.value[1] & mask;
1534 if (invert) {
1535 val1 = mask - val1;
1536 val2 = mask - val2;
1537 }
1538 val1 <<= shift_left;
1539 val2 <<= shift_right;
1540 spin_lock_irq(&chip->reg_lock);
1541 oval = snd_ymfpci_readl(chip, reg);
1542 val1 = (oval & ~((mask << shift_left) | (mask << shift_right))) | val1 | val2;
1543 change = val1 != oval;
1544 snd_ymfpci_writel(chip, reg, val1);
1545 spin_unlock_irq(&chip->reg_lock);
1546 return change;
1547 }
1548
1549 /*
1550 * 4ch duplication
1551 */
1552 static int snd_ymfpci_info_dup4ch(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1553 {
1554 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1555 uinfo->count = 1;
1556 uinfo->value.integer.min = 0;
1557 uinfo->value.integer.max = 1;
1558 return 0;
1559 }
1560
1561 static int snd_ymfpci_get_dup4ch(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1562 {
1563 ymfpci_t *chip = snd_kcontrol_chip(kcontrol);
1564 ucontrol->value.integer.value[0] = chip->mode_dup4ch;
1565 return 0;
1566 }
1567
1568 static int snd_ymfpci_put_dup4ch(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1569 {
1570 ymfpci_t *chip = snd_kcontrol_chip(kcontrol);
1571 int change;
1572 change = (ucontrol->value.integer.value[0] != chip->mode_dup4ch);
1573 if (change)
1574 chip->mode_dup4ch = !!ucontrol->value.integer.value[0];
1575 return change;
1576 }
1577
1578
1579 static snd_kcontrol_new_t snd_ymfpci_controls[] __devinitdata = {
1580 YMFPCI_DOUBLE("Wave Playback Volume", 0, YDSXGR_NATIVEDACOUTVOL),
1581 YMFPCI_DOUBLE("Wave Capture Volume", 0, YDSXGR_NATIVEDACLOOPVOL),
1582 YMFPCI_DOUBLE("Digital Capture Volume", 0, YDSXGR_NATIVEDACINVOL),
1583 YMFPCI_DOUBLE("Digital Capture Volume", 1, YDSXGR_NATIVEADCINVOL),
1584 YMFPCI_DOUBLE("ADC Playback Volume", 0, YDSXGR_PRIADCOUTVOL),
1585 YMFPCI_DOUBLE("ADC Capture Volume", 0, YDSXGR_PRIADCLOOPVOL),
1586 YMFPCI_DOUBLE("ADC Playback Volume", 1, YDSXGR_SECADCOUTVOL),
1587 YMFPCI_DOUBLE("ADC Capture Volume", 1, YDSXGR_SECADCLOOPVOL),
1588 YMFPCI_DOUBLE("FM Legacy Volume", 0, YDSXGR_LEGACYOUTVOL),
1589 YMFPCI_DOUBLE(SNDRV_CTL_NAME_IEC958("AC97 ", PLAYBACK,VOLUME), 0, YDSXGR_ZVOUTVOL),
1590 YMFPCI_DOUBLE(SNDRV_CTL_NAME_IEC958("", CAPTURE,VOLUME), 0, YDSXGR_ZVLOOPVOL),
1591 YMFPCI_DOUBLE(SNDRV_CTL_NAME_IEC958("AC97 ",PLAYBACK,VOLUME), 1, YDSXGR_SPDIFOUTVOL),
1592 YMFPCI_DOUBLE(SNDRV_CTL_NAME_IEC958("",CAPTURE,VOLUME), 1, YDSXGR_SPDIFLOOPVOL),
1593 YMFPCI_SINGLE(SNDRV_CTL_NAME_IEC958("",PLAYBACK,SWITCH), 0, YDSXGR_SPDIFOUTCTRL),
1594 YMFPCI_SINGLE(SNDRV_CTL_NAME_IEC958("",CAPTURE,SWITCH), 0, YDSXGR_SPDIFINCTRL),
1595 {
1596 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1597 .name = "4ch Duplication",
1598 .info = snd_ymfpci_info_dup4ch,
1599 .get = snd_ymfpci_get_dup4ch,
1600 .put = snd_ymfpci_put_dup4ch,
1601 },
1602 };
1603
1604
1605 /*
1606 * GPIO
1607 */
1608
1609 static int snd_ymfpci_get_gpio_out(ymfpci_t *chip, int pin)
1610 {
1611 u16 reg, mode;
1612 unsigned long flags;
1613
1614 spin_lock_irqsave(&chip->reg_lock, flags);
1615 reg = snd_ymfpci_readw(chip, YDSXGR_GPIOFUNCENABLE);
1616 reg &= ~(1 << (pin + 8));
1617 reg |= (1 << pin);
1618 snd_ymfpci_writew(chip, YDSXGR_GPIOFUNCENABLE, reg);
1619 /* set the level mode for input line */
1620 mode = snd_ymfpci_readw(chip, YDSXGR_GPIOTYPECONFIG);
1621 mode &= ~(3 << (pin * 2));
1622 snd_ymfpci_writew(chip, YDSXGR_GPIOTYPECONFIG, mode);
1623 snd_ymfpci_writew(chip, YDSXGR_GPIOFUNCENABLE, reg | (1 << (pin + 8)));
1624 mode = snd_ymfpci_readw(chip, YDSXGR_GPIOINSTATUS);
1625 spin_unlock_irqrestore(&chip->reg_lock, flags);
1626 return (mode >> pin) & 1;
1627 }
1628
1629 static int snd_ymfpci_set_gpio_out(ymfpci_t *chip, int pin, int enable)
1630 {
1631 u16 reg;
1632 unsigned long flags;
1633
1634 spin_lock_irqsave(&chip->reg_lock, flags);
1635 reg = snd_ymfpci_readw(chip, YDSXGR_GPIOFUNCENABLE);
1636 reg &= ~(1 << pin);
1637 reg &= ~(1 << (pin + 8));
1638 snd_ymfpci_writew(chip, YDSXGR_GPIOFUNCENABLE, reg);
1639 snd_ymfpci_writew(chip, YDSXGR_GPIOOUTCTRL, enable << pin);
1640 snd_ymfpci_writew(chip, YDSXGR_GPIOFUNCENABLE, reg | (1 << (pin + 8)));
1641 spin_unlock_irqrestore(&chip->reg_lock, flags);
1642
1643 return 0;
1644 }
1645
1646 static int snd_ymfpci_gpio_sw_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t *uinfo)
1647 {
1648 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1649 uinfo->count = 1;
1650 uinfo->value.integer.min = 0;
1651 uinfo->value.integer.max = 1;
1652 return 0;
1653 }
1654
1655 static int snd_ymfpci_gpio_sw_get(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol)
1656 {
1657 ymfpci_t *chip = snd_kcontrol_chip(kcontrol);
1658 int pin = (int)kcontrol->private_value;
1659 ucontrol->value.integer.value[0] = snd_ymfpci_get_gpio_out(chip, pin);
1660 return 0;
1661 }
1662
1663 static int snd_ymfpci_gpio_sw_put(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol)
1664 {
1665 ymfpci_t *chip = snd_kcontrol_chip(kcontrol);
1666 int pin = (int)kcontrol->private_value;
1667
1668 if (snd_ymfpci_get_gpio_out(chip, pin) != ucontrol->value.integer.value[0]) {
1669 snd_ymfpci_set_gpio_out(chip, pin, !!ucontrol->value.integer.value[0]);
1670 ucontrol->value.integer.value[0] = snd_ymfpci_get_gpio_out(chip, pin);
1671 return 1;
1672 }
1673 return 0;
1674 }
1675
1676 static snd_kcontrol_new_t snd_ymfpci_rear_shared __devinitdata = {
1677 .name = "Shared Rear/Line-In Switch",
1678 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1679 .info = snd_ymfpci_gpio_sw_info,
1680 .get = snd_ymfpci_gpio_sw_get,
1681 .put = snd_ymfpci_gpio_sw_put,
1682 .private_value = 2,
1683 };
1684
1685
1686 /*
1687 * Mixer routines
1688 */
1689
1690 static void snd_ymfpci_mixer_free_ac97_bus(ac97_bus_t *bus)
1691 {
1692 ymfpci_t *chip = bus->private_data;
1693 chip->ac97_bus = NULL;
1694 }
1695
1696 static void snd_ymfpci_mixer_free_ac97(ac97_t *ac97)
1697 {
1698 ymfpci_t *chip = ac97->private_data;
1699 chip->ac97 = NULL;
1700 }
1701
1702 int __devinit snd_ymfpci_mixer(ymfpci_t *chip, int rear_switch)
1703 {
1704 ac97_template_t ac97;
1705 snd_kcontrol_t *kctl;
1706 unsigned int idx;
1707 int err;
1708 static ac97_bus_ops_t ops = {
1709 .write = snd_ymfpci_codec_write,
1710 .read = snd_ymfpci_codec_read,
1711 };
1712
1713 if ((err = snd_ac97_bus(chip->card, 0, &ops, chip, &chip->ac97_bus)) < 0)
1714 return err;
1715 chip->ac97_bus->private_free = snd_ymfpci_mixer_free_ac97_bus;
1716 chip->ac97_bus->no_vra = 1; /* YMFPCI doesn't need VRA */
1717
1718 memset(&ac97, 0, sizeof(ac97));
1719 ac97.private_data = chip;
1720 ac97.private_free = snd_ymfpci_mixer_free_ac97;
1721 if ((err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97)) < 0)
1722 return err;
1723
1724 /* to be sure */
1725 snd_ac97_update_bits(chip->ac97, AC97_EXTENDED_STATUS,
1726 AC97_EA_VRA|AC97_EA_VRM, 0);
1727
1728 for (idx = 0; idx < ARRAY_SIZE(snd_ymfpci_controls); idx++) {
1729 if ((err = snd_ctl_add(chip->card, snd_ctl_new1(&snd_ymfpci_controls[idx], chip))) < 0)
1730 return err;
1731 }
1732
1733 /* add S/PDIF control */
1734 snd_assert(chip->pcm_spdif != NULL, return -EIO);
1735 if ((err = snd_ctl_add(chip->card, kctl = snd_ctl_new1(&snd_ymfpci_spdif_default, chip))) < 0)
1736 return err;
1737 kctl->id.device = chip->pcm_spdif->device;
1738 if ((err = snd_ctl_add(chip->card, kctl = snd_ctl_new1(&snd_ymfpci_spdif_mask, chip))) < 0)
1739 return err;
1740 kctl->id.device = chip->pcm_spdif->device;
1741 if ((err = snd_ctl_add(chip->card, kctl = snd_ctl_new1(&snd_ymfpci_spdif_stream, chip))) < 0)
1742 return err;
1743 kctl->id.device = chip->pcm_spdif->device;
1744 chip->spdif_pcm_ctl = kctl;
1745
1746 /* direct recording source */
1747 if (chip->device_id == PCI_DEVICE_ID_YAMAHA_754 &&
1748 (err = snd_ctl_add(chip->card, kctl = snd_ctl_new1(&snd_ymfpci_drec_source, chip))) < 0)
1749 return err;
1750
1751 /*
1752 * shared rear/line-in
1753 */
1754 if (rear_switch) {
1755 if ((err = snd_ctl_add(chip->card, snd_ctl_new1(&snd_ymfpci_rear_shared, chip))) < 0)
1756 return err;
1757 }
1758
1759 return 0;
1760 }
1761
1762
1763 /*
1764 * timer
1765 */
1766
1767 static int snd_ymfpci_timer_start(snd_timer_t *timer)
1768 {
1769 ymfpci_t *chip;
1770 unsigned long flags;
1771 unsigned int count;
1772
1773 chip = snd_timer_chip(timer);
1774 count = timer->sticks - 1;
1775 if (count == 0) /* minimum time is 20.8 us */
1776 count = 1;
1777 spin_lock_irqsave(&chip->reg_lock, flags);
1778 snd_ymfpci_writew(chip, YDSXGR_TIMERCOUNT, count);
1779 snd_ymfpci_writeb(chip, YDSXGR_TIMERCTRL, 0x03);
1780 spin_unlock_irqrestore(&chip->reg_lock, flags);
1781 return 0;
1782 }
1783
1784 static int snd_ymfpci_timer_stop(snd_timer_t *timer)
1785 {
1786 ymfpci_t *chip;
1787 unsigned long flags;
1788
1789 chip = snd_timer_chip(timer);
1790 spin_lock_irqsave(&chip->reg_lock, flags);
1791 snd_ymfpci_writeb(chip, YDSXGR_TIMERCTRL, 0x00);
1792 spin_unlock_irqrestore(&chip->reg_lock, flags);
1793 return 0;
1794 }
1795
1796 static int snd_ymfpci_timer_precise_resolution(snd_timer_t *timer,
1797 unsigned long *num, unsigned long *den)
1798 {
1799 *num = 1;
1800 *den = 96000;
1801 return 0;
1802 }
1803
1804 static struct _snd_timer_hardware snd_ymfpci_timer_hw = {
1805 .flags = SNDRV_TIMER_HW_AUTO,
1806 .resolution = 10417, /* 1/2fs = 10.41666...us */
1807 .ticks = 65536,
1808 .start = snd_ymfpci_timer_start,
1809 .stop = snd_ymfpci_timer_stop,
1810 .precise_resolution = snd_ymfpci_timer_precise_resolution,
1811 };
1812
1813 int __devinit snd_ymfpci_timer(ymfpci_t *chip, int device)
1814 {
1815 snd_timer_t *timer = NULL;
1816 snd_timer_id_t tid;
1817 int err;
1818
1819 tid.dev_class = SNDRV_TIMER_CLASS_CARD;
1820 tid.dev_sclass = SNDRV_TIMER_SCLASS_NONE;
1821 tid.card = chip->card->number;
1822 tid.device = device;
1823 tid.subdevice = 0;
1824 if ((err = snd_timer_new(chip->card, "YMFPCI", &tid, &timer)) >= 0) {
1825 strcpy(timer->name, "YMFPCI timer");
1826 timer->private_data = chip;
1827 timer->hw = snd_ymfpci_timer_hw;
1828 }
1829 chip->timer = timer;
1830 return err;
1831 }
1832
1833
1834 /*
1835 * proc interface
1836 */
1837
1838 static void snd_ymfpci_proc_read(snd_info_entry_t *entry,
1839 snd_info_buffer_t * buffer)
1840 {
1841 ymfpci_t *chip = entry->private_data;
1842 int i;
1843
1844 snd_iprintf(buffer, "YMFPCI\n\n");
1845 for (i = 0; i <= YDSXGR_WORKBASE; i += 4)
1846 snd_iprintf(buffer, "%04x: %04x\n", i, snd_ymfpci_readl(chip, i));
1847 }
1848
1849 static int __devinit snd_ymfpci_proc_init(snd_card_t * card, ymfpci_t *chip)
1850 {
1851 snd_info_entry_t *entry;
1852
1853 if (! snd_card_proc_new(card, "ymfpci", &entry))
1854 snd_info_set_text_ops(entry, chip, 1024, snd_ymfpci_proc_read);
1855 return 0;
1856 }
1857
1858 /*
1859 * initialization routines
1860 */
1861
1862 static void snd_ymfpci_aclink_reset(struct pci_dev * pci)
1863 {
1864 u8 cmd;
1865
1866 pci_read_config_byte(pci, PCIR_DSXG_CTRL, &cmd);
1867 #if 0 // force to reset
1868 if (cmd & 0x03) {
1869 #endif
1870 pci_write_config_byte(pci, PCIR_DSXG_CTRL, cmd & 0xfc);
1871 pci_write_config_byte(pci, PCIR_DSXG_CTRL, cmd | 0x03);
1872 pci_write_config_byte(pci, PCIR_DSXG_CTRL, cmd & 0xfc);
1873 pci_write_config_word(pci, PCIR_DSXG_PWRCTRL1, 0);
1874 pci_write_config_word(pci, PCIR_DSXG_PWRCTRL2, 0);
1875 #if 0
1876 }
1877 #endif
1878 }
1879
1880 static void snd_ymfpci_enable_dsp(ymfpci_t *chip)
1881 {
1882 snd_ymfpci_writel(chip, YDSXGR_CONFIG, 0x00000001);
1883 }
1884
1885 static void snd_ymfpci_disable_dsp(ymfpci_t *chip)
1886 {
1887 u32 val;
1888 int timeout = 1000;
1889
1890 val = snd_ymfpci_readl(chip, YDSXGR_CONFIG);
1891 if (val)
1892 snd_ymfpci_writel(chip, YDSXGR_CONFIG, 0x00000000);
1893 while (timeout-- > 0) {
1894 val = snd_ymfpci_readl(chip, YDSXGR_STATUS);
1895 if ((val & 0x00000002) == 0)
1896 break;
1897 }
1898 }
1899
1900 #include "ymfpci_image.h"
1901
1902 static void snd_ymfpci_download_image(ymfpci_t *chip)
1903 {
1904 int i;
1905 u16 ctrl;
1906 unsigned long *inst;
1907
1908 snd_ymfpci_writel(chip, YDSXGR_NATIVEDACOUTVOL, 0x00000000);
1909 snd_ymfpci_disable_dsp(chip);
1910 snd_ymfpci_writel(chip, YDSXGR_MODE, 0x00010000);
1911 snd_ymfpci_writel(chip, YDSXGR_MODE, 0x00000000);
1912 snd_ymfpci_writel(chip, YDSXGR_MAPOFREC, 0x00000000);
1913 snd_ymfpci_writel(chip, YDSXGR_MAPOFEFFECT, 0x00000000);
1914 snd_ymfpci_writel(chip, YDSXGR_PLAYCTRLBASE, 0x00000000);
1915 snd_ymfpci_writel(chip, YDSXGR_RECCTRLBASE, 0x00000000);
1916 snd_ymfpci_writel(chip, YDSXGR_EFFCTRLBASE, 0x00000000);
1917 ctrl = snd_ymfpci_readw(chip, YDSXGR_GLOBALCTRL);
1918 snd_ymfpci_writew(chip, YDSXGR_GLOBALCTRL, ctrl & ~0x0007);
1919
1920 /* setup DSP instruction code */
1921 for (i = 0; i < YDSXG_DSPLENGTH / 4; i++)
1922 snd_ymfpci_writel(chip, YDSXGR_DSPINSTRAM + (i << 2), DspInst[i]);
1923
1924 /* setup control instruction code */
1925 switch (chip->device_id) {
1926 case PCI_DEVICE_ID_YAMAHA_724F:
1927 case PCI_DEVICE_ID_YAMAHA_740C:
1928 case PCI_DEVICE_ID_YAMAHA_744:
1929 case PCI_DEVICE_ID_YAMAHA_754:
1930 inst = CntrlInst1E;
1931 break;
1932 default:
1933 inst = CntrlInst;
1934 break;
1935 }
1936 for (i = 0; i < YDSXG_CTRLLENGTH / 4; i++)
1937 snd_ymfpci_writel(chip, YDSXGR_CTRLINSTRAM + (i << 2), inst[i]);
1938
1939 snd_ymfpci_enable_dsp(chip);
1940 }
1941
1942 static int __devinit snd_ymfpci_memalloc(ymfpci_t *chip)
1943 {
1944 long size, playback_ctrl_size;
1945 int voice, bank, reg;
1946 u8 *ptr;
1947 dma_addr_t ptr_addr;
1948
1949 playback_ctrl_size = 4 + 4 * YDSXG_PLAYBACK_VOICES;
1950 chip->bank_size_playback = snd_ymfpci_readl(chip, YDSXGR_PLAYCTRLSIZE) << 2;
1951 chip->bank_size_capture = snd_ymfpci_readl(chip, YDSXGR_RECCTRLSIZE) << 2;
1952 chip->bank_size_effect = snd_ymfpci_readl(chip, YDSXGR_EFFCTRLSIZE) << 2;
1953 chip->work_size = YDSXG_DEFAULT_WORK_SIZE;
1954
1955 size = ((playback_ctrl_size + 0x00ff) & ~0x00ff) +
1956 ((chip->bank_size_playback * 2 * YDSXG_PLAYBACK_VOICES + 0x00ff) & ~0x00ff) +
1957 ((chip->bank_size_capture * 2 * YDSXG_CAPTURE_VOICES + 0x00ff) & ~0x00ff) +
1958 ((chip->bank_size_effect * 2 * YDSXG_EFFECT_VOICES + 0x00ff) & ~0x00ff) +
1959 chip->work_size;
1960 /* work_ptr must be aligned to 256 bytes, but it's already
1961 covered with the kernel page allocation mechanism */
1962 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci),
1963 size, &chip->work_ptr) < 0)
1964 return -ENOMEM;
1965 ptr = chip->work_ptr.area;
1966 ptr_addr = chip->work_ptr.addr;
1967 memset(ptr, 0, size); /* for sure */
1968
1969 chip->bank_base_playback = ptr;
1970 chip->bank_base_playback_addr = ptr_addr;
1971 chip->ctrl_playback = (u32 *)ptr;
1972 chip->ctrl_playback[0] = cpu_to_le32(YDSXG_PLAYBACK_VOICES);
1973 ptr += (playback_ctrl_size + 0x00ff) & ~0x00ff;
1974 ptr_addr += (playback_ctrl_size + 0x00ff) & ~0x00ff;
1975 for (voice = 0; voice < YDSXG_PLAYBACK_VOICES; voice++) {
1976 chip->voices[voice].number = voice;
1977 chip->voices[voice].bank = (snd_ymfpci_playback_bank_t *)ptr;
1978 chip->voices[voice].bank_addr = ptr_addr;
1979 for (bank = 0; bank < 2; bank++) {
1980 chip->bank_playback[voice][bank] = (snd_ymfpci_playback_bank_t *)ptr;
1981 ptr += chip->bank_size_playback;
1982 ptr_addr += chip->bank_size_playback;
1983 }
1984 }
1985 ptr = (char *)(((unsigned long)ptr + 0x00ff) & ~0x00ff);
1986 ptr_addr = (ptr_addr + 0x00ff) & ~0x00ff;
1987 chip->bank_base_capture = ptr;
1988 chip->bank_base_capture_addr = ptr_addr;
1989 for (voice = 0; voice < YDSXG_CAPTURE_VOICES; voice++)
1990 for (bank = 0; bank < 2; bank++) {
1991 chip->bank_capture[voice][bank] = (snd_ymfpci_capture_bank_t *)ptr;
1992 ptr += chip->bank_size_capture;
1993 ptr_addr += chip->bank_size_capture;
1994 }
1995 ptr = (char *)(((unsigned long)ptr + 0x00ff) & ~0x00ff);
1996 ptr_addr = (ptr_addr + 0x00ff) & ~0x00ff;
1997 chip->bank_base_effect = ptr;
1998 chip->bank_base_effect_addr = ptr_addr;
1999 for (voice = 0; voice < YDSXG_EFFECT_VOICES; voice++)
2000 for (bank = 0; bank < 2; bank++) {
2001 chip->bank_effect[voice][bank] = (snd_ymfpci_effect_bank_t *)ptr;
2002 ptr += chip->bank_size_effect;
2003 ptr_addr += chip->bank_size_effect;
2004 }
2005 ptr = (char *)(((unsigned long)ptr + 0x00ff) & ~0x00ff);
2006 ptr_addr = (ptr_addr + 0x00ff) & ~0x00ff;
2007 chip->work_base = ptr;
2008 chip->work_base_addr = ptr_addr;
2009
2010 snd_assert(ptr + chip->work_size == chip->work_ptr.area + chip->work_ptr.bytes, );
2011
2012 snd_ymfpci_writel(chip, YDSXGR_PLAYCTRLBASE, chip->bank_base_playback_addr);
2013 snd_ymfpci_writel(chip, YDSXGR_RECCTRLBASE, chip->bank_base_capture_addr);
2014 snd_ymfpci_writel(chip, YDSXGR_EFFCTRLBASE, chip->bank_base_effect_addr);
2015 snd_ymfpci_writel(chip, YDSXGR_WORKBASE, chip->work_base_addr);
2016 snd_ymfpci_writel(chip, YDSXGR_WORKSIZE, chip->work_size >> 2);
2017
2018 /* S/PDIF output initialization */
2019 chip->spdif_bits = chip->spdif_pcm_bits = SNDRV_PCM_DEFAULT_CON_SPDIF & 0xffff;
2020 snd_ymfpci_writew(chip, YDSXGR_SPDIFOUTCTRL, 0);
2021 snd_ymfpci_writew(chip, YDSXGR_SPDIFOUTSTATUS, chip->spdif_bits);
2022
2023 /* S/PDIF input initialization */
2024 snd_ymfpci_writew(chip, YDSXGR_SPDIFINCTRL, 0);
2025
2026 /* digital mixer setup */
2027 for (reg = 0x80; reg < 0xc0; reg += 4)
2028 snd_ymfpci_writel(chip, reg, 0);
2029 snd_ymfpci_writel(chip, YDSXGR_NATIVEDACOUTVOL, 0x3fff3fff);
2030 snd_ymfpci_writel(chip, YDSXGR_ZVOUTVOL, 0x3fff3fff);
2031 snd_ymfpci_writel(chip, YDSXGR_SPDIFOUTVOL, 0x3fff3fff);
2032 snd_ymfpci_writel(chip, YDSXGR_NATIVEADCINVOL, 0x3fff3fff);
2033 snd_ymfpci_writel(chip, YDSXGR_NATIVEDACINVOL, 0x3fff3fff);
2034 snd_ymfpci_writel(chip, YDSXGR_PRIADCLOOPVOL, 0x3fff3fff);
2035 snd_ymfpci_writel(chip, YDSXGR_LEGACYOUTVOL, 0x3fff3fff);
2036
2037 return 0;
2038 }
2039
2040 static int snd_ymfpci_free(ymfpci_t *chip)
2041 {
2042 u16 ctrl;
2043
2044 snd_assert(chip != NULL, return -EINVAL);
2045
2046 if (chip->res_reg_area) { /* don't touch busy hardware */
2047 snd_ymfpci_writel(chip, YDSXGR_NATIVEDACOUTVOL, 0);
2048 snd_ymfpci_writel(chip, YDSXGR_BUF441OUTVOL, 0);
2049 snd_ymfpci_writel(chip, YDSXGR_LEGACYOUTVOL, 0);
2050 snd_ymfpci_writel(chip, YDSXGR_STATUS, ~0);
2051 snd_ymfpci_disable_dsp(chip);
2052 snd_ymfpci_writel(chip, YDSXGR_PLAYCTRLBASE, 0);
2053 snd_ymfpci_writel(chip, YDSXGR_RECCTRLBASE, 0);
2054 snd_ymfpci_writel(chip, YDSXGR_EFFCTRLBASE, 0);
2055 snd_ymfpci_writel(chip, YDSXGR_WORKBASE, 0);
2056 snd_ymfpci_writel(chip, YDSXGR_WORKSIZE, 0);
2057 ctrl = snd_ymfpci_readw(chip, YDSXGR_GLOBALCTRL);
2058 snd_ymfpci_writew(chip, YDSXGR_GLOBALCTRL, ctrl & ~0x0007);
2059 }
2060
2061 snd_ymfpci_ac3_done(chip);
2062
2063 /* Set PCI device to D3 state */
2064 #if 0
2065 /* FIXME: temporarily disabled, otherwise we cannot fire up
2066 * the chip again unless reboot. ACPI bug?
2067 */
2068 pci_set_power_state(chip->pci, 3);
2069 #endif
2070
2071 #ifdef CONFIG_PM
2072 vfree(chip->saved_regs);
2073 #endif
2074 if (chip->mpu_res) {
2075 release_resource(chip->mpu_res);
2076 kfree_nocheck(chip->mpu_res);
2077 }
2078 if (chip->fm_res) {
2079 release_resource(chip->fm_res);
2080 kfree_nocheck(chip->fm_res);
2081 }
2082 snd_ymfpci_free_gameport(chip);
2083 if (chip->reg_area_virt)
2084 iounmap(chip->reg_area_virt);
2085 if (chip->work_ptr.area)
2086 snd_dma_free_pages(&chip->work_ptr);
2087
2088 if (chip->irq >= 0)
2089 free_irq(chip->irq, (void *)chip);
2090 if (chip->res_reg_area) {
2091 release_resource(chip->res_reg_area);
2092 kfree_nocheck(chip->res_reg_area);
2093 }
2094
2095 pci_write_config_word(chip->pci, 0x40, chip->old_legacy_ctrl);
2096
2097 pci_disable_device(chip->pci);
2098 kfree(chip);
2099 return 0;
2100 }
2101
2102 static int snd_ymfpci_dev_free(snd_device_t *device)
2103 {
2104 ymfpci_t *chip = device->device_data;
2105 return snd_ymfpci_free(chip);
2106 }
2107
2108 #ifdef CONFIG_PM
2109 static int saved_regs_index[] = {
2110 /* spdif */
2111 YDSXGR_SPDIFOUTCTRL,
2112 YDSXGR_SPDIFOUTSTATUS,
2113 YDSXGR_SPDIFINCTRL,
2114 /* volumes */
2115 YDSXGR_PRIADCLOOPVOL,
2116 YDSXGR_NATIVEDACINVOL,
2117 YDSXGR_NATIVEDACOUTVOL,
2118 // YDSXGR_BUF441OUTVOL,
2119 YDSXGR_NATIVEADCINVOL,
2120 YDSXGR_SPDIFLOOPVOL,
2121 YDSXGR_SPDIFOUTVOL,
2122 YDSXGR_ZVOUTVOL,
2123 YDSXGR_LEGACYOUTVOL,
2124 /* address bases */
2125 YDSXGR_PLAYCTRLBASE,
2126 YDSXGR_RECCTRLBASE,
2127 YDSXGR_EFFCTRLBASE,
2128 YDSXGR_WORKBASE,
2129 /* capture set up */
2130 YDSXGR_MAPOFREC,
2131 YDSXGR_RECFORMAT,
2132 YDSXGR_RECSLOTSR,
2133 YDSXGR_ADCFORMAT,
2134 YDSXGR_ADCSLOTSR,
2135 };
2136 #define YDSXGR_NUM_SAVED_REGS ARRAY_SIZE(saved_regs_index)
2137
2138 static int snd_ymfpci_suspend(snd_card_t *card, pm_message_t state)
2139 {
2140 ymfpci_t *chip = card->pm_private_data;
2141 unsigned int i;
2142
2143 snd_pcm_suspend_all(chip->pcm);
2144 snd_pcm_suspend_all(chip->pcm2);
2145 snd_pcm_suspend_all(chip->pcm_spdif);
2146 snd_pcm_suspend_all(chip->pcm_4ch);
2147 snd_ac97_suspend(chip->ac97);
2148 for (i = 0; i < YDSXGR_NUM_SAVED_REGS; i++)
2149 chip->saved_regs[i] = snd_ymfpci_readl(chip, saved_regs_index[i]);
2150 chip->saved_ydsxgr_mode = snd_ymfpci_readl(chip, YDSXGR_MODE);
2151 snd_ymfpci_writel(chip, YDSXGR_NATIVEDACOUTVOL, 0);
2152 snd_ymfpci_disable_dsp(chip);
2153 pci_disable_device(chip->pci);
2154 return 0;
2155 }
2156
2157 static int snd_ymfpci_resume(snd_card_t *card)
2158 {
2159 ymfpci_t *chip = card->pm_private_data;
2160 unsigned int i;
2161
2162 pci_enable_device(chip->pci);
2163 pci_set_master(chip->pci);
2164 snd_ymfpci_aclink_reset(chip->pci);
2165 snd_ymfpci_codec_ready(chip, 0);
2166 snd_ymfpci_download_image(chip);
2167 udelay(100);
2168
2169 for (i = 0; i < YDSXGR_NUM_SAVED_REGS; i++)
2170 snd_ymfpci_writel(chip, saved_regs_index[i], chip->saved_regs[i]);
2171
2172 snd_ac97_resume(chip->ac97);
2173
2174 /* start hw again */
2175 if (chip->start_count > 0) {
2176 spin_lock_irq(&chip->reg_lock);
2177 snd_ymfpci_writel(chip, YDSXGR_MODE, chip->saved_ydsxgr_mode);
2178 chip->active_bank = snd_ymfpci_readl(chip, YDSXGR_CTRLSELECT);
2179 spin_unlock_irq(&chip->reg_lock);
2180 }
2181 return 0;
2182 }
2183 #endif /* CONFIG_PM */
2184
2185 int __devinit snd_ymfpci_create(snd_card_t * card,
2186 struct pci_dev * pci,
2187 unsigned short old_legacy_ctrl,
2188 ymfpci_t ** rchip)
2189 {
2190 ymfpci_t *chip;
2191 int err;
2192 static snd_device_ops_t ops = {
2193 .dev_free = snd_ymfpci_dev_free,
2194 };
2195
2196 *rchip = NULL;
2197
2198 /* enable PCI device */
2199 if ((err = pci_enable_device(pci)) < 0)
2200 return err;
2201
2202 chip = kcalloc(1, sizeof(*chip), GFP_KERNEL);
2203 if (chip == NULL) {
2204 pci_disable_device(pci);
2205 return -ENOMEM;
2206 }
2207 chip->old_legacy_ctrl = old_legacy_ctrl;
2208 spin_lock_init(&chip->reg_lock);
2209 spin_lock_init(&chip->voice_lock);
2210 init_waitqueue_head(&chip->interrupt_sleep);
2211 atomic_set(&chip->interrupt_sleep_count, 0);
2212 chip->card = card;
2213 chip->pci = pci;
2214 chip->irq = -1;
2215 chip->device_id = pci->device;
2216 pci_read_config_byte(pci, PCI_REVISION_ID, (u8 *)&chip->rev);
2217 chip->reg_area_phys = pci_resource_start(pci, 0);
2218 chip->reg_area_virt = ioremap_nocache(chip->reg_area_phys, 0x8000);
2219 pci_set_master(pci);
2220
2221 if ((chip->res_reg_area = request_mem_region(chip->reg_area_phys, 0x8000, "YMFPCI")) == NULL) {
2222 snd_printk("unable to grab memory region 0x%lx-0x%lx\n", chip->reg_area_phys, chip->reg_area_phys + 0x8000 - 1);
2223 snd_ymfpci_free(chip);
2224 return -EBUSY;
2225 }
2226 if (request_irq(pci->irq, snd_ymfpci_interrupt, SA_INTERRUPT|SA_SHIRQ, "YMFPCI", (void *) chip)) {
2227 snd_printk("unable to grab IRQ %d\n", pci->irq);
2228 snd_ymfpci_free(chip);
2229 return -EBUSY;
2230 }
2231 chip->irq = pci->irq;
2232
2233 snd_ymfpci_aclink_reset(pci);
2234 if (snd_ymfpci_codec_ready(chip, 0) < 0) {
2235 snd_ymfpci_free(chip);
2236 return -EIO;
2237 }
2238
2239 snd_ymfpci_download_image(chip);
2240
2241 udelay(100); /* seems we need a delay after downloading image.. */
2242
2243 if (snd_ymfpci_memalloc(chip) < 0) {
2244 snd_ymfpci_free(chip);
2245 return -EIO;
2246 }
2247
2248 if ((err = snd_ymfpci_ac3_init(chip)) < 0) {
2249 snd_ymfpci_free(chip);
2250 return err;
2251 }
2252
2253 #ifdef CONFIG_PM
2254 chip->saved_regs = vmalloc(YDSXGR_NUM_SAVED_REGS * sizeof(u32));
2255 if (chip->saved_regs == NULL) {
2256 snd_ymfpci_free(chip);
2257 return -ENOMEM;
2258 }
2259 snd_card_set_pm_callback(card, snd_ymfpci_suspend, snd_ymfpci_resume, chip);
2260 #endif
2261
2262 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
2263 snd_ymfpci_free(chip);
2264 return err;
2265 }
2266
2267 snd_ymfpci_proc_init(card, chip);
2268
2269 snd_card_set_dev(card, &pci->dev);
2270
2271 *rchip = chip;
2272 return 0;
2273 }
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