1 #include <linux/init.h>
2 #include <linux/bitops.h>
5 #include <asm/processor.h>
10 * B step AMD K6 before B 9730xxxx have hardware bugs that can cause
11 * misexecution of code under Linux. Owners of such processors should
12 * contact AMD for precise details and a CPU swap.
14 * See http://www.multimania.com/poulot/k6bug.html
15 * http://www.amd.com/K6/k6docs/revgd.html
17 * The following test is erm.. interesting. AMD neglected to up
18 * the chip setting when fixing the bug but they also tweaked some
19 * performance at the same time..
22 extern void vide(void);
23 __asm__(".align 4\nvide: ret");
25 static void __init
init_amd(struct cpuinfo_x86
*c
)
28 int mbytes
= num_physpages
>> (20-PAGE_SHIFT
);
32 unsigned long long value
;
34 /* Disable TLB flush filter by setting HWCR.FFDIS on K8
35 * bit 6 of msr C001_0015
37 * Errata 63 for SH-B3 steppings
38 * Errata 122 for all steppings (F+ have it disabled by default)
41 rdmsrl(MSR_K7_HWCR
, value
);
43 wrmsrl(MSR_K7_HWCR
, value
);
48 * FIXME: We should handle the K5 here. Set up the write
49 * range and also turn on MSR 83 bits 4 and 31 (write alloc,
53 /* Bit 31 in normal CPUID used for nonstandard 3DNow ID;
54 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway */
55 clear_bit(0*32+31, c
->x86_capability
);
57 r
= get_model_name(c
);
63 * General Systems BIOSen alias the cpu frequency registers
64 * of the Elan at 0x000df000. Unfortuantly, one of the Linux
65 * drivers subsequently pokes it, and changes the CPU speed.
66 * Workaround : Remove the unneeded alias.
68 #define CBAR (0xfffc) /* Configuration Base Address (32-bit) */
69 #define CBAR_ENB (0x80000000)
70 #define CBAR_KEY (0X000000CB)
71 if (c
->x86_model
==9 || c
->x86_model
== 10) {
72 if (inl (CBAR
) & CBAR_ENB
)
73 outl (0 | CBAR_KEY
, CBAR
);
77 if( c
->x86_model
< 6 )
79 /* Based on AMD doc 20734R - June 2000 */
80 if ( c
->x86_model
== 0 ) {
81 clear_bit(X86_FEATURE_APIC
, c
->x86_capability
);
82 set_bit(X86_FEATURE_PGE
, c
->x86_capability
);
87 if ( c
->x86_model
== 6 && c
->x86_mask
== 1 ) {
88 const int K6_BUG_LOOP
= 1000000;
93 printk(KERN_INFO
"AMD K6 stepping B detected - ");
96 * It looks like AMD fixed the 2.6.2 bug and improved indirect
97 * calls at the same time.
108 /* Knock these two lines out if it debugs out ok */
109 printk(KERN_INFO
"AMD K6 stepping B detected - ");
111 if (d
> 20*K6_BUG_LOOP
)
112 printk("system stability may be impaired when more than 32 MB are used.\n");
114 printk("probably OK (after B9730xxxx).\n");
115 printk(KERN_INFO
"Please see http://membres.lycos.fr/poulot/k6bug.html\n");
118 /* K6 with old style WHCR */
119 if (c
->x86_model
< 8 ||
120 (c
->x86_model
== 8 && c
->x86_mask
< 8)) {
121 /* We can only write allocate on the low 508Mb */
125 rdmsr(MSR_K6_WHCR
, l
, h
);
126 if ((l
&0x0000FFFF)==0) {
128 l
=(1<<0)|((mbytes
/4)<<1);
129 local_irq_save(flags
);
131 wrmsr(MSR_K6_WHCR
, l
, h
);
132 local_irq_restore(flags
);
133 printk(KERN_INFO
"Enabling old style K6 write allocation for %d Mb\n",
139 if ((c
->x86_model
== 8 && c
->x86_mask
>7) ||
140 c
->x86_model
== 9 || c
->x86_model
== 13) {
141 /* The more serious chips .. */
146 rdmsr(MSR_K6_WHCR
, l
, h
);
147 if ((l
&0xFFFF0000)==0) {
149 l
=((mbytes
>>2)<<22)|(1<<16);
150 local_irq_save(flags
);
152 wrmsr(MSR_K6_WHCR
, l
, h
);
153 local_irq_restore(flags
);
154 printk(KERN_INFO
"Enabling new style K6 write allocation for %d Mb\n",
158 /* Set MTRR capability flag if appropriate */
159 if (c
->x86_model
== 13 || c
->x86_model
== 9 ||
160 (c
->x86_model
== 8 && c
->x86_mask
>= 8))
161 set_bit(X86_FEATURE_K6_MTRR
, c
->x86_capability
);
166 case 6: /* An Athlon/Duron */
168 /* Bit 15 of Athlon specific MSR 15, needs to be 0
169 * to enable SSE on Palomino/Morgan/Barton CPU's.
170 * If the BIOS didn't enable it already, enable it here.
172 if (c
->x86_model
>= 6 && c
->x86_model
<= 10) {
173 if (!cpu_has(c
, X86_FEATURE_XMM
)) {
174 printk(KERN_INFO
"Enabling disabled K7/SSE Support.\n");
175 rdmsr(MSR_K7_HWCR
, l
, h
);
177 wrmsr(MSR_K7_HWCR
, l
, h
);
178 set_bit(X86_FEATURE_XMM
, c
->x86_capability
);
182 /* It's been determined by AMD that Athlons since model 8 stepping 1
183 * are more robust with CLK_CTL set to 200xxxxx instead of 600xxxxx
184 * As per AMD technical note 27212 0.2
186 if ((c
->x86_model
== 8 && c
->x86_mask
>=1) || (c
->x86_model
> 8)) {
187 rdmsr(MSR_K7_CLK_CTL
, l
, h
);
188 if ((l
& 0xfff00000) != 0x20000000) {
189 printk ("CPU: CLK_CTL MSR was %x. Reprogramming to %x\n", l
,
190 ((l
& 0x000fffff)|0x20000000));
191 wrmsr(MSR_K7_CLK_CTL
, (l
& 0x000fffff)|0x20000000, h
);
199 set_bit(X86_FEATURE_K8
, c
->x86_capability
);
202 set_bit(X86_FEATURE_K7
, c
->x86_capability
);
206 display_cacheinfo(c
);
208 if (cpuid_eax(0x80000000) >= 0x80000008) {
209 c
->x86_num_cores
= (cpuid_ecx(0x80000008) & 0xff) + 1;
210 if (c
->x86_num_cores
& (c
->x86_num_cores
- 1))
211 c
->x86_num_cores
= 1;
216 * On a AMD dual core setup the lower bits of the APIC id
217 * distingush the cores. Assumes number of cores is a power
220 if (c
->x86_num_cores
> 1) {
221 int cpu
= smp_processor_id();
223 while ((1 << bits
) < c
->x86_num_cores
)
225 cpu_core_id
[cpu
] = phys_proc_id
[cpu
] & ((1<<bits
)-1);
226 phys_proc_id
[cpu
] >>= bits
;
227 printk(KERN_INFO
"CPU %d(%d) -> Core %d\n",
228 cpu
, c
->x86_num_cores
, cpu_core_id
[cpu
]);
233 static unsigned int amd_size_cache(struct cpuinfo_x86
* c
, unsigned int size
)
235 /* AMD errata T13 (order #21922) */
237 if (c
->x86_model
== 3 && c
->x86_mask
== 0) /* Duron Rev A0 */
239 if (c
->x86_model
== 4 &&
240 (c
->x86_mask
==0 || c
->x86_mask
==1)) /* Tbird rev A1/A2 */
246 static struct cpu_dev amd_cpu_dev __initdata
= {
248 .c_ident
= { "AuthenticAMD" },
250 { .vendor
= X86_VENDOR_AMD
, .family
= 4, .model_names
=
262 .c_identify
= generic_identify
,
263 .c_size_cache
= amd_size_cache
,
266 int __init
amd_init_cpu(void)
268 cpu_devs
[X86_VENDOR_AMD
] = &amd_cpu_dev
;
272 //early_arch_initcall(amd_init_cpu);