include/asm-ia64/sn/pcibr_provider.h

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 1992-1997,2000-2004 Silicon Graphics, Inc. All rights reserved.
   7  */
   8 #ifndef _ASM_IA64_SN_PCI_PCIBR_PROVIDER_H
   9 #define _ASM_IA64_SN_PCI_PCIBR_PROVIDER_H
  10
  11 #include <asm/sn/intr.h>
  12 #include <asm/sn/pcibus_provider_defs.h>
  13
  14 /* Workarounds */
  15 #define PV907516 (1 << 1) /* TIOCP: Don't write the write buffer flush reg */
  16
  17 #define BUSTYPE_MASK                    0x1
  18
  19 /* Macros given a pcibus structure */
  20 #define IS_PCIX(ps)     ((ps)->pbi_bridge_mode & BUSTYPE_MASK)
  21 #define IS_PCI_BRIDGE_ASIC(asic) (asic == PCIIO_ASIC_TYPE_PIC || \
  22                 asic == PCIIO_ASIC_TYPE_TIOCP)
  23 #define IS_PIC_SOFT(ps)     (ps->pbi_bridge_type == PCIBR_BRIDGETYPE_PIC)
  24
  25
  26 /*
  27  * The different PCI Bridge types supported on the SGI Altix platforms
  28  */
  29 #define PCIBR_BRIDGETYPE_UNKNOWN       -1
  30 #define PCIBR_BRIDGETYPE_PIC            2
  31 #define PCIBR_BRIDGETYPE_TIOCP          3
  32
  33 /*
  34  * Bridge 64bit Direct Map Attributes
  35  */
  36 #define PCI64_ATTR_PREF                 (1ull << 59)
  37 #define PCI64_ATTR_PREC                 (1ull << 58)
  38 #define PCI64_ATTR_VIRTUAL              (1ull << 57)
  39 #define PCI64_ATTR_BAR                  (1ull << 56)
  40 #define PCI64_ATTR_SWAP                 (1ull << 55)
  41 #define PCI64_ATTR_VIRTUAL1             (1ull << 54)
  42
  43 #define PCI32_LOCAL_BASE                0
  44 #define PCI32_MAPPED_BASE               0x40000000
  45 #define PCI32_DIRECT_BASE               0x80000000
  46
  47 #define IS_PCI32_MAPPED(x)              ((uint64_t)(x) < PCI32_DIRECT_BASE && \
  48                                          (uint64_t)(x) >= PCI32_MAPPED_BASE)
  49 #define IS_PCI32_DIRECT(x)              ((uint64_t)(x) >= PCI32_MAPPED_BASE)
  50
  51
  52 /*
  53  * Bridge PMU Address Transaltion Entry Attibutes
  54  */
  55 #define PCI32_ATE_V                     (0x1 << 0)
  56 #define PCI32_ATE_CO                    (0x1 << 1)
  57 #define PCI32_ATE_PREC                  (0x1 << 2)
  58 #define PCI32_ATE_PREF                  (0x1 << 3)
  59 #define PCI32_ATE_BAR                   (0x1 << 4)
  60 #define PCI32_ATE_ADDR_SHFT             12
  61
  62 #define MINIMAL_ATES_REQUIRED(addr, size) \
  63         (IOPG(IOPGOFF(addr) + (size) - 1) == IOPG((size) - 1))
  64
  65 #define MINIMAL_ATE_FLAG(addr, size) \
  66         (MINIMAL_ATES_REQUIRED((uint64_t)addr, size) ? 1 : 0)
  67
  68 /* bit 29 of the pci address is the SWAP bit */
  69 #define ATE_SWAPSHIFT                   29
  70 #define ATE_SWAP_ON(x)                  ((x) |= (1 << ATE_SWAPSHIFT))
  71 #define ATE_SWAP_OFF(x)                 ((x) &= ~(1 << ATE_SWAPSHIFT))
  72
  73 /*
  74  * I/O page size
  75  */
  76 #if PAGE_SIZE < 16384
  77 #define IOPFNSHIFT                      12      /* 4K per mapped page */
  78 #else
  79 #define IOPFNSHIFT                      14      /* 16K per mapped page */
  80 #endif
  81
  82 #define IOPGSIZE                        (1 << IOPFNSHIFT)
  83 #define IOPG(x)                         ((x) >> IOPFNSHIFT)
  84 #define IOPGOFF(x)                      ((x) & (IOPGSIZE-1))
  85
  86 #define PCIBR_DEV_SWAP_DIR              (1ull << 19)
  87 #define PCIBR_CTRL_PAGE_SIZE            (0x1 << 21)
  88
  89 /*
  90  * PMU resources.
  91  */
  92 struct ate_resource{
  93         uint64_t *ate;
  94         uint64_t num_ate;
  95         uint64_t lowest_free_index;
  96 };
  97
  98 struct pcibus_info {
  99         struct pcibus_bussoft   pbi_buscommon;   /* common header */
 100         uint32_t                pbi_moduleid;
 101         short                   pbi_bridge_type;
 102         short                   pbi_bridge_mode;
 103
 104         struct ate_resource     pbi_int_ate_resource;
 105         uint64_t                pbi_int_ate_size;
 106
 107         uint64_t                pbi_dir_xbase;
 108         char                    pbi_hub_xid;
 109
 110         uint64_t                pbi_devreg[8];
 111
 112         uint32_t                pbi_valid_devices;
 113         uint32_t                pbi_enabled_devices;
 114
 115         spinlock_t              pbi_lock;
 116 };
 117
 118 /*
 119  * pcibus_info structure locking macros
 120  */
 121 inline static unsigned long
 122 pcibr_lock(struct pcibus_info *pcibus_info)
 123 {
 124         unsigned long flag;
 125         spin_lock_irqsave(&pcibus_info->pbi_lock, flag);
 126         return(flag);
 127 }
 128 #define pcibr_unlock(pcibus_info, flag)  spin_unlock_irqrestore(&pcibus_info->pbi_lock, flag)
 129
 130 extern int  pcibr_init_provider(void);
 131 extern void *pcibr_bus_fixup(struct pcibus_bussoft *, struct pci_controller *);
 132 extern dma_addr_t pcibr_dma_map(struct pci_dev *, unsigned long, size_t);
 133 extern dma_addr_t pcibr_dma_map_consistent(struct pci_dev *, unsigned long, size_t);
 134 extern void pcibr_dma_unmap(struct pci_dev *, dma_addr_t, int);
 135
 136 /*
 137  * prototypes for the bridge asic register access routines in pcibr_reg.c
 138  */
 139 extern void             pcireg_control_bit_clr(struct pcibus_info *, uint64_t);
 140 extern void             pcireg_control_bit_set(struct pcibus_info *, uint64_t);
 141 extern uint64_t         pcireg_tflush_get(struct pcibus_info *);
 142 extern uint64_t         pcireg_intr_status_get(struct pcibus_info *);
 143 extern void             pcireg_intr_enable_bit_clr(struct pcibus_info *, uint64_t);
 144 extern void             pcireg_intr_enable_bit_set(struct pcibus_info *, uint64_t);
 145 extern void             pcireg_intr_addr_addr_set(struct pcibus_info *, int, uint64_t);
 146 extern void             pcireg_force_intr_set(struct pcibus_info *, int);
 147 extern uint64_t         pcireg_wrb_flush_get(struct pcibus_info *, int);
 148 extern void             pcireg_int_ate_set(struct pcibus_info *, int, uint64_t);
 149 extern uint64_t *       pcireg_int_ate_addr(struct pcibus_info *, int);
 150 extern void             pcibr_force_interrupt(struct sn_irq_info *sn_irq_info);
 151 extern void             pcibr_change_devices_irq(struct sn_irq_info *sn_irq_info);
 152 extern int              pcibr_ate_alloc(struct pcibus_info *, int);
 153 extern void             pcibr_ate_free(struct pcibus_info *, int);
 154 extern void             ate_write(struct pcibus_info *, int, int, uint64_t);
 155 extern int sal_pcibr_slot_enable(struct pcibus_info *soft, int device,
 156                                  void *resp);
 157 extern int sal_pcibr_slot_disable(struct pcibus_info *soft, int device,
 158                                   int action, void *resp);
 159 #endif