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powerpc: Merge asm/irq.h
[linux-2.6/verdex.git] / include / asm-powerpc / ppc_asm.h
blobe4350e406d2a14b524b57ae2b29b286f386e815e
1 /*
2 * Copyright (C) 1995-1999 Gary Thomas, Paul Mackerras, Cort Dougan.
3 */
4 #ifndef _ASM_POWERPC_PPC_ASM_H
5 #define _ASM_POWERPC_PPC_ASM_H
6
7 #include <linux/stringify.h>
8 #include <linux/config.h>
9
10 #ifdef __ASSEMBLY__
11
12 /*
13 * Macros for storing registers into and loading registers from
14 * exception frames.
15 */
16 #ifdef __powerpc64__
17 #define SAVE_GPR(n, base) std n,GPR0+8*(n)(base)
18 #define REST_GPR(n, base) ld n,GPR0+8*(n)(base)
19 #define SAVE_NVGPRS(base) SAVE_8GPRS(14, base); SAVE_10GPRS(22, base)
20 #define REST_NVGPRS(base) REST_8GPRS(14, base); REST_10GPRS(22, base)
21 #else
22 #define SAVE_GPR(n, base) stw n,GPR0+4*(n)(base)
23 #define REST_GPR(n, base) lwz n,GPR0+4*(n)(base)
24 #define SAVE_NVGPRS(base) SAVE_GPR(13, base); SAVE_8GPRS(14, base); \
25 SAVE_10GPRS(22, base)
26 #define REST_NVGPRS(base) REST_GPR(13, base); REST_8GPRS(14, base); \
27 REST_10GPRS(22, base)
28 #endif
29
30
31 #define SAVE_2GPRS(n, base) SAVE_GPR(n, base); SAVE_GPR(n+1, base)
32 #define SAVE_4GPRS(n, base) SAVE_2GPRS(n, base); SAVE_2GPRS(n+2, base)
33 #define SAVE_8GPRS(n, base) SAVE_4GPRS(n, base); SAVE_4GPRS(n+4, base)
34 #define SAVE_10GPRS(n, base) SAVE_8GPRS(n, base); SAVE_2GPRS(n+8, base)
35 #define REST_2GPRS(n, base) REST_GPR(n, base); REST_GPR(n+1, base)
36 #define REST_4GPRS(n, base) REST_2GPRS(n, base); REST_2GPRS(n+2, base)
37 #define REST_8GPRS(n, base) REST_4GPRS(n, base); REST_4GPRS(n+4, base)
38 #define REST_10GPRS(n, base) REST_8GPRS(n, base); REST_2GPRS(n+8, base)
39
40 #define SAVE_FPR(n, base) stfd n,THREAD_FPR0+8*(n)(base)
41 #define SAVE_2FPRS(n, base) SAVE_FPR(n, base); SAVE_FPR(n+1, base)
42 #define SAVE_4FPRS(n, base) SAVE_2FPRS(n, base); SAVE_2FPRS(n+2, base)
43 #define SAVE_8FPRS(n, base) SAVE_4FPRS(n, base); SAVE_4FPRS(n+4, base)
44 #define SAVE_16FPRS(n, base) SAVE_8FPRS(n, base); SAVE_8FPRS(n+8, base)
45 #define SAVE_32FPRS(n, base) SAVE_16FPRS(n, base); SAVE_16FPRS(n+16, base)
46 #define REST_FPR(n, base) lfd n,THREAD_FPR0+8*(n)(base)
47 #define REST_2FPRS(n, base) REST_FPR(n, base); REST_FPR(n+1, base)
48 #define REST_4FPRS(n, base) REST_2FPRS(n, base); REST_2FPRS(n+2, base)
49 #define REST_8FPRS(n, base) REST_4FPRS(n, base); REST_4FPRS(n+4, base)
50 #define REST_16FPRS(n, base) REST_8FPRS(n, base); REST_8FPRS(n+8, base)
51 #define REST_32FPRS(n, base) REST_16FPRS(n, base); REST_16FPRS(n+16, base)
52
53 #define SAVE_VR(n,b,base) li b,THREAD_VR0+(16*(n)); stvx n,b,base
54 #define SAVE_2VRS(n,b,base) SAVE_VR(n,b,base); SAVE_VR(n+1,b,base)
55 #define SAVE_4VRS(n,b,base) SAVE_2VRS(n,b,base); SAVE_2VRS(n+2,b,base)
56 #define SAVE_8VRS(n,b,base) SAVE_4VRS(n,b,base); SAVE_4VRS(n+4,b,base)
57 #define SAVE_16VRS(n,b,base) SAVE_8VRS(n,b,base); SAVE_8VRS(n+8,b,base)
58 #define SAVE_32VRS(n,b,base) SAVE_16VRS(n,b,base); SAVE_16VRS(n+16,b,base)
59 #define REST_VR(n,b,base) li b,THREAD_VR0+(16*(n)); lvx n,b,base
60 #define REST_2VRS(n,b,base) REST_VR(n,b,base); REST_VR(n+1,b,base)
61 #define REST_4VRS(n,b,base) REST_2VRS(n,b,base); REST_2VRS(n+2,b,base)
62 #define REST_8VRS(n,b,base) REST_4VRS(n,b,base); REST_4VRS(n+4,b,base)
63 #define REST_16VRS(n,b,base) REST_8VRS(n,b,base); REST_8VRS(n+8,b,base)
64 #define REST_32VRS(n,b,base) REST_16VRS(n,b,base); REST_16VRS(n+16,b,base)
65
66 #define SAVE_EVR(n,s,base) evmergehi s,s,n; stw s,THREAD_EVR0+4*(n)(base)
67 #define SAVE_2EVRS(n,s,base) SAVE_EVR(n,s,base); SAVE_EVR(n+1,s,base)
68 #define SAVE_4EVRS(n,s,base) SAVE_2EVRS(n,s,base); SAVE_2EVRS(n+2,s,base)
69 #define SAVE_8EVRS(n,s,base) SAVE_4EVRS(n,s,base); SAVE_4EVRS(n+4,s,base)
70 #define SAVE_16EVRS(n,s,base) SAVE_8EVRS(n,s,base); SAVE_8EVRS(n+8,s,base)
71 #define SAVE_32EVRS(n,s,base) SAVE_16EVRS(n,s,base); SAVE_16EVRS(n+16,s,base)
72 #define REST_EVR(n,s,base) lwz s,THREAD_EVR0+4*(n)(base); evmergelo n,s,n
73 #define REST_2EVRS(n,s,base) REST_EVR(n,s,base); REST_EVR(n+1,s,base)
74 #define REST_4EVRS(n,s,base) REST_2EVRS(n,s,base); REST_2EVRS(n+2,s,base)
75 #define REST_8EVRS(n,s,base) REST_4EVRS(n,s,base); REST_4EVRS(n+4,s,base)
76 #define REST_16EVRS(n,s,base) REST_8EVRS(n,s,base); REST_8EVRS(n+8,s,base)
77 #define REST_32EVRS(n,s,base) REST_16EVRS(n,s,base); REST_16EVRS(n+16,s,base)
78
79 /* Macros to adjust thread priority for Iseries hardware multithreading */
80 #define HMT_VERY_LOW or 31,31,31 # very low priority\n"
81 #define HMT_LOW or 1,1,1
82 #define HMT_MEDIUM_LOW or 6,6,6 # medium low priority\n"
83 #define HMT_MEDIUM or 2,2,2
84 #define HMT_MEDIUM_HIGH or 5,5,5 # medium high priority\n"
85 #define HMT_HIGH or 3,3,3
86
87 /* handle instructions that older assemblers may not know */
88 #define RFCI .long 0x4c000066 /* rfci instruction */
89 #define RFDI .long 0x4c00004e /* rfdi instruction */
90 #define RFMCI .long 0x4c00004c /* rfmci instruction */
91
92 #ifdef CONFIG_PPC64
93
94 #define XGLUE(a,b) a##b
95 #define GLUE(a,b) XGLUE(a,b)
96
97 #define _GLOBAL(name) \
98 .section ".text"; \
99 .align 2 ; \
100 .globl name; \
101 .globl GLUE(.,name); \
102 .section ".opd","aw"; \
103 name: \
104 .quad GLUE(.,name); \
105 .quad .TOC.@tocbase; \
106 .quad 0; \
107 .previous; \
108 .type GLUE(.,name),@function; \
109 GLUE(.,name):
110
111 #define _KPROBE(name) \
112 .section ".kprobes.text","a"; \
113 .align 2 ; \
114 .globl name; \
115 .globl GLUE(.,name); \
116 .section ".opd","aw"; \
117 name: \
118 .quad GLUE(.,name); \
119 .quad .TOC.@tocbase; \
120 .quad 0; \
121 .previous; \
122 .type GLUE(.,name),@function; \
123 GLUE(.,name):
124
125 #define _STATIC(name) \
126 .section ".text"; \
127 .align 2 ; \
128 .section ".opd","aw"; \
129 name: \
130 .quad GLUE(.,name); \
131 .quad .TOC.@tocbase; \
132 .quad 0; \
133 .previous; \
134 .type GLUE(.,name),@function; \
135 GLUE(.,name):
136
137 #else /* 32-bit */
138
139 #define _GLOBAL(n) \
140 .text; \
141 .stabs __stringify(n:F-1),N_FUN,0,0,n;\
142 .globl n; \
143 n:
144
145 #define _KPROBE(n) \
146 .section ".kprobes.text","a"; \
147 .globl n; \
148 n:
149
150 #endif
151
152 /*
153 * LOADADDR( rn, name )
154 * loads the address of 'name' into 'rn'
155 *
156 * LOADBASE( rn, name )
157 * loads the address (less the low 16 bits) of 'name' into 'rn'
158 * suitable for base+disp addressing
159 */
160 #ifdef __powerpc64__
161 #define LOADADDR(rn,name) \
162 lis rn,name##@highest; \
163 ori rn,rn,name##@higher; \
164 rldicr rn,rn,32,31; \
165 oris rn,rn,name##@h; \
166 ori rn,rn,name##@l
167
168 #define LOADBASE(rn,name) \
169 .section .toc,"aw"; \
170 1: .tc name[TC],name; \
171 .previous; \
172 ld rn,1b@toc(r2)
173
174 #define OFF(name) 0
175
176 #define SET_REG_TO_CONST(reg, value) \
177 lis reg,(((value)>>48)&0xFFFF); \
178 ori reg,reg,(((value)>>32)&0xFFFF); \
179 rldicr reg,reg,32,31; \
180 oris reg,reg,(((value)>>16)&0xFFFF); \
181 ori reg,reg,((value)&0xFFFF);
182
183 #define SET_REG_TO_LABEL(reg, label) \
184 lis reg,(label)@highest; \
185 ori reg,reg,(label)@higher; \
186 rldicr reg,reg,32,31; \
187 oris reg,reg,(label)@h; \
188 ori reg,reg,(label)@l;
189
190 /* operations for longs and pointers */
191 #define LDL ld
192 #define STL std
193 #define CMPI cmpdi
194
195 #else /* 32-bit */
196 #define LOADBASE(rn,name) \
197 lis rn,name@ha
198
199 #define OFF(name) name@l
200
201 /* operations for longs and pointers */
202 #define LDL lwz
203 #define STL stw
204 #define CMPI cmpwi
205
206 #endif
207
208 /* various errata or part fixups */
209 #ifdef CONFIG_PPC601_SYNC_FIX
210 #define SYNC \
211 BEGIN_FTR_SECTION \
212 sync; \
213 isync; \
214 END_FTR_SECTION_IFSET(CPU_FTR_601)
215 #define SYNC_601 \
216 BEGIN_FTR_SECTION \
217 sync; \
218 END_FTR_SECTION_IFSET(CPU_FTR_601)
219 #define ISYNC_601 \
220 BEGIN_FTR_SECTION \
221 isync; \
222 END_FTR_SECTION_IFSET(CPU_FTR_601)
223 #else
224 #define SYNC
225 #define SYNC_601
226 #define ISYNC_601
227 #endif
228
229
230 #ifndef CONFIG_SMP
231 #define TLBSYNC
232 #else /* CONFIG_SMP */
233 /* tlbsync is not implemented on 601 */
234 #define TLBSYNC \
235 BEGIN_FTR_SECTION \
236 tlbsync; \
237 sync; \
238 END_FTR_SECTION_IFCLR(CPU_FTR_601)
239 #endif
240
241
242 /*
243 * This instruction is not implemented on the PPC 603 or 601; however, on
244 * the 403GCX and 405GP tlbia IS defined and tlbie is not.
245 * All of these instructions exist in the 8xx, they have magical powers,
246 * and they must be used.
247 */
248
249 #if !defined(CONFIG_4xx) && !defined(CONFIG_8xx)
250 #define tlbia \
251 li r4,1024; \
252 mtctr r4; \
253 lis r4,KERNELBASE@h; \
254 0: tlbie r4; \
255 addi r4,r4,0x1000; \
256 bdnz 0b
257 #endif
258
259
260 #ifdef CONFIG_IBM405_ERR77
261 #define PPC405_ERR77(ra,rb) dcbt ra, rb;
262 #define PPC405_ERR77_SYNC sync;
263 #else
264 #define PPC405_ERR77(ra,rb)
265 #define PPC405_ERR77_SYNC
266 #endif
267
268
269 #ifdef CONFIG_IBM440EP_ERR42
270 #define PPC440EP_ERR42 isync
271 #else
272 #define PPC440EP_ERR42
273 #endif
274
275
276 #if defined(CONFIG_BOOKE)
277 #define tophys(rd,rs) \
278 addis rd,rs,0
279
280 #define tovirt(rd,rs) \
281 addis rd,rs,0
282
283 #elif defined(CONFIG_PPC64)
284 /* PPPBBB - DRENG If KERNELBASE is always 0xC0...,
285 * Then we can easily do this with one asm insn. -Peter
286 */
287 #define tophys(rd,rs) \
288 lis rd,((KERNELBASE>>48)&0xFFFF); \
289 rldicr rd,rd,32,31; \
290 sub rd,rs,rd
291
292 #define tovirt(rd,rs) \
293 lis rd,((KERNELBASE>>48)&0xFFFF); \
294 rldicr rd,rd,32,31; \
295 add rd,rs,rd
296 #else
297 /*
298 * On APUS (Amiga PowerPC cpu upgrade board), we don't know the
299 * physical base address of RAM at compile time.
300 */
301 #define tophys(rd,rs) \
302 0: addis rd,rs,-KERNELBASE@h; \
303 .section ".vtop_fixup","aw"; \
304 .align 1; \
305 .long 0b; \
306 .previous
307
308 #define tovirt(rd,rs) \
309 0: addis rd,rs,KERNELBASE@h; \
310 .section ".ptov_fixup","aw"; \
311 .align 1; \
312 .long 0b; \
313 .previous
314 #endif
315
316 #ifdef CONFIG_PPC64
317 #define RFI rfid
318 #define MTMSRD(r) mtmsrd r
319
320 #else
321 #define FIX_SRR1(ra, rb)
322 #ifndef CONFIG_40x
323 #define RFI rfi
324 #else
325 #define RFI rfi; b . /* Prevent prefetch past rfi */
326 #endif
327 #define MTMSRD(r) mtmsr r
328 #define CLR_TOP32(r)
329 #endif
330
331 /* The boring bits... */
332
333 /* Condition Register Bit Fields */
334
335 #define cr0 0
336 #define cr1 1
337 #define cr2 2
338 #define cr3 3
339 #define cr4 4
340 #define cr5 5
341 #define cr6 6
342 #define cr7 7
343
344
345 /* General Purpose Registers (GPRs) */
346
347 #define r0 0
348 #define r1 1
349 #define r2 2
350 #define r3 3
351 #define r4 4
352 #define r5 5
353 #define r6 6
354 #define r7 7
355 #define r8 8
356 #define r9 9
357 #define r10 10
358 #define r11 11
359 #define r12 12
360 #define r13 13
361 #define r14 14
362 #define r15 15
363 #define r16 16
364 #define r17 17
365 #define r18 18
366 #define r19 19
367 #define r20 20
368 #define r21 21
369 #define r22 22
370 #define r23 23
371 #define r24 24
372 #define r25 25
373 #define r26 26
374 #define r27 27
375 #define r28 28
376 #define r29 29
377 #define r30 30
378 #define r31 31
379
380
381 /* Floating Point Registers (FPRs) */
382
383 #define fr0 0
384 #define fr1 1
385 #define fr2 2
386 #define fr3 3
387 #define fr4 4
388 #define fr5 5
389 #define fr6 6
390 #define fr7 7
391 #define fr8 8
392 #define fr9 9
393 #define fr10 10
394 #define fr11 11
395 #define fr12 12
396 #define fr13 13
397 #define fr14 14
398 #define fr15 15
399 #define fr16 16
400 #define fr17 17
401 #define fr18 18
402 #define fr19 19
403 #define fr20 20
404 #define fr21 21
405 #define fr22 22
406 #define fr23 23
407 #define fr24 24
408 #define fr25 25
409 #define fr26 26
410 #define fr27 27
411 #define fr28 28
412 #define fr29 29
413 #define fr30 30
414 #define fr31 31
415
416 /* AltiVec Registers (VPRs) */
417
418 #define vr0 0
419 #define vr1 1
420 #define vr2 2
421 #define vr3 3
422 #define vr4 4
423 #define vr5 5
424 #define vr6 6
425 #define vr7 7
426 #define vr8 8
427 #define vr9 9
428 #define vr10 10
429 #define vr11 11
430 #define vr12 12
431 #define vr13 13
432 #define vr14 14
433 #define vr15 15
434 #define vr16 16
435 #define vr17 17
436 #define vr18 18
437 #define vr19 19
438 #define vr20 20
439 #define vr21 21
440 #define vr22 22
441 #define vr23 23
442 #define vr24 24
443 #define vr25 25
444 #define vr26 26
445 #define vr27 27
446 #define vr28 28
447 #define vr29 29
448 #define vr30 30
449 #define vr31 31
450
451 /* SPE Registers (EVPRs) */
452
453 #define evr0 0
454 #define evr1 1
455 #define evr2 2
456 #define evr3 3
457 #define evr4 4
458 #define evr5 5
459 #define evr6 6
460 #define evr7 7
461 #define evr8 8
462 #define evr9 9
463 #define evr10 10
464 #define evr11 11
465 #define evr12 12
466 #define evr13 13
467 #define evr14 14
468 #define evr15 15
469 #define evr16 16
470 #define evr17 17
471 #define evr18 18
472 #define evr19 19
473 #define evr20 20
474 #define evr21 21
475 #define evr22 22
476 #define evr23 23
477 #define evr24 24
478 #define evr25 25
479 #define evr26 26
480 #define evr27 27
481 #define evr28 28
482 #define evr29 29
483 #define evr30 30
484 #define evr31 31
485
486 /* some stab codes */
487 #define N_FUN 36
488 #define N_RSYM 64
489 #define N_SLINE 68
490 #define N_SO 100
491
492 #define ASM_CONST(x) x
493 #else
494 #define __ASM_CONST(x) x##UL
495 #define ASM_CONST(x) __ASM_CONST(x)
496 #endif /* __ASSEMBLY__ */
497
498 #endif /* _ASM_POWERPC_PPC_ASM_H */
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