include/asm-powerpc/system.h

   1 /*
   2  * Copyright (C) 1999 Cort Dougan <cort@cs.nmt.edu>
   3  */
   4 #ifndef _ASM_POWERPC_SYSTEM_H
   5 #define _ASM_POWERPC_SYSTEM_H
   6
   7 #include <linux/config.h>
   8 #include <linux/kernel.h>
   9
  10 #include <asm/hw_irq.h>
  11 #include <asm/ppc_asm.h>
  12 #include <asm/atomic.h>
  13
  14 /*
  15  * Memory barrier.
  16  * The sync instruction guarantees that all memory accesses initiated
  17  * by this processor have been performed (with respect to all other
  18  * mechanisms that access memory).  The eieio instruction is a barrier
  19  * providing an ordering (separately) for (a) cacheable stores and (b)
  20  * loads and stores to non-cacheable memory (e.g. I/O devices).
  21  *
  22  * mb() prevents loads and stores being reordered across this point.
  23  * rmb() prevents loads being reordered across this point.
  24  * wmb() prevents stores being reordered across this point.
  25  * read_barrier_depends() prevents data-dependent loads being reordered
  26  *      across this point (nop on PPC).
  27  *
  28  * We have to use the sync instructions for mb(), since lwsync doesn't
  29  * order loads with respect to previous stores.  Lwsync is fine for
  30  * rmb(), though.  Note that lwsync is interpreted as sync by
  31  * 32-bit and older 64-bit CPUs.
  32  *
  33  * For wmb(), we use sync since wmb is used in drivers to order
  34  * stores to system memory with respect to writes to the device.
  35  * However, smp_wmb() can be a lighter-weight eieio barrier on
  36  * SMP since it is only used to order updates to system memory.
  37  */
  38 #define mb()   __asm__ __volatile__ ("sync" : : : "memory")
  39 #define rmb()  __asm__ __volatile__ ("lwsync" : : : "memory")
  40 #define wmb()  __asm__ __volatile__ ("sync" : : : "memory")
  41 #define read_barrier_depends()  do { } while(0)
  42
  43 #define set_mb(var, value)      do { var = value; mb(); } while (0)
  44 #define set_wmb(var, value)     do { var = value; wmb(); } while (0)
  45
  46 #ifdef CONFIG_SMP
  47 #define smp_mb()        mb()
  48 #define smp_rmb()       rmb()
  49 #define smp_wmb()       __asm__ __volatile__ ("eieio" : : : "memory")
  50 #define smp_read_barrier_depends()      read_barrier_depends()
  51 #else
  52 #define smp_mb()        barrier()
  53 #define smp_rmb()       barrier()
  54 #define smp_wmb()       barrier()
  55 #define smp_read_barrier_depends()      do { } while(0)
  56 #endif /* CONFIG_SMP */
  57
  58 #ifdef __KERNEL__
  59 struct task_struct;
  60 struct pt_regs;
  61
  62 #ifdef CONFIG_DEBUGGER
  63
  64 extern int (*__debugger)(struct pt_regs *regs);
  65 extern int (*__debugger_ipi)(struct pt_regs *regs);
  66 extern int (*__debugger_bpt)(struct pt_regs *regs);
  67 extern int (*__debugger_sstep)(struct pt_regs *regs);
  68 extern int (*__debugger_iabr_match)(struct pt_regs *regs);
  69 extern int (*__debugger_dabr_match)(struct pt_regs *regs);
  70 extern int (*__debugger_fault_handler)(struct pt_regs *regs);
  71
  72 #define DEBUGGER_BOILERPLATE(__NAME) \
  73 static inline int __NAME(struct pt_regs *regs) \
  74 { \
  75         if (unlikely(__ ## __NAME)) \
  76                 return __ ## __NAME(regs); \
  77         return 0; \
  78 }
  79
  80 DEBUGGER_BOILERPLATE(debugger)
  81 DEBUGGER_BOILERPLATE(debugger_ipi)
  82 DEBUGGER_BOILERPLATE(debugger_bpt)
  83 DEBUGGER_BOILERPLATE(debugger_sstep)
  84 DEBUGGER_BOILERPLATE(debugger_iabr_match)
  85 DEBUGGER_BOILERPLATE(debugger_dabr_match)
  86 DEBUGGER_BOILERPLATE(debugger_fault_handler)
  87
  88 #ifdef CONFIG_XMON
  89 extern void xmon_init(int enable);
  90 #endif
  91
  92 #else
  93 static inline int debugger(struct pt_regs *regs) { return 0; }
  94 static inline int debugger_ipi(struct pt_regs *regs) { return 0; }
  95 static inline int debugger_bpt(struct pt_regs *regs) { return 0; }
  96 static inline int debugger_sstep(struct pt_regs *regs) { return 0; }
  97 static inline int debugger_iabr_match(struct pt_regs *regs) { return 0; }
  98 static inline int debugger_dabr_match(struct pt_regs *regs) { return 0; }
  99 static inline int debugger_fault_handler(struct pt_regs *regs) { return 0; }
 100 #endif
 101
 102 extern int set_dabr(unsigned long dabr);
 103 extern void print_backtrace(unsigned long *);
 104 extern void show_regs(struct pt_regs * regs);
 105 extern void flush_instruction_cache(void);
 106 extern void hard_reset_now(void);
 107 extern void poweroff_now(void);
 108
 109 #ifdef CONFIG_6xx
 110 extern long _get_L2CR(void);
 111 extern long _get_L3CR(void);
 112 extern void _set_L2CR(unsigned long);
 113 extern void _set_L3CR(unsigned long);
 114 #else
 115 #define _get_L2CR()     0L
 116 #define _get_L3CR()     0L
 117 #define _set_L2CR(val)  do { } while(0)
 118 #define _set_L3CR(val)  do { } while(0)
 119 #endif
 120
 121 extern void via_cuda_init(void);
 122 extern void read_rtc_time(void);
 123 extern void pmac_find_display(void);
 124 extern void giveup_fpu(struct task_struct *);
 125 extern void disable_kernel_fp(void);
 126 extern void enable_kernel_fp(void);
 127 extern void flush_fp_to_thread(struct task_struct *);
 128 extern void enable_kernel_altivec(void);
 129 extern void giveup_altivec(struct task_struct *);
 130 extern void load_up_altivec(struct task_struct *);
 131 extern int emulate_altivec(struct pt_regs *);
 132 extern void giveup_spe(struct task_struct *);
 133 extern void load_up_spe(struct task_struct *);
 134 extern int fix_alignment(struct pt_regs *);
 135 extern void cvt_fd(float *from, double *to, unsigned long *fpscr);
 136 extern void cvt_df(double *from, float *to, unsigned long *fpscr);
 137
 138 #ifdef CONFIG_ALTIVEC
 139 extern void flush_altivec_to_thread(struct task_struct *);
 140 #else
 141 static inline void flush_altivec_to_thread(struct task_struct *t)
 142 {
 143 }
 144 #endif
 145
 146 #ifdef CONFIG_SPE
 147 extern void flush_spe_to_thread(struct task_struct *);
 148 #else
 149 static inline void flush_spe_to_thread(struct task_struct *t)
 150 {
 151 }
 152 #endif
 153
 154 extern int call_rtas(const char *, int, int, unsigned long *, ...);
 155 extern void cacheable_memzero(void *p, unsigned int nb);
 156 extern void *cacheable_memcpy(void *, const void *, unsigned int);
 157 extern int do_page_fault(struct pt_regs *, unsigned long, unsigned long);
 158 extern void bad_page_fault(struct pt_regs *, unsigned long, int);
 159 extern int die(const char *, struct pt_regs *, long);
 160 extern void _exception(int, struct pt_regs *, int, unsigned long);
 161 #ifdef CONFIG_BOOKE_WDT
 162 extern u32 booke_wdt_enabled;
 163 extern u32 booke_wdt_period;
 164 #endif /* CONFIG_BOOKE_WDT */
 165
 166 /* EBCDIC -> ASCII conversion for [0-9A-Z] on iSeries */
 167 extern unsigned char e2a(unsigned char);
 168
 169 struct device_node;
 170 extern void note_scsi_host(struct device_node *, void *);
 171
 172 extern struct task_struct *__switch_to(struct task_struct *,
 173         struct task_struct *);
 174 #define switch_to(prev, next, last)     ((last) = __switch_to((prev), (next)))
 175
 176 struct thread_struct;
 177 extern struct task_struct *_switch(struct thread_struct *prev,
 178                                    struct thread_struct *next);
 179
 180 extern unsigned int rtas_data;
 181 extern int mem_init_done;       /* set on boot once kmalloc can be called */
 182
 183 /*
 184  * Atomic exchange
 185  *
 186  * Changes the memory location '*ptr' to be val and returns
 187  * the previous value stored there.
 188  */
 189 static __inline__ unsigned long
 190 __xchg_u32(volatile void *p, unsigned long val)
 191 {
 192         unsigned long prev;
 193
 194         __asm__ __volatile__(
 195         EIEIO_ON_SMP
 196 "1:     lwarx   %0,0,%2 \n"
 197         PPC405_ERR77(0,%2)
 198 "       stwcx.  %3,0,%2 \n\
 199         bne-    1b"
 200         ISYNC_ON_SMP
 201         : "=&r" (prev), "=m" (*(volatile unsigned int *)p)
 202         : "r" (p), "r" (val), "m" (*(volatile unsigned int *)p)
 203         : "cc", "memory");
 204
 205         return prev;
 206 }
 207
 208 #ifdef CONFIG_PPC64
 209 static __inline__ unsigned long
 210 __xchg_u64(volatile void *p, unsigned long val)
 211 {
 212         unsigned long prev;
 213
 214         __asm__ __volatile__(
 215         EIEIO_ON_SMP
 216 "1:     ldarx   %0,0,%2 \n"
 217         PPC405_ERR77(0,%2)
 218 "       stdcx.  %3,0,%2 \n\
 219         bne-    1b"
 220         ISYNC_ON_SMP
 221         : "=&r" (prev), "=m" (*(volatile unsigned long *)p)
 222         : "r" (p), "r" (val), "m" (*(volatile unsigned long *)p)
 223         : "cc", "memory");
 224
 225         return prev;
 226 }
 227 #endif
 228
 229 /*
 230  * This function doesn't exist, so you'll get a linker error
 231  * if something tries to do an invalid xchg().
 232  */
 233 extern void __xchg_called_with_bad_pointer(void);
 234
 235 static __inline__ unsigned long
 236 __xchg(volatile void *ptr, unsigned long x, unsigned int size)
 237 {
 238         switch (size) {
 239         case 4:
 240                 return __xchg_u32(ptr, x);
 241 #ifdef CONFIG_PPC64
 242         case 8:
 243                 return __xchg_u64(ptr, x);
 244 #endif
 245         }
 246         __xchg_called_with_bad_pointer();
 247         return x;
 248 }
 249
 250 #define xchg(ptr,x)                                                          \
 251   ({                                                                         \
 252      __typeof__(*(ptr)) _x_ = (x);                                           \
 253      (__typeof__(*(ptr))) __xchg((ptr), (unsigned long)_x_, sizeof(*(ptr))); \
 254   })
 255
 256 #define tas(ptr) (xchg((ptr),1))
 257
 258 /*
 259  * Compare and exchange - if *p == old, set it to new,
 260  * and return the old value of *p.
 261  */
 262 #define __HAVE_ARCH_CMPXCHG     1
 263
 264 static __inline__ unsigned long
 265 __cmpxchg_u32(volatile unsigned int *p, unsigned long old, unsigned long new)
 266 {
 267         unsigned int prev;
 268
 269         __asm__ __volatile__ (
 270         EIEIO_ON_SMP
 271 "1:     lwarx   %0,0,%2         # __cmpxchg_u32\n\
 272         cmpw    0,%0,%3\n\
 273         bne-    2f\n"
 274         PPC405_ERR77(0,%2)
 275 "       stwcx.  %4,0,%2\n\
 276         bne-    1b"
 277         ISYNC_ON_SMP
 278         "\n\
 279 2:"
 280         : "=&r" (prev), "=m" (*p)
 281         : "r" (p), "r" (old), "r" (new), "m" (*p)
 282         : "cc", "memory");
 283
 284         return prev;
 285 }
 286
 287 #ifdef CONFIG_PPC64
 288 static __inline__ unsigned long
 289 __cmpxchg_u64(volatile long *p, unsigned long old, unsigned long new)
 290 {
 291         unsigned long prev;
 292
 293         __asm__ __volatile__ (
 294         EIEIO_ON_SMP
 295 "1:     ldarx   %0,0,%2         # __cmpxchg_u64\n\
 296         cmpd    0,%0,%3\n\
 297         bne-    2f\n\
 298         stdcx.  %4,0,%2\n\
 299         bne-    1b"
 300         ISYNC_ON_SMP
 301         "\n\
 302 2:"
 303         : "=&r" (prev), "=m" (*p)
 304         : "r" (p), "r" (old), "r" (new), "m" (*p)
 305         : "cc", "memory");
 306
 307         return prev;
 308 }
 309 #endif
 310
 311 /* This function doesn't exist, so you'll get a linker error
 312    if something tries to do an invalid cmpxchg().  */
 313 extern void __cmpxchg_called_with_bad_pointer(void);
 314
 315 static __inline__ unsigned long
 316 __cmpxchg(volatile void *ptr, unsigned long old, unsigned long new,
 317           unsigned int size)
 318 {
 319         switch (size) {
 320         case 4:
 321                 return __cmpxchg_u32(ptr, old, new);
 322 #ifdef CONFIG_PPC64
 323         case 8:
 324                 return __cmpxchg_u64(ptr, old, new);
 325 #endif
 326         }
 327         __cmpxchg_called_with_bad_pointer();
 328         return old;
 329 }
 330
 331 #define cmpxchg(ptr,o,n)                                                 \
 332   ({                                                                     \
 333      __typeof__(*(ptr)) _o_ = (o);                                       \
 334      __typeof__(*(ptr)) _n_ = (n);                                       \
 335      (__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_,           \
 336                                     (unsigned long)_n_, sizeof(*(ptr))); \
 337   })
 338
 339 #ifdef CONFIG_PPC64
 340 /*
 341  * We handle most unaligned accesses in hardware. On the other hand
 342  * unaligned DMA can be very expensive on some ppc64 IO chips (it does
 343  * powers of 2 writes until it reaches sufficient alignment).
 344  *
 345  * Based on this we disable the IP header alignment in network drivers.
 346  */
 347 #define NET_IP_ALIGN   0
 348 #endif
 349
 350 #define arch_align_stack(x) (x)
 351
 352 /* Used in very early kernel initialization. */
 353 extern unsigned long reloc_offset(void);
 354 extern unsigned long add_reloc_offset(unsigned long);
 355 extern void reloc_got2(unsigned long);
 356
 357 #define PTRRELOC(x)     ((typeof(x)) add_reloc_offset((unsigned long)(x)))
 358
 359 #endif /* __KERNEL__ */
 360 #endif /* _ASM_POWERPC_SYSTEM_H */