include/asm-arm/arch-ixp4xx/io.h

   1 /*
   2  * linux/include/asm-arm/arch-ixp4xx/io.h
   3  *
   4  * Author: Deepak Saxena <dsaxena@plexity.net>
   5  *
   6  * Copyright (C) 2002-2005  MontaVista Software, Inc.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12
  13 #ifndef __ASM_ARM_ARCH_IO_H
  14 #define __ASM_ARM_ARCH_IO_H
  15
  16 #include <asm/hardware.h>
  17
  18 #define IO_SPACE_LIMIT 0xffff0000
  19
  20 #define BIT(x)  ((1)<<(x))
  21
  22
  23 extern int (*ixp4xx_pci_read)(u32 addr, u32 cmd, u32* data);
  24 extern int ixp4xx_pci_write(u32 addr, u32 cmd, u32 data);
  25
  26
  27 /*
  28  * IXP4xx provides two methods of accessing PCI memory space:
  29  *
  30  * 1) A direct mapped window from 0x48000000 to 0x4bffffff (64MB).
  31  *    To access PCI via this space, we simply ioremap() the BAR
  32  *    into the kernel and we can use the standard read[bwl]/write[bwl]
  33  *    macros. This is the preffered method due to speed but it
  34  *    limits the system to just 64MB of PCI memory. This can be
  35  *    problamatic if using video cards and other memory-heavy
  36  *    targets.
  37  *
  38  * 2) If > 64MB of memory space is required, the IXP4xx can be configured
  39  *    to use indirect registers to access PCI (as we do below for I/O
  40  *    transactions). This allows for up to 128MB (0x48000000 to 0x4fffffff)
  41  *    of memory on the bus. The disadvantage of this is that every
  42  *    PCI access requires three local register accesses plus a spinlock,
  43  *    but in some cases the performance hit is acceptable. In addition,
  44  *    you cannot mmap() PCI devices in this case.
  45  *
  46  */
  47 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
  48
  49 #define __mem_pci(a)            (a)
  50
  51 #else
  52
  53 #include <linux/mm.h>
  54
  55 /*
  56  * In the case of using indirect PCI, we simply return the actual PCI
  57  * address and our read/write implementation use that to drive the
  58  * access registers. If something outside of PCI is ioremap'd, we
  59  * fallback to the default.
  60  */
  61 static inline void __iomem *
  62 __ixp4xx_ioremap(unsigned long addr, size_t size, unsigned long flags)
  63 {
  64         if((addr < 0x48000000) || (addr > 0x4fffffff))
  65                 return __ioremap(addr, size, flags);
  66
  67         return (void *)addr;
  68 }
  69
  70 static inline void
  71 __ixp4xx_iounmap(void __iomem *addr)
  72 {
  73         if ((u32)addr >= VMALLOC_START)
  74                 __iounmap(addr);
  75 }
  76
  77 #define __arch_ioremap(a, s, f)         __ixp4xx_ioremap(a, s, f)
  78 #define __arch_iounmap(a)               __ixp4xx_iounmap(a)
  79
  80 #define writeb(v, p)                    __ixp4xx_writeb(v, p)
  81 #define writew(v, p)                    __ixp4xx_writew(v, p)
  82 #define writel(v, p)                    __ixp4xx_writel(v, p)
  83
  84 #define writesb(p, v, l)                __ixp4xx_writesb(p, v, l)
  85 #define writesw(p, v, l)                __ixp4xx_writesw(p, v, l)
  86 #define writesl(p, v, l)                __ixp4xx_writesl(p, v, l)
  87
  88 #define readb(p)                        __ixp4xx_readb(p)
  89 #define readw(p)                        __ixp4xx_readw(p)
  90 #define readl(p)                        __ixp4xx_readl(p)
  91
  92 #define readsb(p, v, l)                 __ixp4xx_readsb(p, v, l)
  93 #define readsw(p, v, l)                 __ixp4xx_readsw(p, v, l)
  94 #define readsl(p, v, l)                 __ixp4xx_readsl(p, v, l)
  95
  96 static inline void
  97 __ixp4xx_writeb(u8 value, volatile void __iomem *p)
  98 {
  99         u32 addr = (u32)p;
 100         u32 n, byte_enables, data;
 101
 102         if (addr >= VMALLOC_START) {
 103                 __raw_writeb(value, addr);
 104                 return;
 105         }
 106
 107         n = addr % 4;
 108         byte_enables = (0xf & ~BIT(n)) << IXP4XX_PCI_NP_CBE_BESL;
 109         data = value << (8*n);
 110         ixp4xx_pci_write(addr, byte_enables | NP_CMD_MEMWRITE, data);
 111 }
 112
 113 static inline void
 114 __ixp4xx_writesb(volatile void __iomem *bus_addr, const u8 *vaddr, int count)
 115 {
 116         while (count--)
 117                 writeb(*vaddr++, bus_addr);
 118 }
 119
 120 static inline void
 121 __ixp4xx_writew(u16 value, volatile void __iomem *p)
 122 {
 123         u32 addr = (u32)p;
 124         u32 n, byte_enables, data;
 125
 126         if (addr >= VMALLOC_START) {
 127                 __raw_writew(value, addr);
 128                 return;
 129         }
 130
 131         n = addr % 4;
 132         byte_enables = (0xf & ~(BIT(n) | BIT(n+1))) << IXP4XX_PCI_NP_CBE_BESL;
 133         data = value << (8*n);
 134         ixp4xx_pci_write(addr, byte_enables | NP_CMD_MEMWRITE, data);
 135 }
 136
 137 static inline void
 138 __ixp4xx_writesw(volatile void __iomem *bus_addr, const u16 *vaddr, int count)
 139 {
 140         while (count--)
 141                 writew(*vaddr++, bus_addr);
 142 }
 143
 144 static inline void
 145 __ixp4xx_writel(u32 value, volatile void __iomem *p)
 146 {
 147         u32 addr = (u32)p;
 148         if (addr >= VMALLOC_START) {
 149                 __raw_writel(value, addr);
 150                 return;
 151         }
 152
 153         ixp4xx_pci_write(addr, NP_CMD_MEMWRITE, value);
 154 }
 155
 156 static inline void
 157 __ixp4xx_writesl(volatile void __iomem *bus_addr, const u32 *vaddr, int count)
 158 {
 159         while (count--)
 160                 writel(*vaddr++, bus_addr);
 161 }
 162
 163 static inline unsigned char
 164 __ixp4xx_readb(const volatile void __iomem *p)
 165 {
 166         u32 addr = (u32)p;
 167         u32 n, byte_enables, data;
 168
 169         if (addr >= VMALLOC_START)
 170                 return __raw_readb(addr);
 171
 172         n = addr % 4;
 173         byte_enables = (0xf & ~BIT(n)) << IXP4XX_PCI_NP_CBE_BESL;
 174         if (ixp4xx_pci_read(addr, byte_enables | NP_CMD_MEMREAD, &data))
 175                 return 0xff;
 176
 177         return data >> (8*n);
 178 }
 179
 180 static inline void
 181 __ixp4xx_readsb(const volatile void __iomem *bus_addr, u8 *vaddr, u32 count)
 182 {
 183         while (count--)
 184                 *vaddr++ = readb(bus_addr);
 185 }
 186
 187 static inline unsigned short
 188 __ixp4xx_readw(const volatile void __iomem *p)
 189 {
 190         u32 addr = (u32)p;
 191         u32 n, byte_enables, data;
 192
 193         if (addr >= VMALLOC_START)
 194                 return __raw_readw(addr);
 195
 196         n = addr % 4;
 197         byte_enables = (0xf & ~(BIT(n) | BIT(n+1))) << IXP4XX_PCI_NP_CBE_BESL;
 198         if (ixp4xx_pci_read(addr, byte_enables | NP_CMD_MEMREAD, &data))
 199                 return 0xffff;
 200
 201         return data>>(8*n);
 202 }
 203
 204 static inline void
 205 __ixp4xx_readsw(const volatile void __iomem *bus_addr, u16 *vaddr, u32 count)
 206 {
 207         while (count--)
 208                 *vaddr++ = readw(bus_addr);
 209 }
 210
 211 static inline unsigned long
 212 __ixp4xx_readl(const volatile void __iomem *p)
 213 {
 214         u32 addr = (u32)p;
 215         u32 data;
 216
 217         if (addr >= VMALLOC_START)
 218                 return __raw_readl(addr);
 219
 220         if (ixp4xx_pci_read(addr, NP_CMD_MEMREAD, &data))
 221                 return 0xffffffff;
 222
 223         return data;
 224 }
 225
 226 static inline void
 227 __ixp4xx_readsl(const volatile void __iomem *bus_addr, u32 *vaddr, u32 count)
 228 {
 229         while (count--)
 230                 *vaddr++ = readl(bus_addr);
 231 }
 232
 233
 234 /*
 235  * We can use the built-in functions b/c they end up calling writeb/readb
 236  */
 237 #define memset_io(c,v,l)                _memset_io((c),(v),(l))
 238 #define memcpy_fromio(a,c,l)            _memcpy_fromio((a),(c),(l))
 239 #define memcpy_toio(c,a,l)              _memcpy_toio((c),(a),(l))
 240
 241 #define eth_io_copy_and_sum(s,c,l,b) \
 242                                 eth_copy_and_sum((s),__mem_pci(c),(l),(b))
 243
 244 static inline int
 245 check_signature(const unsigned char __iomem *bus_addr, const unsigned char *signature,
 246                 int length)
 247 {
 248         int retval = 0;
 249         do {
 250                 if (readb(bus_addr) != *signature)
 251                         goto out;
 252                 bus_addr++;
 253                 signature++;
 254                 length--;
 255         } while (length);
 256         retval = 1;
 257 out:
 258         return retval;
 259 }
 260
 261 #endif
 262
 263 #ifndef CONFIG_PCI
 264
 265 #define __io(v)         v
 266
 267 #else
 268
 269 /*
 270  * IXP4xx does not have a transparent cpu -> PCI I/O translation
 271  * window.  Instead, it has a set of registers that must be tweaked
 272  * with the proper byte lanes, command types, and address for the
 273  * transaction.  This means that we need to override the default
 274  * I/O functions.
 275  */
 276 #define outb(p, v)                      __ixp4xx_outb(p, v)
 277 #define outw(p, v)                      __ixp4xx_outw(p, v)
 278 #define outl(p, v)                      __ixp4xx_outl(p, v)
 279
 280 #define outsb(p, v, l)                  __ixp4xx_outsb(p, v, l)
 281 #define outsw(p, v, l)                  __ixp4xx_outsw(p, v, l)
 282 #define outsl(p, v, l)                  __ixp4xx_outsl(p, v, l)
 283
 284 #define inb(p)                          __ixp4xx_inb(p)
 285 #define inw(p)                          __ixp4xx_inw(p)
 286 #define inl(p)                          __ixp4xx_inl(p)
 287
 288 #define insb(p, v, l)                   __ixp4xx_insb(p, v, l)
 289 #define insw(p, v, l)                   __ixp4xx_insw(p, v, l)
 290 #define insl(p, v, l)                   __ixp4xx_insl(p, v, l)
 291
 292
 293 static inline void
 294 __ixp4xx_outb(u8 value, u32 addr)
 295 {
 296         u32 n, byte_enables, data;
 297         n = addr % 4;
 298         byte_enables = (0xf & ~BIT(n)) << IXP4XX_PCI_NP_CBE_BESL;
 299         data = value << (8*n);
 300         ixp4xx_pci_write(addr, byte_enables | NP_CMD_IOWRITE, data);
 301 }
 302
 303 static inline void
 304 __ixp4xx_outsb(u32 io_addr, const u8 *vaddr, u32 count)
 305 {
 306         while (count--)
 307                 outb(*vaddr++, io_addr);
 308 }
 309
 310 static inline void
 311 __ixp4xx_outw(u16 value, u32 addr)
 312 {
 313         u32 n, byte_enables, data;
 314         n = addr % 4;
 315         byte_enables = (0xf & ~(BIT(n) | BIT(n+1))) << IXP4XX_PCI_NP_CBE_BESL;
 316         data = value << (8*n);
 317         ixp4xx_pci_write(addr, byte_enables | NP_CMD_IOWRITE, data);
 318 }
 319
 320 static inline void
 321 __ixp4xx_outsw(u32 io_addr, const u16 *vaddr, u32 count)
 322 {
 323         while (count--)
 324                 outw(cpu_to_le16(*vaddr++), io_addr);
 325 }
 326
 327 static inline void
 328 __ixp4xx_outl(u32 value, u32 addr)
 329 {
 330         ixp4xx_pci_write(addr, NP_CMD_IOWRITE, value);
 331 }
 332
 333 static inline void
 334 __ixp4xx_outsl(u32 io_addr, const u32 *vaddr, u32 count)
 335 {
 336         while (count--)
 337                 outl(*vaddr++, io_addr);
 338 }
 339
 340 static inline u8
 341 __ixp4xx_inb(u32 addr)
 342 {
 343         u32 n, byte_enables, data;
 344         n = addr % 4;
 345         byte_enables = (0xf & ~BIT(n)) << IXP4XX_PCI_NP_CBE_BESL;
 346         if (ixp4xx_pci_read(addr, byte_enables | NP_CMD_IOREAD, &data))
 347                 return 0xff;
 348
 349         return data >> (8*n);
 350 }
 351
 352 static inline void
 353 __ixp4xx_insb(u32 io_addr, u8 *vaddr, u32 count)
 354 {
 355         while (count--)
 356                 *vaddr++ = inb(io_addr);
 357 }
 358
 359 static inline u16
 360 __ixp4xx_inw(u32 addr)
 361 {
 362         u32 n, byte_enables, data;
 363         n = addr % 4;
 364         byte_enables = (0xf & ~(BIT(n) | BIT(n+1))) << IXP4XX_PCI_NP_CBE_BESL;
 365         if (ixp4xx_pci_read(addr, byte_enables | NP_CMD_IOREAD, &data))
 366                 return 0xffff;
 367
 368         return data>>(8*n);
 369 }
 370
 371 static inline void
 372 __ixp4xx_insw(u32 io_addr, u16 *vaddr, u32 count)
 373 {
 374         while (count--)
 375                 *vaddr++ = le16_to_cpu(inw(io_addr));
 376 }
 377
 378 static inline u32
 379 __ixp4xx_inl(u32 addr)
 380 {
 381         u32 data;
 382         if (ixp4xx_pci_read(addr, NP_CMD_IOREAD, &data))
 383                 return 0xffffffff;
 384
 385         return data;
 386 }
 387
 388 static inline void
 389 __ixp4xx_insl(u32 io_addr, u32 *vaddr, u32 count)
 390 {
 391         while (count--)
 392                 *vaddr++ = inl(io_addr);
 393 }
 394
 395 #define PIO_OFFSET      0x10000UL
 396 #define PIO_MASK        0x0ffffUL
 397
 398 #define __is_io_address(p)      (((unsigned long)p >= PIO_OFFSET) && \
 399                                         ((unsigned long)p <= (PIO_MASK + PIO_OFFSET)))
 400 static inline unsigned int
 401 __ixp4xx_ioread8(const void __iomem *addr)
 402 {
 403         unsigned long port = (unsigned long __force)addr;
 404         if (__is_io_address(port))
 405                 return  (unsigned int)__ixp4xx_inb(port & PIO_MASK);
 406         else
 407 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
 408                 return (unsigned int)__raw_readb(port);
 409 #else
 410                 return (unsigned int)__ixp4xx_readb(addr);
 411 #endif
 412 }
 413
 414 static inline void
 415 __ixp4xx_ioread8_rep(const void __iomem *addr, void *vaddr, u32 count)
 416 {
 417         unsigned long port = (unsigned long __force)addr;
 418         if (__is_io_address(port))
 419                 __ixp4xx_insb(port & PIO_MASK, vaddr, count);
 420         else
 421 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
 422                 __raw_readsb(addr, vaddr, count);
 423 #else
 424                 __ixp4xx_readsb(addr, vaddr, count);
 425 #endif
 426 }
 427
 428 static inline unsigned int
 429 __ixp4xx_ioread16(const void __iomem *addr)
 430 {
 431         unsigned long port = (unsigned long __force)addr;
 432         if (__is_io_address(port))
 433                 return  (unsigned int)__ixp4xx_inw(port & PIO_MASK);
 434         else
 435 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
 436                 return le16_to_cpu(__raw_readw((u32)port));
 437 #else
 438                 return (unsigned int)__ixp4xx_readw(addr);
 439 #endif
 440 }
 441
 442 static inline void
 443 __ixp4xx_ioread16_rep(const void __iomem *addr, void *vaddr, u32 count)
 444 {
 445         unsigned long port = (unsigned long __force)addr;
 446         if (__is_io_address(port))
 447                 __ixp4xx_insw(port & PIO_MASK, vaddr, count);
 448         else
 449 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
 450                 __raw_readsw(addr, vaddr, count);
 451 #else
 452                 __ixp4xx_readsw(addr, vaddr, count);
 453 #endif
 454 }
 455
 456 static inline unsigned int
 457 __ixp4xx_ioread32(const void __iomem *addr)
 458 {
 459         unsigned long port = (unsigned long __force)addr;
 460         if (__is_io_address(port))
 461                 return  (unsigned int)__ixp4xx_inl(port & PIO_MASK);
 462         else {
 463 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
 464                 return le32_to_cpu(__raw_readl((u32)port));
 465 #else
 466                 return (unsigned int)__ixp4xx_readl(addr);
 467 #endif
 468         }
 469 }
 470
 471 static inline void
 472 __ixp4xx_ioread32_rep(const void __iomem *addr, void *vaddr, u32 count)
 473 {
 474         unsigned long port = (unsigned long __force)addr;
 475         if (__is_io_address(port))
 476                 __ixp4xx_insl(port & PIO_MASK, vaddr, count);
 477         else
 478 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
 479                 __raw_readsl(addr, vaddr, count);
 480 #else
 481                 __ixp4xx_readsl(addr, vaddr, count);
 482 #endif
 483 }
 484
 485 static inline void
 486 __ixp4xx_iowrite8(u8 value, void __iomem *addr)
 487 {
 488         unsigned long port = (unsigned long __force)addr;
 489         if (__is_io_address(port))
 490                 __ixp4xx_outb(value, port & PIO_MASK);
 491         else
 492 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
 493                 __raw_writeb(value, port);
 494 #else
 495                 __ixp4xx_writeb(value, addr);
 496 #endif
 497 }
 498
 499 static inline void
 500 __ixp4xx_iowrite8_rep(void __iomem *addr, const void *vaddr, u32 count)
 501 {
 502         unsigned long port = (unsigned long __force)addr;
 503         if (__is_io_address(port))
 504                 __ixp4xx_outsb(port & PIO_MASK, vaddr, count);
 505         else
 506 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
 507                 __raw_writesb(addr, vaddr, count);
 508 #else
 509                 __ixp4xx_writesb(addr, vaddr, count);
 510 #endif
 511 }
 512
 513 static inline void
 514 __ixp4xx_iowrite16(u16 value, void __iomem *addr)
 515 {
 516         unsigned long port = (unsigned long __force)addr;
 517         if (__is_io_address(port))
 518                 __ixp4xx_outw(value, port & PIO_MASK);
 519         else
 520 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
 521                 __raw_writew(cpu_to_le16(value), addr);
 522 #else
 523                 __ixp4xx_writew(value, addr);
 524 #endif
 525 }
 526
 527 static inline void
 528 __ixp4xx_iowrite16_rep(void __iomem *addr, const void *vaddr, u32 count)
 529 {
 530         unsigned long port = (unsigned long __force)addr;
 531         if (__is_io_address(port))
 532                 __ixp4xx_outsw(port & PIO_MASK, vaddr, count);
 533         else
 534 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
 535                 __raw_writesw(addr, vaddr, count);
 536 #else
 537                 __ixp4xx_writesw(addr, vaddr, count);
 538 #endif
 539 }
 540
 541 static inline void
 542 __ixp4xx_iowrite32(u32 value, void __iomem *addr)
 543 {
 544         unsigned long port = (unsigned long __force)addr;
 545         if (__is_io_address(port))
 546                 __ixp4xx_outl(value, port & PIO_MASK);
 547         else
 548 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
 549                 __raw_writel(cpu_to_le32(value), port);
 550 #else
 551                 __ixp4xx_writel(value, addr);
 552 #endif
 553 }
 554
 555 static inline void
 556 __ixp4xx_iowrite32_rep(void __iomem *addr, const void *vaddr, u32 count)
 557 {
 558         unsigned long port = (unsigned long __force)addr;
 559         if (__is_io_address(port))
 560                 __ixp4xx_outsl(port & PIO_MASK, vaddr, count);
 561         else
 562 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
 563                 __raw_writesl(addr, vaddr, count);
 564 #else
 565                 __ixp4xx_writesl(addr, vaddr, count);
 566 #endif
 567 }
 568
 569 #define ioread8(p)                      __ixp4xx_ioread8(p)
 570 #define ioread16(p)                     __ixp4xx_ioread16(p)
 571 #define ioread32(p)                     __ixp4xx_ioread32(p)
 572
 573 #define ioread8_rep(p, v, c)            __ixp4xx_ioread8_rep(p, v, c)
 574 #define ioread16_rep(p, v, c)           __ixp4xx_ioread16_rep(p, v, c)
 575 #define ioread32_rep(p, v, c)           __ixp4xx_ioread32_rep(p, v, c)
 576
 577 #define iowrite8(v,p)                   __ixp4xx_iowrite8(v,p)
 578 #define iowrite16(v,p)                  __ixp4xx_iowrite16(v,p)
 579 #define iowrite32(v,p)                  __ixp4xx_iowrite32(v,p)
 580
 581 #define iowrite8_rep(p, v, c)           __ixp4xx_iowrite8_rep(p, v, c)
 582 #define iowrite16_rep(p, v, c)          __ixp4xx_iowrite16_rep(p, v, c)
 583 #define iowrite32_rep(p, v, c)          __ixp4xx_iowrite32_rep(p, v, c)
 584
 585 #define ioport_map(port, nr)            ((void __iomem*)(port + PIO_OFFSET))
 586 #define ioport_unmap(addr)
 587 #endif  // !CONFIG_PCI
 588
 589 #endif  //  __ASM_ARM_ARCH_IO_H
 590