arch/ppc/syslib/gt64260_pic.c

   1 /*
   2  * arch/ppc/syslib/gt64260_pic.c
   3  *
   4  * Interrupt controller support for Galileo's GT64260.
   5  *
   6  * Author: Chris Zankel <source@mvista.com>
   7  * Modified by: Mark A. Greer <mgreer@mvista.com>
   8  *
   9  * Based on sources from Rabeeh Khoury / Galileo Technology
  10  *
  11  * 2001 (c) MontaVista, Software, Inc.  This file is licensed under
  12  * the terms of the GNU General Public License version 2.  This program
  13  * is licensed "as is" without any warranty of any kind, whether express
  14  * or implied.
  15  */
  16
  17 /*
  18  * This file contains the specific functions to support the GT64260
  19  * interrupt controller.
  20  *
  21  * The GT64260 has two main interrupt registers (high and low) that
  22  * summarizes the interrupts generated by the units of the GT64260.
  23  * Each bit is assigned to an interrupt number, where the low register
  24  * are assigned from IRQ0 to IRQ31 and the high cause register
  25  * from IRQ32 to IRQ63
  26  * The GPP (General Purpose Port) interrupts are assigned from IRQ64 (GPP0)
  27  * to IRQ95 (GPP31).
  28  * get_irq() returns the lowest interrupt number that is currently asserted.
  29  *
  30  * Note:
  31  *  - This driver does not initialize the GPP when used as an interrupt
  32  *    input.
  33  */
  34
  35 #include <linux/stddef.h>
  36 #include <linux/init.h>
  37 #include <linux/interrupt.h>
  38 #include <linux/sched.h>
  39 #include <linux/signal.h>
  40 #include <linux/stddef.h>
  41 #include <linux/delay.h>
  42 #include <linux/irq.h>
  43
  44 #include <asm/io.h>
  45 #include <asm/system.h>
  46 #include <asm/irq.h>
  47 #include <asm/mv64x60.h>
  48
  49 #define CPU_INTR_STR    "gt64260 cpu interface error"
  50 #define PCI0_INTR_STR   "gt64260 pci 0 error"
  51 #define PCI1_INTR_STR   "gt64260 pci 1 error"
  52
  53 /* ========================== forward declaration ========================== */
  54
  55 static void gt64260_unmask_irq(unsigned int);
  56 static void gt64260_mask_irq(unsigned int);
  57
  58 /* ========================== local declarations =========================== */
  59
  60 struct hw_interrupt_type gt64260_pic = {
  61         .typename = " gt64260_pic ",
  62         .enable   = gt64260_unmask_irq,
  63         .disable  = gt64260_mask_irq,
  64         .ack      = gt64260_mask_irq,
  65         .end      = gt64260_unmask_irq,
  66 };
  67
  68 u32 gt64260_irq_base = 0;       /* GT64260 handles the next 96 IRQs from here */
  69
  70 static struct mv64x60_handle bh;
  71
  72 /* gt64260_init_irq()
  73  *
  74  *  This function initializes the interrupt controller. It assigns
  75  *  all interrupts from IRQ0 to IRQ95 to the gt64260 interrupt controller.
  76  *
  77  * Note:
  78  *  We register all GPP inputs as interrupt source, but disable them.
  79  */
  80 void __init
  81 gt64260_init_irq(void)
  82 {
  83         int i;
  84
  85         if (ppc_md.progress)
  86                 ppc_md.progress("gt64260_init_irq: enter", 0x0);
  87
  88         bh.v_base = mv64x60_get_bridge_vbase();
  89
  90         ppc_cached_irq_mask[0] = 0;
  91         ppc_cached_irq_mask[1] = 0x0f000000;    /* Enable GPP intrs */
  92         ppc_cached_irq_mask[2] = 0;
  93
  94         /* disable all interrupts and clear current interrupts */
  95         mv64x60_write(&bh, MV64x60_GPP_INTR_MASK, ppc_cached_irq_mask[2]);
  96         mv64x60_write(&bh, MV64x60_GPP_INTR_CAUSE, 0);
  97         mv64x60_write(&bh, GT64260_IC_CPU_INTR_MASK_LO, ppc_cached_irq_mask[0]);
  98         mv64x60_write(&bh, GT64260_IC_CPU_INTR_MASK_HI, ppc_cached_irq_mask[1]);
  99
 100         /* use the gt64260 for all (possible) interrupt sources */
 101         for (i = gt64260_irq_base; i < (gt64260_irq_base + 96); i++)
 102                 irq_desc[i].handler = &gt64260_pic;
 103
 104         if (ppc_md.progress)
 105                 ppc_md.progress("gt64260_init_irq: exit", 0x0);
 106 }
 107
 108 /*
 109  * gt64260_get_irq()
 110  *
 111  *  This function returns the lowest interrupt number of all interrupts that
 112  *  are currently asserted.
 113  *
 114  * Input Variable(s):
 115  *  struct pt_regs*     not used
 116  *
 117  * Output Variable(s):
 118  *  None.
 119  *
 120  * Returns:
 121  *  int <interrupt number> or -2 (bogus interrupt)
 122  */
 123 int
 124 gt64260_get_irq(struct pt_regs *regs)
 125 {
 126         int irq;
 127         int irq_gpp;
 128
 129         irq = mv64x60_read(&bh, GT64260_IC_MAIN_CAUSE_LO);
 130         irq = __ilog2((irq & 0x3dfffffe) & ppc_cached_irq_mask[0]);
 131
 132         if (irq == -1) {
 133                 irq = mv64x60_read(&bh, GT64260_IC_MAIN_CAUSE_HI);
 134                 irq = __ilog2((irq & 0x0f000db7) & ppc_cached_irq_mask[1]);
 135
 136                 if (irq == -1)
 137                         irq = -2; /* bogus interrupt, should never happen */
 138                 else {
 139                         if (irq >= 24) {
 140                                 irq_gpp = mv64x60_read(&bh,
 141                                         MV64x60_GPP_INTR_CAUSE);
 142                                 irq_gpp = __ilog2(irq_gpp &
 143                                         ppc_cached_irq_mask[2]);
 144
 145                                 if (irq_gpp == -1)
 146                                         irq = -2;
 147                                 else {
 148                                         irq = irq_gpp + 64;
 149                                         mv64x60_write(&bh,
 150                                                 MV64x60_GPP_INTR_CAUSE,
 151                                                 ~(1 << (irq - 64)));
 152                                 }
 153                         } else
 154                                 irq += 32;
 155                 }
 156         }
 157
 158         (void)mv64x60_read(&bh, MV64x60_GPP_INTR_CAUSE);
 159
 160         if (irq < 0)
 161                 return (irq);
 162         else
 163                 return (gt64260_irq_base + irq);
 164 }
 165
 166 /* gt64260_unmask_irq()
 167  *
 168  *  This function enables an interrupt.
 169  *
 170  * Input Variable(s):
 171  *  unsigned int        interrupt number (IRQ0...IRQ95).
 172  *
 173  * Output Variable(s):
 174  *  None.
 175  *
 176  * Returns:
 177  *  void
 178  */
 179 static void
 180 gt64260_unmask_irq(unsigned int irq)
 181 {
 182         irq -= gt64260_irq_base;
 183
 184         if (irq > 31)
 185                 if (irq > 63) /* unmask GPP irq */
 186                         mv64x60_write(&bh, MV64x60_GPP_INTR_MASK,
 187                                 ppc_cached_irq_mask[2] |= (1 << (irq - 64)));
 188                 else /* mask high interrupt register */
 189                         mv64x60_write(&bh, GT64260_IC_CPU_INTR_MASK_HI,
 190                                 ppc_cached_irq_mask[1] |= (1 << (irq - 32)));
 191         else /* mask low interrupt register */
 192                 mv64x60_write(&bh, GT64260_IC_CPU_INTR_MASK_LO,
 193                         ppc_cached_irq_mask[0] |= (1 << irq));
 194
 195         (void)mv64x60_read(&bh, MV64x60_GPP_INTR_MASK);
 196         return;
 197 }
 198
 199 /* gt64260_mask_irq()
 200  *
 201  *  This function disables the requested interrupt.
 202  *
 203  * Input Variable(s):
 204  *  unsigned int        interrupt number (IRQ0...IRQ95).
 205  *
 206  * Output Variable(s):
 207  *  None.
 208  *
 209  * Returns:
 210  *  void
 211  */
 212 static void
 213 gt64260_mask_irq(unsigned int irq)
 214 {
 215         irq -= gt64260_irq_base;
 216
 217         if (irq > 31)
 218                 if (irq > 63) /* mask GPP irq */
 219                         mv64x60_write(&bh, MV64x60_GPP_INTR_MASK,
 220                                 ppc_cached_irq_mask[2] &= ~(1 << (irq - 64)));
 221                 else /* mask high interrupt register */
 222                         mv64x60_write(&bh, GT64260_IC_CPU_INTR_MASK_HI,
 223                                 ppc_cached_irq_mask[1] &= ~(1 << (irq - 32)));
 224         else /* mask low interrupt register */
 225                 mv64x60_write(&bh, GT64260_IC_CPU_INTR_MASK_LO,
 226                         ppc_cached_irq_mask[0] &= ~(1 << irq));
 227
 228         (void)mv64x60_read(&bh, MV64x60_GPP_INTR_MASK);
 229         return;
 230 }
 231
 232 static irqreturn_t
 233 gt64260_cpu_error_int_handler(int irq, void *dev_id, struct pt_regs *regs)
 234 {
 235         printk(KERN_ERR "gt64260_cpu_error_int_handler: %s 0x%08x\n",
 236                 "Error on CPU interface - Cause regiser",
 237                 mv64x60_read(&bh, MV64x60_CPU_ERR_CAUSE));
 238         printk(KERN_ERR "\tCPU error register dump:\n");
 239         printk(KERN_ERR "\tAddress low  0x%08x\n",
 240                mv64x60_read(&bh, MV64x60_CPU_ERR_ADDR_LO));
 241         printk(KERN_ERR "\tAddress high 0x%08x\n",
 242                mv64x60_read(&bh, MV64x60_CPU_ERR_ADDR_HI));
 243         printk(KERN_ERR "\tData low     0x%08x\n",
 244                mv64x60_read(&bh, MV64x60_CPU_ERR_DATA_LO));
 245         printk(KERN_ERR "\tData high    0x%08x\n",
 246                mv64x60_read(&bh, MV64x60_CPU_ERR_DATA_HI));
 247         printk(KERN_ERR "\tParity       0x%08x\n",
 248                mv64x60_read(&bh, MV64x60_CPU_ERR_PARITY));
 249         mv64x60_write(&bh, MV64x60_CPU_ERR_CAUSE, 0);
 250         return IRQ_HANDLED;
 251 }
 252
 253 static irqreturn_t
 254 gt64260_pci_error_int_handler(int irq, void *dev_id, struct pt_regs *regs)
 255 {
 256         u32 val;
 257         unsigned int pci_bus = (unsigned int)dev_id;
 258
 259         if (pci_bus == 0) {     /* Error on PCI 0 */
 260                 val = mv64x60_read(&bh, MV64x60_PCI0_ERR_CAUSE);
 261                 printk(KERN_ERR "%s: Error in PCI %d Interface\n",
 262                         "gt64260_pci_error_int_handler", pci_bus);
 263                 printk(KERN_ERR "\tPCI %d error register dump:\n", pci_bus);
 264                 printk(KERN_ERR "\tCause register 0x%08x\n", val);
 265                 printk(KERN_ERR "\tAddress Low    0x%08x\n",
 266                        mv64x60_read(&bh, MV64x60_PCI0_ERR_ADDR_LO));
 267                 printk(KERN_ERR "\tAddress High   0x%08x\n",
 268                        mv64x60_read(&bh, MV64x60_PCI0_ERR_ADDR_HI));
 269                 printk(KERN_ERR "\tAttribute      0x%08x\n",
 270                        mv64x60_read(&bh, MV64x60_PCI0_ERR_DATA_LO));
 271                 printk(KERN_ERR "\tCommand        0x%08x\n",
 272                        mv64x60_read(&bh, MV64x60_PCI0_ERR_CMD));
 273                 mv64x60_write(&bh, MV64x60_PCI0_ERR_CAUSE, ~val);
 274         }
 275         if (pci_bus == 1) {     /* Error on PCI 1 */
 276                 val = mv64x60_read(&bh, MV64x60_PCI1_ERR_CAUSE);
 277                 printk(KERN_ERR "%s: Error in PCI %d Interface\n",
 278                         "gt64260_pci_error_int_handler", pci_bus);
 279                 printk(KERN_ERR "\tPCI %d error register dump:\n", pci_bus);
 280                 printk(KERN_ERR "\tCause register 0x%08x\n", val);
 281                 printk(KERN_ERR "\tAddress Low    0x%08x\n",
 282                        mv64x60_read(&bh, MV64x60_PCI1_ERR_ADDR_LO));
 283                 printk(KERN_ERR "\tAddress High   0x%08x\n",
 284                        mv64x60_read(&bh, MV64x60_PCI1_ERR_ADDR_HI));
 285                 printk(KERN_ERR "\tAttribute      0x%08x\n",
 286                        mv64x60_read(&bh, MV64x60_PCI1_ERR_DATA_LO));
 287                 printk(KERN_ERR "\tCommand        0x%08x\n",
 288                        mv64x60_read(&bh, MV64x60_PCI1_ERR_CMD));
 289                 mv64x60_write(&bh, MV64x60_PCI1_ERR_CAUSE, ~val);
 290         }
 291         return IRQ_HANDLED;
 292 }
 293
 294 static int __init
 295 gt64260_register_hdlrs(void)
 296 {
 297         int rc;
 298
 299         /* Register CPU interface error interrupt handler */
 300         if ((rc = request_irq(MV64x60_IRQ_CPU_ERR,
 301                 gt64260_cpu_error_int_handler, SA_INTERRUPT, CPU_INTR_STR, 0)))
 302                 printk(KERN_WARNING "Can't register cpu error handler: %d", rc);
 303
 304         mv64x60_write(&bh, MV64x60_CPU_ERR_MASK, 0);
 305         mv64x60_write(&bh, MV64x60_CPU_ERR_MASK, 0x000000fe);
 306
 307         /* Register PCI 0 error interrupt handler */
 308         if ((rc = request_irq(MV64360_IRQ_PCI0, gt64260_pci_error_int_handler,
 309                     SA_INTERRUPT, PCI0_INTR_STR, (void *)0)))
 310                 printk(KERN_WARNING "Can't register pci 0 error handler: %d",
 311                         rc);
 312
 313         mv64x60_write(&bh, MV64x60_PCI0_ERR_MASK, 0);
 314         mv64x60_write(&bh, MV64x60_PCI0_ERR_MASK, 0x003c0c24);
 315
 316         /* Register PCI 1 error interrupt handler */
 317         if ((rc = request_irq(MV64360_IRQ_PCI1, gt64260_pci_error_int_handler,
 318                     SA_INTERRUPT, PCI1_INTR_STR, (void *)1)))
 319                 printk(KERN_WARNING "Can't register pci 1 error handler: %d",
 320                         rc);
 321
 322         mv64x60_write(&bh, MV64x60_PCI1_ERR_MASK, 0);
 323         mv64x60_write(&bh, MV64x60_PCI1_ERR_MASK, 0x003c0c24);
 324
 325         return 0;
 326 }
 327
 328 arch_initcall(gt64260_register_hdlrs);