2 * Intel e7xxx Memory Controller kernel module
3 * (C) 2003 Linux Networx (http://lnxi.com)
4 * This file may be distributed under the terms of the
5 * GNU General Public License.
7 * See "enum e7xxx_chips" below for supported chipsets
9 * Written by Thayne Harbaugh
10 * Based on work by Dan Hollis <goemon at anime dot net> and others.
11 * http://www.anime.net/~goemon/linux-ecc/
14 * Eric Biederman (Linux Networx)
15 * Tom Zimmerman (Linux Networx)
16 * Jim Garlick (Lawrence Livermore National Labs)
17 * Dave Peterson (Lawrence Livermore National Labs)
18 * That One Guy (Some other place)
19 * Wang Zhenyu (intel.com)
21 * $Id: edac_e7xxx.c,v 1.5.2.9 2005/10/05 00:43:44 dsp_llnl Exp $
25 #include <linux/module.h>
26 #include <linux/init.h>
27 #include <linux/pci.h>
28 #include <linux/pci_ids.h>
29 #include <linux/slab.h>
32 #define E7XXX_REVISION " Ver: 2.0.0 " __DATE__
34 #define e7xxx_printk(level, fmt, arg...) \
35 edac_printk(level, "e7xxx", fmt, ##arg)
37 #define e7xxx_mc_printk(mci, level, fmt, arg...) \
38 edac_mc_chipset_printk(mci, level, "e7xxx", fmt, ##arg)
40 #ifndef PCI_DEVICE_ID_INTEL_7205_0
41 #define PCI_DEVICE_ID_INTEL_7205_0 0x255d
42 #endif /* PCI_DEVICE_ID_INTEL_7205_0 */
44 #ifndef PCI_DEVICE_ID_INTEL_7205_1_ERR
45 #define PCI_DEVICE_ID_INTEL_7205_1_ERR 0x2551
46 #endif /* PCI_DEVICE_ID_INTEL_7205_1_ERR */
48 #ifndef PCI_DEVICE_ID_INTEL_7500_0
49 #define PCI_DEVICE_ID_INTEL_7500_0 0x2540
50 #endif /* PCI_DEVICE_ID_INTEL_7500_0 */
52 #ifndef PCI_DEVICE_ID_INTEL_7500_1_ERR
53 #define PCI_DEVICE_ID_INTEL_7500_1_ERR 0x2541
54 #endif /* PCI_DEVICE_ID_INTEL_7500_1_ERR */
56 #ifndef PCI_DEVICE_ID_INTEL_7501_0
57 #define PCI_DEVICE_ID_INTEL_7501_0 0x254c
58 #endif /* PCI_DEVICE_ID_INTEL_7501_0 */
60 #ifndef PCI_DEVICE_ID_INTEL_7501_1_ERR
61 #define PCI_DEVICE_ID_INTEL_7501_1_ERR 0x2541
62 #endif /* PCI_DEVICE_ID_INTEL_7501_1_ERR */
64 #ifndef PCI_DEVICE_ID_INTEL_7505_0
65 #define PCI_DEVICE_ID_INTEL_7505_0 0x2550
66 #endif /* PCI_DEVICE_ID_INTEL_7505_0 */
68 #ifndef PCI_DEVICE_ID_INTEL_7505_1_ERR
69 #define PCI_DEVICE_ID_INTEL_7505_1_ERR 0x2551
70 #endif /* PCI_DEVICE_ID_INTEL_7505_1_ERR */
72 #define E7XXX_NR_CSROWS 8 /* number of csrows */
73 #define E7XXX_NR_DIMMS 8 /* FIXME - is this correct? */
75 /* E7XXX register addresses - device 0 function 0 */
76 #define E7XXX_DRB 0x60 /* DRAM row boundary register (8b) */
77 #define E7XXX_DRA 0x70 /* DRAM row attribute register (8b) */
79 * 31 Device width row 7 0=x8 1=x4
80 * 27 Device width row 6
81 * 23 Device width row 5
82 * 19 Device width row 4
83 * 15 Device width row 3
84 * 11 Device width row 2
85 * 7 Device width row 1
86 * 3 Device width row 0
88 #define E7XXX_DRC 0x7C /* DRAM controller mode reg (32b) */
90 * 22 Number channels 0=1,1=2
91 * 19:18 DRB Granularity 32/64MB
93 #define E7XXX_TOLM 0xC4 /* DRAM top of low memory reg (16b) */
94 #define E7XXX_REMAPBASE 0xC6 /* DRAM remap base address reg (16b) */
95 #define E7XXX_REMAPLIMIT 0xC8 /* DRAM remap limit address reg (16b) */
97 /* E7XXX register addresses - device 0 function 1 */
98 #define E7XXX_DRAM_FERR 0x80 /* DRAM first error register (8b) */
99 #define E7XXX_DRAM_NERR 0x82 /* DRAM next error register (8b) */
100 #define E7XXX_DRAM_CELOG_ADD 0xA0 /* DRAM first correctable memory */
101 /* error address register (32b) */
104 * 27:6 CE address (4k block 33:12)
107 #define E7XXX_DRAM_UELOG_ADD 0xB0 /* DRAM first uncorrectable memory */
108 /* error address register (32b) */
111 * 27:6 CE address (4k block 33:12)
114 #define E7XXX_DRAM_CELOG_SYNDROME 0xD0 /* DRAM first correctable memory */
115 /* error syndrome register (16b) */
125 struct pci_dev
*bridge_ck
;
129 const struct e7xxx_dev_info
*dev_info
;
132 struct e7xxx_dev_info
{
134 const char *ctl_name
;
137 struct e7xxx_error_info
{
141 u16 dram_celog_syndrome
;
145 static const struct e7xxx_dev_info e7xxx_devs
[] = {
147 .err_dev
= PCI_DEVICE_ID_INTEL_7500_1_ERR
,
151 .err_dev
= PCI_DEVICE_ID_INTEL_7501_1_ERR
,
155 .err_dev
= PCI_DEVICE_ID_INTEL_7505_1_ERR
,
159 .err_dev
= PCI_DEVICE_ID_INTEL_7205_1_ERR
,
164 /* FIXME - is this valid for both SECDED and S4ECD4ED? */
165 static inline int e7xxx_find_channel(u16 syndrome
)
167 debugf3("%s()\n", __func__
);
169 if ((syndrome
& 0xff00) == 0)
172 if ((syndrome
& 0x00ff) == 0)
175 if ((syndrome
& 0xf000) == 0 || (syndrome
& 0x0f00) == 0)
181 static unsigned long ctl_page_to_phys(struct mem_ctl_info
*mci
,
185 struct e7xxx_pvt
*pvt
= (struct e7xxx_pvt
*) mci
->pvt_info
;
187 debugf3("%s()\n", __func__
);
189 if ((page
< pvt
->tolm
) ||
190 ((page
>= 0x100000) && (page
< pvt
->remapbase
)))
193 remap
= (page
- pvt
->tolm
) + pvt
->remapbase
;
195 if (remap
< pvt
->remaplimit
)
198 e7xxx_printk(KERN_ERR
, "Invalid page %lx - out of range\n", page
);
199 return pvt
->tolm
- 1;
202 static void process_ce(struct mem_ctl_info
*mci
,
203 struct e7xxx_error_info
*info
)
210 debugf3("%s()\n", __func__
);
211 /* read the error address */
212 error_1b
= info
->dram_celog_add
;
213 /* FIXME - should use PAGE_SHIFT */
214 page
= error_1b
>> 6; /* convert the address to 4k page */
215 /* read the syndrome */
216 syndrome
= info
->dram_celog_syndrome
;
217 /* FIXME - check for -1 */
218 row
= edac_mc_find_csrow_by_page(mci
, page
);
219 /* convert syndrome to channel */
220 channel
= e7xxx_find_channel(syndrome
);
221 edac_mc_handle_ce(mci
, page
, 0, syndrome
, row
, channel
, "e7xxx CE");
224 static void process_ce_no_info(struct mem_ctl_info
*mci
)
226 debugf3("%s()\n", __func__
);
227 edac_mc_handle_ce_no_info(mci
, "e7xxx CE log register overflow");
230 static void process_ue(struct mem_ctl_info
*mci
,
231 struct e7xxx_error_info
*info
)
233 u32 error_2b
, block_page
;
236 debugf3("%s()\n", __func__
);
237 /* read the error address */
238 error_2b
= info
->dram_uelog_add
;
239 /* FIXME - should use PAGE_SHIFT */
240 block_page
= error_2b
>> 6; /* convert to 4k address */
241 row
= edac_mc_find_csrow_by_page(mci
, block_page
);
242 edac_mc_handle_ue(mci
, block_page
, 0, row
, "e7xxx UE");
245 static void process_ue_no_info(struct mem_ctl_info
*mci
)
247 debugf3("%s()\n", __func__
);
248 edac_mc_handle_ue_no_info(mci
, "e7xxx UE log register overflow");
251 static void e7xxx_get_error_info (struct mem_ctl_info
*mci
,
252 struct e7xxx_error_info
*info
)
254 struct e7xxx_pvt
*pvt
;
256 pvt
= (struct e7xxx_pvt
*) mci
->pvt_info
;
257 pci_read_config_byte(pvt
->bridge_ck
, E7XXX_DRAM_FERR
,
259 pci_read_config_byte(pvt
->bridge_ck
, E7XXX_DRAM_NERR
,
262 if ((info
->dram_ferr
& 1) || (info
->dram_nerr
& 1)) {
263 pci_read_config_dword(pvt
->bridge_ck
, E7XXX_DRAM_CELOG_ADD
,
264 &info
->dram_celog_add
);
265 pci_read_config_word(pvt
->bridge_ck
,
266 E7XXX_DRAM_CELOG_SYNDROME
,
267 &info
->dram_celog_syndrome
);
270 if ((info
->dram_ferr
& 2) || (info
->dram_nerr
& 2))
271 pci_read_config_dword(pvt
->bridge_ck
, E7XXX_DRAM_UELOG_ADD
,
272 &info
->dram_uelog_add
);
274 if (info
->dram_ferr
& 3)
275 pci_write_bits8(pvt
->bridge_ck
, E7XXX_DRAM_FERR
, 0x03, 0x03);
277 if (info
->dram_nerr
& 3)
278 pci_write_bits8(pvt
->bridge_ck
, E7XXX_DRAM_NERR
, 0x03, 0x03);
281 static int e7xxx_process_error_info (struct mem_ctl_info
*mci
,
282 struct e7xxx_error_info
*info
, int handle_errors
)
288 /* decode and report errors */
289 if (info
->dram_ferr
& 1) { /* check first error correctable */
293 process_ce(mci
, info
);
296 if (info
->dram_ferr
& 2) { /* check first error uncorrectable */
300 process_ue(mci
, info
);
303 if (info
->dram_nerr
& 1) { /* check next error correctable */
307 if (info
->dram_ferr
& 1)
308 process_ce_no_info(mci
);
310 process_ce(mci
, info
);
314 if (info
->dram_nerr
& 2) { /* check next error uncorrectable */
318 if (info
->dram_ferr
& 2)
319 process_ue_no_info(mci
);
321 process_ue(mci
, info
);
328 static void e7xxx_check(struct mem_ctl_info
*mci
)
330 struct e7xxx_error_info info
;
332 debugf3("%s()\n", __func__
);
333 e7xxx_get_error_info(mci
, &info
);
334 e7xxx_process_error_info(mci
, &info
, 1);
337 /* Return 1 if dual channel mode is active. Else return 0. */
338 static inline int dual_channel_active(u32 drc
, int dev_idx
)
340 return (dev_idx
== E7501
) ? ((drc
>> 22) & 0x1) : 1;
344 /* Return DRB granularity (0=32mb, 1=64mb). */
345 static inline int drb_granularity(u32 drc
, int dev_idx
)
347 /* only e7501 can be single channel */
348 return (dev_idx
== E7501
) ? ((drc
>> 18) & 0x3) : 1;
352 static void e7xxx_init_csrows(struct mem_ctl_info
*mci
, struct pci_dev
*pdev
,
353 int dev_idx
, u32 drc
)
355 unsigned long last_cumul_size
;
359 int drc_chan
, drc_drbg
, drc_ddim
, mem_dev
;
360 struct csrow_info
*csrow
;
362 pci_read_config_dword(pdev
, E7XXX_DRA
, &dra
);
363 drc_chan
= dual_channel_active(drc
, dev_idx
);
364 drc_drbg
= drb_granularity(drc
, dev_idx
);
365 drc_ddim
= (drc
>> 20) & 0x3;
368 /* The dram row boundary (DRB) reg values are boundary address
369 * for each DRAM row with a granularity of 32 or 64MB (single/dual
370 * channel operation). DRB regs are cumulative; therefore DRB7 will
371 * contain the total memory contained in all eight rows.
373 for (index
= 0; index
< mci
->nr_csrows
; index
++) {
374 /* mem_dev 0=x8, 1=x4 */
375 mem_dev
= (dra
>> (index
* 4 + 3)) & 0x1;
376 csrow
= &mci
->csrows
[index
];
378 pci_read_config_byte(pdev
, E7XXX_DRB
+ index
, &value
);
379 /* convert a 64 or 32 MiB DRB to a page size. */
380 cumul_size
= value
<< (25 + drc_drbg
- PAGE_SHIFT
);
381 debugf3("%s(): (%d) cumul_size 0x%x\n", __func__
, index
,
383 if (cumul_size
== last_cumul_size
)
384 continue; /* not populated */
386 csrow
->first_page
= last_cumul_size
;
387 csrow
->last_page
= cumul_size
- 1;
388 csrow
->nr_pages
= cumul_size
- last_cumul_size
;
389 last_cumul_size
= cumul_size
;
390 csrow
->grain
= 1 << 12; /* 4KiB - resolution of CELOG */
391 csrow
->mtype
= MEM_RDDR
; /* only one type supported */
392 csrow
->dtype
= mem_dev
? DEV_X4
: DEV_X8
;
395 * if single channel or x8 devices then SECDED
396 * if dual channel and x4 then S4ECD4ED
399 if (drc_chan
&& mem_dev
) {
400 csrow
->edac_mode
= EDAC_S4ECD4ED
;
401 mci
->edac_cap
|= EDAC_FLAG_S4ECD4ED
;
403 csrow
->edac_mode
= EDAC_SECDED
;
404 mci
->edac_cap
|= EDAC_FLAG_SECDED
;
407 csrow
->edac_mode
= EDAC_NONE
;
411 static int e7xxx_probe1(struct pci_dev
*pdev
, int dev_idx
)
414 struct mem_ctl_info
*mci
= NULL
;
415 struct e7xxx_pvt
*pvt
= NULL
;
418 struct e7xxx_error_info discard
;
420 debugf0("%s(): mci\n", __func__
);
421 pci_read_config_dword(pdev
, E7XXX_DRC
, &drc
);
423 drc_chan
= dual_channel_active(drc
, dev_idx
);
424 mci
= edac_mc_alloc(sizeof(*pvt
), E7XXX_NR_CSROWS
, drc_chan
+ 1);
429 debugf3("%s(): init mci\n", __func__
);
430 mci
->mtype_cap
= MEM_FLAG_RDDR
;
431 mci
->edac_ctl_cap
= EDAC_FLAG_NONE
| EDAC_FLAG_SECDED
|
433 /* FIXME - what if different memory types are in different csrows? */
434 mci
->mod_name
= EDAC_MOD_STR
;
435 mci
->mod_ver
= E7XXX_REVISION
;
436 mci
->dev
= &pdev
->dev
;
437 debugf3("%s(): init pvt\n", __func__
);
438 pvt
= (struct e7xxx_pvt
*) mci
->pvt_info
;
439 pvt
->dev_info
= &e7xxx_devs
[dev_idx
];
440 pvt
->bridge_ck
= pci_get_device(PCI_VENDOR_ID_INTEL
,
441 pvt
->dev_info
->err_dev
,
444 if (!pvt
->bridge_ck
) {
445 e7xxx_printk(KERN_ERR
, "error reporting device not found:"
446 "vendor %x device 0x%x (broken BIOS?)\n",
447 PCI_VENDOR_ID_INTEL
, e7xxx_devs
[dev_idx
].err_dev
);
451 debugf3("%s(): more mci init\n", __func__
);
452 mci
->ctl_name
= pvt
->dev_info
->ctl_name
;
453 mci
->edac_check
= e7xxx_check
;
454 mci
->ctl_page_to_phys
= ctl_page_to_phys
;
455 e7xxx_init_csrows(mci
, pdev
, dev_idx
, drc
);
456 mci
->edac_cap
|= EDAC_FLAG_NONE
;
457 debugf3("%s(): tolm, remapbase, remaplimit\n", __func__
);
458 /* load the top of low memory, remap base, and remap limit vars */
459 pci_read_config_word(pdev
, E7XXX_TOLM
, &pci_data
);
460 pvt
->tolm
= ((u32
) pci_data
) << 4;
461 pci_read_config_word(pdev
, E7XXX_REMAPBASE
, &pci_data
);
462 pvt
->remapbase
= ((u32
) pci_data
) << 14;
463 pci_read_config_word(pdev
, E7XXX_REMAPLIMIT
, &pci_data
);
464 pvt
->remaplimit
= ((u32
) pci_data
) << 14;
465 e7xxx_printk(KERN_INFO
,
466 "tolm = %x, remapbase = %x, remaplimit = %x\n", pvt
->tolm
,
467 pvt
->remapbase
, pvt
->remaplimit
);
469 /* clear any pending errors, or initial state bits */
470 e7xxx_get_error_info(mci
, &discard
);
472 /* Here we assume that we will never see multiple instances of this
473 * type of memory controller. The ID is therefore hardcoded to 0.
475 if (edac_mc_add_mc(mci
,0)) {
476 debugf3("%s(): failed edac_mc_add_mc()\n", __func__
);
480 /* get this far and it's successful */
481 debugf3("%s(): success\n", __func__
);
485 pci_dev_put(pvt
->bridge_ck
);
493 /* returns count (>= 0), or negative on error */
494 static int __devinit
e7xxx_init_one(struct pci_dev
*pdev
,
495 const struct pci_device_id
*ent
)
497 debugf0("%s()\n", __func__
);
499 /* wake up and enable device */
500 return pci_enable_device(pdev
) ?
501 -EIO
: e7xxx_probe1(pdev
, ent
->driver_data
);
504 static void __devexit
e7xxx_remove_one(struct pci_dev
*pdev
)
506 struct mem_ctl_info
*mci
;
507 struct e7xxx_pvt
*pvt
;
509 debugf0("%s()\n", __func__
);
511 if ((mci
= edac_mc_del_mc(&pdev
->dev
)) == NULL
)
514 pvt
= (struct e7xxx_pvt
*) mci
->pvt_info
;
515 pci_dev_put(pvt
->bridge_ck
);
519 static const struct pci_device_id e7xxx_pci_tbl
[] __devinitdata
= {
521 PCI_VEND_DEV(INTEL
, 7205_0
), PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
525 PCI_VEND_DEV(INTEL
, 7500_0
), PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
529 PCI_VEND_DEV(INTEL
, 7501_0
), PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
533 PCI_VEND_DEV(INTEL
, 7505_0
), PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
538 } /* 0 terminated list. */
541 MODULE_DEVICE_TABLE(pci
, e7xxx_pci_tbl
);
543 static struct pci_driver e7xxx_driver
= {
544 .name
= EDAC_MOD_STR
,
545 .probe
= e7xxx_init_one
,
546 .remove
= __devexit_p(e7xxx_remove_one
),
547 .id_table
= e7xxx_pci_tbl
,
550 static int __init
e7xxx_init(void)
552 return pci_register_driver(&e7xxx_driver
);
555 static void __exit
e7xxx_exit(void)
557 pci_unregister_driver(&e7xxx_driver
);
560 module_init(e7xxx_init
);
561 module_exit(e7xxx_exit
);
563 MODULE_LICENSE("GPL");
564 MODULE_AUTHOR("Linux Networx (http://lnxi.com) Thayne Harbaugh et al\n"
565 "Based on.work by Dan Hollis et al");
566 MODULE_DESCRIPTION("MC support for Intel e7xxx memory controllers");