?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
kbuild: document howto build external modules using several directories
[linux-2.6/verdex.git] / drivers / infiniband / hw / mthca / mthca_eq.c
blob34d68e5a72d863723b0de968591d9e302a395142
1 /*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
10 *
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
13 * conditions are met:
14 *
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
17 * disclaimer.
18 *
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
23 *
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 * SOFTWARE.
32 *
33 * $Id: mthca_eq.c 1382 2004-12-24 02:21:02Z roland $
34 */
35
36 #include <linux/init.h>
37 #include <linux/errno.h>
38 #include <linux/interrupt.h>
39 #include <linux/pci.h>
40
41 #include "mthca_dev.h"
42 #include "mthca_cmd.h"
43 #include "mthca_config_reg.h"
44
45 enum {
46 MTHCA_NUM_ASYNC_EQE = 0x80,
47 MTHCA_NUM_CMD_EQE = 0x80,
48 MTHCA_EQ_ENTRY_SIZE = 0x20
49 };
50
51 /*
52 * Must be packed because start is 64 bits but only aligned to 32 bits.
53 */
54 struct mthca_eq_context {
55 __be32 flags;
56 __be64 start;
57 __be32 logsize_usrpage;
58 __be32 tavor_pd; /* reserved for Arbel */
59 u8 reserved1[3];
60 u8 intr;
61 __be32 arbel_pd; /* lost_count for Tavor */
62 __be32 lkey;
63 u32 reserved2[2];
64 __be32 consumer_index;
65 __be32 producer_index;
66 u32 reserved3[4];
67 } __attribute__((packed));
68
69 #define MTHCA_EQ_STATUS_OK ( 0 << 28)
70 #define MTHCA_EQ_STATUS_OVERFLOW ( 9 << 28)
71 #define MTHCA_EQ_STATUS_WRITE_FAIL (10 << 28)
72 #define MTHCA_EQ_OWNER_SW ( 0 << 24)
73 #define MTHCA_EQ_OWNER_HW ( 1 << 24)
74 #define MTHCA_EQ_FLAG_TR ( 1 << 18)
75 #define MTHCA_EQ_FLAG_OI ( 1 << 17)
76 #define MTHCA_EQ_STATE_ARMED ( 1 << 8)
77 #define MTHCA_EQ_STATE_FIRED ( 2 << 8)
78 #define MTHCA_EQ_STATE_ALWAYS_ARMED ( 3 << 8)
79 #define MTHCA_EQ_STATE_ARBEL ( 8 << 8)
80
81 enum {
82 MTHCA_EVENT_TYPE_COMP = 0x00,
83 MTHCA_EVENT_TYPE_PATH_MIG = 0x01,
84 MTHCA_EVENT_TYPE_COMM_EST = 0x02,
85 MTHCA_EVENT_TYPE_SQ_DRAINED = 0x03,
86 MTHCA_EVENT_TYPE_SRQ_QP_LAST_WQE = 0x13,
87 MTHCA_EVENT_TYPE_SRQ_LIMIT = 0x14,
88 MTHCA_EVENT_TYPE_CQ_ERROR = 0x04,
89 MTHCA_EVENT_TYPE_WQ_CATAS_ERROR = 0x05,
90 MTHCA_EVENT_TYPE_EEC_CATAS_ERROR = 0x06,
91 MTHCA_EVENT_TYPE_PATH_MIG_FAILED = 0x07,
92 MTHCA_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
93 MTHCA_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11,
94 MTHCA_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12,
95 MTHCA_EVENT_TYPE_LOCAL_CATAS_ERROR = 0x08,
96 MTHCA_EVENT_TYPE_PORT_CHANGE = 0x09,
97 MTHCA_EVENT_TYPE_EQ_OVERFLOW = 0x0f,
98 MTHCA_EVENT_TYPE_ECC_DETECT = 0x0e,
99 MTHCA_EVENT_TYPE_CMD = 0x0a
100 };
101
102 #define MTHCA_ASYNC_EVENT_MASK ((1ULL << MTHCA_EVENT_TYPE_PATH_MIG) | \
103 (1ULL << MTHCA_EVENT_TYPE_COMM_EST) | \
104 (1ULL << MTHCA_EVENT_TYPE_SQ_DRAINED) | \
105 (1ULL << MTHCA_EVENT_TYPE_CQ_ERROR) | \
106 (1ULL << MTHCA_EVENT_TYPE_WQ_CATAS_ERROR) | \
107 (1ULL << MTHCA_EVENT_TYPE_EEC_CATAS_ERROR) | \
108 (1ULL << MTHCA_EVENT_TYPE_PATH_MIG_FAILED) | \
109 (1ULL << MTHCA_EVENT_TYPE_WQ_INVAL_REQ_ERROR) | \
110 (1ULL << MTHCA_EVENT_TYPE_WQ_ACCESS_ERROR) | \
111 (1ULL << MTHCA_EVENT_TYPE_LOCAL_CATAS_ERROR) | \
112 (1ULL << MTHCA_EVENT_TYPE_PORT_CHANGE) | \
113 (1ULL << MTHCA_EVENT_TYPE_ECC_DETECT))
114 #define MTHCA_SRQ_EVENT_MASK ((1ULL << MTHCA_EVENT_TYPE_SRQ_CATAS_ERROR) | \
115 (1ULL << MTHCA_EVENT_TYPE_SRQ_QP_LAST_WQE) | \
116 (1ULL << MTHCA_EVENT_TYPE_SRQ_LIMIT))
117 #define MTHCA_CMD_EVENT_MASK (1ULL << MTHCA_EVENT_TYPE_CMD)
118
119 #define MTHCA_EQ_DB_INC_CI (1 << 24)
120 #define MTHCA_EQ_DB_REQ_NOT (2 << 24)
121 #define MTHCA_EQ_DB_DISARM_CQ (3 << 24)
122 #define MTHCA_EQ_DB_SET_CI (4 << 24)
123 #define MTHCA_EQ_DB_ALWAYS_ARM (5 << 24)
124
125 struct mthca_eqe {
126 u8 reserved1;
127 u8 type;
128 u8 reserved2;
129 u8 subtype;
130 union {
131 u32 raw[6];
132 struct {
133 __be32 cqn;
134 } __attribute__((packed)) comp;
135 struct {
136 u16 reserved1;
137 __be16 token;
138 u32 reserved2;
139 u8 reserved3[3];
140 u8 status;
141 __be64 out_param;
142 } __attribute__((packed)) cmd;
143 struct {
144 __be32 qpn;
145 } __attribute__((packed)) qp;
146 struct {
147 __be32 srqn;
148 } __attribute__((packed)) srq;
149 struct {
150 __be32 cqn;
151 u32 reserved1;
152 u8 reserved2[3];
153 u8 syndrome;
154 } __attribute__((packed)) cq_err;
155 struct {
156 u32 reserved1[2];
157 __be32 port;
158 } __attribute__((packed)) port_change;
159 } event;
160 u8 reserved3[3];
161 u8 owner;
162 } __attribute__((packed));
163
164 #define MTHCA_EQ_ENTRY_OWNER_SW (0 << 7)
165 #define MTHCA_EQ_ENTRY_OWNER_HW (1 << 7)
166
167 static inline u64 async_mask(struct mthca_dev *dev)
168 {
169 return dev->mthca_flags & MTHCA_FLAG_SRQ ?
170 MTHCA_ASYNC_EVENT_MASK | MTHCA_SRQ_EVENT_MASK :
171 MTHCA_ASYNC_EVENT_MASK;
172 }
173
174 static inline void tavor_set_eq_ci(struct mthca_dev *dev, struct mthca_eq *eq, u32 ci)
175 {
176 __be32 doorbell[2];
177
178 doorbell[0] = cpu_to_be32(MTHCA_EQ_DB_SET_CI | eq->eqn);
179 doorbell[1] = cpu_to_be32(ci & (eq->nent - 1));
180
181 /*
182 * This barrier makes sure that all updates to ownership bits
183 * done by set_eqe_hw() hit memory before the consumer index
184 * is updated. set_eq_ci() allows the HCA to possibly write
185 * more EQ entries, and we want to avoid the exceedingly
186 * unlikely possibility of the HCA writing an entry and then
187 * having set_eqe_hw() overwrite the owner field.
188 */
189 wmb();
190 mthca_write64(doorbell,
191 dev->kar + MTHCA_EQ_DOORBELL,
192 MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
193 }
194
195 static inline void arbel_set_eq_ci(struct mthca_dev *dev, struct mthca_eq *eq, u32 ci)
196 {
197 /* See comment in tavor_set_eq_ci() above. */
198 wmb();
199 __raw_writel((__force u32) cpu_to_be32(ci),
200 dev->eq_regs.arbel.eq_set_ci_base + eq->eqn * 8);
201 /* We still want ordering, just not swabbing, so add a barrier */
202 mb();
203 }
204
205 static inline void set_eq_ci(struct mthca_dev *dev, struct mthca_eq *eq, u32 ci)
206 {
207 if (mthca_is_memfree(dev))
208 arbel_set_eq_ci(dev, eq, ci);
209 else
210 tavor_set_eq_ci(dev, eq, ci);
211 }
212
213 static inline void tavor_eq_req_not(struct mthca_dev *dev, int eqn)
214 {
215 __be32 doorbell[2];
216
217 doorbell[0] = cpu_to_be32(MTHCA_EQ_DB_REQ_NOT | eqn);
218 doorbell[1] = 0;
219
220 mthca_write64(doorbell,
221 dev->kar + MTHCA_EQ_DOORBELL,
222 MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
223 }
224
225 static inline void arbel_eq_req_not(struct mthca_dev *dev, u32 eqn_mask)
226 {
227 writel(eqn_mask, dev->eq_regs.arbel.eq_arm);
228 }
229
230 static inline void disarm_cq(struct mthca_dev *dev, int eqn, int cqn)
231 {
232 if (!mthca_is_memfree(dev)) {
233 __be32 doorbell[2];
234
235 doorbell[0] = cpu_to_be32(MTHCA_EQ_DB_DISARM_CQ | eqn);
236 doorbell[1] = cpu_to_be32(cqn);
237
238 mthca_write64(doorbell,
239 dev->kar + MTHCA_EQ_DOORBELL,
240 MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
241 }
242 }
243
244 static inline struct mthca_eqe *get_eqe(struct mthca_eq *eq, u32 entry)
245 {
246 unsigned long off = (entry & (eq->nent - 1)) * MTHCA_EQ_ENTRY_SIZE;
247 return eq->page_list[off / PAGE_SIZE].buf + off % PAGE_SIZE;
248 }
249
250 static inline struct mthca_eqe* next_eqe_sw(struct mthca_eq *eq)
251 {
252 struct mthca_eqe* eqe;
253 eqe = get_eqe(eq, eq->cons_index);
254 return (MTHCA_EQ_ENTRY_OWNER_HW & eqe->owner) ? NULL : eqe;
255 }
256
257 static inline void set_eqe_hw(struct mthca_eqe *eqe)
258 {
259 eqe->owner = MTHCA_EQ_ENTRY_OWNER_HW;
260 }
261
262 static void port_change(struct mthca_dev *dev, int port, int active)
263 {
264 struct ib_event record;
265
266 mthca_dbg(dev, "Port change to %s for port %d\n",
267 active ? "active" : "down", port);
268
269 record.device = &dev->ib_dev;
270 record.event = active ? IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
271 record.element.port_num = port;
272
273 ib_dispatch_event(&record);
274 }
275
276 static int mthca_eq_int(struct mthca_dev *dev, struct mthca_eq *eq)
277 {
278 struct mthca_eqe *eqe;
279 int disarm_cqn;
280 int eqes_found = 0;
281
282 while ((eqe = next_eqe_sw(eq))) {
283 int set_ci = 0;
284
285 /*
286 * Make sure we read EQ entry contents after we've
287 * checked the ownership bit.
288 */
289 rmb();
290
291 switch (eqe->type) {
292 case MTHCA_EVENT_TYPE_COMP:
293 disarm_cqn = be32_to_cpu(eqe->event.comp.cqn) & 0xffffff;
294 disarm_cq(dev, eq->eqn, disarm_cqn);
295 mthca_cq_completion(dev, disarm_cqn);
296 break;
297
298 case MTHCA_EVENT_TYPE_PATH_MIG:
299 mthca_qp_event(dev, be32_to_cpu(eqe->event.qp.qpn) & 0xffffff,
300 IB_EVENT_PATH_MIG);
301 break;
302
303 case MTHCA_EVENT_TYPE_COMM_EST:
304 mthca_qp_event(dev, be32_to_cpu(eqe->event.qp.qpn) & 0xffffff,
305 IB_EVENT_COMM_EST);
306 break;
307
308 case MTHCA_EVENT_TYPE_SQ_DRAINED:
309 mthca_qp_event(dev, be32_to_cpu(eqe->event.qp.qpn) & 0xffffff,
310 IB_EVENT_SQ_DRAINED);
311 break;
312
313 case MTHCA_EVENT_TYPE_SRQ_QP_LAST_WQE:
314 mthca_qp_event(dev, be32_to_cpu(eqe->event.qp.qpn) & 0xffffff,
315 IB_EVENT_QP_LAST_WQE_REACHED);
316 break;
317
318 case MTHCA_EVENT_TYPE_SRQ_LIMIT:
319 mthca_srq_event(dev, be32_to_cpu(eqe->event.srq.srqn) & 0xffffff,
320 IB_EVENT_SRQ_LIMIT_REACHED);
321 break;
322
323 case MTHCA_EVENT_TYPE_WQ_CATAS_ERROR:
324 mthca_qp_event(dev, be32_to_cpu(eqe->event.qp.qpn) & 0xffffff,
325 IB_EVENT_QP_FATAL);
326 break;
327
328 case MTHCA_EVENT_TYPE_PATH_MIG_FAILED:
329 mthca_qp_event(dev, be32_to_cpu(eqe->event.qp.qpn) & 0xffffff,
330 IB_EVENT_PATH_MIG_ERR);
331 break;
332
333 case MTHCA_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
334 mthca_qp_event(dev, be32_to_cpu(eqe->event.qp.qpn) & 0xffffff,
335 IB_EVENT_QP_REQ_ERR);
336 break;
337
338 case MTHCA_EVENT_TYPE_WQ_ACCESS_ERROR:
339 mthca_qp_event(dev, be32_to_cpu(eqe->event.qp.qpn) & 0xffffff,
340 IB_EVENT_QP_ACCESS_ERR);
341 break;
342
343 case MTHCA_EVENT_TYPE_CMD:
344 mthca_cmd_event(dev,
345 be16_to_cpu(eqe->event.cmd.token),
346 eqe->event.cmd.status,
347 be64_to_cpu(eqe->event.cmd.out_param));
348 /*
349 * cmd_event() may add more commands.
350 * The card will think the queue has overflowed if
351 * we don't tell it we've been processing events.
352 */
353 set_ci = 1;
354 break;
355
356 case MTHCA_EVENT_TYPE_PORT_CHANGE:
357 port_change(dev,
358 (be32_to_cpu(eqe->event.port_change.port) >> 28) & 3,
359 eqe->subtype == 0x4);
360 break;
361
362 case MTHCA_EVENT_TYPE_CQ_ERROR:
363 mthca_warn(dev, "CQ %s on CQN %06x\n",
364 eqe->event.cq_err.syndrome == 1 ?
365 "overrun" : "access violation",
366 be32_to_cpu(eqe->event.cq_err.cqn) & 0xffffff);
367 mthca_cq_event(dev, be32_to_cpu(eqe->event.cq_err.cqn),
368 IB_EVENT_CQ_ERR);
369 break;
370
371 case MTHCA_EVENT_TYPE_EQ_OVERFLOW:
372 mthca_warn(dev, "EQ overrun on EQN %d\n", eq->eqn);
373 break;
374
375 case MTHCA_EVENT_TYPE_EEC_CATAS_ERROR:
376 case MTHCA_EVENT_TYPE_SRQ_CATAS_ERROR:
377 case MTHCA_EVENT_TYPE_LOCAL_CATAS_ERROR:
378 case MTHCA_EVENT_TYPE_ECC_DETECT:
379 default:
380 mthca_warn(dev, "Unhandled event %02x(%02x) on EQ %d\n",
381 eqe->type, eqe->subtype, eq->eqn);
382 break;
383 };
384
385 set_eqe_hw(eqe);
386 ++eq->cons_index;
387 eqes_found = 1;
388
389 if (unlikely(set_ci)) {
390 /*
391 * Conditional on hca_type is OK here because
392 * this is a rare case, not the fast path.
393 */
394 set_eq_ci(dev, eq, eq->cons_index);
395 set_ci = 0;
396 }
397 }
398
399 /*
400 * Rely on caller to set consumer index so that we don't have
401 * to test hca_type in our interrupt handling fast path.
402 */
403 return eqes_found;
404 }
405
406 static irqreturn_t mthca_tavor_interrupt(int irq, void *dev_ptr, struct pt_regs *regs)
407 {
408 struct mthca_dev *dev = dev_ptr;
409 u32 ecr;
410 int i;
411
412 if (dev->eq_table.clr_mask)
413 writel(dev->eq_table.clr_mask, dev->eq_table.clr_int);
414
415 ecr = readl(dev->eq_regs.tavor.ecr_base + 4);
416 if (!ecr)
417 return IRQ_NONE;
418
419 writel(ecr, dev->eq_regs.tavor.ecr_base +
420 MTHCA_ECR_CLR_BASE - MTHCA_ECR_BASE + 4);
421
422 for (i = 0; i < MTHCA_NUM_EQ; ++i)
423 if (ecr & dev->eq_table.eq[i].eqn_mask) {
424 if (mthca_eq_int(dev, &dev->eq_table.eq[i]))
425 tavor_set_eq_ci(dev, &dev->eq_table.eq[i],
426 dev->eq_table.eq[i].cons_index);
427 tavor_eq_req_not(dev, dev->eq_table.eq[i].eqn);
428 }
429
430 return IRQ_HANDLED;
431 }
432
433 static irqreturn_t mthca_tavor_msi_x_interrupt(int irq, void *eq_ptr,
434 struct pt_regs *regs)
435 {
436 struct mthca_eq *eq = eq_ptr;
437 struct mthca_dev *dev = eq->dev;
438
439 mthca_eq_int(dev, eq);
440 tavor_set_eq_ci(dev, eq, eq->cons_index);
441 tavor_eq_req_not(dev, eq->eqn);
442
443 /* MSI-X vectors always belong to us */
444 return IRQ_HANDLED;
445 }
446
447 static irqreturn_t mthca_arbel_interrupt(int irq, void *dev_ptr, struct pt_regs *regs)
448 {
449 struct mthca_dev *dev = dev_ptr;
450 int work = 0;
451 int i;
452
453 if (dev->eq_table.clr_mask)
454 writel(dev->eq_table.clr_mask, dev->eq_table.clr_int);
455
456 for (i = 0; i < MTHCA_NUM_EQ; ++i)
457 if (mthca_eq_int(dev, &dev->eq_table.eq[i])) {
458 work = 1;
459 arbel_set_eq_ci(dev, &dev->eq_table.eq[i],
460 dev->eq_table.eq[i].cons_index);
461 }
462
463 arbel_eq_req_not(dev, dev->eq_table.arm_mask);
464
465 return IRQ_RETVAL(work);
466 }
467
468 static irqreturn_t mthca_arbel_msi_x_interrupt(int irq, void *eq_ptr,
469 struct pt_regs *regs)
470 {
471 struct mthca_eq *eq = eq_ptr;
472 struct mthca_dev *dev = eq->dev;
473
474 mthca_eq_int(dev, eq);
475 arbel_set_eq_ci(dev, eq, eq->cons_index);
476 arbel_eq_req_not(dev, eq->eqn_mask);
477
478 /* MSI-X vectors always belong to us */
479 return IRQ_HANDLED;
480 }
481
482 static int __devinit mthca_create_eq(struct mthca_dev *dev,
483 int nent,
484 u8 intr,
485 struct mthca_eq *eq)
486 {
487 int npages = (nent * MTHCA_EQ_ENTRY_SIZE + PAGE_SIZE - 1) /
488 PAGE_SIZE;
489 u64 *dma_list = NULL;
490 dma_addr_t t;
491 struct mthca_mailbox *mailbox;
492 struct mthca_eq_context *eq_context;
493 int err = -ENOMEM;
494 int i;
495 u8 status;
496
497 eq->dev = dev;
498 eq->nent = roundup_pow_of_two(max(nent, 2));
499
500 eq->page_list = kmalloc(npages * sizeof *eq->page_list,
501 GFP_KERNEL);
502 if (!eq->page_list)
503 goto err_out;
504
505 for (i = 0; i < npages; ++i)
506 eq->page_list[i].buf = NULL;
507
508 dma_list = kmalloc(npages * sizeof *dma_list, GFP_KERNEL);
509 if (!dma_list)
510 goto err_out_free;
511
512 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
513 if (IS_ERR(mailbox))
514 goto err_out_free;
515 eq_context = mailbox->buf;
516
517 for (i = 0; i < npages; ++i) {
518 eq->page_list[i].buf = dma_alloc_coherent(&dev->pdev->dev,
519 PAGE_SIZE, &t, GFP_KERNEL);
520 if (!eq->page_list[i].buf)
521 goto err_out_free_pages;
522
523 dma_list[i] = t;
524 pci_unmap_addr_set(&eq->page_list[i], mapping, t);
525
526 memset(eq->page_list[i].buf, 0, PAGE_SIZE);
527 }
528
529 for (i = 0; i < eq->nent; ++i)
530 set_eqe_hw(get_eqe(eq, i));
531
532 eq->eqn = mthca_alloc(&dev->eq_table.alloc);
533 if (eq->eqn == -1)
534 goto err_out_free_pages;
535
536 err = mthca_mr_alloc_phys(dev, dev->driver_pd.pd_num,
537 dma_list, PAGE_SHIFT, npages,
538 0, npages * PAGE_SIZE,
539 MTHCA_MPT_FLAG_LOCAL_WRITE |
540 MTHCA_MPT_FLAG_LOCAL_READ,
541 &eq->mr);
542 if (err)
543 goto err_out_free_eq;
544
545 memset(eq_context, 0, sizeof *eq_context);
546 eq_context->flags = cpu_to_be32(MTHCA_EQ_STATUS_OK |
547 MTHCA_EQ_OWNER_HW |
548 MTHCA_EQ_STATE_ARMED |
549 MTHCA_EQ_FLAG_TR);
550 if (mthca_is_memfree(dev))
551 eq_context->flags |= cpu_to_be32(MTHCA_EQ_STATE_ARBEL);
552
553 eq_context->logsize_usrpage = cpu_to_be32((ffs(eq->nent) - 1) << 24);
554 if (mthca_is_memfree(dev)) {
555 eq_context->arbel_pd = cpu_to_be32(dev->driver_pd.pd_num);
556 } else {
557 eq_context->logsize_usrpage |= cpu_to_be32(dev->driver_uar.index);
558 eq_context->tavor_pd = cpu_to_be32(dev->driver_pd.pd_num);
559 }
560 eq_context->intr = intr;
561 eq_context->lkey = cpu_to_be32(eq->mr.ibmr.lkey);
562
563 err = mthca_SW2HW_EQ(dev, mailbox, eq->eqn, &status);
564 if (err) {
565 mthca_warn(dev, "SW2HW_EQ failed (%d)\n", err);
566 goto err_out_free_mr;
567 }
568 if (status) {
569 mthca_warn(dev, "SW2HW_EQ returned status 0x%02x\n",
570 status);
571 err = -EINVAL;
572 goto err_out_free_mr;
573 }
574
575 kfree(dma_list);
576 mthca_free_mailbox(dev, mailbox);
577
578 eq->eqn_mask = swab32(1 << eq->eqn);
579 eq->cons_index = 0;
580
581 dev->eq_table.arm_mask |= eq->eqn_mask;
582
583 mthca_dbg(dev, "Allocated EQ %d with %d entries\n",
584 eq->eqn, eq->nent);
585
586 return err;
587
588 err_out_free_mr:
589 mthca_free_mr(dev, &eq->mr);
590
591 err_out_free_eq:
592 mthca_free(&dev->eq_table.alloc, eq->eqn);
593
594 err_out_free_pages:
595 for (i = 0; i < npages; ++i)
596 if (eq->page_list[i].buf)
597 dma_free_coherent(&dev->pdev->dev, PAGE_SIZE,
598 eq->page_list[i].buf,
599 pci_unmap_addr(&eq->page_list[i],
600 mapping));
601
602 mthca_free_mailbox(dev, mailbox);
603
604 err_out_free:
605 kfree(eq->page_list);
606 kfree(dma_list);
607
608 err_out:
609 return err;
610 }
611
612 static void mthca_free_eq(struct mthca_dev *dev,
613 struct mthca_eq *eq)
614 {
615 struct mthca_mailbox *mailbox;
616 int err;
617 u8 status;
618 int npages = (eq->nent * MTHCA_EQ_ENTRY_SIZE + PAGE_SIZE - 1) /
619 PAGE_SIZE;
620 int i;
621
622 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
623 if (IS_ERR(mailbox))
624 return;
625
626 err = mthca_HW2SW_EQ(dev, mailbox, eq->eqn, &status);
627 if (err)
628 mthca_warn(dev, "HW2SW_EQ failed (%d)\n", err);
629 if (status)
630 mthca_warn(dev, "HW2SW_EQ returned status 0x%02x\n", status);
631
632 dev->eq_table.arm_mask &= ~eq->eqn_mask;
633
634 if (0) {
635 mthca_dbg(dev, "Dumping EQ context %02x:\n", eq->eqn);
636 for (i = 0; i < sizeof (struct mthca_eq_context) / 4; ++i) {
637 if (i % 4 == 0)
638 printk("[%02x] ", i * 4);
639 printk(" %08x", be32_to_cpup(mailbox->buf + i * 4));
640 if ((i + 1) % 4 == 0)
641 printk("\n");
642 }
643 }
644
645 mthca_free_mr(dev, &eq->mr);
646 for (i = 0; i < npages; ++i)
647 pci_free_consistent(dev->pdev, PAGE_SIZE,
648 eq->page_list[i].buf,
649 pci_unmap_addr(&eq->page_list[i], mapping));
650
651 kfree(eq->page_list);
652 mthca_free_mailbox(dev, mailbox);
653 }
654
655 static void mthca_free_irqs(struct mthca_dev *dev)
656 {
657 int i;
658
659 if (dev->eq_table.have_irq)
660 free_irq(dev->pdev->irq, dev);
661 for (i = 0; i < MTHCA_NUM_EQ; ++i)
662 if (dev->eq_table.eq[i].have_irq)
663 free_irq(dev->eq_table.eq[i].msi_x_vector,
664 dev->eq_table.eq + i);
665 }
666
667 static int __devinit mthca_map_reg(struct mthca_dev *dev,
668 unsigned long offset, unsigned long size,
669 void __iomem **map)
670 {
671 unsigned long base = pci_resource_start(dev->pdev, 0);
672
673 if (!request_mem_region(base + offset, size, DRV_NAME))
674 return -EBUSY;
675
676 *map = ioremap(base + offset, size);
677 if (!*map) {
678 release_mem_region(base + offset, size);
679 return -ENOMEM;
680 }
681
682 return 0;
683 }
684
685 static void mthca_unmap_reg(struct mthca_dev *dev, unsigned long offset,
686 unsigned long size, void __iomem *map)
687 {
688 unsigned long base = pci_resource_start(dev->pdev, 0);
689
690 release_mem_region(base + offset, size);
691 iounmap(map);
692 }
693
694 static int __devinit mthca_map_eq_regs(struct mthca_dev *dev)
695 {
696 unsigned long mthca_base;
697
698 mthca_base = pci_resource_start(dev->pdev, 0);
699
700 if (mthca_is_memfree(dev)) {
701 /*
702 * We assume that the EQ arm and EQ set CI registers
703 * fall within the first BAR. We can't trust the
704 * values firmware gives us, since those addresses are
705 * valid on the HCA's side of the PCI bus but not
706 * necessarily the host side.
707 */
708 if (mthca_map_reg(dev, (pci_resource_len(dev->pdev, 0) - 1) &
709 dev->fw.arbel.clr_int_base, MTHCA_CLR_INT_SIZE,
710 &dev->clr_base)) {
711 mthca_err(dev, "Couldn't map interrupt clear register, "
712 "aborting.\n");
713 return -ENOMEM;
714 }
715
716 /*
717 * Add 4 because we limit ourselves to EQs 0 ... 31,
718 * so we only need the low word of the register.
719 */
720 if (mthca_map_reg(dev, ((pci_resource_len(dev->pdev, 0) - 1) &
721 dev->fw.arbel.eq_arm_base) + 4, 4,
722 &dev->eq_regs.arbel.eq_arm)) {
723 mthca_err(dev, "Couldn't map EQ arm register, aborting.\n");
724 mthca_unmap_reg(dev, (pci_resource_len(dev->pdev, 0) - 1) &
725 dev->fw.arbel.clr_int_base, MTHCA_CLR_INT_SIZE,
726 dev->clr_base);
727 return -ENOMEM;
728 }
729
730 if (mthca_map_reg(dev, (pci_resource_len(dev->pdev, 0) - 1) &
731 dev->fw.arbel.eq_set_ci_base,
732 MTHCA_EQ_SET_CI_SIZE,
733 &dev->eq_regs.arbel.eq_set_ci_base)) {
734 mthca_err(dev, "Couldn't map EQ CI register, aborting.\n");
735 mthca_unmap_reg(dev, ((pci_resource_len(dev->pdev, 0) - 1) &
736 dev->fw.arbel.eq_arm_base) + 4, 4,
737 dev->eq_regs.arbel.eq_arm);
738 mthca_unmap_reg(dev, (pci_resource_len(dev->pdev, 0) - 1) &
739 dev->fw.arbel.clr_int_base, MTHCA_CLR_INT_SIZE,
740 dev->clr_base);
741 return -ENOMEM;
742 }
743 } else {
744 if (mthca_map_reg(dev, MTHCA_CLR_INT_BASE, MTHCA_CLR_INT_SIZE,
745 &dev->clr_base)) {
746 mthca_err(dev, "Couldn't map interrupt clear register, "
747 "aborting.\n");
748 return -ENOMEM;
749 }
750
751 if (mthca_map_reg(dev, MTHCA_ECR_BASE,
752 MTHCA_ECR_SIZE + MTHCA_ECR_CLR_SIZE,
753 &dev->eq_regs.tavor.ecr_base)) {
754 mthca_err(dev, "Couldn't map ecr register, "
755 "aborting.\n");
756 mthca_unmap_reg(dev, MTHCA_CLR_INT_BASE, MTHCA_CLR_INT_SIZE,
757 dev->clr_base);
758 return -ENOMEM;
759 }
760 }
761
762 return 0;
763
764 }
765
766 static void __devexit mthca_unmap_eq_regs(struct mthca_dev *dev)
767 {
768 if (mthca_is_memfree(dev)) {
769 mthca_unmap_reg(dev, (pci_resource_len(dev->pdev, 0) - 1) &
770 dev->fw.arbel.eq_set_ci_base,
771 MTHCA_EQ_SET_CI_SIZE,
772 dev->eq_regs.arbel.eq_set_ci_base);
773 mthca_unmap_reg(dev, ((pci_resource_len(dev->pdev, 0) - 1) &
774 dev->fw.arbel.eq_arm_base) + 4, 4,
775 dev->eq_regs.arbel.eq_arm);
776 mthca_unmap_reg(dev, (pci_resource_len(dev->pdev, 0) - 1) &
777 dev->fw.arbel.clr_int_base, MTHCA_CLR_INT_SIZE,
778 dev->clr_base);
779 } else {
780 mthca_unmap_reg(dev, MTHCA_ECR_BASE,
781 MTHCA_ECR_SIZE + MTHCA_ECR_CLR_SIZE,
782 dev->eq_regs.tavor.ecr_base);
783 mthca_unmap_reg(dev, MTHCA_CLR_INT_BASE, MTHCA_CLR_INT_SIZE,
784 dev->clr_base);
785 }
786 }
787
788 int __devinit mthca_map_eq_icm(struct mthca_dev *dev, u64 icm_virt)
789 {
790 int ret;
791 u8 status;
792
793 /*
794 * We assume that mapping one page is enough for the whole EQ
795 * context table. This is fine with all current HCAs, because
796 * we only use 32 EQs and each EQ uses 32 bytes of context
797 * memory, or 1 KB total.
798 */
799 dev->eq_table.icm_virt = icm_virt;
800 dev->eq_table.icm_page = alloc_page(GFP_HIGHUSER);
801 if (!dev->eq_table.icm_page)
802 return -ENOMEM;
803 dev->eq_table.icm_dma = pci_map_page(dev->pdev, dev->eq_table.icm_page, 0,
804 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
805 if (pci_dma_mapping_error(dev->eq_table.icm_dma)) {
806 __free_page(dev->eq_table.icm_page);
807 return -ENOMEM;
808 }
809
810 ret = mthca_MAP_ICM_page(dev, dev->eq_table.icm_dma, icm_virt, &status);
811 if (!ret && status)
812 ret = -EINVAL;
813 if (ret) {
814 pci_unmap_page(dev->pdev, dev->eq_table.icm_dma, PAGE_SIZE,
815 PCI_DMA_BIDIRECTIONAL);
816 __free_page(dev->eq_table.icm_page);
817 }
818
819 return ret;
820 }
821
822 void __devexit mthca_unmap_eq_icm(struct mthca_dev *dev)
823 {
824 u8 status;
825
826 mthca_UNMAP_ICM(dev, dev->eq_table.icm_virt, PAGE_SIZE / 4096, &status);
827 pci_unmap_page(dev->pdev, dev->eq_table.icm_dma, PAGE_SIZE,
828 PCI_DMA_BIDIRECTIONAL);
829 __free_page(dev->eq_table.icm_page);
830 }
831
832 int __devinit mthca_init_eq_table(struct mthca_dev *dev)
833 {
834 int err;
835 u8 status;
836 u8 intr;
837 int i;
838
839 err = mthca_alloc_init(&dev->eq_table.alloc,
840 dev->limits.num_eqs,
841 dev->limits.num_eqs - 1,
842 dev->limits.reserved_eqs);
843 if (err)
844 return err;
845
846 err = mthca_map_eq_regs(dev);
847 if (err)
848 goto err_out_free;
849
850 if (dev->mthca_flags & MTHCA_FLAG_MSI ||
851 dev->mthca_flags & MTHCA_FLAG_MSI_X) {
852 dev->eq_table.clr_mask = 0;
853 } else {
854 dev->eq_table.clr_mask =
855 swab32(1 << (dev->eq_table.inta_pin & 31));
856 dev->eq_table.clr_int = dev->clr_base +
857 (dev->eq_table.inta_pin < 32 ? 4 : 0);
858 }
859
860 dev->eq_table.arm_mask = 0;
861
862 intr = (dev->mthca_flags & MTHCA_FLAG_MSI) ?
863 128 : dev->eq_table.inta_pin;
864
865 err = mthca_create_eq(dev, dev->limits.num_cqs,
866 (dev->mthca_flags & MTHCA_FLAG_MSI_X) ? 128 : intr,
867 &dev->eq_table.eq[MTHCA_EQ_COMP]);
868 if (err)
869 goto err_out_unmap;
870
871 err = mthca_create_eq(dev, MTHCA_NUM_ASYNC_EQE,
872 (dev->mthca_flags & MTHCA_FLAG_MSI_X) ? 129 : intr,
873 &dev->eq_table.eq[MTHCA_EQ_ASYNC]);
874 if (err)
875 goto err_out_comp;
876
877 err = mthca_create_eq(dev, MTHCA_NUM_CMD_EQE,
878 (dev->mthca_flags & MTHCA_FLAG_MSI_X) ? 130 : intr,
879 &dev->eq_table.eq[MTHCA_EQ_CMD]);
880 if (err)
881 goto err_out_async;
882
883 if (dev->mthca_flags & MTHCA_FLAG_MSI_X) {
884 static const char *eq_name[] = {
885 [MTHCA_EQ_COMP] = DRV_NAME " (comp)",
886 [MTHCA_EQ_ASYNC] = DRV_NAME " (async)",
887 [MTHCA_EQ_CMD] = DRV_NAME " (cmd)"
888 };
889
890 for (i = 0; i < MTHCA_NUM_EQ; ++i) {
891 err = request_irq(dev->eq_table.eq[i].msi_x_vector,
892 mthca_is_memfree(dev) ?
893 mthca_arbel_msi_x_interrupt :
894 mthca_tavor_msi_x_interrupt,
895 0, eq_name[i], dev->eq_table.eq + i);
896 if (err)
897 goto err_out_cmd;
898 dev->eq_table.eq[i].have_irq = 1;
899 }
900 } else {
901 err = request_irq(dev->pdev->irq,
902 mthca_is_memfree(dev) ?
903 mthca_arbel_interrupt :
904 mthca_tavor_interrupt,
905 SA_SHIRQ, DRV_NAME, dev);
906 if (err)
907 goto err_out_cmd;
908 dev->eq_table.have_irq = 1;
909 }
910
911 err = mthca_MAP_EQ(dev, async_mask(dev),
912 0, dev->eq_table.eq[MTHCA_EQ_ASYNC].eqn, &status);
913 if (err)
914 mthca_warn(dev, "MAP_EQ for async EQ %d failed (%d)\n",
915 dev->eq_table.eq[MTHCA_EQ_ASYNC].eqn, err);
916 if (status)
917 mthca_warn(dev, "MAP_EQ for async EQ %d returned status 0x%02x\n",
918 dev->eq_table.eq[MTHCA_EQ_ASYNC].eqn, status);
919
920 err = mthca_MAP_EQ(dev, MTHCA_CMD_EVENT_MASK,
921 0, dev->eq_table.eq[MTHCA_EQ_CMD].eqn, &status);
922 if (err)
923 mthca_warn(dev, "MAP_EQ for cmd EQ %d failed (%d)\n",
924 dev->eq_table.eq[MTHCA_EQ_CMD].eqn, err);
925 if (status)
926 mthca_warn(dev, "MAP_EQ for cmd EQ %d returned status 0x%02x\n",
927 dev->eq_table.eq[MTHCA_EQ_CMD].eqn, status);
928
929 for (i = 0; i < MTHCA_EQ_CMD; ++i)
930 if (mthca_is_memfree(dev))
931 arbel_eq_req_not(dev, dev->eq_table.eq[i].eqn_mask);
932 else
933 tavor_eq_req_not(dev, dev->eq_table.eq[i].eqn);
934
935 return 0;
936
937 err_out_cmd:
938 mthca_free_irqs(dev);
939 mthca_free_eq(dev, &dev->eq_table.eq[MTHCA_EQ_CMD]);
940
941 err_out_async:
942 mthca_free_eq(dev, &dev->eq_table.eq[MTHCA_EQ_ASYNC]);
943
944 err_out_comp:
945 mthca_free_eq(dev, &dev->eq_table.eq[MTHCA_EQ_COMP]);
946
947 err_out_unmap:
948 mthca_unmap_eq_regs(dev);
949
950 err_out_free:
951 mthca_alloc_cleanup(&dev->eq_table.alloc);
952 return err;
953 }
954
955 void __devexit mthca_cleanup_eq_table(struct mthca_dev *dev)
956 {
957 u8 status;
958 int i;
959
960 mthca_free_irqs(dev);
961
962 mthca_MAP_EQ(dev, async_mask(dev),
963 1, dev->eq_table.eq[MTHCA_EQ_ASYNC].eqn, &status);
964 mthca_MAP_EQ(dev, MTHCA_CMD_EVENT_MASK,
965 1, dev->eq_table.eq[MTHCA_EQ_CMD].eqn, &status);
966
967 for (i = 0; i < MTHCA_NUM_EQ; ++i)
968 mthca_free_eq(dev, &dev->eq_table.eq[i]);
969
970 mthca_unmap_eq_regs(dev);
971
972 mthca_alloc_cleanup(&dev->eq_table.alloc);
973 }
Verdex Pro support