kbuild: document howto build external modules using several directories
[linux-2.6/verdex.git] / drivers / mmc / au1xmmc.c
blobaaf04638054e64148babae42a6e18e12079019cb
1 /*
2 * linux/drivers/mmc/au1xmmc.c - AU1XX0 MMC driver
4 * Copyright (c) 2005, Advanced Micro Devices, Inc.
6 * Developed with help from the 2.4.30 MMC AU1XXX controller including
7 * the following copyright notices:
8 * Copyright (c) 2003-2004 Embedded Edge, LLC.
9 * Portions Copyright (C) 2002 Embedix, Inc
10 * Copyright 2002 Hewlett-Packard Company
12 * 2.6 version of this driver inspired by:
13 * (drivers/mmc/wbsd.c) Copyright (C) 2004-2005 Pierre Ossman,
14 * All Rights Reserved.
15 * (drivers/mmc/pxa.c) Copyright (C) 2003 Russell King,
16 * All Rights Reserved.
19 * This program is free software; you can redistribute it and/or modify
20 * it under the terms of the GNU General Public License version 2 as
21 * published by the Free Software Foundation.
24 /* Why is a timer used to detect insert events?
26 * From the AU1100 MMC application guide:
27 * If the Au1100-based design is intended to support both MultiMediaCards
28 * and 1- or 4-data bit SecureDigital cards, then the solution is to
29 * connect a weak (560KOhm) pull-up resistor to connector pin 1.
30 * In doing so, a MMC card never enters SPI-mode communications,
31 * but now the SecureDigital card-detect feature of CD/DAT3 is ineffective
32 * (the low to high transition will not occur).
34 * So we use the timer to check the status manually.
37 #include <linux/config.h>
38 #include <linux/module.h>
39 #include <linux/init.h>
40 #include <linux/device.h>
41 #include <linux/mm.h>
42 #include <linux/interrupt.h>
43 #include <linux/dma-mapping.h>
45 #include <linux/mmc/host.h>
46 #include <linux/mmc/protocol.h>
47 #include <asm/io.h>
48 #include <asm/mach-au1x00/au1000.h>
49 #include <asm/mach-au1x00/au1xxx_dbdma.h>
50 #include <asm/mach-au1x00/au1100_mmc.h>
51 #include <asm/scatterlist.h>
53 #include <au1xxx.h>
54 #include "au1xmmc.h"
56 #define DRIVER_NAME "au1xxx-mmc"
58 /* Set this to enable special debugging macros */
59 /* #define MMC_DEBUG */
61 #ifdef MMC_DEBUG
62 #define DEBUG(fmt, idx, args...) printk("au1xx(%d): DEBUG: " fmt, idx, ##args)
63 #else
64 #define DEBUG(fmt, idx, args...)
65 #endif
67 const struct {
68 u32 iobase;
69 u32 tx_devid, rx_devid;
70 u16 bcsrpwr;
71 u16 bcsrstatus;
72 u16 wpstatus;
73 } au1xmmc_card_table[] = {
74 { SD0_BASE, DSCR_CMD0_SDMS_TX0, DSCR_CMD0_SDMS_RX0,
75 BCSR_BOARD_SD0PWR, BCSR_INT_SD0INSERT, BCSR_STATUS_SD0WP },
76 #ifndef CONFIG_MIPS_DB1200
77 { SD1_BASE, DSCR_CMD0_SDMS_TX1, DSCR_CMD0_SDMS_RX1,
78 BCSR_BOARD_DS1PWR, BCSR_INT_SD1INSERT, BCSR_STATUS_SD1WP }
79 #endif
82 #define AU1XMMC_CONTROLLER_COUNT \
83 (sizeof(au1xmmc_card_table) / sizeof(au1xmmc_card_table[0]))
85 /* This array stores pointers for the hosts (used by the IRQ handler) */
86 struct au1xmmc_host *au1xmmc_hosts[AU1XMMC_CONTROLLER_COUNT];
87 static int dma = 1;
89 #ifdef MODULE
90 MODULE_PARM(dma, "i");
91 MODULE_PARM_DESC(dma, "Use DMA engine for data transfers (0 = disabled)");
92 #endif
94 static inline void IRQ_ON(struct au1xmmc_host *host, u32 mask)
96 u32 val = au_readl(HOST_CONFIG(host));
97 val |= mask;
98 au_writel(val, HOST_CONFIG(host));
99 au_sync();
102 static inline void FLUSH_FIFO(struct au1xmmc_host *host)
104 u32 val = au_readl(HOST_CONFIG2(host));
106 au_writel(val | SD_CONFIG2_FF, HOST_CONFIG2(host));
107 au_sync_delay(1);
109 /* SEND_STOP will turn off clock control - this re-enables it */
110 val &= ~SD_CONFIG2_DF;
112 au_writel(val, HOST_CONFIG2(host));
113 au_sync();
116 static inline void IRQ_OFF(struct au1xmmc_host *host, u32 mask)
118 u32 val = au_readl(HOST_CONFIG(host));
119 val &= ~mask;
120 au_writel(val, HOST_CONFIG(host));
121 au_sync();
124 static inline void SEND_STOP(struct au1xmmc_host *host)
127 /* We know the value of CONFIG2, so avoid a read we don't need */
128 u32 mask = SD_CONFIG2_EN;
130 WARN_ON(host->status != HOST_S_DATA);
131 host->status = HOST_S_STOP;
133 au_writel(mask | SD_CONFIG2_DF, HOST_CONFIG2(host));
134 au_sync();
136 /* Send the stop commmand */
137 au_writel(STOP_CMD, HOST_CMD(host));
140 static void au1xmmc_set_power(struct au1xmmc_host *host, int state)
143 u32 val = au1xmmc_card_table[host->id].bcsrpwr;
145 bcsr->board &= ~val;
146 if (state) bcsr->board |= val;
148 au_sync_delay(1);
151 static inline int au1xmmc_card_inserted(struct au1xmmc_host *host)
153 return (bcsr->sig_status & au1xmmc_card_table[host->id].bcsrstatus)
154 ? 1 : 0;
157 static inline int au1xmmc_card_readonly(struct au1xmmc_host *host)
159 return (bcsr->status & au1xmmc_card_table[host->id].wpstatus)
160 ? 1 : 0;
163 static void au1xmmc_finish_request(struct au1xmmc_host *host)
166 struct mmc_request *mrq = host->mrq;
168 host->mrq = NULL;
169 host->flags &= HOST_F_ACTIVE;
171 host->dma.len = 0;
172 host->dma.dir = 0;
174 host->pio.index = 0;
175 host->pio.offset = 0;
176 host->pio.len = 0;
178 host->status = HOST_S_IDLE;
180 bcsr->disk_leds |= (1 << 8);
182 mmc_request_done(host->mmc, mrq);
185 static void au1xmmc_tasklet_finish(unsigned long param)
187 struct au1xmmc_host *host = (struct au1xmmc_host *) param;
188 au1xmmc_finish_request(host);
191 static int au1xmmc_send_command(struct au1xmmc_host *host, int wait,
192 struct mmc_command *cmd)
195 u32 mmccmd = (cmd->opcode << SD_CMD_CI_SHIFT);
197 switch(cmd->flags) {
198 case MMC_RSP_R1:
199 mmccmd |= SD_CMD_RT_1;
200 break;
201 case MMC_RSP_R1B:
202 mmccmd |= SD_CMD_RT_1B;
203 break;
204 case MMC_RSP_R2:
205 mmccmd |= SD_CMD_RT_2;
206 break;
207 case MMC_RSP_R3:
208 mmccmd |= SD_CMD_RT_3;
209 break;
212 switch(cmd->opcode) {
213 case MMC_READ_SINGLE_BLOCK:
214 case SD_APP_SEND_SCR:
215 mmccmd |= SD_CMD_CT_2;
216 break;
217 case MMC_READ_MULTIPLE_BLOCK:
218 mmccmd |= SD_CMD_CT_4;
219 break;
220 case MMC_WRITE_BLOCK:
221 mmccmd |= SD_CMD_CT_1;
222 break;
224 case MMC_WRITE_MULTIPLE_BLOCK:
225 mmccmd |= SD_CMD_CT_3;
226 break;
227 case MMC_STOP_TRANSMISSION:
228 mmccmd |= SD_CMD_CT_7;
229 break;
232 au_writel(cmd->arg, HOST_CMDARG(host));
233 au_sync();
235 if (wait)
236 IRQ_OFF(host, SD_CONFIG_CR);
238 au_writel((mmccmd | SD_CMD_GO), HOST_CMD(host));
239 au_sync();
241 /* Wait for the command to go on the line */
243 while(1) {
244 if (!(au_readl(HOST_CMD(host)) & SD_CMD_GO))
245 break;
248 /* Wait for the command to come back */
250 if (wait) {
251 u32 status = au_readl(HOST_STATUS(host));
253 while(!(status & SD_STATUS_CR))
254 status = au_readl(HOST_STATUS(host));
256 /* Clear the CR status */
257 au_writel(SD_STATUS_CR, HOST_STATUS(host));
259 IRQ_ON(host, SD_CONFIG_CR);
262 return MMC_ERR_NONE;
265 static void au1xmmc_data_complete(struct au1xmmc_host *host, u32 status)
268 struct mmc_request *mrq = host->mrq;
269 struct mmc_data *data;
270 u32 crc;
272 WARN_ON(host->status != HOST_S_DATA && host->status != HOST_S_STOP);
274 if (host->mrq == NULL)
275 return;
277 data = mrq->cmd->data;
279 if (status == 0)
280 status = au_readl(HOST_STATUS(host));
282 /* The transaction is really over when the SD_STATUS_DB bit is clear */
284 while((host->flags & HOST_F_XMIT) && (status & SD_STATUS_DB))
285 status = au_readl(HOST_STATUS(host));
287 data->error = MMC_ERR_NONE;
288 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, host->dma.dir);
290 /* Process any errors */
292 crc = (status & (SD_STATUS_WC | SD_STATUS_RC));
293 if (host->flags & HOST_F_XMIT)
294 crc |= ((status & 0x07) == 0x02) ? 0 : 1;
296 if (crc)
297 data->error = MMC_ERR_BADCRC;
299 /* Clear the CRC bits */
300 au_writel(SD_STATUS_WC | SD_STATUS_RC, HOST_STATUS(host));
302 data->bytes_xfered = 0;
304 if (data->error == MMC_ERR_NONE) {
305 if (host->flags & HOST_F_DMA) {
306 u32 chan = DMA_CHANNEL(host);
308 chan_tab_t *c = *((chan_tab_t **) chan);
309 au1x_dma_chan_t *cp = c->chan_ptr;
310 data->bytes_xfered = cp->ddma_bytecnt;
312 else
313 data->bytes_xfered =
314 (data->blocks * (1 << data->blksz_bits)) -
315 host->pio.len;
318 au1xmmc_finish_request(host);
321 static void au1xmmc_tasklet_data(unsigned long param)
323 struct au1xmmc_host *host = (struct au1xmmc_host *) param;
325 u32 status = au_readl(HOST_STATUS(host));
326 au1xmmc_data_complete(host, status);
329 #define AU1XMMC_MAX_TRANSFER 8
331 static void au1xmmc_send_pio(struct au1xmmc_host *host)
334 struct mmc_data *data = 0;
335 int sg_len, max, count = 0;
336 unsigned char *sg_ptr;
337 u32 status = 0;
338 struct scatterlist *sg;
340 data = host->mrq->data;
342 if (!(host->flags & HOST_F_XMIT))
343 return;
345 /* This is the pointer to the data buffer */
346 sg = &data->sg[host->pio.index];
347 sg_ptr = page_address(sg->page) + sg->offset + host->pio.offset;
349 /* This is the space left inside the buffer */
350 sg_len = data->sg[host->pio.index].length - host->pio.offset;
352 /* Check to if we need less then the size of the sg_buffer */
354 max = (sg_len > host->pio.len) ? host->pio.len : sg_len;
355 if (max > AU1XMMC_MAX_TRANSFER) max = AU1XMMC_MAX_TRANSFER;
357 for(count = 0; count < max; count++ ) {
358 unsigned char val;
360 status = au_readl(HOST_STATUS(host));
362 if (!(status & SD_STATUS_TH))
363 break;
365 val = *sg_ptr++;
367 au_writel((unsigned long) val, HOST_TXPORT(host));
368 au_sync();
371 host->pio.len -= count;
372 host->pio.offset += count;
374 if (count == sg_len) {
375 host->pio.index++;
376 host->pio.offset = 0;
379 if (host->pio.len == 0) {
380 IRQ_OFF(host, SD_CONFIG_TH);
382 if (host->flags & HOST_F_STOP)
383 SEND_STOP(host);
385 tasklet_schedule(&host->data_task);
389 static void au1xmmc_receive_pio(struct au1xmmc_host *host)
392 struct mmc_data *data = 0;
393 int sg_len = 0, max = 0, count = 0;
394 unsigned char *sg_ptr = 0;
395 u32 status = 0;
396 struct scatterlist *sg;
398 data = host->mrq->data;
400 if (!(host->flags & HOST_F_RECV))
401 return;
403 max = host->pio.len;
405 if (host->pio.index < host->dma.len) {
406 sg = &data->sg[host->pio.index];
407 sg_ptr = page_address(sg->page) + sg->offset + host->pio.offset;
409 /* This is the space left inside the buffer */
410 sg_len = sg_dma_len(&data->sg[host->pio.index]) - host->pio.offset;
412 /* Check to if we need less then the size of the sg_buffer */
413 if (sg_len < max) max = sg_len;
416 if (max > AU1XMMC_MAX_TRANSFER)
417 max = AU1XMMC_MAX_TRANSFER;
419 for(count = 0; count < max; count++ ) {
420 u32 val;
421 status = au_readl(HOST_STATUS(host));
423 if (!(status & SD_STATUS_NE))
424 break;
426 if (status & SD_STATUS_RC) {
427 DEBUG("RX CRC Error [%d + %d].\n", host->id,
428 host->pio.len, count);
429 break;
432 if (status & SD_STATUS_RO) {
433 DEBUG("RX Overrun [%d + %d]\n", host->id,
434 host->pio.len, count);
435 break;
437 else if (status & SD_STATUS_RU) {
438 DEBUG("RX Underrun [%d + %d]\n", host->id,
439 host->pio.len, count);
440 break;
443 val = au_readl(HOST_RXPORT(host));
445 if (sg_ptr)
446 *sg_ptr++ = (unsigned char) (val & 0xFF);
449 host->pio.len -= count;
450 host->pio.offset += count;
452 if (sg_len && count == sg_len) {
453 host->pio.index++;
454 host->pio.offset = 0;
457 if (host->pio.len == 0) {
458 //IRQ_OFF(host, SD_CONFIG_RA | SD_CONFIG_RF);
459 IRQ_OFF(host, SD_CONFIG_NE);
461 if (host->flags & HOST_F_STOP)
462 SEND_STOP(host);
464 tasklet_schedule(&host->data_task);
468 /* static void au1xmmc_cmd_complete
469 This is called when a command has been completed - grab the response
470 and check for errors. Then start the data transfer if it is indicated.
473 static void au1xmmc_cmd_complete(struct au1xmmc_host *host, u32 status)
476 struct mmc_request *mrq = host->mrq;
477 struct mmc_command *cmd;
478 int trans;
480 if (!host->mrq)
481 return;
483 cmd = mrq->cmd;
484 cmd->error = MMC_ERR_NONE;
486 if ((cmd->flags & MMC_RSP_MASK) == MMC_RSP_SHORT) {
488 /* Techincally, we should be getting all 48 bits of the response
489 * (SD_RESP1 + SD_RESP2), but because our response omits the CRC,
490 * our data ends up being shifted 8 bits to the right. In this case,
491 * that means that the OSR data starts at bit 31, so we can just
492 * read RESP0 and return that
495 cmd->resp[0] = au_readl(host->iobase + SD_RESP0);
497 else if ((cmd->flags & MMC_RSP_MASK) == MMC_RSP_LONG) {
498 u32 r[4];
499 int i;
501 r[0] = au_readl(host->iobase + SD_RESP3);
502 r[1] = au_readl(host->iobase + SD_RESP2);
503 r[2] = au_readl(host->iobase + SD_RESP1);
504 r[3] = au_readl(host->iobase + SD_RESP0);
506 /* The CRC is omitted from the response, so really we only got
507 * 120 bytes, but the engine expects 128 bits, so we have to shift
508 * things up
511 for(i = 0; i < 4; i++) {
512 cmd->resp[i] = (r[i] & 0x00FFFFFF) << 8;
513 if (i != 3) cmd->resp[i] |= (r[i + 1] & 0xFF000000) >> 24;
517 /* Figure out errors */
519 if (status & (SD_STATUS_SC | SD_STATUS_WC | SD_STATUS_RC))
520 cmd->error = MMC_ERR_BADCRC;
522 trans = host->flags & (HOST_F_XMIT | HOST_F_RECV);
524 if (!trans || cmd->error != MMC_ERR_NONE) {
526 IRQ_OFF(host, SD_CONFIG_TH | SD_CONFIG_RA|SD_CONFIG_RF);
527 tasklet_schedule(&host->finish_task);
528 return;
531 host->status = HOST_S_DATA;
533 if (host->flags & HOST_F_DMA) {
534 u32 channel = DMA_CHANNEL(host);
536 /* Start the DMA as soon as the buffer gets something in it */
538 if (host->flags & HOST_F_RECV) {
539 u32 mask = SD_STATUS_DB | SD_STATUS_NE;
541 while((status & mask) != mask)
542 status = au_readl(HOST_STATUS(host));
545 au1xxx_dbdma_start(channel);
549 static void au1xmmc_set_clock(struct au1xmmc_host *host, int rate)
552 unsigned int pbus = get_au1x00_speed();
553 unsigned int divisor;
554 u32 config;
556 /* From databook:
557 divisor = ((((cpuclock / sbus_divisor) / 2) / mmcclock) / 2) - 1
560 pbus /= ((au_readl(SYS_POWERCTRL) & 0x3) + 2);
561 pbus /= 2;
563 divisor = ((pbus / rate) / 2) - 1;
565 config = au_readl(HOST_CONFIG(host));
567 config &= ~(SD_CONFIG_DIV);
568 config |= (divisor & SD_CONFIG_DIV) | SD_CONFIG_DE;
570 au_writel(config, HOST_CONFIG(host));
571 au_sync();
574 static int
575 au1xmmc_prepare_data(struct au1xmmc_host *host, struct mmc_data *data)
578 int datalen = data->blocks * (1 << data->blksz_bits);
580 if (dma != 0)
581 host->flags |= HOST_F_DMA;
583 if (data->flags & MMC_DATA_READ)
584 host->flags |= HOST_F_RECV;
585 else
586 host->flags |= HOST_F_XMIT;
588 if (host->mrq->stop)
589 host->flags |= HOST_F_STOP;
591 host->dma.dir = DMA_BIDIRECTIONAL;
593 host->dma.len = dma_map_sg(mmc_dev(host->mmc), data->sg,
594 data->sg_len, host->dma.dir);
596 if (host->dma.len == 0)
597 return MMC_ERR_TIMEOUT;
599 au_writel((1 << data->blksz_bits) - 1, HOST_BLKSIZE(host));
601 if (host->flags & HOST_F_DMA) {
602 int i;
603 u32 channel = DMA_CHANNEL(host);
605 au1xxx_dbdma_stop(channel);
607 for(i = 0; i < host->dma.len; i++) {
608 u32 ret = 0, flags = DDMA_FLAGS_NOIE;
609 struct scatterlist *sg = &data->sg[i];
610 int sg_len = sg->length;
612 int len = (datalen > sg_len) ? sg_len : datalen;
614 if (i == host->dma.len - 1)
615 flags = DDMA_FLAGS_IE;
617 if (host->flags & HOST_F_XMIT){
618 ret = au1xxx_dbdma_put_source_flags(channel,
619 (void *) (page_address(sg->page) +
620 sg->offset),
621 len, flags);
623 else {
624 ret = au1xxx_dbdma_put_dest_flags(channel,
625 (void *) (page_address(sg->page) +
626 sg->offset),
627 len, flags);
630 if (!ret)
631 goto dataerr;
633 datalen -= len;
636 else {
637 host->pio.index = 0;
638 host->pio.offset = 0;
639 host->pio.len = datalen;
641 if (host->flags & HOST_F_XMIT)
642 IRQ_ON(host, SD_CONFIG_TH);
643 else
644 IRQ_ON(host, SD_CONFIG_NE);
645 //IRQ_ON(host, SD_CONFIG_RA|SD_CONFIG_RF);
648 return MMC_ERR_NONE;
650 dataerr:
651 dma_unmap_sg(mmc_dev(host->mmc),data->sg,data->sg_len,host->dma.dir);
652 return MMC_ERR_TIMEOUT;
655 /* static void au1xmmc_request
656 This actually starts a command or data transaction
659 static void au1xmmc_request(struct mmc_host* mmc, struct mmc_request* mrq)
662 struct au1xmmc_host *host = mmc_priv(mmc);
663 int ret = MMC_ERR_NONE;
665 WARN_ON(irqs_disabled());
666 WARN_ON(host->status != HOST_S_IDLE);
668 host->mrq = mrq;
669 host->status = HOST_S_CMD;
671 bcsr->disk_leds &= ~(1 << 8);
673 if (mrq->data) {
674 FLUSH_FIFO(host);
675 ret = au1xmmc_prepare_data(host, mrq->data);
678 if (ret == MMC_ERR_NONE)
679 ret = au1xmmc_send_command(host, 0, mrq->cmd);
681 if (ret != MMC_ERR_NONE) {
682 mrq->cmd->error = ret;
683 au1xmmc_finish_request(host);
687 static void au1xmmc_reset_controller(struct au1xmmc_host *host)
690 /* Apply the clock */
691 au_writel(SD_ENABLE_CE, HOST_ENABLE(host));
692 au_sync_delay(1);
694 au_writel(SD_ENABLE_R | SD_ENABLE_CE, HOST_ENABLE(host));
695 au_sync_delay(5);
697 au_writel(~0, HOST_STATUS(host));
698 au_sync();
700 au_writel(0, HOST_BLKSIZE(host));
701 au_writel(0x001fffff, HOST_TIMEOUT(host));
702 au_sync();
704 au_writel(SD_CONFIG2_EN, HOST_CONFIG2(host));
705 au_sync();
707 au_writel(SD_CONFIG2_EN | SD_CONFIG2_FF, HOST_CONFIG2(host));
708 au_sync_delay(1);
710 au_writel(SD_CONFIG2_EN, HOST_CONFIG2(host));
711 au_sync();
713 /* Configure interrupts */
714 au_writel(AU1XMMC_INTERRUPTS, HOST_CONFIG(host));
715 au_sync();
719 static void au1xmmc_set_ios(struct mmc_host* mmc, struct mmc_ios* ios)
721 struct au1xmmc_host *host = mmc_priv(mmc);
723 DEBUG("set_ios (power=%u, clock=%uHz, vdd=%u, mode=%u)\n",
724 host->id, ios->power_mode, ios->clock, ios->vdd,
725 ios->bus_mode);
727 if (ios->power_mode == MMC_POWER_OFF)
728 au1xmmc_set_power(host, 0);
729 else if (ios->power_mode == MMC_POWER_ON) {
730 au1xmmc_set_power(host, 1);
733 if (ios->clock && ios->clock != host->clock) {
734 au1xmmc_set_clock(host, ios->clock);
735 host->clock = ios->clock;
739 static void au1xmmc_dma_callback(int irq, void *dev_id, struct pt_regs *regs)
741 struct au1xmmc_host *host = (struct au1xmmc_host *) dev_id;
742 u32 status;
744 /* Avoid spurious interrupts */
746 if (!host->mrq)
747 return;
749 if (host->flags & HOST_F_STOP)
750 SEND_STOP(host);
752 tasklet_schedule(&host->data_task);
755 #define STATUS_TIMEOUT (SD_STATUS_RAT | SD_STATUS_DT)
756 #define STATUS_DATA_IN (SD_STATUS_NE)
757 #define STATUS_DATA_OUT (SD_STATUS_TH)
759 static irqreturn_t au1xmmc_irq(int irq, void *dev_id, struct pt_regs *regs)
762 u32 status;
763 int i, ret = 0;
765 disable_irq(AU1100_SD_IRQ);
767 for(i = 0; i < AU1XMMC_CONTROLLER_COUNT; i++) {
768 struct au1xmmc_host * host = au1xmmc_hosts[i];
769 u32 handled = 1;
771 status = au_readl(HOST_STATUS(host));
773 if (host->mrq && (status & STATUS_TIMEOUT)) {
774 if (status & SD_STATUS_RAT)
775 host->mrq->cmd->error = MMC_ERR_TIMEOUT;
777 else if (status & SD_STATUS_DT)
778 host->mrq->data->error = MMC_ERR_TIMEOUT;
780 /* In PIO mode, interrupts might still be enabled */
781 IRQ_OFF(host, SD_CONFIG_NE | SD_CONFIG_TH);
783 //IRQ_OFF(host, SD_CONFIG_TH|SD_CONFIG_RA|SD_CONFIG_RF);
784 tasklet_schedule(&host->finish_task);
786 #if 0
787 else if (status & SD_STATUS_DD) {
789 /* Sometimes we get a DD before a NE in PIO mode */
791 if (!(host->flags & HOST_F_DMA) &&
792 (status & SD_STATUS_NE))
793 au1xmmc_receive_pio(host);
794 else {
795 au1xmmc_data_complete(host, status);
796 //tasklet_schedule(&host->data_task);
799 #endif
800 else if (status & (SD_STATUS_CR)) {
801 if (host->status == HOST_S_CMD)
802 au1xmmc_cmd_complete(host,status);
804 else if (!(host->flags & HOST_F_DMA)) {
805 if ((host->flags & HOST_F_XMIT) &&
806 (status & STATUS_DATA_OUT))
807 au1xmmc_send_pio(host);
808 else if ((host->flags & HOST_F_RECV) &&
809 (status & STATUS_DATA_IN))
810 au1xmmc_receive_pio(host);
812 else if (status & 0x203FBC70) {
813 DEBUG("Unhandled status %8.8x\n", host->id, status);
814 handled = 0;
817 au_writel(status, HOST_STATUS(host));
818 au_sync();
820 ret |= handled;
823 enable_irq(AU1100_SD_IRQ);
824 return ret;
827 static void au1xmmc_poll_event(unsigned long arg)
829 struct au1xmmc_host *host = (struct au1xmmc_host *) arg;
831 int card = au1xmmc_card_inserted(host);
832 int controller = (host->flags & HOST_F_ACTIVE) ? 1 : 0;
834 if (card != controller) {
835 host->flags &= ~HOST_F_ACTIVE;
836 if (card) host->flags |= HOST_F_ACTIVE;
837 mmc_detect_change(host->mmc, 0);
840 if (host->mrq != NULL) {
841 u32 status = au_readl(HOST_STATUS(host));
842 DEBUG("PENDING - %8.8x\n", host->id, status);
845 mod_timer(&host->timer, jiffies + AU1XMMC_DETECT_TIMEOUT);
848 static dbdev_tab_t au1xmmc_mem_dbdev =
850 DSCR_CMD0_ALWAYS, DEV_FLAGS_ANYUSE, 0, 8, 0x00000000, 0, 0
853 static void au1xmmc_init_dma(struct au1xmmc_host *host)
856 u32 rxchan, txchan;
858 int txid = au1xmmc_card_table[host->id].tx_devid;
859 int rxid = au1xmmc_card_table[host->id].rx_devid;
861 /* DSCR_CMD0_ALWAYS has a stride of 32 bits, we need a stride
862 of 8 bits. And since devices are shared, we need to create
863 our own to avoid freaking out other devices
866 int memid = au1xxx_ddma_add_device(&au1xmmc_mem_dbdev);
868 txchan = au1xxx_dbdma_chan_alloc(memid, txid,
869 au1xmmc_dma_callback, (void *) host);
871 rxchan = au1xxx_dbdma_chan_alloc(rxid, memid,
872 au1xmmc_dma_callback, (void *) host);
874 au1xxx_dbdma_set_devwidth(txchan, 8);
875 au1xxx_dbdma_set_devwidth(rxchan, 8);
877 au1xxx_dbdma_ring_alloc(txchan, AU1XMMC_DESCRIPTOR_COUNT);
878 au1xxx_dbdma_ring_alloc(rxchan, AU1XMMC_DESCRIPTOR_COUNT);
880 host->tx_chan = txchan;
881 host->rx_chan = rxchan;
884 struct mmc_host_ops au1xmmc_ops = {
885 .request = au1xmmc_request,
886 .set_ios = au1xmmc_set_ios,
889 static int au1xmmc_probe(struct device *dev)
892 int i, ret = 0;
894 /* THe interrupt is shared among all controllers */
895 ret = request_irq(AU1100_SD_IRQ, au1xmmc_irq, SA_INTERRUPT, "MMC", 0);
897 if (ret) {
898 printk(DRIVER_NAME "ERROR: Couldn't get int %d: %d\n",
899 AU1100_SD_IRQ, ret);
900 return -ENXIO;
903 disable_irq(AU1100_SD_IRQ);
905 for(i = 0; i < AU1XMMC_CONTROLLER_COUNT; i++) {
906 struct mmc_host *mmc = mmc_alloc_host(sizeof(struct au1xmmc_host), dev);
907 struct au1xmmc_host *host = 0;
909 if (!mmc) {
910 printk(DRIVER_NAME "ERROR: no mem for host %d\n", i);
911 au1xmmc_hosts[i] = 0;
912 continue;
915 mmc->ops = &au1xmmc_ops;
917 mmc->f_min = 450000;
918 mmc->f_max = 24000000;
920 mmc->max_seg_size = AU1XMMC_DESCRIPTOR_SIZE;
921 mmc->max_phys_segs = AU1XMMC_DESCRIPTOR_COUNT;
923 mmc->ocr_avail = AU1XMMC_OCR;
925 host = mmc_priv(mmc);
926 host->mmc = mmc;
928 host->id = i;
929 host->iobase = au1xmmc_card_table[host->id].iobase;
930 host->clock = 0;
931 host->power_mode = MMC_POWER_OFF;
933 host->flags = au1xmmc_card_inserted(host) ? HOST_F_ACTIVE : 0;
934 host->status = HOST_S_IDLE;
936 init_timer(&host->timer);
938 host->timer.function = au1xmmc_poll_event;
939 host->timer.data = (unsigned long) host;
940 host->timer.expires = jiffies + AU1XMMC_DETECT_TIMEOUT;
942 tasklet_init(&host->data_task, au1xmmc_tasklet_data,
943 (unsigned long) host);
945 tasklet_init(&host->finish_task, au1xmmc_tasklet_finish,
946 (unsigned long) host);
948 spin_lock_init(&host->lock);
950 if (dma != 0)
951 au1xmmc_init_dma(host);
953 au1xmmc_reset_controller(host);
955 mmc_add_host(mmc);
956 au1xmmc_hosts[i] = host;
958 add_timer(&host->timer);
960 printk(KERN_INFO DRIVER_NAME ": MMC Controller %d set up at %8.8X (mode=%s)\n",
961 host->id, host->iobase, dma ? "dma" : "pio");
964 enable_irq(AU1100_SD_IRQ);
966 return 0;
969 static int au1xmmc_remove(struct device *dev)
972 int i;
974 disable_irq(AU1100_SD_IRQ);
976 for(i = 0; i < AU1XMMC_CONTROLLER_COUNT; i++) {
977 struct au1xmmc_host *host = au1xmmc_hosts[i];
978 if (!host) continue;
980 tasklet_kill(&host->data_task);
981 tasklet_kill(&host->finish_task);
983 del_timer_sync(&host->timer);
984 au1xmmc_set_power(host, 0);
986 mmc_remove_host(host->mmc);
988 au1xxx_dbdma_chan_free(host->tx_chan);
989 au1xxx_dbdma_chan_free(host->rx_chan);
991 au_writel(0x0, HOST_ENABLE(host));
992 au_sync();
995 free_irq(AU1100_SD_IRQ, 0);
996 return 0;
999 static struct device_driver au1xmmc_driver = {
1000 .name = DRIVER_NAME,
1001 .bus = &platform_bus_type,
1002 .probe = au1xmmc_probe,
1003 .remove = au1xmmc_remove,
1004 .suspend = NULL,
1005 .resume = NULL
1008 static int __init au1xmmc_init(void)
1010 return driver_register(&au1xmmc_driver);
1013 static void __exit au1xmmc_exit(void)
1015 driver_unregister(&au1xmmc_driver);
1018 module_init(au1xmmc_init);
1019 module_exit(au1xmmc_exit);
1021 #ifdef MODULE
1022 MODULE_AUTHOR("Advanced Micro Devices, Inc");
1023 MODULE_DESCRIPTION("MMC/SD driver for the Alchemy Au1XXX");
1024 MODULE_LICENSE("GPL");
1025 #endif