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kbuild: document howto build external modules using several directories
[linux-2.6/verdex.git] / drivers / video / ffb.c
blobc4870d559afc47d7a644d081ef548ef64717685c
1 /* ffb.c: Creator/Elite3D frame buffer driver
2 *
3 * Copyright (C) 2003 David S. Miller (davem@redhat.com)
4 * Copyright (C) 1997,1998,1999 Jakub Jelinek (jj@ultra.linux.cz)
5 *
6 * Driver layout based loosely on tgafb.c, see that file for credits.
7 */
8
9 #include <linux/module.h>
10 #include <linux/kernel.h>
11 #include <linux/errno.h>
12 #include <linux/string.h>
13 #include <linux/slab.h>
14 #include <linux/delay.h>
15 #include <linux/init.h>
16 #include <linux/fb.h>
17 #include <linux/mm.h>
18 #include <linux/timer.h>
19
20 #include <asm/io.h>
21 #include <asm/upa.h>
22 #include <asm/oplib.h>
23 #include <asm/fbio.h>
24
25 #include "sbuslib.h"
26
27 /*
28 * Local functions.
29 */
30
31 static int ffb_setcolreg(unsigned, unsigned, unsigned, unsigned,
32 unsigned, struct fb_info *);
33 static int ffb_blank(int, struct fb_info *);
34 static void ffb_init_fix(struct fb_info *);
35
36 static void ffb_imageblit(struct fb_info *, const struct fb_image *);
37 static void ffb_fillrect(struct fb_info *, const struct fb_fillrect *);
38 static void ffb_copyarea(struct fb_info *, const struct fb_copyarea *);
39 static int ffb_sync(struct fb_info *);
40 static int ffb_mmap(struct fb_info *, struct file *, struct vm_area_struct *);
41 static int ffb_ioctl(struct inode *, struct file *, unsigned int,
42 unsigned long, struct fb_info *);
43 static int ffb_pan_display(struct fb_var_screeninfo *, struct fb_info *);
44
45 /*
46 * Frame buffer operations
47 */
48
49 static struct fb_ops ffb_ops = {
50 .owner = THIS_MODULE,
51 .fb_setcolreg = ffb_setcolreg,
52 .fb_blank = ffb_blank,
53 .fb_pan_display = ffb_pan_display,
54 .fb_fillrect = ffb_fillrect,
55 .fb_copyarea = ffb_copyarea,
56 .fb_imageblit = ffb_imageblit,
57 .fb_sync = ffb_sync,
58 .fb_mmap = ffb_mmap,
59 .fb_ioctl = ffb_ioctl,
60 #ifdef CONFIG_COMPAT
61 .fb_compat_ioctl = sbusfb_compat_ioctl,
62 #endif
63 };
64
65 /* Register layout and definitions */
66 #define FFB_SFB8R_VOFF 0x00000000
67 #define FFB_SFB8G_VOFF 0x00400000
68 #define FFB_SFB8B_VOFF 0x00800000
69 #define FFB_SFB8X_VOFF 0x00c00000
70 #define FFB_SFB32_VOFF 0x01000000
71 #define FFB_SFB64_VOFF 0x02000000
72 #define FFB_FBC_REGS_VOFF 0x04000000
73 #define FFB_BM_FBC_REGS_VOFF 0x04002000
74 #define FFB_DFB8R_VOFF 0x04004000
75 #define FFB_DFB8G_VOFF 0x04404000
76 #define FFB_DFB8B_VOFF 0x04804000
77 #define FFB_DFB8X_VOFF 0x04c04000
78 #define FFB_DFB24_VOFF 0x05004000
79 #define FFB_DFB32_VOFF 0x06004000
80 #define FFB_DFB422A_VOFF 0x07004000 /* DFB 422 mode write to A */
81 #define FFB_DFB422AD_VOFF 0x07804000 /* DFB 422 mode with line doubling */
82 #define FFB_DFB24B_VOFF 0x08004000 /* DFB 24bit mode write to B */
83 #define FFB_DFB422B_VOFF 0x09004000 /* DFB 422 mode write to B */
84 #define FFB_DFB422BD_VOFF 0x09804000 /* DFB 422 mode with line doubling */
85 #define FFB_SFB16Z_VOFF 0x0a004000 /* 16bit mode Z planes */
86 #define FFB_SFB8Z_VOFF 0x0a404000 /* 8bit mode Z planes */
87 #define FFB_SFB422_VOFF 0x0ac04000 /* SFB 422 mode write to A/B */
88 #define FFB_SFB422D_VOFF 0x0b404000 /* SFB 422 mode with line doubling */
89 #define FFB_FBC_KREGS_VOFF 0x0bc04000
90 #define FFB_DAC_VOFF 0x0bc06000
91 #define FFB_PROM_VOFF 0x0bc08000
92 #define FFB_EXP_VOFF 0x0bc18000
93
94 #define FFB_SFB8R_POFF 0x04000000UL
95 #define FFB_SFB8G_POFF 0x04400000UL
96 #define FFB_SFB8B_POFF 0x04800000UL
97 #define FFB_SFB8X_POFF 0x04c00000UL
98 #define FFB_SFB32_POFF 0x05000000UL
99 #define FFB_SFB64_POFF 0x06000000UL
100 #define FFB_FBC_REGS_POFF 0x00600000UL
101 #define FFB_BM_FBC_REGS_POFF 0x00600000UL
102 #define FFB_DFB8R_POFF 0x01000000UL
103 #define FFB_DFB8G_POFF 0x01400000UL
104 #define FFB_DFB8B_POFF 0x01800000UL
105 #define FFB_DFB8X_POFF 0x01c00000UL
106 #define FFB_DFB24_POFF 0x02000000UL
107 #define FFB_DFB32_POFF 0x03000000UL
108 #define FFB_FBC_KREGS_POFF 0x00610000UL
109 #define FFB_DAC_POFF 0x00400000UL
110 #define FFB_PROM_POFF 0x00000000UL
111 #define FFB_EXP_POFF 0x00200000UL
112 #define FFB_DFB422A_POFF 0x09000000UL
113 #define FFB_DFB422AD_POFF 0x09800000UL
114 #define FFB_DFB24B_POFF 0x0a000000UL
115 #define FFB_DFB422B_POFF 0x0b000000UL
116 #define FFB_DFB422BD_POFF 0x0b800000UL
117 #define FFB_SFB16Z_POFF 0x0c800000UL
118 #define FFB_SFB8Z_POFF 0x0c000000UL
119 #define FFB_SFB422_POFF 0x0d000000UL
120 #define FFB_SFB422D_POFF 0x0d800000UL
121
122 /* Draw operations */
123 #define FFB_DRAWOP_DOT 0x00
124 #define FFB_DRAWOP_AADOT 0x01
125 #define FFB_DRAWOP_BRLINECAP 0x02
126 #define FFB_DRAWOP_BRLINEOPEN 0x03
127 #define FFB_DRAWOP_DDLINE 0x04
128 #define FFB_DRAWOP_AALINE 0x05
129 #define FFB_DRAWOP_TRIANGLE 0x06
130 #define FFB_DRAWOP_POLYGON 0x07
131 #define FFB_DRAWOP_RECTANGLE 0x08
132 #define FFB_DRAWOP_FASTFILL 0x09
133 #define FFB_DRAWOP_BCOPY 0x0a
134 #define FFB_DRAWOP_VSCROLL 0x0b
135
136 /* Pixel processor control */
137 /* Force WID */
138 #define FFB_PPC_FW_DISABLE 0x800000
139 #define FFB_PPC_FW_ENABLE 0xc00000
140 /* Auxiliary clip */
141 #define FFB_PPC_ACE_DISABLE 0x040000
142 #define FFB_PPC_ACE_AUX_SUB 0x080000
143 #define FFB_PPC_ACE_AUX_ADD 0x0c0000
144 /* Depth cue */
145 #define FFB_PPC_DCE_DISABLE 0x020000
146 #define FFB_PPC_DCE_ENABLE 0x030000
147 /* Alpha blend */
148 #define FFB_PPC_ABE_DISABLE 0x008000
149 #define FFB_PPC_ABE_ENABLE 0x00c000
150 /* View clip */
151 #define FFB_PPC_VCE_DISABLE 0x001000
152 #define FFB_PPC_VCE_2D 0x002000
153 #define FFB_PPC_VCE_3D 0x003000
154 /* Area pattern */
155 #define FFB_PPC_APE_DISABLE 0x000800
156 #define FFB_PPC_APE_ENABLE 0x000c00
157 /* Transparent background */
158 #define FFB_PPC_TBE_OPAQUE 0x000200
159 #define FFB_PPC_TBE_TRANSPARENT 0x000300
160 /* Z source */
161 #define FFB_PPC_ZS_VAR 0x000080
162 #define FFB_PPC_ZS_CONST 0x0000c0
163 /* Y source */
164 #define FFB_PPC_YS_VAR 0x000020
165 #define FFB_PPC_YS_CONST 0x000030
166 /* X source */
167 #define FFB_PPC_XS_WID 0x000004
168 #define FFB_PPC_XS_VAR 0x000008
169 #define FFB_PPC_XS_CONST 0x00000c
170 /* Color (BGR) source */
171 #define FFB_PPC_CS_VAR 0x000002
172 #define FFB_PPC_CS_CONST 0x000003
173
174 #define FFB_ROP_NEW 0x83
175 #define FFB_ROP_OLD 0x85
176 #define FFB_ROP_NEW_XOR_OLD 0x86
177
178 #define FFB_UCSR_FIFO_MASK 0x00000fff
179 #define FFB_UCSR_FB_BUSY 0x01000000
180 #define FFB_UCSR_RP_BUSY 0x02000000
181 #define FFB_UCSR_ALL_BUSY (FFB_UCSR_RP_BUSY|FFB_UCSR_FB_BUSY)
182 #define FFB_UCSR_READ_ERR 0x40000000
183 #define FFB_UCSR_FIFO_OVFL 0x80000000
184 #define FFB_UCSR_ALL_ERRORS (FFB_UCSR_READ_ERR|FFB_UCSR_FIFO_OVFL)
185
186 struct ffb_fbc {
187 /* Next vertex registers */
188 u32 xxx1[3];
189 volatile u32 alpha;
190 volatile u32 red;
191 volatile u32 green;
192 volatile u32 blue;
193 volatile u32 depth;
194 volatile u32 y;
195 volatile u32 x;
196 u32 xxx2[2];
197 volatile u32 ryf;
198 volatile u32 rxf;
199 u32 xxx3[2];
200
201 volatile u32 dmyf;
202 volatile u32 dmxf;
203 u32 xxx4[2];
204 volatile u32 ebyi;
205 volatile u32 ebxi;
206 u32 xxx5[2];
207 volatile u32 by;
208 volatile u32 bx;
209 u32 dy;
210 u32 dx;
211 volatile u32 bh;
212 volatile u32 bw;
213 u32 xxx6[2];
214
215 u32 xxx7[32];
216
217 /* Setup unit vertex state register */
218 volatile u32 suvtx;
219 u32 xxx8[63];
220
221 /* Control registers */
222 volatile u32 ppc;
223 volatile u32 wid;
224 volatile u32 fg;
225 volatile u32 bg;
226 volatile u32 consty;
227 volatile u32 constz;
228 volatile u32 xclip;
229 volatile u32 dcss;
230 volatile u32 vclipmin;
231 volatile u32 vclipmax;
232 volatile u32 vclipzmin;
233 volatile u32 vclipzmax;
234 volatile u32 dcsf;
235 volatile u32 dcsb;
236 volatile u32 dczf;
237 volatile u32 dczb;
238
239 u32 xxx9;
240 volatile u32 blendc;
241 volatile u32 blendc1;
242 volatile u32 blendc2;
243 volatile u32 fbramitc;
244 volatile u32 fbc;
245 volatile u32 rop;
246 volatile u32 cmp;
247 volatile u32 matchab;
248 volatile u32 matchc;
249 volatile u32 magnab;
250 volatile u32 magnc;
251 volatile u32 fbcfg0;
252 volatile u32 fbcfg1;
253 volatile u32 fbcfg2;
254 volatile u32 fbcfg3;
255
256 u32 ppcfg;
257 volatile u32 pick;
258 volatile u32 fillmode;
259 volatile u32 fbramwac;
260 volatile u32 pmask;
261 volatile u32 xpmask;
262 volatile u32 ypmask;
263 volatile u32 zpmask;
264 volatile u32 clip0min;
265 volatile u32 clip0max;
266 volatile u32 clip1min;
267 volatile u32 clip1max;
268 volatile u32 clip2min;
269 volatile u32 clip2max;
270 volatile u32 clip3min;
271 volatile u32 clip3max;
272
273 /* New 3dRAM III support regs */
274 volatile u32 rawblend2;
275 volatile u32 rawpreblend;
276 volatile u32 rawstencil;
277 volatile u32 rawstencilctl;
278 volatile u32 threedram1;
279 volatile u32 threedram2;
280 volatile u32 passin;
281 volatile u32 rawclrdepth;
282 volatile u32 rawpmask;
283 volatile u32 rawcsrc;
284 volatile u32 rawmatch;
285 volatile u32 rawmagn;
286 volatile u32 rawropblend;
287 volatile u32 rawcmp;
288 volatile u32 rawwac;
289 volatile u32 fbramid;
290
291 volatile u32 drawop;
292 u32 xxx10[2];
293 volatile u32 fontlpat;
294 u32 xxx11;
295 volatile u32 fontxy;
296 volatile u32 fontw;
297 volatile u32 fontinc;
298 volatile u32 font;
299 u32 xxx12[3];
300 volatile u32 blend2;
301 volatile u32 preblend;
302 volatile u32 stencil;
303 volatile u32 stencilctl;
304
305 u32 xxx13[4];
306 volatile u32 dcss1;
307 volatile u32 dcss2;
308 volatile u32 dcss3;
309 volatile u32 widpmask;
310 volatile u32 dcs2;
311 volatile u32 dcs3;
312 volatile u32 dcs4;
313 u32 xxx14;
314 volatile u32 dcd2;
315 volatile u32 dcd3;
316 volatile u32 dcd4;
317 u32 xxx15;
318
319 volatile u32 pattern[32];
320
321 u32 xxx16[256];
322
323 volatile u32 devid;
324 u32 xxx17[63];
325
326 volatile u32 ucsr;
327 u32 xxx18[31];
328
329 volatile u32 mer;
330 };
331
332 struct ffb_dac {
333 volatile u32 type;
334 volatile u32 value;
335 volatile u32 type2;
336 volatile u32 value2;
337 };
338
339 struct ffb_par {
340 spinlock_t lock;
341 struct ffb_fbc *fbc;
342 struct ffb_dac *dac;
343
344 u32 flags;
345 #define FFB_FLAG_AFB 0x00000001
346 #define FFB_FLAG_BLANKED 0x00000002
347
348 u32 fg_cache __attribute__((aligned (8)));
349 u32 bg_cache;
350 u32 rop_cache;
351
352 int fifo_cache;
353
354 unsigned long physbase;
355 unsigned long fbsize;
356
357 char name[64];
358 int prom_node;
359 int prom_parent_node;
360 int dac_rev;
361 int board_type;
362 };
363
364 static void FFBFifo(struct ffb_par *par, int n)
365 {
366 struct ffb_fbc *fbc;
367 int cache = par->fifo_cache;
368
369 if (cache - n < 0) {
370 fbc = par->fbc;
371 do { cache = (upa_readl(&fbc->ucsr) & FFB_UCSR_FIFO_MASK) - 8;
372 } while (cache - n < 0);
373 }
374 par->fifo_cache = cache - n;
375 }
376
377 static void FFBWait(struct ffb_par *par)
378 {
379 struct ffb_fbc *fbc;
380 int limit = 10000;
381
382 fbc = par->fbc;
383 do {
384 if ((upa_readl(&fbc->ucsr) & FFB_UCSR_ALL_BUSY) == 0)
385 break;
386 if ((upa_readl(&fbc->ucsr) & FFB_UCSR_ALL_ERRORS) != 0) {
387 upa_writel(FFB_UCSR_ALL_ERRORS, &fbc->ucsr);
388 }
389 udelay(10);
390 } while(--limit > 0);
391 }
392
393 static int ffb_sync(struct fb_info *p)
394 {
395 struct ffb_par *par = (struct ffb_par *) p->par;
396
397 FFBWait(par);
398 return 0;
399 }
400
401 static __inline__ void ffb_rop(struct ffb_par *par, u32 rop)
402 {
403 if (par->rop_cache != rop) {
404 FFBFifo(par, 1);
405 upa_writel(rop, &par->fbc->rop);
406 par->rop_cache = rop;
407 }
408 }
409
410 static void ffb_switch_from_graph(struct ffb_par *par)
411 {
412 struct ffb_fbc *fbc = par->fbc;
413 struct ffb_dac *dac = par->dac;
414 unsigned long flags;
415
416 spin_lock_irqsave(&par->lock, flags);
417 FFBWait(par);
418 par->fifo_cache = 0;
419 FFBFifo(par, 7);
420 upa_writel(FFB_PPC_VCE_DISABLE|FFB_PPC_TBE_OPAQUE|
421 FFB_PPC_APE_DISABLE|FFB_PPC_CS_CONST,
422 &fbc->ppc);
423 upa_writel(0x2000707f, &fbc->fbc);
424 upa_writel(par->rop_cache, &fbc->rop);
425 upa_writel(0xffffffff, &fbc->pmask);
426 upa_writel((1 << 16) | (0 << 0), &fbc->fontinc);
427 upa_writel(par->fg_cache, &fbc->fg);
428 upa_writel(par->bg_cache, &fbc->bg);
429 FFBWait(par);
430
431 /* Disable cursor. */
432 upa_writel(0x100, &dac->type2);
433 if (par->dac_rev <= 2)
434 upa_writel(0, &dac->value2);
435 else
436 upa_writel(3, &dac->value2);
437
438 spin_unlock_irqrestore(&par->lock, flags);
439 }
440
441 static int ffb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
442 {
443 struct ffb_par *par = (struct ffb_par *) info->par;
444
445 /* We just use this to catch switches out of
446 * graphics mode.
447 */
448 ffb_switch_from_graph(par);
449
450 if (var->xoffset || var->yoffset || var->vmode)
451 return -EINVAL;
452 return 0;
453 }
454
455 /**
456 * ffb_fillrect - REQUIRED function. Can use generic routines if
457 * non acclerated hardware and packed pixel based.
458 * Draws a rectangle on the screen.
459 *
460 * @info: frame buffer structure that represents a single frame buffer
461 * @rect: structure defining the rectagle and operation.
462 */
463 static void ffb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
464 {
465 struct ffb_par *par = (struct ffb_par *) info->par;
466 struct ffb_fbc *fbc = par->fbc;
467 unsigned long flags;
468 u32 fg;
469
470 if (rect->rop != ROP_COPY && rect->rop != ROP_XOR)
471 BUG();
472
473 fg = ((u32 *)info->pseudo_palette)[rect->color];
474
475 spin_lock_irqsave(&par->lock, flags);
476
477 if (fg != par->fg_cache) {
478 FFBFifo(par, 1);
479 upa_writel(fg, &fbc->fg);
480 par->fg_cache = fg;
481 }
482
483 ffb_rop(par, (rect->rop == ROP_COPY ?
484 FFB_ROP_NEW :
485 FFB_ROP_NEW_XOR_OLD));
486
487 FFBFifo(par, 5);
488 upa_writel(FFB_DRAWOP_RECTANGLE, &fbc->drawop);
489 upa_writel(rect->dy, &fbc->by);
490 upa_writel(rect->dx, &fbc->bx);
491 upa_writel(rect->height, &fbc->bh);
492 upa_writel(rect->width, &fbc->bw);
493
494 spin_unlock_irqrestore(&par->lock, flags);
495 }
496
497 /**
498 * ffb_copyarea - REQUIRED function. Can use generic routines if
499 * non acclerated hardware and packed pixel based.
500 * Copies on area of the screen to another area.
501 *
502 * @info: frame buffer structure that represents a single frame buffer
503 * @area: structure defining the source and destination.
504 */
505
506 static void
507 ffb_copyarea(struct fb_info *info, const struct fb_copyarea *area)
508 {
509 struct ffb_par *par = (struct ffb_par *) info->par;
510 struct ffb_fbc *fbc = par->fbc;
511 unsigned long flags;
512
513 if (area->dx != area->sx ||
514 area->dy == area->sy) {
515 cfb_copyarea(info, area);
516 return;
517 }
518
519 spin_lock_irqsave(&par->lock, flags);
520
521 ffb_rop(par, FFB_ROP_OLD);
522
523 FFBFifo(par, 7);
524 upa_writel(FFB_DRAWOP_VSCROLL, &fbc->drawop);
525 upa_writel(area->sy, &fbc->by);
526 upa_writel(area->sx, &fbc->bx);
527 upa_writel(area->dy, &fbc->dy);
528 upa_writel(area->dx, &fbc->dx);
529 upa_writel(area->height, &fbc->bh);
530 upa_writel(area->width, &fbc->bw);
531
532 spin_unlock_irqrestore(&par->lock, flags);
533 }
534
535 /**
536 * ffb_imageblit - REQUIRED function. Can use generic routines if
537 * non acclerated hardware and packed pixel based.
538 * Copies a image from system memory to the screen.
539 *
540 * @info: frame buffer structure that represents a single frame buffer
541 * @image: structure defining the image.
542 */
543 static void ffb_imageblit(struct fb_info *info, const struct fb_image *image)
544 {
545 struct ffb_par *par = (struct ffb_par *) info->par;
546 struct ffb_fbc *fbc = par->fbc;
547 const u8 *data = image->data;
548 unsigned long flags;
549 u32 fg, bg, xy;
550 u64 fgbg;
551 int i, width, stride;
552
553 if (image->depth > 1) {
554 cfb_imageblit(info, image);
555 return;
556 }
557
558 fg = ((u32 *)info->pseudo_palette)[image->fg_color];
559 bg = ((u32 *)info->pseudo_palette)[image->bg_color];
560 fgbg = ((u64) fg << 32) | (u64) bg;
561 xy = (image->dy << 16) | image->dx;
562 width = image->width;
563 stride = ((width + 7) >> 3);
564
565 spin_lock_irqsave(&par->lock, flags);
566
567 if (fgbg != *(u64 *)&par->fg_cache) {
568 FFBFifo(par, 2);
569 upa_writeq(fgbg, &fbc->fg);
570 *(u64 *)&par->fg_cache = fgbg;
571 }
572
573 if (width >= 32) {
574 FFBFifo(par, 1);
575 upa_writel(32, &fbc->fontw);
576 }
577
578 while (width >= 32) {
579 const u8 *next_data = data + 4;
580
581 FFBFifo(par, 1);
582 upa_writel(xy, &fbc->fontxy);
583 xy += (32 << 0);
584
585 for (i = 0; i < image->height; i++) {
586 u32 val = (((u32)data[0] << 24) |
587 ((u32)data[1] << 16) |
588 ((u32)data[2] << 8) |
589 ((u32)data[3] << 0));
590 FFBFifo(par, 1);
591 upa_writel(val, &fbc->font);
592
593 data += stride;
594 }
595
596 data = next_data;
597 width -= 32;
598 }
599
600 if (width) {
601 FFBFifo(par, 2);
602 upa_writel(width, &fbc->fontw);
603 upa_writel(xy, &fbc->fontxy);
604
605 for (i = 0; i < image->height; i++) {
606 u32 val = (((u32)data[0] << 24) |
607 ((u32)data[1] << 16) |
608 ((u32)data[2] << 8) |
609 ((u32)data[3] << 0));
610 FFBFifo(par, 1);
611 upa_writel(val, &fbc->font);
612
613 data += stride;
614 }
615 }
616
617 spin_unlock_irqrestore(&par->lock, flags);
618 }
619
620 static void ffb_fixup_var_rgb(struct fb_var_screeninfo *var)
621 {
622 var->red.offset = 0;
623 var->red.length = 8;
624 var->green.offset = 8;
625 var->green.length = 8;
626 var->blue.offset = 16;
627 var->blue.length = 8;
628 var->transp.offset = 0;
629 var->transp.length = 0;
630 }
631
632 /**
633 * ffb_setcolreg - Optional function. Sets a color register.
634 * @regno: boolean, 0 copy local, 1 get_user() function
635 * @red: frame buffer colormap structure
636 * @green: The green value which can be up to 16 bits wide
637 * @blue: The blue value which can be up to 16 bits wide.
638 * @transp: If supported the alpha value which can be up to 16 bits wide.
639 * @info: frame buffer info structure
640 */
641 static int ffb_setcolreg(unsigned regno,
642 unsigned red, unsigned green, unsigned blue,
643 unsigned transp, struct fb_info *info)
644 {
645 u32 value;
646
647 if (regno >= 256)
648 return 1;
649
650 red >>= 8;
651 green >>= 8;
652 blue >>= 8;
653
654 value = (blue << 16) | (green << 8) | red;
655 ((u32 *)info->pseudo_palette)[regno] = value;
656
657 return 0;
658 }
659
660 /**
661 * ffb_blank - Optional function. Blanks the display.
662 * @blank_mode: the blank mode we want.
663 * @info: frame buffer structure that represents a single frame buffer
664 */
665 static int
666 ffb_blank(int blank, struct fb_info *info)
667 {
668 struct ffb_par *par = (struct ffb_par *) info->par;
669 struct ffb_dac *dac = par->dac;
670 unsigned long flags;
671 u32 tmp;
672
673 spin_lock_irqsave(&par->lock, flags);
674
675 FFBWait(par);
676
677 switch (blank) {
678 case FB_BLANK_UNBLANK: /* Unblanking */
679 upa_writel(0x6000, &dac->type);
680 tmp = (upa_readl(&dac->value) | 0x1);
681 upa_writel(0x6000, &dac->type);
682 upa_writel(tmp, &dac->value);
683 par->flags &= ~FFB_FLAG_BLANKED;
684 break;
685
686 case FB_BLANK_NORMAL: /* Normal blanking */
687 case FB_BLANK_VSYNC_SUSPEND: /* VESA blank (vsync off) */
688 case FB_BLANK_HSYNC_SUSPEND: /* VESA blank (hsync off) */
689 case FB_BLANK_POWERDOWN: /* Poweroff */
690 upa_writel(0x6000, &dac->type);
691 tmp = (upa_readl(&dac->value) & ~0x1);
692 upa_writel(0x6000, &dac->type);
693 upa_writel(tmp, &dac->value);
694 par->flags |= FFB_FLAG_BLANKED;
695 break;
696 }
697
698 spin_unlock_irqrestore(&par->lock, flags);
699
700 return 0;
701 }
702
703 static struct sbus_mmap_map ffb_mmap_map[] = {
704 {
705 .voff = FFB_SFB8R_VOFF,
706 .poff = FFB_SFB8R_POFF,
707 .size = 0x0400000
708 },
709 {
710 .voff = FFB_SFB8G_VOFF,
711 .poff = FFB_SFB8G_POFF,
712 .size = 0x0400000
713 },
714 {
715 .voff = FFB_SFB8B_VOFF,
716 .poff = FFB_SFB8B_POFF,
717 .size = 0x0400000
718 },
719 {
720 .voff = FFB_SFB8X_VOFF,
721 .poff = FFB_SFB8X_POFF,
722 .size = 0x0400000
723 },
724 {
725 .voff = FFB_SFB32_VOFF,
726 .poff = FFB_SFB32_POFF,
727 .size = 0x1000000
728 },
729 {
730 .voff = FFB_SFB64_VOFF,
731 .poff = FFB_SFB64_POFF,
732 .size = 0x2000000
733 },
734 {
735 .voff = FFB_FBC_REGS_VOFF,
736 .poff = FFB_FBC_REGS_POFF,
737 .size = 0x0002000
738 },
739 {
740 .voff = FFB_BM_FBC_REGS_VOFF,
741 .poff = FFB_BM_FBC_REGS_POFF,
742 .size = 0x0002000
743 },
744 {
745 .voff = FFB_DFB8R_VOFF,
746 .poff = FFB_DFB8R_POFF,
747 .size = 0x0400000
748 },
749 {
750 .voff = FFB_DFB8G_VOFF,
751 .poff = FFB_DFB8G_POFF,
752 .size = 0x0400000
753 },
754 {
755 .voff = FFB_DFB8B_VOFF,
756 .poff = FFB_DFB8B_POFF,
757 .size = 0x0400000
758 },
759 {
760 .voff = FFB_DFB8X_VOFF,
761 .poff = FFB_DFB8X_POFF,
762 .size = 0x0400000
763 },
764 {
765 .voff = FFB_DFB24_VOFF,
766 .poff = FFB_DFB24_POFF,
767 .size = 0x1000000
768 },
769 {
770 .voff = FFB_DFB32_VOFF,
771 .poff = FFB_DFB32_POFF,
772 .size = 0x1000000
773 },
774 {
775 .voff = FFB_FBC_KREGS_VOFF,
776 .poff = FFB_FBC_KREGS_POFF,
777 .size = 0x0002000
778 },
779 {
780 .voff = FFB_DAC_VOFF,
781 .poff = FFB_DAC_POFF,
782 .size = 0x0002000
783 },
784 {
785 .voff = FFB_PROM_VOFF,
786 .poff = FFB_PROM_POFF,
787 .size = 0x0010000
788 },
789 {
790 .voff = FFB_EXP_VOFF,
791 .poff = FFB_EXP_POFF,
792 .size = 0x0002000
793 },
794 {
795 .voff = FFB_DFB422A_VOFF,
796 .poff = FFB_DFB422A_POFF,
797 .size = 0x0800000
798 },
799 {
800 .voff = FFB_DFB422AD_VOFF,
801 .poff = FFB_DFB422AD_POFF,
802 .size = 0x0800000
803 },
804 {
805 .voff = FFB_DFB24B_VOFF,
806 .poff = FFB_DFB24B_POFF,
807 .size = 0x1000000
808 },
809 {
810 .voff = FFB_DFB422B_VOFF,
811 .poff = FFB_DFB422B_POFF,
812 .size = 0x0800000
813 },
814 {
815 .voff = FFB_DFB422BD_VOFF,
816 .poff = FFB_DFB422BD_POFF,
817 .size = 0x0800000
818 },
819 {
820 .voff = FFB_SFB16Z_VOFF,
821 .poff = FFB_SFB16Z_POFF,
822 .size = 0x0800000
823 },
824 {
825 .voff = FFB_SFB8Z_VOFF,
826 .poff = FFB_SFB8Z_POFF,
827 .size = 0x0800000
828 },
829 {
830 .voff = FFB_SFB422_VOFF,
831 .poff = FFB_SFB422_POFF,
832 .size = 0x0800000
833 },
834 {
835 .voff = FFB_SFB422D_VOFF,
836 .poff = FFB_SFB422D_POFF,
837 .size = 0x0800000
838 },
839 { .size = 0 }
840 };
841
842 static int ffb_mmap(struct fb_info *info, struct file *file, struct vm_area_struct *vma)
843 {
844 struct ffb_par *par = (struct ffb_par *)info->par;
845
846 return sbusfb_mmap_helper(ffb_mmap_map,
847 par->physbase, par->fbsize,
848 0, vma);
849 }
850
851 static int ffb_ioctl(struct inode *inode, struct file *file, unsigned int cmd,
852 unsigned long arg, struct fb_info *info)
853 {
854 struct ffb_par *par = (struct ffb_par *) info->par;
855
856 return sbusfb_ioctl_helper(cmd, arg, info,
857 FBTYPE_CREATOR, 24, par->fbsize);
858 }
859
860 /*
861 * Initialisation
862 */
863
864 static void
865 ffb_init_fix(struct fb_info *info)
866 {
867 struct ffb_par *par = (struct ffb_par *)info->par;
868 const char *ffb_type_name;
869
870 if (!(par->flags & FFB_FLAG_AFB)) {
871 if ((par->board_type & 0x7) == 0x3)
872 ffb_type_name = "Creator 3D";
873 else
874 ffb_type_name = "Creator";
875 } else
876 ffb_type_name = "Elite 3D";
877
878 strlcpy(info->fix.id, ffb_type_name, sizeof(info->fix.id));
879
880 info->fix.type = FB_TYPE_PACKED_PIXELS;
881 info->fix.visual = FB_VISUAL_TRUECOLOR;
882
883 /* Framebuffer length is the same regardless of resolution. */
884 info->fix.line_length = 8192;
885
886 info->fix.accel = FB_ACCEL_SUN_CREATOR;
887 }
888
889 static int ffb_apply_upa_parent_ranges(int parent,
890 struct linux_prom64_registers *regs)
891 {
892 struct linux_prom64_ranges ranges[PROMREG_MAX];
893 char name[128];
894 int len, i;
895
896 prom_getproperty(parent, "name", name, sizeof(name));
897 if (strcmp(name, "upa") != 0)
898 return 0;
899
900 len = prom_getproperty(parent, "ranges", (void *) ranges, sizeof(ranges));
901 if (len <= 0)
902 return 1;
903
904 len /= sizeof(struct linux_prom64_ranges);
905 for (i = 0; i < len; i++) {
906 struct linux_prom64_ranges *rng = &ranges[i];
907 u64 phys_addr = regs->phys_addr;
908
909 if (phys_addr >= rng->ot_child_base &&
910 phys_addr < (rng->ot_child_base + rng->or_size)) {
911 regs->phys_addr -= rng->ot_child_base;
912 regs->phys_addr += rng->ot_parent_base;
913 return 0;
914 }
915 }
916
917 return 1;
918 }
919
920 struct all_info {
921 struct fb_info info;
922 struct ffb_par par;
923 u32 pseudo_palette[256];
924 struct list_head list;
925 };
926 static LIST_HEAD(ffb_list);
927
928 static void ffb_init_one(int node, int parent)
929 {
930 struct linux_prom64_registers regs[2*PROMREG_MAX];
931 struct ffb_fbc *fbc;
932 struct ffb_dac *dac;
933 struct all_info *all;
934
935 if (prom_getproperty(node, "reg", (void *) regs, sizeof(regs)) <= 0) {
936 printk("ffb: Cannot get reg device node property.\n");
937 return;
938 }
939
940 if (ffb_apply_upa_parent_ranges(parent, &regs[0])) {
941 printk("ffb: Cannot apply parent ranges to regs.\n");
942 return;
943 }
944
945 all = kmalloc(sizeof(*all), GFP_KERNEL);
946 if (!all) {
947 printk(KERN_ERR "ffb: Cannot allocate memory.\n");
948 return;
949 }
950 memset(all, 0, sizeof(*all));
951
952 INIT_LIST_HEAD(&all->list);
953
954 spin_lock_init(&all->par.lock);
955 all->par.fbc = (struct ffb_fbc *)(regs[0].phys_addr + FFB_FBC_REGS_POFF);
956 all->par.dac = (struct ffb_dac *)(regs[0].phys_addr + FFB_DAC_POFF);
957 all->par.rop_cache = FFB_ROP_NEW;
958 all->par.physbase = regs[0].phys_addr;
959 all->par.prom_node = node;
960 all->par.prom_parent_node = parent;
961
962 /* Don't mention copyarea, so SCROLL_REDRAW is always
963 * used. It is the fastest on this chip.
964 */
965 all->info.flags = (FBINFO_DEFAULT |
966 /* FBINFO_HWACCEL_COPYAREA | */
967 FBINFO_HWACCEL_FILLRECT |
968 FBINFO_HWACCEL_IMAGEBLIT);
969 all->info.fbops = &ffb_ops;
970 all->info.screen_base = (char *) all->par.physbase + FFB_DFB24_POFF;
971 all->info.par = &all->par;
972 all->info.pseudo_palette = all->pseudo_palette;
973
974 sbusfb_fill_var(&all->info.var, all->par.prom_node, 32);
975 all->par.fbsize = PAGE_ALIGN(all->info.var.xres *
976 all->info.var.yres *
977 4);
978 ffb_fixup_var_rgb(&all->info.var);
979
980 all->info.var.accel_flags = FB_ACCELF_TEXT;
981
982 prom_getstring(node, "name", all->par.name, sizeof(all->par.name));
983 if (!strcmp(all->par.name, "SUNW,afb"))
984 all->par.flags |= FFB_FLAG_AFB;
985
986 all->par.board_type = prom_getintdefault(node, "board_type", 0);
987
988 fbc = all->par.fbc;
989 if((upa_readl(&fbc->ucsr) & FFB_UCSR_ALL_ERRORS) != 0)
990 upa_writel(FFB_UCSR_ALL_ERRORS, &fbc->ucsr);
991
992 ffb_switch_from_graph(&all->par);
993
994 dac = all->par.dac;
995 upa_writel(0x8000, &dac->type);
996 all->par.dac_rev = upa_readl(&dac->value) >> 0x1c;
997
998 /* Elite3D has different DAC revision numbering, and no DAC revisions
999 * have the reversed meaning of cursor enable.
1000 */
1001 if (all->par.flags & FFB_FLAG_AFB)
1002 all->par.dac_rev = 10;
1003
1004 /* Unblank it just to be sure. When there are multiple
1005 * FFB/AFB cards in the system, or it is not the OBP
1006 * chosen console, it will have video outputs off in
1007 * the DAC.
1008 */
1009 ffb_blank(0, &all->info);
1010
1011 if (fb_alloc_cmap(&all->info.cmap, 256, 0)) {
1012 printk(KERN_ERR "ffb: Could not allocate color map.\n");
1013 kfree(all);
1014 return;
1015 }
1016
1017 ffb_init_fix(&all->info);
1018
1019 if (register_framebuffer(&all->info) < 0) {
1020 printk(KERN_ERR "ffb: Could not register framebuffer.\n");
1021 fb_dealloc_cmap(&all->info.cmap);
1022 kfree(all);
1023 return;
1024 }
1025
1026 list_add(&all->list, &ffb_list);
1027
1028 printk("ffb: %s at %016lx type %d DAC %d\n",
1029 ((all->par.flags & FFB_FLAG_AFB) ? "AFB" : "FFB"),
1030 regs[0].phys_addr, all->par.board_type, all->par.dac_rev);
1031 }
1032
1033 static void ffb_scan_siblings(int root)
1034 {
1035 int node, child;
1036
1037 child = prom_getchild(root);
1038 for (node = prom_searchsiblings(child, "SUNW,ffb"); node;
1039 node = prom_searchsiblings(prom_getsibling(node), "SUNW,ffb"))
1040 ffb_init_one(node, root);
1041 for (node = prom_searchsiblings(child, "SUNW,afb"); node;
1042 node = prom_searchsiblings(prom_getsibling(node), "SUNW,afb"))
1043 ffb_init_one(node, root);
1044 }
1045
1046 int __init ffb_init(void)
1047 {
1048 int root;
1049
1050 if (fb_get_options("ffb", NULL))
1051 return -ENODEV;
1052
1053 ffb_scan_siblings(prom_root_node);
1054
1055 root = prom_getchild(prom_root_node);
1056 for (root = prom_searchsiblings(root, "upa"); root;
1057 root = prom_searchsiblings(prom_getsibling(root), "upa"))
1058 ffb_scan_siblings(root);
1059
1060 return 0;
1061 }
1062
1063 void __exit ffb_exit(void)
1064 {
1065 struct list_head *pos, *tmp;
1066
1067 list_for_each_safe(pos, tmp, &ffb_list) {
1068 struct all_info *all = list_entry(pos, typeof(*all), list);
1069
1070 unregister_framebuffer(&all->info);
1071 fb_dealloc_cmap(&all->info.cmap);
1072 kfree(all);
1073 }
1074 }
1075
1076 int __init
1077 ffb_setup(char *arg)
1078 {
1079 /* No cmdline options yet... */
1080 return 0;
1081 }
1082
1083 module_init(ffb_init);
1084
1085 #ifdef MODULE
1086 module_exit(ffb_exit);
1087 #endif
1088
1089 MODULE_DESCRIPTION("framebuffer driver for Creator/Elite3D chipsets");
1090 MODULE_AUTHOR("David S. Miller <davem@redhat.com>");
1091 MODULE_LICENSE("GPL");
Verdex Pro support