2 * linux/drivers/video/pxafb.c
4 * Copyright (C) 1999 Eric A. Thomas.
5 * Copyright (C) 2004 Jean-Frederic Clere.
6 * Copyright (C) 2004 Ian Campbell.
7 * Copyright (C) 2004 Jeff Lackey.
8 * Based on sa1100fb.c Copyright (C) 1999 Eric A. Thomas
10 * Based on acornfb.c Copyright (C) Russell King.
12 * This file is subject to the terms and conditions of the GNU General Public
13 * License. See the file COPYING in the main directory of this archive for
16 * Intel PXA250/210 LCD Controller Frame Buffer Driver
18 * Please direct your questions and comments on this driver to the following
21 * linux-arm-kernel@lists.arm.linux.org.uk
25 #include <linux/config.h>
26 #include <linux/module.h>
27 #include <linux/moduleparam.h>
28 #include <linux/kernel.h>
29 #include <linux/sched.h>
30 #include <linux/errno.h>
31 #include <linux/string.h>
32 #include <linux/interrupt.h>
33 #include <linux/slab.h>
35 #include <linux/delay.h>
36 #include <linux/init.h>
37 #include <linux/ioport.h>
38 #include <linux/cpufreq.h>
39 #include <linux/platform_device.h>
40 #include <linux/dma-mapping.h>
42 #include <asm/hardware.h>
45 #include <asm/uaccess.h>
46 #include <asm/div64.h>
47 #include <asm/arch/pxa-regs.h>
48 #include <asm/arch/bitfield.h>
49 #include <asm/arch/pxafb.h>
52 * Complain if VAR is out of range.
58 /* Bits which should not be set in machine configuration structures */
59 #define LCCR0_INVALID_CONFIG_MASK (LCCR0_OUM|LCCR0_BM|LCCR0_QDM|LCCR0_DIS|LCCR0_EFM|LCCR0_IUM|LCCR0_SFM|LCCR0_LDM|LCCR0_ENB)
60 #define LCCR3_INVALID_CONFIG_MASK (LCCR3_HSP|LCCR3_VSP|LCCR3_PCD|LCCR3_BPP)
62 static void (*pxafb_backlight_power
)(int);
63 static void (*pxafb_lcd_power
)(int);
65 static int pxafb_activate_var(struct fb_var_screeninfo
*var
, struct pxafb_info
*);
66 static void set_ctrlr_state(struct pxafb_info
*fbi
, u_int state
);
68 #ifdef CONFIG_FB_PXA_PARAMETERS
69 #define PXAFB_OPTIONS_SIZE 256
70 static char g_options
[PXAFB_OPTIONS_SIZE
] __initdata
= "";
73 static inline void pxafb_schedule_work(struct pxafb_info
*fbi
, u_int state
)
77 local_irq_save(flags
);
79 * We need to handle two requests being made at the same time.
80 * There are two important cases:
81 * 1. When we are changing VT (C_REENABLE) while unblanking (C_ENABLE)
82 * We must perform the unblanking, which will do our REENABLE for us.
83 * 2. When we are blanking, but immediately unblank before we have
84 * blanked. We do the "REENABLE" thing here as well, just to be sure.
86 if (fbi
->task_state
== C_ENABLE
&& state
== C_REENABLE
)
88 if (fbi
->task_state
== C_DISABLE
&& state
== C_ENABLE
)
91 if (state
!= (u_int
)-1) {
92 fbi
->task_state
= state
;
93 schedule_work(&fbi
->task
);
95 local_irq_restore(flags
);
98 static inline u_int
chan_to_field(u_int chan
, struct fb_bitfield
*bf
)
101 chan
>>= 16 - bf
->length
;
102 return chan
<< bf
->offset
;
106 pxafb_setpalettereg(u_int regno
, u_int red
, u_int green
, u_int blue
,
107 u_int trans
, struct fb_info
*info
)
109 struct pxafb_info
*fbi
= (struct pxafb_info
*)info
;
112 if (regno
< fbi
->palette_size
) {
113 if (fbi
->fb
.var
.grayscale
) {
114 val
= ((blue
>> 8) & 0x00ff);
116 val
= ((red
>> 0) & 0xf800);
117 val
|= ((green
>> 5) & 0x07e0);
118 val
|= ((blue
>> 11) & 0x001f);
120 fbi
->palette_cpu
[regno
] = val
;
127 pxafb_setcolreg(u_int regno
, u_int red
, u_int green
, u_int blue
,
128 u_int trans
, struct fb_info
*info
)
130 struct pxafb_info
*fbi
= (struct pxafb_info
*)info
;
135 * If inverse mode was selected, invert all the colours
136 * rather than the register number. The register number
137 * is what you poke into the framebuffer to produce the
138 * colour you requested.
140 if (fbi
->cmap_inverse
) {
142 green
= 0xffff - green
;
143 blue
= 0xffff - blue
;
147 * If greyscale is true, then we convert the RGB value
148 * to greyscale no matter what visual we are using.
150 if (fbi
->fb
.var
.grayscale
)
151 red
= green
= blue
= (19595 * red
+ 38470 * green
+
154 switch (fbi
->fb
.fix
.visual
) {
155 case FB_VISUAL_TRUECOLOR
:
157 * 16-bit True Colour. We encode the RGB value
158 * according to the RGB bitfield information.
161 u32
*pal
= fbi
->fb
.pseudo_palette
;
163 val
= chan_to_field(red
, &fbi
->fb
.var
.red
);
164 val
|= chan_to_field(green
, &fbi
->fb
.var
.green
);
165 val
|= chan_to_field(blue
, &fbi
->fb
.var
.blue
);
172 case FB_VISUAL_STATIC_PSEUDOCOLOR
:
173 case FB_VISUAL_PSEUDOCOLOR
:
174 ret
= pxafb_setpalettereg(regno
, red
, green
, blue
, trans
, info
);
182 * pxafb_bpp_to_lccr3():
183 * Convert a bits per pixel value to the correct bit pattern for LCCR3
185 static int pxafb_bpp_to_lccr3(struct fb_var_screeninfo
*var
)
188 switch (var
->bits_per_pixel
) {
189 case 1: ret
= LCCR3_1BPP
; break;
190 case 2: ret
= LCCR3_2BPP
; break;
191 case 4: ret
= LCCR3_4BPP
; break;
192 case 8: ret
= LCCR3_8BPP
; break;
193 case 16: ret
= LCCR3_16BPP
; break;
198 #ifdef CONFIG_CPU_FREQ
200 * pxafb_display_dma_period()
201 * Calculate the minimum period (in picoseconds) between two DMA
202 * requests for the LCD controller. If we hit this, it means we're
203 * doing nothing but LCD DMA.
205 static unsigned int pxafb_display_dma_period(struct fb_var_screeninfo
*var
)
208 * Period = pixclock * bits_per_byte * bytes_per_transfer
209 * / memory_bits_per_pixel;
211 return var
->pixclock
* 8 * 16 / var
->bits_per_pixel
;
214 extern unsigned int get_clk_frequency_khz(int info
);
219 * Get the video params out of 'var'. If a value doesn't fit, round it up,
220 * if it's too big, return -EINVAL.
222 * Round up in the following order: bits_per_pixel, xres,
223 * yres, xres_virtual, yres_virtual, xoffset, yoffset, grayscale,
224 * bitfields, horizontal timing, vertical timing.
226 static int pxafb_check_var(struct fb_var_screeninfo
*var
, struct fb_info
*info
)
228 struct pxafb_info
*fbi
= (struct pxafb_info
*)info
;
230 if (var
->xres
< MIN_XRES
)
231 var
->xres
= MIN_XRES
;
232 if (var
->yres
< MIN_YRES
)
233 var
->yres
= MIN_YRES
;
234 if (var
->xres
> fbi
->max_xres
)
235 var
->xres
= fbi
->max_xres
;
236 if (var
->yres
> fbi
->max_yres
)
237 var
->yres
= fbi
->max_yres
;
239 max(var
->xres_virtual
, var
->xres
);
241 max(var
->yres_virtual
, var
->yres
);
244 * Setup the RGB parameters for this display.
246 * The pixel packing format is described on page 7-11 of the
247 * PXA2XX Developer's Manual.
249 if (var
->bits_per_pixel
== 16) {
250 var
->red
.offset
= 11; var
->red
.length
= 5;
251 var
->green
.offset
= 5; var
->green
.length
= 6;
252 var
->blue
.offset
= 0; var
->blue
.length
= 5;
253 var
->transp
.offset
= var
->transp
.length
= 0;
255 var
->red
.offset
= var
->green
.offset
= var
->blue
.offset
= var
->transp
.offset
= 0;
257 var
->green
.length
= 8;
258 var
->blue
.length
= 8;
259 var
->transp
.length
= 0;
262 #ifdef CONFIG_CPU_FREQ
263 pr_debug("pxafb: dma period = %d ps, clock = %d kHz\n",
264 pxafb_display_dma_period(var
),
265 get_clk_frequency_khz(0));
271 static inline void pxafb_set_truecolor(u_int is_true_color
)
273 pr_debug("pxafb: true_color = %d\n", is_true_color
);
274 // do your machine-specific setup if needed
279 * Set the user defined part of the display for the specified console
281 static int pxafb_set_par(struct fb_info
*info
)
283 struct pxafb_info
*fbi
= (struct pxafb_info
*)info
;
284 struct fb_var_screeninfo
*var
= &info
->var
;
285 unsigned long palette_mem_size
;
287 pr_debug("pxafb: set_par\n");
289 if (var
->bits_per_pixel
== 16)
290 fbi
->fb
.fix
.visual
= FB_VISUAL_TRUECOLOR
;
291 else if (!fbi
->cmap_static
)
292 fbi
->fb
.fix
.visual
= FB_VISUAL_PSEUDOCOLOR
;
295 * Some people have weird ideas about wanting static
296 * pseudocolor maps. I suspect their user space
297 * applications are broken.
299 fbi
->fb
.fix
.visual
= FB_VISUAL_STATIC_PSEUDOCOLOR
;
302 fbi
->fb
.fix
.line_length
= var
->xres_virtual
*
303 var
->bits_per_pixel
/ 8;
304 if (var
->bits_per_pixel
== 16)
305 fbi
->palette_size
= 0;
307 fbi
->palette_size
= var
->bits_per_pixel
== 1 ? 4 : 1 << var
->bits_per_pixel
;
309 palette_mem_size
= fbi
->palette_size
* sizeof(u16
);
311 pr_debug("pxafb: palette_mem_size = 0x%08lx\n", palette_mem_size
);
313 fbi
->palette_cpu
= (u16
*)(fbi
->map_cpu
+ PAGE_SIZE
- palette_mem_size
);
314 fbi
->palette_dma
= fbi
->map_dma
+ PAGE_SIZE
- palette_mem_size
;
317 * Set (any) board control register to handle new color depth
319 pxafb_set_truecolor(fbi
->fb
.fix
.visual
== FB_VISUAL_TRUECOLOR
);
321 if (fbi
->fb
.var
.bits_per_pixel
== 16)
322 fb_dealloc_cmap(&fbi
->fb
.cmap
);
324 fb_alloc_cmap(&fbi
->fb
.cmap
, 1<<fbi
->fb
.var
.bits_per_pixel
, 0);
326 pxafb_activate_var(var
, fbi
);
332 * Formal definition of the VESA spec:
334 * This refers to the state of the display when it is in full operation
336 * This defines an optional operating state of minimal power reduction with
337 * the shortest recovery time
339 * This refers to a level of power management in which substantial power
340 * reduction is achieved by the display. The display can have a longer
341 * recovery time from this state than from the Stand-by state
343 * This indicates that the display is consuming the lowest level of power
344 * and is non-operational. Recovery from this state may optionally require
345 * the user to manually power on the monitor
347 * Now, the fbdev driver adds an additional state, (blank), where they
348 * turn off the video (maybe by colormap tricks), but don't mess with the
349 * video itself: think of it semantically between on and Stand-By.
351 * So here's what we should do in our fbdev blank routine:
353 * VESA_NO_BLANKING (mode 0) Video on, front/back light on
354 * VESA_VSYNC_SUSPEND (mode 1) Video on, front/back light off
355 * VESA_HSYNC_SUSPEND (mode 2) Video on, front/back light off
356 * VESA_POWERDOWN (mode 3) Video off, front/back light off
358 * This will match the matrox implementation.
363 * Blank the display by setting all palette values to zero. Note, the
364 * 16 bpp mode does not really use the palette, so this will not
365 * blank the display in all modes.
367 static int pxafb_blank(int blank
, struct fb_info
*info
)
369 struct pxafb_info
*fbi
= (struct pxafb_info
*)info
;
372 pr_debug("pxafb: blank=%d\n", blank
);
375 case FB_BLANK_POWERDOWN
:
376 case FB_BLANK_VSYNC_SUSPEND
:
377 case FB_BLANK_HSYNC_SUSPEND
:
378 case FB_BLANK_NORMAL
:
379 if (fbi
->fb
.fix
.visual
== FB_VISUAL_PSEUDOCOLOR
||
380 fbi
->fb
.fix
.visual
== FB_VISUAL_STATIC_PSEUDOCOLOR
)
381 for (i
= 0; i
< fbi
->palette_size
; i
++)
382 pxafb_setpalettereg(i
, 0, 0, 0, 0, info
);
384 pxafb_schedule_work(fbi
, C_DISABLE
);
385 //TODO if (pxafb_blank_helper) pxafb_blank_helper(blank);
388 case FB_BLANK_UNBLANK
:
389 //TODO if (pxafb_blank_helper) pxafb_blank_helper(blank);
390 if (fbi
->fb
.fix
.visual
== FB_VISUAL_PSEUDOCOLOR
||
391 fbi
->fb
.fix
.visual
== FB_VISUAL_STATIC_PSEUDOCOLOR
)
392 fb_set_cmap(&fbi
->fb
.cmap
, info
);
393 pxafb_schedule_work(fbi
, C_ENABLE
);
398 static int pxafb_mmap(struct fb_info
*info
, struct file
*file
,
399 struct vm_area_struct
*vma
)
401 struct pxafb_info
*fbi
= (struct pxafb_info
*)info
;
402 unsigned long off
= vma
->vm_pgoff
<< PAGE_SHIFT
;
404 if (off
< info
->fix
.smem_len
) {
406 return dma_mmap_writecombine(fbi
->dev
, vma
, fbi
->map_cpu
,
407 fbi
->map_dma
, fbi
->map_size
);
412 static struct fb_ops pxafb_ops
= {
413 .owner
= THIS_MODULE
,
414 .fb_check_var
= pxafb_check_var
,
415 .fb_set_par
= pxafb_set_par
,
416 .fb_setcolreg
= pxafb_setcolreg
,
417 .fb_fillrect
= cfb_fillrect
,
418 .fb_copyarea
= cfb_copyarea
,
419 .fb_imageblit
= cfb_imageblit
,
420 .fb_blank
= pxafb_blank
,
421 .fb_mmap
= pxafb_mmap
,
425 * Calculate the PCD value from the clock rate (in picoseconds).
426 * We take account of the PPCR clock setting.
427 * From PXA Developer's Manual:
438 * LCLK = LCD/Memory Clock
441 * PixelClock here is in Hz while the pixclock argument given is the
442 * period in picoseconds. Hence PixelClock = 1 / ( pixclock * 10^-12 )
444 * The function get_lclk_frequency_10khz returns LCLK in units of
445 * 10khz. Calling the result of this function lclk gives us the
448 * PCD = (lclk * 10^4 ) * ( pixclock * 10^-12 )
449 * -------------------------------------- - 1
452 * Factoring the 10^4 and 10^-12 out gives 10^-8 == 1 / 100000000 as used below.
454 static inline unsigned int get_pcd(unsigned int pixclock
)
456 unsigned long long pcd
;
458 /* FIXME: Need to take into account Double Pixel Clock mode
459 * (DPC) bit? or perhaps set it based on the various clock
462 pcd
= (unsigned long long)get_lcdclk_frequency_10khz() * pixclock
;
463 do_div(pcd
, 100000000 * 2);
464 /* no need for this, since we should subtract 1 anyway. they cancel */
465 /* pcd += 1; */ /* make up for integer math truncations */
466 return (unsigned int)pcd
;
470 * Some touchscreens need hsync information from the video driver to
471 * function correctly. We export it here.
473 static inline void set_hsync_time(struct pxafb_info
*fbi
, unsigned int pcd
)
475 unsigned long long htime
;
477 if ((pcd
== 0) || (fbi
->fb
.var
.hsync_len
== 0)) {
482 htime
= (unsigned long long)get_lcdclk_frequency_10khz() * 10000;
483 do_div(htime
, pcd
* fbi
->fb
.var
.hsync_len
);
484 fbi
->hsync_time
= htime
;
487 unsigned long pxafb_get_hsync_time(struct device
*dev
)
489 struct pxafb_info
*fbi
= dev_get_drvdata(dev
);
491 /* If display is blanked/suspended, hsync isn't active */
492 if (!fbi
|| (fbi
->state
!= C_ENABLE
))
495 return fbi
->hsync_time
;
497 EXPORT_SYMBOL(pxafb_get_hsync_time
);
500 * pxafb_activate_var():
501 * Configures LCD Controller based on entries in var parameter. Settings are
502 * only written to the controller if changes were made.
504 static int pxafb_activate_var(struct fb_var_screeninfo
*var
, struct pxafb_info
*fbi
)
506 struct pxafb_lcd_reg new_regs
;
508 u_int lines_per_panel
, pcd
= get_pcd(var
->pixclock
);
510 pr_debug("pxafb: Configuring PXA LCD\n");
512 pr_debug("var: xres=%d hslen=%d lm=%d rm=%d\n",
513 var
->xres
, var
->hsync_len
,
514 var
->left_margin
, var
->right_margin
);
515 pr_debug("var: yres=%d vslen=%d um=%d bm=%d\n",
516 var
->yres
, var
->vsync_len
,
517 var
->upper_margin
, var
->lower_margin
);
518 pr_debug("var: pixclock=%d pcd=%d\n", var
->pixclock
, pcd
);
521 if (var
->xres
< 16 || var
->xres
> 1024)
522 printk(KERN_ERR
"%s: invalid xres %d\n",
523 fbi
->fb
.fix
.id
, var
->xres
);
524 switch(var
->bits_per_pixel
) {
532 printk(KERN_ERR
"%s: invalid bit depth %d\n",
533 fbi
->fb
.fix
.id
, var
->bits_per_pixel
);
536 if (var
->hsync_len
< 1 || var
->hsync_len
> 64)
537 printk(KERN_ERR
"%s: invalid hsync_len %d\n",
538 fbi
->fb
.fix
.id
, var
->hsync_len
);
539 if (var
->left_margin
< 1 || var
->left_margin
> 255)
540 printk(KERN_ERR
"%s: invalid left_margin %d\n",
541 fbi
->fb
.fix
.id
, var
->left_margin
);
542 if (var
->right_margin
< 1 || var
->right_margin
> 255)
543 printk(KERN_ERR
"%s: invalid right_margin %d\n",
544 fbi
->fb
.fix
.id
, var
->right_margin
);
545 if (var
->yres
< 1 || var
->yres
> 1024)
546 printk(KERN_ERR
"%s: invalid yres %d\n",
547 fbi
->fb
.fix
.id
, var
->yres
);
548 if (var
->vsync_len
< 1 || var
->vsync_len
> 64)
549 printk(KERN_ERR
"%s: invalid vsync_len %d\n",
550 fbi
->fb
.fix
.id
, var
->vsync_len
);
551 if (var
->upper_margin
< 0 || var
->upper_margin
> 255)
552 printk(KERN_ERR
"%s: invalid upper_margin %d\n",
553 fbi
->fb
.fix
.id
, var
->upper_margin
);
554 if (var
->lower_margin
< 0 || var
->lower_margin
> 255)
555 printk(KERN_ERR
"%s: invalid lower_margin %d\n",
556 fbi
->fb
.fix
.id
, var
->lower_margin
);
559 new_regs
.lccr0
= fbi
->lccr0
|
560 (LCCR0_LDM
| LCCR0_SFM
| LCCR0_IUM
| LCCR0_EFM
|
561 LCCR0_QDM
| LCCR0_BM
| LCCR0_OUM
);
564 LCCR1_DisWdth(var
->xres
) +
565 LCCR1_HorSnchWdth(var
->hsync_len
) +
566 LCCR1_BegLnDel(var
->left_margin
) +
567 LCCR1_EndLnDel(var
->right_margin
);
570 * If we have a dual scan LCD, we need to halve
571 * the YRES parameter.
573 lines_per_panel
= var
->yres
;
574 if ((fbi
->lccr0
& LCCR0_SDS
) == LCCR0_Dual
)
575 lines_per_panel
/= 2;
578 LCCR2_DisHght(lines_per_panel
) +
579 LCCR2_VrtSnchWdth(var
->vsync_len
) +
580 LCCR2_BegFrmDel(var
->upper_margin
) +
581 LCCR2_EndFrmDel(var
->lower_margin
);
583 new_regs
.lccr3
= fbi
->lccr3
|
584 pxafb_bpp_to_lccr3(var
) |
585 (var
->sync
& FB_SYNC_HOR_HIGH_ACT
? LCCR3_HorSnchH
: LCCR3_HorSnchL
) |
586 (var
->sync
& FB_SYNC_VERT_HIGH_ACT
? LCCR3_VrtSnchH
: LCCR3_VrtSnchL
);
589 new_regs
.lccr3
|= LCCR3_PixClkDiv(pcd
);
591 pr_debug("nlccr0 = 0x%08x\n", new_regs
.lccr0
);
592 pr_debug("nlccr1 = 0x%08x\n", new_regs
.lccr1
);
593 pr_debug("nlccr2 = 0x%08x\n", new_regs
.lccr2
);
594 pr_debug("nlccr3 = 0x%08x\n", new_regs
.lccr3
);
596 /* Update shadow copy atomically */
597 local_irq_save(flags
);
599 /* setup dma descriptors */
600 fbi
->dmadesc_fblow_cpu
= (struct pxafb_dma_descriptor
*)((unsigned int)fbi
->palette_cpu
- 3*16);
601 fbi
->dmadesc_fbhigh_cpu
= (struct pxafb_dma_descriptor
*)((unsigned int)fbi
->palette_cpu
- 2*16);
602 fbi
->dmadesc_palette_cpu
= (struct pxafb_dma_descriptor
*)((unsigned int)fbi
->palette_cpu
- 1*16);
604 fbi
->dmadesc_fblow_dma
= fbi
->palette_dma
- 3*16;
605 fbi
->dmadesc_fbhigh_dma
= fbi
->palette_dma
- 2*16;
606 fbi
->dmadesc_palette_dma
= fbi
->palette_dma
- 1*16;
608 #define BYTES_PER_PANEL (lines_per_panel * fbi->fb.fix.line_length)
610 /* populate descriptors */
611 fbi
->dmadesc_fblow_cpu
->fdadr
= fbi
->dmadesc_fblow_dma
;
612 fbi
->dmadesc_fblow_cpu
->fsadr
= fbi
->screen_dma
+ BYTES_PER_PANEL
;
613 fbi
->dmadesc_fblow_cpu
->fidr
= 0;
614 fbi
->dmadesc_fblow_cpu
->ldcmd
= BYTES_PER_PANEL
;
616 fbi
->fdadr1
= fbi
->dmadesc_fblow_dma
; /* only used in dual-panel mode */
618 fbi
->dmadesc_fbhigh_cpu
->fsadr
= fbi
->screen_dma
;
619 fbi
->dmadesc_fbhigh_cpu
->fidr
= 0;
620 fbi
->dmadesc_fbhigh_cpu
->ldcmd
= BYTES_PER_PANEL
;
622 fbi
->dmadesc_palette_cpu
->fsadr
= fbi
->palette_dma
;
623 fbi
->dmadesc_palette_cpu
->fidr
= 0;
624 fbi
->dmadesc_palette_cpu
->ldcmd
= (fbi
->palette_size
* 2) | LDCMD_PAL
;
626 if (var
->bits_per_pixel
== 16) {
627 /* palette shouldn't be loaded in true-color mode */
628 fbi
->dmadesc_fbhigh_cpu
->fdadr
= fbi
->dmadesc_fbhigh_dma
;
629 fbi
->fdadr0
= fbi
->dmadesc_fbhigh_dma
; /* no pal just fbhigh */
630 /* init it to something, even though we won't be using it */
631 fbi
->dmadesc_palette_cpu
->fdadr
= fbi
->dmadesc_palette_dma
;
633 fbi
->dmadesc_palette_cpu
->fdadr
= fbi
->dmadesc_fbhigh_dma
;
634 fbi
->dmadesc_fbhigh_cpu
->fdadr
= fbi
->dmadesc_palette_dma
;
635 fbi
->fdadr0
= fbi
->dmadesc_palette_dma
; /* flips back and forth between pal and fbhigh */
639 pr_debug("fbi->dmadesc_fblow_cpu = 0x%p\n", fbi
->dmadesc_fblow_cpu
);
640 pr_debug("fbi->dmadesc_fbhigh_cpu = 0x%p\n", fbi
->dmadesc_fbhigh_cpu
);
641 pr_debug("fbi->dmadesc_palette_cpu = 0x%p\n", fbi
->dmadesc_palette_cpu
);
642 pr_debug("fbi->dmadesc_fblow_dma = 0x%x\n", fbi
->dmadesc_fblow_dma
);
643 pr_debug("fbi->dmadesc_fbhigh_dma = 0x%x\n", fbi
->dmadesc_fbhigh_dma
);
644 pr_debug("fbi->dmadesc_palette_dma = 0x%x\n", fbi
->dmadesc_palette_dma
);
646 pr_debug("fbi->dmadesc_fblow_cpu->fdadr = 0x%x\n", fbi
->dmadesc_fblow_cpu
->fdadr
);
647 pr_debug("fbi->dmadesc_fbhigh_cpu->fdadr = 0x%x\n", fbi
->dmadesc_fbhigh_cpu
->fdadr
);
648 pr_debug("fbi->dmadesc_palette_cpu->fdadr = 0x%x\n", fbi
->dmadesc_palette_cpu
->fdadr
);
650 pr_debug("fbi->dmadesc_fblow_cpu->fsadr = 0x%x\n", fbi
->dmadesc_fblow_cpu
->fsadr
);
651 pr_debug("fbi->dmadesc_fbhigh_cpu->fsadr = 0x%x\n", fbi
->dmadesc_fbhigh_cpu
->fsadr
);
652 pr_debug("fbi->dmadesc_palette_cpu->fsadr = 0x%x\n", fbi
->dmadesc_palette_cpu
->fsadr
);
654 pr_debug("fbi->dmadesc_fblow_cpu->ldcmd = 0x%x\n", fbi
->dmadesc_fblow_cpu
->ldcmd
);
655 pr_debug("fbi->dmadesc_fbhigh_cpu->ldcmd = 0x%x\n", fbi
->dmadesc_fbhigh_cpu
->ldcmd
);
656 pr_debug("fbi->dmadesc_palette_cpu->ldcmd = 0x%x\n", fbi
->dmadesc_palette_cpu
->ldcmd
);
659 fbi
->reg_lccr0
= new_regs
.lccr0
;
660 fbi
->reg_lccr1
= new_regs
.lccr1
;
661 fbi
->reg_lccr2
= new_regs
.lccr2
;
662 fbi
->reg_lccr3
= new_regs
.lccr3
;
663 set_hsync_time(fbi
, pcd
);
664 local_irq_restore(flags
);
667 * Only update the registers if the controller is enabled
668 * and something has changed.
670 if ((LCCR0
!= fbi
->reg_lccr0
) || (LCCR1
!= fbi
->reg_lccr1
) ||
671 (LCCR2
!= fbi
->reg_lccr2
) || (LCCR3
!= fbi
->reg_lccr3
) ||
672 (FDADR0
!= fbi
->fdadr0
) || (FDADR1
!= fbi
->fdadr1
))
673 pxafb_schedule_work(fbi
, C_REENABLE
);
679 * NOTE! The following functions are purely helpers for set_ctrlr_state.
680 * Do not call them directly; set_ctrlr_state does the correct serialisation
681 * to ensure that things happen in the right way 100% of time time.
684 static inline void __pxafb_backlight_power(struct pxafb_info
*fbi
, int on
)
686 pr_debug("pxafb: backlight o%s\n", on
? "n" : "ff");
688 if (pxafb_backlight_power
)
689 pxafb_backlight_power(on
);
692 static inline void __pxafb_lcd_power(struct pxafb_info
*fbi
, int on
)
694 pr_debug("pxafb: LCD power o%s\n", on
? "n" : "ff");
700 static void pxafb_setup_gpio(struct pxafb_info
*fbi
)
703 unsigned int lccr0
= fbi
->lccr0
;
706 * setup is based on type of panel supported
709 /* 4 bit interface */
710 if ((lccr0
& LCCR0_CMS
) == LCCR0_Mono
&&
711 (lccr0
& LCCR0_SDS
) == LCCR0_Sngl
&&
712 (lccr0
& LCCR0_DPD
) == LCCR0_4PixMono
)
715 /* 8 bit interface */
716 else if (((lccr0
& LCCR0_CMS
) == LCCR0_Mono
&&
717 ((lccr0
& LCCR0_SDS
) == LCCR0_Dual
|| (lccr0
& LCCR0_DPD
) == LCCR0_8PixMono
)) ||
718 ((lccr0
& LCCR0_CMS
) == LCCR0_Color
&&
719 (lccr0
& LCCR0_PAS
) == LCCR0_Pas
&& (lccr0
& LCCR0_SDS
) == LCCR0_Sngl
))
722 /* 16 bit interface */
723 else if ((lccr0
& LCCR0_CMS
) == LCCR0_Color
&&
724 ((lccr0
& LCCR0_SDS
) == LCCR0_Dual
|| (lccr0
& LCCR0_PAS
) == LCCR0_Act
))
728 printk(KERN_ERR
"pxafb_setup_gpio: unable to determine bits per pixel\n");
732 for (gpio
= 58; ldd_bits
; gpio
++, ldd_bits
--)
733 pxa_gpio_mode(gpio
| GPIO_ALT_FN_2_OUT
);
734 pxa_gpio_mode(GPIO74_LCD_FCLK_MD
);
735 pxa_gpio_mode(GPIO75_LCD_LCLK_MD
);
736 pxa_gpio_mode(GPIO76_LCD_PCLK_MD
);
737 pxa_gpio_mode(GPIO77_LCD_ACBIAS_MD
);
740 static void pxafb_enable_controller(struct pxafb_info
*fbi
)
742 pr_debug("pxafb: Enabling LCD controller\n");
743 pr_debug("fdadr0 0x%08x\n", (unsigned int) fbi
->fdadr0
);
744 pr_debug("fdadr1 0x%08x\n", (unsigned int) fbi
->fdadr1
);
745 pr_debug("reg_lccr0 0x%08x\n", (unsigned int) fbi
->reg_lccr0
);
746 pr_debug("reg_lccr1 0x%08x\n", (unsigned int) fbi
->reg_lccr1
);
747 pr_debug("reg_lccr2 0x%08x\n", (unsigned int) fbi
->reg_lccr2
);
748 pr_debug("reg_lccr3 0x%08x\n", (unsigned int) fbi
->reg_lccr3
);
750 /* enable LCD controller clock */
751 pxa_set_cken(CKEN16_LCD
, 1);
753 /* Sequence from 11.7.10 */
754 LCCR3
= fbi
->reg_lccr3
;
755 LCCR2
= fbi
->reg_lccr2
;
756 LCCR1
= fbi
->reg_lccr1
;
757 LCCR0
= fbi
->reg_lccr0
& ~LCCR0_ENB
;
759 FDADR0
= fbi
->fdadr0
;
760 FDADR1
= fbi
->fdadr1
;
763 pr_debug("FDADR0 0x%08x\n", (unsigned int) FDADR0
);
764 pr_debug("FDADR1 0x%08x\n", (unsigned int) FDADR1
);
765 pr_debug("LCCR0 0x%08x\n", (unsigned int) LCCR0
);
766 pr_debug("LCCR1 0x%08x\n", (unsigned int) LCCR1
);
767 pr_debug("LCCR2 0x%08x\n", (unsigned int) LCCR2
);
768 pr_debug("LCCR3 0x%08x\n", (unsigned int) LCCR3
);
771 static void pxafb_disable_controller(struct pxafb_info
*fbi
)
773 DECLARE_WAITQUEUE(wait
, current
);
775 pr_debug("pxafb: disabling LCD controller\n");
777 set_current_state(TASK_UNINTERRUPTIBLE
);
778 add_wait_queue(&fbi
->ctrlr_wait
, &wait
);
780 LCSR
= 0xffffffff; /* Clear LCD Status Register */
781 LCCR0
&= ~LCCR0_LDM
; /* Enable LCD Disable Done Interrupt */
782 LCCR0
|= LCCR0_DIS
; /* Disable LCD Controller */
784 schedule_timeout(20 * HZ
/ 1000);
785 remove_wait_queue(&fbi
->ctrlr_wait
, &wait
);
787 /* disable LCD controller clock */
788 pxa_set_cken(CKEN16_LCD
, 0);
792 * pxafb_handle_irq: Handle 'LCD DONE' interrupts.
794 static irqreturn_t
pxafb_handle_irq(int irq
, void *dev_id
, struct pt_regs
*regs
)
796 struct pxafb_info
*fbi
= dev_id
;
797 unsigned int lcsr
= LCSR
;
799 if (lcsr
& LCSR_LDD
) {
801 wake_up(&fbi
->ctrlr_wait
);
809 * This function must be called from task context only, since it will
810 * sleep when disabling the LCD controller, or if we get two contending
811 * processes trying to alter state.
813 static void set_ctrlr_state(struct pxafb_info
*fbi
, u_int state
)
817 down(&fbi
->ctrlr_sem
);
819 old_state
= fbi
->state
;
822 * Hack around fbcon initialisation.
824 if (old_state
== C_STARTUP
&& state
== C_REENABLE
)
828 case C_DISABLE_CLKCHANGE
:
830 * Disable controller for clock change. If the
831 * controller is already disabled, then do nothing.
833 if (old_state
!= C_DISABLE
&& old_state
!= C_DISABLE_PM
) {
835 //TODO __pxafb_lcd_power(fbi, 0);
836 pxafb_disable_controller(fbi
);
845 if (old_state
!= C_DISABLE
) {
847 __pxafb_backlight_power(fbi
, 0);
848 __pxafb_lcd_power(fbi
, 0);
849 if (old_state
!= C_DISABLE_CLKCHANGE
)
850 pxafb_disable_controller(fbi
);
854 case C_ENABLE_CLKCHANGE
:
856 * Enable the controller after clock change. Only
857 * do this if we were disabled for the clock change.
859 if (old_state
== C_DISABLE_CLKCHANGE
) {
860 fbi
->state
= C_ENABLE
;
861 pxafb_enable_controller(fbi
);
862 //TODO __pxafb_lcd_power(fbi, 1);
868 * Re-enable the controller only if it was already
869 * enabled. This is so we reprogram the control
872 if (old_state
== C_ENABLE
) {
873 pxafb_disable_controller(fbi
);
874 pxafb_setup_gpio(fbi
);
875 pxafb_enable_controller(fbi
);
881 * Re-enable the controller after PM. This is not
882 * perfect - think about the case where we were doing
883 * a clock change, and we suspended half-way through.
885 if (old_state
!= C_DISABLE_PM
)
891 * Power up the LCD screen, enable controller, and
892 * turn on the backlight.
894 if (old_state
!= C_ENABLE
) {
895 fbi
->state
= C_ENABLE
;
896 pxafb_setup_gpio(fbi
);
897 pxafb_enable_controller(fbi
);
898 __pxafb_lcd_power(fbi
, 1);
899 __pxafb_backlight_power(fbi
, 1);
907 * Our LCD controller task (which is called when we blank or unblank)
910 static void pxafb_task(void *dummy
)
912 struct pxafb_info
*fbi
= dummy
;
913 u_int state
= xchg(&fbi
->task_state
, -1);
915 set_ctrlr_state(fbi
, state
);
918 #ifdef CONFIG_CPU_FREQ
920 * CPU clock speed change handler. We need to adjust the LCD timing
921 * parameters when the CPU clock is adjusted by the power management
924 * TODO: Determine why f->new != 10*get_lclk_frequency_10khz()
927 pxafb_freq_transition(struct notifier_block
*nb
, unsigned long val
, void *data
)
929 struct pxafb_info
*fbi
= TO_INF(nb
, freq_transition
);
930 //TODO struct cpufreq_freqs *f = data;
934 case CPUFREQ_PRECHANGE
:
935 set_ctrlr_state(fbi
, C_DISABLE_CLKCHANGE
);
938 case CPUFREQ_POSTCHANGE
:
939 pcd
= get_pcd(fbi
->fb
.var
.pixclock
);
940 set_hsync_time(fbi
, pcd
);
941 fbi
->reg_lccr3
= (fbi
->reg_lccr3
& ~0xff) | LCCR3_PixClkDiv(pcd
);
942 set_ctrlr_state(fbi
, C_ENABLE_CLKCHANGE
);
949 pxafb_freq_policy(struct notifier_block
*nb
, unsigned long val
, void *data
)
951 struct pxafb_info
*fbi
= TO_INF(nb
, freq_policy
);
952 struct fb_var_screeninfo
*var
= &fbi
->fb
.var
;
953 struct cpufreq_policy
*policy
= data
;
957 case CPUFREQ_INCOMPATIBLE
:
958 printk(KERN_DEBUG
"min dma period: %d ps, "
959 "new clock %d kHz\n", pxafb_display_dma_period(var
),
961 // TODO: fill in min/max values
965 printk(KERN_ERR
"%s: got CPUFREQ_NOTIFY\n", __FUNCTION__
);
967 /* todo: panic if min/max values aren't fulfilled
968 * [can't really happen unless there's a bug in the
969 * CPU policy verification process *
980 * Power management hooks. Note that we won't be called from IRQ context,
981 * unlike the blank functions above, so we may sleep.
983 static int pxafb_suspend(struct platform_device
*dev
, pm_message_t state
)
985 struct pxafb_info
*fbi
= platform_get_drvdata(dev
);
987 set_ctrlr_state(fbi
, C_DISABLE_PM
);
991 static int pxafb_resume(struct platform_device
*dev
)
993 struct pxafb_info
*fbi
= platform_get_drvdata(dev
);
995 set_ctrlr_state(fbi
, C_ENABLE_PM
);
999 #define pxafb_suspend NULL
1000 #define pxafb_resume NULL
1004 * pxafb_map_video_memory():
1005 * Allocates the DRAM memory for the frame buffer. This buffer is
1006 * remapped into a non-cached, non-buffered, memory region to
1007 * allow palette and pixel writes to occur without flushing the
1008 * cache. Once this area is remapped, all virtual memory
1009 * access to the video memory should occur at the new region.
1011 static int __init
pxafb_map_video_memory(struct pxafb_info
*fbi
)
1013 u_long palette_mem_size
;
1016 * We reserve one page for the palette, plus the size
1017 * of the framebuffer.
1019 fbi
->map_size
= PAGE_ALIGN(fbi
->fb
.fix
.smem_len
+ PAGE_SIZE
);
1020 fbi
->map_cpu
= dma_alloc_writecombine(fbi
->dev
, fbi
->map_size
,
1021 &fbi
->map_dma
, GFP_KERNEL
);
1024 /* prevent initial garbage on screen */
1025 memset(fbi
->map_cpu
, 0, fbi
->map_size
);
1026 fbi
->fb
.screen_base
= fbi
->map_cpu
+ PAGE_SIZE
;
1027 fbi
->screen_dma
= fbi
->map_dma
+ PAGE_SIZE
;
1029 * FIXME: this is actually the wrong thing to place in
1030 * smem_start. But fbdev suffers from the problem that
1031 * it needs an API which doesn't exist (in this case,
1032 * dma_writecombine_mmap)
1034 fbi
->fb
.fix
.smem_start
= fbi
->screen_dma
;
1036 fbi
->palette_size
= fbi
->fb
.var
.bits_per_pixel
== 8 ? 256 : 16;
1038 palette_mem_size
= fbi
->palette_size
* sizeof(u16
);
1039 pr_debug("pxafb: palette_mem_size = 0x%08lx\n", palette_mem_size
);
1041 fbi
->palette_cpu
= (u16
*)(fbi
->map_cpu
+ PAGE_SIZE
- palette_mem_size
);
1042 fbi
->palette_dma
= fbi
->map_dma
+ PAGE_SIZE
- palette_mem_size
;
1045 return fbi
->map_cpu
? 0 : -ENOMEM
;
1048 static struct pxafb_info
* __init
pxafb_init_fbinfo(struct device
*dev
)
1050 struct pxafb_info
*fbi
;
1052 struct pxafb_mach_info
*inf
= dev
->platform_data
;
1054 /* Alloc the pxafb_info and pseudo_palette in one step */
1055 fbi
= kmalloc(sizeof(struct pxafb_info
) + sizeof(u32
) * 16, GFP_KERNEL
);
1059 memset(fbi
, 0, sizeof(struct pxafb_info
));
1062 strcpy(fbi
->fb
.fix
.id
, PXA_NAME
);
1064 fbi
->fb
.fix
.type
= FB_TYPE_PACKED_PIXELS
;
1065 fbi
->fb
.fix
.type_aux
= 0;
1066 fbi
->fb
.fix
.xpanstep
= 0;
1067 fbi
->fb
.fix
.ypanstep
= 0;
1068 fbi
->fb
.fix
.ywrapstep
= 0;
1069 fbi
->fb
.fix
.accel
= FB_ACCEL_NONE
;
1071 fbi
->fb
.var
.nonstd
= 0;
1072 fbi
->fb
.var
.activate
= FB_ACTIVATE_NOW
;
1073 fbi
->fb
.var
.height
= -1;
1074 fbi
->fb
.var
.width
= -1;
1075 fbi
->fb
.var
.accel_flags
= 0;
1076 fbi
->fb
.var
.vmode
= FB_VMODE_NONINTERLACED
;
1078 fbi
->fb
.fbops
= &pxafb_ops
;
1079 fbi
->fb
.flags
= FBINFO_DEFAULT
;
1083 addr
= addr
+ sizeof(struct pxafb_info
);
1084 fbi
->fb
.pseudo_palette
= addr
;
1086 fbi
->max_xres
= inf
->xres
;
1087 fbi
->fb
.var
.xres
= inf
->xres
;
1088 fbi
->fb
.var
.xres_virtual
= inf
->xres
;
1089 fbi
->max_yres
= inf
->yres
;
1090 fbi
->fb
.var
.yres
= inf
->yres
;
1091 fbi
->fb
.var
.yres_virtual
= inf
->yres
;
1092 fbi
->max_bpp
= inf
->bpp
;
1093 fbi
->fb
.var
.bits_per_pixel
= inf
->bpp
;
1094 fbi
->fb
.var
.pixclock
= inf
->pixclock
;
1095 fbi
->fb
.var
.hsync_len
= inf
->hsync_len
;
1096 fbi
->fb
.var
.left_margin
= inf
->left_margin
;
1097 fbi
->fb
.var
.right_margin
= inf
->right_margin
;
1098 fbi
->fb
.var
.vsync_len
= inf
->vsync_len
;
1099 fbi
->fb
.var
.upper_margin
= inf
->upper_margin
;
1100 fbi
->fb
.var
.lower_margin
= inf
->lower_margin
;
1101 fbi
->fb
.var
.sync
= inf
->sync
;
1102 fbi
->fb
.var
.grayscale
= inf
->cmap_greyscale
;
1103 fbi
->cmap_inverse
= inf
->cmap_inverse
;
1104 fbi
->cmap_static
= inf
->cmap_static
;
1105 fbi
->lccr0
= inf
->lccr0
;
1106 fbi
->lccr3
= inf
->lccr3
;
1107 fbi
->state
= C_STARTUP
;
1108 fbi
->task_state
= (u_char
)-1;
1109 fbi
->fb
.fix
.smem_len
= fbi
->max_xres
* fbi
->max_yres
*
1112 init_waitqueue_head(&fbi
->ctrlr_wait
);
1113 INIT_WORK(&fbi
->task
, pxafb_task
, fbi
);
1114 init_MUTEX(&fbi
->ctrlr_sem
);
1119 #ifdef CONFIG_FB_PXA_PARAMETERS
1120 static int __init
pxafb_parse_options(struct device
*dev
, char *options
)
1122 struct pxafb_mach_info
*inf
= dev
->platform_data
;
1125 if (!options
|| !*options
)
1128 dev_dbg(dev
, "options are \"%s\"\n", options
? options
: "null");
1130 /* could be made table driven or similar?... */
1131 while ((this_opt
= strsep(&options
, ",")) != NULL
) {
1132 if (!strncmp(this_opt
, "mode:", 5)) {
1133 const char *name
= this_opt
+5;
1134 unsigned int namelen
= strlen(name
);
1135 int res_specified
= 0, bpp_specified
= 0;
1136 unsigned int xres
= 0, yres
= 0, bpp
= 0;
1137 int yres_specified
= 0;
1139 for (i
= namelen
-1; i
>= 0; i
--) {
1143 if (!bpp_specified
&& !yres_specified
) {
1144 bpp
= simple_strtoul(&name
[i
+1], NULL
, 0);
1150 if (!yres_specified
) {
1151 yres
= simple_strtoul(&name
[i
+1], NULL
, 0);
1162 if (i
< 0 && yres_specified
) {
1163 xres
= simple_strtoul(name
, NULL
, 0);
1167 if (res_specified
) {
1168 dev_info(dev
, "overriding resolution: %dx%d\n", xres
, yres
);
1169 inf
->xres
= xres
; inf
->yres
= yres
;
1179 dev_info(dev
, "overriding bit depth: %d\n", bpp
);
1182 dev_err(dev
, "Depth %d is not valid\n", bpp
);
1184 } else if (!strncmp(this_opt
, "pixclock:", 9)) {
1185 inf
->pixclock
= simple_strtoul(this_opt
+9, NULL
, 0);
1186 dev_info(dev
, "override pixclock: %ld\n", inf
->pixclock
);
1187 } else if (!strncmp(this_opt
, "left:", 5)) {
1188 inf
->left_margin
= simple_strtoul(this_opt
+5, NULL
, 0);
1189 dev_info(dev
, "override left: %u\n", inf
->left_margin
);
1190 } else if (!strncmp(this_opt
, "right:", 6)) {
1191 inf
->right_margin
= simple_strtoul(this_opt
+6, NULL
, 0);
1192 dev_info(dev
, "override right: %u\n", inf
->right_margin
);
1193 } else if (!strncmp(this_opt
, "upper:", 6)) {
1194 inf
->upper_margin
= simple_strtoul(this_opt
+6, NULL
, 0);
1195 dev_info(dev
, "override upper: %u\n", inf
->upper_margin
);
1196 } else if (!strncmp(this_opt
, "lower:", 6)) {
1197 inf
->lower_margin
= simple_strtoul(this_opt
+6, NULL
, 0);
1198 dev_info(dev
, "override lower: %u\n", inf
->lower_margin
);
1199 } else if (!strncmp(this_opt
, "hsynclen:", 9)) {
1200 inf
->hsync_len
= simple_strtoul(this_opt
+9, NULL
, 0);
1201 dev_info(dev
, "override hsynclen: %u\n", inf
->hsync_len
);
1202 } else if (!strncmp(this_opt
, "vsynclen:", 9)) {
1203 inf
->vsync_len
= simple_strtoul(this_opt
+9, NULL
, 0);
1204 dev_info(dev
, "override vsynclen: %u\n", inf
->vsync_len
);
1205 } else if (!strncmp(this_opt
, "hsync:", 6)) {
1206 if (simple_strtoul(this_opt
+6, NULL
, 0) == 0) {
1207 dev_info(dev
, "override hsync: Active Low\n");
1208 inf
->sync
&= ~FB_SYNC_HOR_HIGH_ACT
;
1210 dev_info(dev
, "override hsync: Active High\n");
1211 inf
->sync
|= FB_SYNC_HOR_HIGH_ACT
;
1213 } else if (!strncmp(this_opt
, "vsync:", 6)) {
1214 if (simple_strtoul(this_opt
+6, NULL
, 0) == 0) {
1215 dev_info(dev
, "override vsync: Active Low\n");
1216 inf
->sync
&= ~FB_SYNC_VERT_HIGH_ACT
;
1218 dev_info(dev
, "override vsync: Active High\n");
1219 inf
->sync
|= FB_SYNC_VERT_HIGH_ACT
;
1221 } else if (!strncmp(this_opt
, "dpc:", 4)) {
1222 if (simple_strtoul(this_opt
+4, NULL
, 0) == 0) {
1223 dev_info(dev
, "override double pixel clock: false\n");
1224 inf
->lccr3
&= ~LCCR3_DPC
;
1226 dev_info(dev
, "override double pixel clock: true\n");
1227 inf
->lccr3
|= LCCR3_DPC
;
1229 } else if (!strncmp(this_opt
, "outputen:", 9)) {
1230 if (simple_strtoul(this_opt
+9, NULL
, 0) == 0) {
1231 dev_info(dev
, "override output enable: active low\n");
1232 inf
->lccr3
= (inf
->lccr3
& ~LCCR3_OEP
) | LCCR3_OutEnL
;
1234 dev_info(dev
, "override output enable: active high\n");
1235 inf
->lccr3
= (inf
->lccr3
& ~LCCR3_OEP
) | LCCR3_OutEnH
;
1237 } else if (!strncmp(this_opt
, "pixclockpol:", 12)) {
1238 if (simple_strtoul(this_opt
+12, NULL
, 0) == 0) {
1239 dev_info(dev
, "override pixel clock polarity: falling edge\n");
1240 inf
->lccr3
= (inf
->lccr3
& ~LCCR3_PCP
) | LCCR3_PixFlEdg
;
1242 dev_info(dev
, "override pixel clock polarity: rising edge\n");
1243 inf
->lccr3
= (inf
->lccr3
& ~LCCR3_PCP
) | LCCR3_PixRsEdg
;
1245 } else if (!strncmp(this_opt
, "color", 5)) {
1246 inf
->lccr0
= (inf
->lccr0
& ~LCCR0_CMS
) | LCCR0_Color
;
1247 } else if (!strncmp(this_opt
, "mono", 4)) {
1248 inf
->lccr0
= (inf
->lccr0
& ~LCCR0_CMS
) | LCCR0_Mono
;
1249 } else if (!strncmp(this_opt
, "active", 6)) {
1250 inf
->lccr0
= (inf
->lccr0
& ~LCCR0_PAS
) | LCCR0_Act
;
1251 } else if (!strncmp(this_opt
, "passive", 7)) {
1252 inf
->lccr0
= (inf
->lccr0
& ~LCCR0_PAS
) | LCCR0_Pas
;
1253 } else if (!strncmp(this_opt
, "single", 6)) {
1254 inf
->lccr0
= (inf
->lccr0
& ~LCCR0_SDS
) | LCCR0_Sngl
;
1255 } else if (!strncmp(this_opt
, "dual", 4)) {
1256 inf
->lccr0
= (inf
->lccr0
& ~LCCR0_SDS
) | LCCR0_Dual
;
1257 } else if (!strncmp(this_opt
, "4pix", 4)) {
1258 inf
->lccr0
= (inf
->lccr0
& ~LCCR0_DPD
) | LCCR0_4PixMono
;
1259 } else if (!strncmp(this_opt
, "8pix", 4)) {
1260 inf
->lccr0
= (inf
->lccr0
& ~LCCR0_DPD
) | LCCR0_8PixMono
;
1262 dev_err(dev
, "unknown option: %s\n", this_opt
);
1271 int __init
pxafb_probe(struct platform_device
*dev
)
1273 struct pxafb_info
*fbi
;
1274 struct pxafb_mach_info
*inf
;
1277 dev_dbg(dev
, "pxafb_probe\n");
1279 inf
= dev
->dev
.platform_data
;
1285 #ifdef CONFIG_FB_PXA_PARAMETERS
1286 ret
= pxafb_parse_options(&dev
->dev
, g_options
);
1292 /* Check for various illegal bit-combinations. Currently only
1293 * a warning is given. */
1295 if (inf
->lccr0
& LCCR0_INVALID_CONFIG_MASK
)
1296 dev_warn(&dev
->dev
, "machine LCCR0 setting contains illegal bits: %08x\n",
1297 inf
->lccr0
& LCCR0_INVALID_CONFIG_MASK
);
1298 if (inf
->lccr3
& LCCR3_INVALID_CONFIG_MASK
)
1299 dev_warn(&dev
->dev
, "machine LCCR3 setting contains illegal bits: %08x\n",
1300 inf
->lccr3
& LCCR3_INVALID_CONFIG_MASK
);
1301 if (inf
->lccr0
& LCCR0_DPD
&&
1302 ((inf
->lccr0
& LCCR0_PAS
) != LCCR0_Pas
||
1303 (inf
->lccr0
& LCCR0_SDS
) != LCCR0_Sngl
||
1304 (inf
->lccr0
& LCCR0_CMS
) != LCCR0_Mono
))
1305 dev_warn(&dev
->dev
, "Double Pixel Data (DPD) mode is only valid in passive mono"
1306 " single panel mode\n");
1307 if ((inf
->lccr0
& LCCR0_PAS
) == LCCR0_Act
&&
1308 (inf
->lccr0
& LCCR0_SDS
) == LCCR0_Dual
)
1309 dev_warn(&dev
->dev
, "Dual panel only valid in passive mode\n");
1310 if ((inf
->lccr0
& LCCR0_PAS
) == LCCR0_Pas
&&
1311 (inf
->upper_margin
|| inf
->lower_margin
))
1312 dev_warn(&dev
->dev
, "Upper and lower margins must be 0 in passive mode\n");
1315 dev_dbg(&dev
->dev
, "got a %dx%dx%d LCD\n",inf
->xres
, inf
->yres
, inf
->bpp
);
1316 if (inf
->xres
== 0 || inf
->yres
== 0 || inf
->bpp
== 0) {
1317 dev_err(&dev
->dev
, "Invalid resolution or bit depth\n");
1321 pxafb_backlight_power
= inf
->pxafb_backlight_power
;
1322 pxafb_lcd_power
= inf
->pxafb_lcd_power
;
1323 fbi
= pxafb_init_fbinfo(&dev
->dev
);
1325 dev_err(&dev
->dev
, "Failed to initialize framebuffer device\n");
1326 ret
= -ENOMEM
; // only reason for pxafb_init_fbinfo to fail is kmalloc
1330 /* Initialize video memory */
1331 ret
= pxafb_map_video_memory(fbi
);
1333 dev_err(&dev
->dev
, "Failed to allocate video RAM: %d\n", ret
);
1338 ret
= request_irq(IRQ_LCD
, pxafb_handle_irq
, SA_INTERRUPT
, "LCD", fbi
);
1340 dev_err(&dev
->dev
, "request_irq failed: %d\n", ret
);
1346 * This makes sure that our colour bitfield
1347 * descriptors are correctly initialised.
1349 pxafb_check_var(&fbi
->fb
.var
, &fbi
->fb
);
1350 pxafb_set_par(&fbi
->fb
);
1352 platform_set_drvdata(dev
, fbi
);
1354 ret
= register_framebuffer(&fbi
->fb
);
1356 dev_err(&dev
->dev
, "Failed to register framebuffer device: %d\n", ret
);
1364 #ifdef CONFIG_CPU_FREQ
1365 fbi
->freq_transition
.notifier_call
= pxafb_freq_transition
;
1366 fbi
->freq_policy
.notifier_call
= pxafb_freq_policy
;
1367 cpufreq_register_notifier(&fbi
->freq_transition
, CPUFREQ_TRANSITION_NOTIFIER
);
1368 cpufreq_register_notifier(&fbi
->freq_policy
, CPUFREQ_POLICY_NOTIFIER
);
1372 * Ok, now enable the LCD controller
1374 set_ctrlr_state(fbi
, C_ENABLE
);
1379 platform_set_drvdata(dev
, NULL
);
1384 static struct platform_driver pxafb_driver
= {
1385 .probe
= pxafb_probe
,
1387 .suspend
= pxafb_suspend
,
1388 .resume
= pxafb_resume
,
1391 .name
= "pxa2xx-fb",
1396 int __devinit
pxafb_setup(char *options
)
1398 # ifdef CONFIG_FB_PXA_PARAMETERS
1400 strlcpy(g_options
, options
, sizeof(g_options
));
1405 # ifdef CONFIG_FB_PXA_PARAMETERS
1406 module_param_string(options
, g_options
, sizeof(g_options
), 0);
1407 MODULE_PARM_DESC(options
, "LCD parameters (see Documentation/fb/pxafb.txt)");
1411 int __devinit
pxafb_init(void)
1414 char *option
= NULL
;
1416 if (fb_get_options("pxafb", &option
))
1418 pxafb_setup(option
);
1420 return platform_driver_register(&pxafb_driver
);
1423 module_init(pxafb_init
);
1425 MODULE_DESCRIPTION("loadable framebuffer driver for PXA");
1426 MODULE_LICENSE("GPL");