1 /*************************************************************************
2 * myri10ge.c: Myricom Myri-10G Ethernet driver.
4 * Copyright (C) 2005 - 2009 Myricom, Inc.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. Neither the name of Myricom, Inc. nor the names of its contributors
16 * may be used to endorse or promote products derived from this software
17 * without specific prior written permission.
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
32 * If the eeprom on your board is not recent enough, you will need to get a
33 * newer firmware image at:
34 * http://www.myri.com/scs/download-Myri10GE.html
36 * Contact Information:
38 * Myricom, Inc., 325N Santa Anita Avenue, Arcadia, CA 91006
39 *************************************************************************/
41 #include <linux/tcp.h>
42 #include <linux/netdevice.h>
43 #include <linux/skbuff.h>
44 #include <linux/string.h>
45 #include <linux/module.h>
46 #include <linux/pci.h>
47 #include <linux/dma-mapping.h>
48 #include <linux/etherdevice.h>
49 #include <linux/if_ether.h>
50 #include <linux/if_vlan.h>
51 #include <linux/inet_lro.h>
52 #include <linux/dca.h>
54 #include <linux/inet.h>
56 #include <linux/ethtool.h>
57 #include <linux/firmware.h>
58 #include <linux/delay.h>
59 #include <linux/timer.h>
60 #include <linux/vmalloc.h>
61 #include <linux/crc32.h>
62 #include <linux/moduleparam.h>
64 #include <linux/log2.h>
65 #include <net/checksum.h>
68 #include <asm/byteorder.h>
70 #include <asm/processor.h>
75 #include "myri10ge_mcp.h"
76 #include "myri10ge_mcp_gen_header.h"
78 #define MYRI10GE_VERSION_STR "1.4.4-1.401"
80 MODULE_DESCRIPTION("Myricom 10G driver (10GbE)");
81 MODULE_AUTHOR("Maintainer: help@myri.com");
82 MODULE_VERSION(MYRI10GE_VERSION_STR
);
83 MODULE_LICENSE("Dual BSD/GPL");
85 #define MYRI10GE_MAX_ETHER_MTU 9014
87 #define MYRI10GE_ETH_STOPPED 0
88 #define MYRI10GE_ETH_STOPPING 1
89 #define MYRI10GE_ETH_STARTING 2
90 #define MYRI10GE_ETH_RUNNING 3
91 #define MYRI10GE_ETH_OPEN_FAILED 4
93 #define MYRI10GE_EEPROM_STRINGS_SIZE 256
94 #define MYRI10GE_MAX_SEND_DESC_TSO ((65536 / 2048) * 2)
95 #define MYRI10GE_MAX_LRO_DESCRIPTORS 8
96 #define MYRI10GE_LRO_MAX_PKTS 64
98 #define MYRI10GE_NO_CONFIRM_DATA htonl(0xffffffff)
99 #define MYRI10GE_NO_RESPONSE_RESULT 0xffffffff
101 #define MYRI10GE_ALLOC_ORDER 0
102 #define MYRI10GE_ALLOC_SIZE ((1 << MYRI10GE_ALLOC_ORDER) * PAGE_SIZE)
103 #define MYRI10GE_MAX_FRAGS_PER_FRAME (MYRI10GE_MAX_ETHER_MTU/MYRI10GE_ALLOC_SIZE + 1)
105 #define MYRI10GE_MAX_SLICES 32
107 struct myri10ge_rx_buffer_state
{
110 DECLARE_PCI_UNMAP_ADDR(bus
)
111 DECLARE_PCI_UNMAP_LEN(len
)
114 struct myri10ge_tx_buffer_state
{
117 DECLARE_PCI_UNMAP_ADDR(bus
)
118 DECLARE_PCI_UNMAP_LEN(len
)
121 struct myri10ge_cmd
{
127 struct myri10ge_rx_buf
{
128 struct mcp_kreq_ether_recv __iomem
*lanai
; /* lanai ptr for recv ring */
129 struct mcp_kreq_ether_recv
*shadow
; /* host shadow of recv ring */
130 struct myri10ge_rx_buffer_state
*info
;
137 int mask
; /* number of rx slots -1 */
141 struct myri10ge_tx_buf
{
142 struct mcp_kreq_ether_send __iomem
*lanai
; /* lanai ptr for sendq */
143 __be32 __iomem
*send_go
; /* "go" doorbell ptr */
144 __be32 __iomem
*send_stop
; /* "stop" doorbell ptr */
145 struct mcp_kreq_ether_send
*req_list
; /* host shadow of sendq */
147 struct myri10ge_tx_buffer_state
*info
;
148 int mask
; /* number of transmit slots -1 */
149 int req ____cacheline_aligned
; /* transmit slots submitted */
150 int pkt_start
; /* packets started */
153 int done ____cacheline_aligned
; /* transmit slots completed */
154 int pkt_done
; /* packets completed */
159 struct myri10ge_rx_done
{
160 struct mcp_slot
*entry
;
164 struct net_lro_mgr lro_mgr
;
165 struct net_lro_desc lro_desc
[MYRI10GE_MAX_LRO_DESCRIPTORS
];
168 struct myri10ge_slice_netstats
{
169 unsigned long rx_packets
;
170 unsigned long tx_packets
;
171 unsigned long rx_bytes
;
172 unsigned long tx_bytes
;
173 unsigned long rx_dropped
;
174 unsigned long tx_dropped
;
177 struct myri10ge_slice_state
{
178 struct myri10ge_tx_buf tx
; /* transmit ring */
179 struct myri10ge_rx_buf rx_small
;
180 struct myri10ge_rx_buf rx_big
;
181 struct myri10ge_rx_done rx_done
;
182 struct net_device
*dev
;
183 struct napi_struct napi
;
184 struct myri10ge_priv
*mgp
;
185 struct myri10ge_slice_netstats stats
;
186 __be32 __iomem
*irq_claim
;
187 struct mcp_irq_data
*fw_stats
;
188 dma_addr_t fw_stats_bus
;
189 int watchdog_tx_done
;
191 #ifdef CONFIG_MYRI10GE_DCA
194 __be32 __iomem
*dca_tag
;
199 struct myri10ge_priv
{
200 struct myri10ge_slice_state
*ss
;
201 int tx_boundary
; /* boundary transmits cannot cross */
203 int running
; /* running? */
204 int csum_flag
; /* rx_csums? */
208 struct net_device
*dev
;
209 struct net_device_stats stats
;
210 spinlock_t stats_lock
;
213 unsigned long board_span
;
214 unsigned long iomem_base
;
215 __be32 __iomem
*irq_deassert
;
216 char *mac_addr_string
;
217 struct mcp_cmd_response
*cmd
;
219 struct pci_dev
*pdev
;
222 struct msix_entry
*msix_vectors
;
223 #ifdef CONFIG_MYRI10GE_DCA
227 unsigned int rdma_tags_available
;
229 __be32 __iomem
*intr_coal_delay_ptr
;
233 wait_queue_head_t down_wq
;
234 struct work_struct watchdog_work
;
235 struct timer_list watchdog_timer
;
240 char eeprom_strings
[MYRI10GE_EEPROM_STRINGS_SIZE
];
241 char *product_code_string
;
242 char fw_version
[128];
246 int adopted_rx_filter_bug
;
247 u8 mac_addr
[6]; /* eeprom mac address */
248 unsigned long serial_number
;
249 int vendor_specific_offset
;
250 int fw_multicast_support
;
251 unsigned long features
;
260 static char *myri10ge_fw_unaligned
= "myri10ge_ethp_z8e.dat";
261 static char *myri10ge_fw_aligned
= "myri10ge_eth_z8e.dat";
262 static char *myri10ge_fw_rss_unaligned
= "myri10ge_rss_ethp_z8e.dat";
263 static char *myri10ge_fw_rss_aligned
= "myri10ge_rss_eth_z8e.dat";
265 static char *myri10ge_fw_name
= NULL
;
266 module_param(myri10ge_fw_name
, charp
, S_IRUGO
| S_IWUSR
);
267 MODULE_PARM_DESC(myri10ge_fw_name
, "Firmware image name");
269 static int myri10ge_ecrc_enable
= 1;
270 module_param(myri10ge_ecrc_enable
, int, S_IRUGO
);
271 MODULE_PARM_DESC(myri10ge_ecrc_enable
, "Enable Extended CRC on PCI-E");
273 static int myri10ge_small_bytes
= -1; /* -1 == auto */
274 module_param(myri10ge_small_bytes
, int, S_IRUGO
| S_IWUSR
);
275 MODULE_PARM_DESC(myri10ge_small_bytes
, "Threshold of small packets");
277 static int myri10ge_msi
= 1; /* enable msi by default */
278 module_param(myri10ge_msi
, int, S_IRUGO
| S_IWUSR
);
279 MODULE_PARM_DESC(myri10ge_msi
, "Enable Message Signalled Interrupts");
281 static int myri10ge_intr_coal_delay
= 75;
282 module_param(myri10ge_intr_coal_delay
, int, S_IRUGO
);
283 MODULE_PARM_DESC(myri10ge_intr_coal_delay
, "Interrupt coalescing delay");
285 static int myri10ge_flow_control
= 1;
286 module_param(myri10ge_flow_control
, int, S_IRUGO
);
287 MODULE_PARM_DESC(myri10ge_flow_control
, "Pause parameter");
289 static int myri10ge_deassert_wait
= 1;
290 module_param(myri10ge_deassert_wait
, int, S_IRUGO
| S_IWUSR
);
291 MODULE_PARM_DESC(myri10ge_deassert_wait
,
292 "Wait when deasserting legacy interrupts");
294 static int myri10ge_force_firmware
= 0;
295 module_param(myri10ge_force_firmware
, int, S_IRUGO
);
296 MODULE_PARM_DESC(myri10ge_force_firmware
,
297 "Force firmware to assume aligned completions");
299 static int myri10ge_initial_mtu
= MYRI10GE_MAX_ETHER_MTU
- ETH_HLEN
;
300 module_param(myri10ge_initial_mtu
, int, S_IRUGO
);
301 MODULE_PARM_DESC(myri10ge_initial_mtu
, "Initial MTU");
303 static int myri10ge_napi_weight
= 64;
304 module_param(myri10ge_napi_weight
, int, S_IRUGO
);
305 MODULE_PARM_DESC(myri10ge_napi_weight
, "Set NAPI weight");
307 static int myri10ge_watchdog_timeout
= 1;
308 module_param(myri10ge_watchdog_timeout
, int, S_IRUGO
);
309 MODULE_PARM_DESC(myri10ge_watchdog_timeout
, "Set watchdog timeout");
311 static int myri10ge_max_irq_loops
= 1048576;
312 module_param(myri10ge_max_irq_loops
, int, S_IRUGO
);
313 MODULE_PARM_DESC(myri10ge_max_irq_loops
,
314 "Set stuck legacy IRQ detection threshold");
316 #define MYRI10GE_MSG_DEFAULT NETIF_MSG_LINK
318 static int myri10ge_debug
= -1; /* defaults above */
319 module_param(myri10ge_debug
, int, 0);
320 MODULE_PARM_DESC(myri10ge_debug
, "Debug level (0=none,...,16=all)");
322 static int myri10ge_lro
= 1;
323 module_param(myri10ge_lro
, int, S_IRUGO
);
324 MODULE_PARM_DESC(myri10ge_lro
, "Enable large receive offload");
326 static int myri10ge_lro_max_pkts
= MYRI10GE_LRO_MAX_PKTS
;
327 module_param(myri10ge_lro_max_pkts
, int, S_IRUGO
);
328 MODULE_PARM_DESC(myri10ge_lro_max_pkts
,
329 "Number of LRO packets to be aggregated");
331 static int myri10ge_fill_thresh
= 256;
332 module_param(myri10ge_fill_thresh
, int, S_IRUGO
| S_IWUSR
);
333 MODULE_PARM_DESC(myri10ge_fill_thresh
, "Number of empty rx slots allowed");
335 static int myri10ge_reset_recover
= 1;
337 static int myri10ge_max_slices
= 1;
338 module_param(myri10ge_max_slices
, int, S_IRUGO
);
339 MODULE_PARM_DESC(myri10ge_max_slices
, "Max tx/rx queues");
341 static int myri10ge_rss_hash
= MXGEFW_RSS_HASH_TYPE_SRC_PORT
;
342 module_param(myri10ge_rss_hash
, int, S_IRUGO
);
343 MODULE_PARM_DESC(myri10ge_rss_hash
, "Type of RSS hashing to do");
345 static int myri10ge_dca
= 1;
346 module_param(myri10ge_dca
, int, S_IRUGO
);
347 MODULE_PARM_DESC(myri10ge_dca
, "Enable DCA if possible");
349 #define MYRI10GE_FW_OFFSET 1024*1024
350 #define MYRI10GE_HIGHPART_TO_U32(X) \
351 (sizeof (X) == 8) ? ((u32)((u64)(X) >> 32)) : (0)
352 #define MYRI10GE_LOWPART_TO_U32(X) ((u32)(X))
354 #define myri10ge_pio_copy(to,from,size) __iowrite64_copy(to,from,size/8)
356 static void myri10ge_set_multicast_list(struct net_device
*dev
);
357 static int myri10ge_sw_tso(struct sk_buff
*skb
, struct net_device
*dev
);
359 static inline void put_be32(__be32 val
, __be32 __iomem
* p
)
361 __raw_writel((__force __u32
) val
, (__force
void __iomem
*)p
);
365 myri10ge_send_cmd(struct myri10ge_priv
*mgp
, u32 cmd
,
366 struct myri10ge_cmd
*data
, int atomic
)
369 char buf_bytes
[sizeof(*buf
) + 8];
370 struct mcp_cmd_response
*response
= mgp
->cmd
;
371 char __iomem
*cmd_addr
= mgp
->sram
+ MXGEFW_ETH_CMD
;
372 u32 dma_low
, dma_high
, result
, value
;
375 /* ensure buf is aligned to 8 bytes */
376 buf
= (struct mcp_cmd
*)ALIGN((unsigned long)buf_bytes
, 8);
378 buf
->data0
= htonl(data
->data0
);
379 buf
->data1
= htonl(data
->data1
);
380 buf
->data2
= htonl(data
->data2
);
381 buf
->cmd
= htonl(cmd
);
382 dma_low
= MYRI10GE_LOWPART_TO_U32(mgp
->cmd_bus
);
383 dma_high
= MYRI10GE_HIGHPART_TO_U32(mgp
->cmd_bus
);
385 buf
->response_addr
.low
= htonl(dma_low
);
386 buf
->response_addr
.high
= htonl(dma_high
);
387 response
->result
= htonl(MYRI10GE_NO_RESPONSE_RESULT
);
389 myri10ge_pio_copy(cmd_addr
, buf
, sizeof(*buf
));
391 /* wait up to 15ms. Longest command is the DMA benchmark,
392 * which is capped at 5ms, but runs from a timeout handler
393 * that runs every 7.8ms. So a 15ms timeout leaves us with
397 /* if atomic is set, do not sleep,
398 * and try to get the completion quickly
399 * (1ms will be enough for those commands) */
400 for (sleep_total
= 0;
402 && response
->result
== htonl(MYRI10GE_NO_RESPONSE_RESULT
);
408 /* use msleep for most command */
409 for (sleep_total
= 0;
411 && response
->result
== htonl(MYRI10GE_NO_RESPONSE_RESULT
);
416 result
= ntohl(response
->result
);
417 value
= ntohl(response
->data
);
418 if (result
!= MYRI10GE_NO_RESPONSE_RESULT
) {
422 } else if (result
== MXGEFW_CMD_UNKNOWN
) {
424 } else if (result
== MXGEFW_CMD_ERROR_UNALIGNED
) {
426 } else if (result
== MXGEFW_CMD_ERROR_RANGE
&&
427 cmd
== MXGEFW_CMD_ENABLE_RSS_QUEUES
&&
429 data1
& MXGEFW_SLICE_ENABLE_MULTIPLE_TX_QUEUES
) !=
433 dev_err(&mgp
->pdev
->dev
,
434 "command %d failed, result = %d\n",
440 dev_err(&mgp
->pdev
->dev
, "command %d timed out, result = %d\n",
446 * The eeprom strings on the lanaiX have the format
449 * PT:ddd mmm xx xx:xx:xx xx\0
450 * PV:ddd mmm xx xx:xx:xx xx\0
452 static int myri10ge_read_mac_addr(struct myri10ge_priv
*mgp
)
457 ptr
= mgp
->eeprom_strings
;
458 limit
= mgp
->eeprom_strings
+ MYRI10GE_EEPROM_STRINGS_SIZE
;
460 while (*ptr
!= '\0' && ptr
< limit
) {
461 if (memcmp(ptr
, "MAC=", 4) == 0) {
463 mgp
->mac_addr_string
= ptr
;
464 for (i
= 0; i
< 6; i
++) {
465 if ((ptr
+ 2) > limit
)
468 simple_strtoul(ptr
, &ptr
, 16);
472 if (memcmp(ptr
, "PC=", 3) == 0) {
474 mgp
->product_code_string
= ptr
;
476 if (memcmp((const void *)ptr
, "SN=", 3) == 0) {
478 mgp
->serial_number
= simple_strtoul(ptr
, &ptr
, 10);
480 while (ptr
< limit
&& *ptr
++) ;
486 dev_err(&mgp
->pdev
->dev
, "failed to parse eeprom_strings\n");
491 * Enable or disable periodic RDMAs from the host to make certain
492 * chipsets resend dropped PCIe messages
495 static void myri10ge_dummy_rdma(struct myri10ge_priv
*mgp
, int enable
)
497 char __iomem
*submit
;
498 __be32 buf
[16] __attribute__ ((__aligned__(8)));
499 u32 dma_low
, dma_high
;
502 /* clear confirmation addr */
506 /* send a rdma command to the PCIe engine, and wait for the
507 * response in the confirmation address. The firmware should
508 * write a -1 there to indicate it is alive and well
510 dma_low
= MYRI10GE_LOWPART_TO_U32(mgp
->cmd_bus
);
511 dma_high
= MYRI10GE_HIGHPART_TO_U32(mgp
->cmd_bus
);
513 buf
[0] = htonl(dma_high
); /* confirm addr MSW */
514 buf
[1] = htonl(dma_low
); /* confirm addr LSW */
515 buf
[2] = MYRI10GE_NO_CONFIRM_DATA
; /* confirm data */
516 buf
[3] = htonl(dma_high
); /* dummy addr MSW */
517 buf
[4] = htonl(dma_low
); /* dummy addr LSW */
518 buf
[5] = htonl(enable
); /* enable? */
520 submit
= mgp
->sram
+ MXGEFW_BOOT_DUMMY_RDMA
;
522 myri10ge_pio_copy(submit
, &buf
, sizeof(buf
));
523 for (i
= 0; mgp
->cmd
->data
!= MYRI10GE_NO_CONFIRM_DATA
&& i
< 20; i
++)
525 if (mgp
->cmd
->data
!= MYRI10GE_NO_CONFIRM_DATA
)
526 dev_err(&mgp
->pdev
->dev
, "dummy rdma %s failed\n",
527 (enable
? "enable" : "disable"));
531 myri10ge_validate_firmware(struct myri10ge_priv
*mgp
,
532 struct mcp_gen_header
*hdr
)
534 struct device
*dev
= &mgp
->pdev
->dev
;
536 /* check firmware type */
537 if (ntohl(hdr
->mcp_type
) != MCP_TYPE_ETH
) {
538 dev_err(dev
, "Bad firmware type: 0x%x\n", ntohl(hdr
->mcp_type
));
542 /* save firmware version for ethtool */
543 strncpy(mgp
->fw_version
, hdr
->version
, sizeof(mgp
->fw_version
));
545 sscanf(mgp
->fw_version
, "%d.%d.%d", &mgp
->fw_ver_major
,
546 &mgp
->fw_ver_minor
, &mgp
->fw_ver_tiny
);
548 if (!(mgp
->fw_ver_major
== MXGEFW_VERSION_MAJOR
549 && mgp
->fw_ver_minor
== MXGEFW_VERSION_MINOR
)) {
550 dev_err(dev
, "Found firmware version %s\n", mgp
->fw_version
);
551 dev_err(dev
, "Driver needs %d.%d\n", MXGEFW_VERSION_MAJOR
,
552 MXGEFW_VERSION_MINOR
);
558 static int myri10ge_load_hotplug_firmware(struct myri10ge_priv
*mgp
, u32
* size
)
560 unsigned crc
, reread_crc
;
561 const struct firmware
*fw
;
562 struct device
*dev
= &mgp
->pdev
->dev
;
563 unsigned char *fw_readback
;
564 struct mcp_gen_header
*hdr
;
569 if ((status
= request_firmware(&fw
, mgp
->fw_name
, dev
)) < 0) {
570 dev_err(dev
, "Unable to load %s firmware image via hotplug\n",
573 goto abort_with_nothing
;
578 if (fw
->size
>= mgp
->sram_size
- MYRI10GE_FW_OFFSET
||
579 fw
->size
< MCP_HEADER_PTR_OFFSET
+ 4) {
580 dev_err(dev
, "Firmware size invalid:%d\n", (int)fw
->size
);
586 hdr_offset
= ntohl(*(__be32
*) (fw
->data
+ MCP_HEADER_PTR_OFFSET
));
587 if ((hdr_offset
& 3) || hdr_offset
+ sizeof(*hdr
) > fw
->size
) {
588 dev_err(dev
, "Bad firmware file\n");
592 hdr
= (void *)(fw
->data
+ hdr_offset
);
594 status
= myri10ge_validate_firmware(mgp
, hdr
);
598 crc
= crc32(~0, fw
->data
, fw
->size
);
599 for (i
= 0; i
< fw
->size
; i
+= 256) {
600 myri10ge_pio_copy(mgp
->sram
+ MYRI10GE_FW_OFFSET
+ i
,
602 min(256U, (unsigned)(fw
->size
- i
)));
606 fw_readback
= vmalloc(fw
->size
);
611 /* corruption checking is good for parity recovery and buggy chipset */
612 memcpy_fromio(fw_readback
, mgp
->sram
+ MYRI10GE_FW_OFFSET
, fw
->size
);
613 reread_crc
= crc32(~0, fw_readback
, fw
->size
);
615 if (crc
!= reread_crc
) {
616 dev_err(dev
, "CRC failed(fw-len=%u), got 0x%x (expect 0x%x)\n",
617 (unsigned)fw
->size
, reread_crc
, crc
);
621 *size
= (u32
) fw
->size
;
624 release_firmware(fw
);
630 static int myri10ge_adopt_running_firmware(struct myri10ge_priv
*mgp
)
632 struct mcp_gen_header
*hdr
;
633 struct device
*dev
= &mgp
->pdev
->dev
;
634 const size_t bytes
= sizeof(struct mcp_gen_header
);
638 /* find running firmware header */
639 hdr_offset
= swab32(readl(mgp
->sram
+ MCP_HEADER_PTR_OFFSET
));
641 if ((hdr_offset
& 3) || hdr_offset
+ sizeof(*hdr
) > mgp
->sram_size
) {
642 dev_err(dev
, "Running firmware has bad header offset (%d)\n",
647 /* copy header of running firmware from SRAM to host memory to
648 * validate firmware */
649 hdr
= kmalloc(bytes
, GFP_KERNEL
);
651 dev_err(dev
, "could not malloc firmware hdr\n");
654 memcpy_fromio(hdr
, mgp
->sram
+ hdr_offset
, bytes
);
655 status
= myri10ge_validate_firmware(mgp
, hdr
);
658 /* check to see if adopted firmware has bug where adopting
659 * it will cause broadcasts to be filtered unless the NIC
660 * is kept in ALLMULTI mode */
661 if (mgp
->fw_ver_major
== 1 && mgp
->fw_ver_minor
== 4 &&
662 mgp
->fw_ver_tiny
>= 4 && mgp
->fw_ver_tiny
<= 11) {
663 mgp
->adopted_rx_filter_bug
= 1;
664 dev_warn(dev
, "Adopting fw %d.%d.%d: "
665 "working around rx filter bug\n",
666 mgp
->fw_ver_major
, mgp
->fw_ver_minor
,
672 static int myri10ge_get_firmware_capabilities(struct myri10ge_priv
*mgp
)
674 struct myri10ge_cmd cmd
;
677 /* probe for IPv6 TSO support */
678 mgp
->features
= NETIF_F_SG
| NETIF_F_HW_CSUM
| NETIF_F_TSO
;
679 status
= myri10ge_send_cmd(mgp
, MXGEFW_CMD_GET_MAX_TSO6_HDR_SIZE
,
682 mgp
->max_tso6
= cmd
.data0
;
683 mgp
->features
|= NETIF_F_TSO6
;
686 status
= myri10ge_send_cmd(mgp
, MXGEFW_CMD_GET_RX_RING_SIZE
, &cmd
, 0);
688 dev_err(&mgp
->pdev
->dev
,
689 "failed MXGEFW_CMD_GET_RX_RING_SIZE\n");
693 mgp
->max_intr_slots
= 2 * (cmd
.data0
/ sizeof(struct mcp_dma_addr
));
698 static int myri10ge_load_firmware(struct myri10ge_priv
*mgp
, int adopt
)
700 char __iomem
*submit
;
701 __be32 buf
[16] __attribute__ ((__aligned__(8)));
702 u32 dma_low
, dma_high
, size
;
706 status
= myri10ge_load_hotplug_firmware(mgp
, &size
);
710 dev_warn(&mgp
->pdev
->dev
, "hotplug firmware loading failed\n");
712 /* Do not attempt to adopt firmware if there
717 status
= myri10ge_adopt_running_firmware(mgp
);
719 dev_err(&mgp
->pdev
->dev
,
720 "failed to adopt running firmware\n");
723 dev_info(&mgp
->pdev
->dev
,
724 "Successfully adopted running firmware\n");
725 if (mgp
->tx_boundary
== 4096) {
726 dev_warn(&mgp
->pdev
->dev
,
727 "Using firmware currently running on NIC"
729 dev_warn(&mgp
->pdev
->dev
,
730 "performance consider loading optimized "
732 dev_warn(&mgp
->pdev
->dev
, "via hotplug\n");
735 mgp
->fw_name
= "adopted";
736 mgp
->tx_boundary
= 2048;
737 myri10ge_dummy_rdma(mgp
, 1);
738 status
= myri10ge_get_firmware_capabilities(mgp
);
742 /* clear confirmation addr */
746 /* send a reload command to the bootstrap MCP, and wait for the
747 * response in the confirmation address. The firmware should
748 * write a -1 there to indicate it is alive and well
750 dma_low
= MYRI10GE_LOWPART_TO_U32(mgp
->cmd_bus
);
751 dma_high
= MYRI10GE_HIGHPART_TO_U32(mgp
->cmd_bus
);
753 buf
[0] = htonl(dma_high
); /* confirm addr MSW */
754 buf
[1] = htonl(dma_low
); /* confirm addr LSW */
755 buf
[2] = MYRI10GE_NO_CONFIRM_DATA
; /* confirm data */
757 /* FIX: All newest firmware should un-protect the bottom of
758 * the sram before handoff. However, the very first interfaces
759 * do not. Therefore the handoff copy must skip the first 8 bytes
761 buf
[3] = htonl(MYRI10GE_FW_OFFSET
+ 8); /* where the code starts */
762 buf
[4] = htonl(size
- 8); /* length of code */
763 buf
[5] = htonl(8); /* where to copy to */
764 buf
[6] = htonl(0); /* where to jump to */
766 submit
= mgp
->sram
+ MXGEFW_BOOT_HANDOFF
;
768 myri10ge_pio_copy(submit
, &buf
, sizeof(buf
));
773 while (mgp
->cmd
->data
!= MYRI10GE_NO_CONFIRM_DATA
&& i
< 9) {
777 if (mgp
->cmd
->data
!= MYRI10GE_NO_CONFIRM_DATA
) {
778 dev_err(&mgp
->pdev
->dev
, "handoff failed\n");
781 myri10ge_dummy_rdma(mgp
, 1);
782 status
= myri10ge_get_firmware_capabilities(mgp
);
787 static int myri10ge_update_mac_address(struct myri10ge_priv
*mgp
, u8
* addr
)
789 struct myri10ge_cmd cmd
;
792 cmd
.data0
= ((addr
[0] << 24) | (addr
[1] << 16)
793 | (addr
[2] << 8) | addr
[3]);
795 cmd
.data1
= ((addr
[4] << 8) | (addr
[5]));
797 status
= myri10ge_send_cmd(mgp
, MXGEFW_SET_MAC_ADDRESS
, &cmd
, 0);
801 static int myri10ge_change_pause(struct myri10ge_priv
*mgp
, int pause
)
803 struct myri10ge_cmd cmd
;
806 ctl
= pause
? MXGEFW_ENABLE_FLOW_CONTROL
: MXGEFW_DISABLE_FLOW_CONTROL
;
807 status
= myri10ge_send_cmd(mgp
, ctl
, &cmd
, 0);
811 "myri10ge: %s: Failed to set flow control mode\n",
820 myri10ge_change_promisc(struct myri10ge_priv
*mgp
, int promisc
, int atomic
)
822 struct myri10ge_cmd cmd
;
825 ctl
= promisc
? MXGEFW_ENABLE_PROMISC
: MXGEFW_DISABLE_PROMISC
;
826 status
= myri10ge_send_cmd(mgp
, ctl
, &cmd
, atomic
);
828 printk(KERN_ERR
"myri10ge: %s: Failed to set promisc mode\n",
832 static int myri10ge_dma_test(struct myri10ge_priv
*mgp
, int test_type
)
834 struct myri10ge_cmd cmd
;
837 struct page
*dmatest_page
;
838 dma_addr_t dmatest_bus
;
841 dmatest_page
= alloc_page(GFP_KERNEL
);
844 dmatest_bus
= pci_map_page(mgp
->pdev
, dmatest_page
, 0, PAGE_SIZE
,
847 /* Run a small DMA test.
848 * The magic multipliers to the length tell the firmware
849 * to do DMA read, write, or read+write tests. The
850 * results are returned in cmd.data0. The upper 16
851 * bits or the return is the number of transfers completed.
852 * The lower 16 bits is the time in 0.5us ticks that the
853 * transfers took to complete.
856 len
= mgp
->tx_boundary
;
858 cmd
.data0
= MYRI10GE_LOWPART_TO_U32(dmatest_bus
);
859 cmd
.data1
= MYRI10GE_HIGHPART_TO_U32(dmatest_bus
);
860 cmd
.data2
= len
* 0x10000;
861 status
= myri10ge_send_cmd(mgp
, test_type
, &cmd
, 0);
866 mgp
->read_dma
= ((cmd
.data0
>> 16) * len
* 2) / (cmd
.data0
& 0xffff);
867 cmd
.data0
= MYRI10GE_LOWPART_TO_U32(dmatest_bus
);
868 cmd
.data1
= MYRI10GE_HIGHPART_TO_U32(dmatest_bus
);
869 cmd
.data2
= len
* 0x1;
870 status
= myri10ge_send_cmd(mgp
, test_type
, &cmd
, 0);
875 mgp
->write_dma
= ((cmd
.data0
>> 16) * len
* 2) / (cmd
.data0
& 0xffff);
877 cmd
.data0
= MYRI10GE_LOWPART_TO_U32(dmatest_bus
);
878 cmd
.data1
= MYRI10GE_HIGHPART_TO_U32(dmatest_bus
);
879 cmd
.data2
= len
* 0x10001;
880 status
= myri10ge_send_cmd(mgp
, test_type
, &cmd
, 0);
885 mgp
->read_write_dma
= ((cmd
.data0
>> 16) * len
* 2 * 2) /
886 (cmd
.data0
& 0xffff);
889 pci_unmap_page(mgp
->pdev
, dmatest_bus
, PAGE_SIZE
, DMA_BIDIRECTIONAL
);
890 put_page(dmatest_page
);
892 if (status
!= 0 && test_type
!= MXGEFW_CMD_UNALIGNED_TEST
)
893 dev_warn(&mgp
->pdev
->dev
, "DMA %s benchmark failed: %d\n",
899 static int myri10ge_reset(struct myri10ge_priv
*mgp
)
901 struct myri10ge_cmd cmd
;
902 struct myri10ge_slice_state
*ss
;
905 #ifdef CONFIG_MYRI10GE_DCA
906 unsigned long dca_tag_off
;
909 /* try to send a reset command to the card to see if it
911 memset(&cmd
, 0, sizeof(cmd
));
912 status
= myri10ge_send_cmd(mgp
, MXGEFW_CMD_RESET
, &cmd
, 0);
914 dev_err(&mgp
->pdev
->dev
, "failed reset\n");
918 (void)myri10ge_dma_test(mgp
, MXGEFW_DMA_TEST
);
920 * Use non-ndis mcp_slot (eg, 4 bytes total,
921 * no toeplitz hash value returned. Older firmware will
922 * not understand this command, but will use the correct
923 * sized mcp_slot, so we ignore error returns
925 cmd
.data0
= MXGEFW_RSS_MCP_SLOT_TYPE_MIN
;
926 (void)myri10ge_send_cmd(mgp
, MXGEFW_CMD_SET_RSS_MCP_SLOT_TYPE
, &cmd
, 0);
928 /* Now exchange information about interrupts */
930 bytes
= mgp
->max_intr_slots
* sizeof(*mgp
->ss
[0].rx_done
.entry
);
931 cmd
.data0
= (u32
) bytes
;
932 status
= myri10ge_send_cmd(mgp
, MXGEFW_CMD_SET_INTRQ_SIZE
, &cmd
, 0);
935 * Even though we already know how many slices are supported
936 * via myri10ge_probe_slices() MXGEFW_CMD_GET_MAX_RSS_QUEUES
937 * has magic side effects, and must be called after a reset.
938 * It must be called prior to calling any RSS related cmds,
939 * including assigning an interrupt queue for anything but
940 * slice 0. It must also be called *after*
941 * MXGEFW_CMD_SET_INTRQ_SIZE, since the intrq size is used by
942 * the firmware to compute offsets.
945 if (mgp
->num_slices
> 1) {
947 /* ask the maximum number of slices it supports */
948 status
= myri10ge_send_cmd(mgp
, MXGEFW_CMD_GET_MAX_RSS_QUEUES
,
951 dev_err(&mgp
->pdev
->dev
,
952 "failed to get number of slices\n");
956 * MXGEFW_CMD_ENABLE_RSS_QUEUES must be called prior
957 * to setting up the interrupt queue DMA
960 cmd
.data0
= mgp
->num_slices
;
961 cmd
.data1
= MXGEFW_SLICE_INTR_MODE_ONE_PER_SLICE
;
962 if (mgp
->dev
->real_num_tx_queues
> 1)
963 cmd
.data1
|= MXGEFW_SLICE_ENABLE_MULTIPLE_TX_QUEUES
;
964 status
= myri10ge_send_cmd(mgp
, MXGEFW_CMD_ENABLE_RSS_QUEUES
,
967 /* Firmware older than 1.4.32 only supports multiple
968 * RX queues, so if we get an error, first retry using a
969 * single TX queue before giving up */
970 if (status
!= 0 && mgp
->dev
->real_num_tx_queues
> 1) {
971 mgp
->dev
->real_num_tx_queues
= 1;
972 cmd
.data0
= mgp
->num_slices
;
973 cmd
.data1
= MXGEFW_SLICE_INTR_MODE_ONE_PER_SLICE
;
974 status
= myri10ge_send_cmd(mgp
,
975 MXGEFW_CMD_ENABLE_RSS_QUEUES
,
980 dev_err(&mgp
->pdev
->dev
,
981 "failed to set number of slices\n");
986 for (i
= 0; i
< mgp
->num_slices
; i
++) {
988 cmd
.data0
= MYRI10GE_LOWPART_TO_U32(ss
->rx_done
.bus
);
989 cmd
.data1
= MYRI10GE_HIGHPART_TO_U32(ss
->rx_done
.bus
);
991 status
|= myri10ge_send_cmd(mgp
, MXGEFW_CMD_SET_INTRQ_DMA
,
996 myri10ge_send_cmd(mgp
, MXGEFW_CMD_GET_IRQ_ACK_OFFSET
, &cmd
, 0);
997 for (i
= 0; i
< mgp
->num_slices
; i
++) {
1000 (__iomem __be32
*) (mgp
->sram
+ cmd
.data0
+ 8 * i
);
1002 status
|= myri10ge_send_cmd(mgp
, MXGEFW_CMD_GET_IRQ_DEASSERT_OFFSET
,
1004 mgp
->irq_deassert
= (__iomem __be32
*) (mgp
->sram
+ cmd
.data0
);
1006 status
|= myri10ge_send_cmd
1007 (mgp
, MXGEFW_CMD_GET_INTR_COAL_DELAY_OFFSET
, &cmd
, 0);
1008 mgp
->intr_coal_delay_ptr
= (__iomem __be32
*) (mgp
->sram
+ cmd
.data0
);
1010 dev_err(&mgp
->pdev
->dev
, "failed set interrupt parameters\n");
1013 put_be32(htonl(mgp
->intr_coal_delay
), mgp
->intr_coal_delay_ptr
);
1015 #ifdef CONFIG_MYRI10GE_DCA
1016 status
= myri10ge_send_cmd(mgp
, MXGEFW_CMD_GET_DCA_OFFSET
, &cmd
, 0);
1017 dca_tag_off
= cmd
.data0
;
1018 for (i
= 0; i
< mgp
->num_slices
; i
++) {
1021 ss
->dca_tag
= (__iomem __be32
*)
1022 (mgp
->sram
+ dca_tag_off
+ 4 * i
);
1027 #endif /* CONFIG_MYRI10GE_DCA */
1029 /* reset mcp/driver shared state back to 0 */
1031 mgp
->link_changes
= 0;
1032 for (i
= 0; i
< mgp
->num_slices
; i
++) {
1035 memset(ss
->rx_done
.entry
, 0, bytes
);
1038 ss
->tx
.pkt_start
= 0;
1039 ss
->tx
.pkt_done
= 0;
1041 ss
->rx_small
.cnt
= 0;
1042 ss
->rx_done
.idx
= 0;
1043 ss
->rx_done
.cnt
= 0;
1044 ss
->tx
.wake_queue
= 0;
1045 ss
->tx
.stop_queue
= 0;
1048 status
= myri10ge_update_mac_address(mgp
, mgp
->dev
->dev_addr
);
1049 myri10ge_change_pause(mgp
, mgp
->pause
);
1050 myri10ge_set_multicast_list(mgp
->dev
);
1054 #ifdef CONFIG_MYRI10GE_DCA
1056 myri10ge_write_dca(struct myri10ge_slice_state
*ss
, int cpu
, int tag
)
1059 ss
->cached_dca_tag
= tag
;
1060 put_be32(htonl(tag
), ss
->dca_tag
);
1063 static inline void myri10ge_update_dca(struct myri10ge_slice_state
*ss
)
1065 int cpu
= get_cpu();
1068 if (cpu
!= ss
->cpu
) {
1069 tag
= dca_get_tag(cpu
);
1070 if (ss
->cached_dca_tag
!= tag
)
1071 myri10ge_write_dca(ss
, cpu
, tag
);
1076 static void myri10ge_setup_dca(struct myri10ge_priv
*mgp
)
1079 struct pci_dev
*pdev
= mgp
->pdev
;
1081 if (mgp
->ss
[0].dca_tag
== NULL
|| mgp
->dca_enabled
)
1083 if (!myri10ge_dca
) {
1084 dev_err(&pdev
->dev
, "dca disabled by administrator\n");
1087 err
= dca_add_requester(&pdev
->dev
);
1091 "dca_add_requester() failed, err=%d\n", err
);
1094 mgp
->dca_enabled
= 1;
1095 for (i
= 0; i
< mgp
->num_slices
; i
++)
1096 myri10ge_write_dca(&mgp
->ss
[i
], -1, 0);
1099 static void myri10ge_teardown_dca(struct myri10ge_priv
*mgp
)
1101 struct pci_dev
*pdev
= mgp
->pdev
;
1104 if (!mgp
->dca_enabled
)
1106 mgp
->dca_enabled
= 0;
1107 err
= dca_remove_requester(&pdev
->dev
);
1110 static int myri10ge_notify_dca_device(struct device
*dev
, void *data
)
1112 struct myri10ge_priv
*mgp
;
1113 unsigned long event
;
1115 mgp
= dev_get_drvdata(dev
);
1116 event
= *(unsigned long *)data
;
1118 if (event
== DCA_PROVIDER_ADD
)
1119 myri10ge_setup_dca(mgp
);
1120 else if (event
== DCA_PROVIDER_REMOVE
)
1121 myri10ge_teardown_dca(mgp
);
1124 #endif /* CONFIG_MYRI10GE_DCA */
1127 myri10ge_submit_8rx(struct mcp_kreq_ether_recv __iomem
* dst
,
1128 struct mcp_kreq_ether_recv
*src
)
1132 low
= src
->addr_low
;
1133 src
->addr_low
= htonl(DMA_BIT_MASK(32));
1134 myri10ge_pio_copy(dst
, src
, 4 * sizeof(*src
));
1136 myri10ge_pio_copy(dst
+ 4, src
+ 4, 4 * sizeof(*src
));
1138 src
->addr_low
= low
;
1139 put_be32(low
, &dst
->addr_low
);
1143 static inline void myri10ge_vlan_ip_csum(struct sk_buff
*skb
, __wsum hw_csum
)
1145 struct vlan_hdr
*vh
= (struct vlan_hdr
*)(skb
->data
);
1147 if ((skb
->protocol
== htons(ETH_P_8021Q
)) &&
1148 (vh
->h_vlan_encapsulated_proto
== htons(ETH_P_IP
) ||
1149 vh
->h_vlan_encapsulated_proto
== htons(ETH_P_IPV6
))) {
1150 skb
->csum
= hw_csum
;
1151 skb
->ip_summed
= CHECKSUM_COMPLETE
;
1156 myri10ge_rx_skb_build(struct sk_buff
*skb
, u8
* va
,
1157 struct skb_frag_struct
*rx_frags
, int len
, int hlen
)
1159 struct skb_frag_struct
*skb_frags
;
1161 skb
->len
= skb
->data_len
= len
;
1162 skb
->truesize
= len
+ sizeof(struct sk_buff
);
1163 /* attach the page(s) */
1165 skb_frags
= skb_shinfo(skb
)->frags
;
1167 memcpy(skb_frags
, rx_frags
, sizeof(*skb_frags
));
1168 len
-= rx_frags
->size
;
1171 skb_shinfo(skb
)->nr_frags
++;
1174 /* pskb_may_pull is not available in irq context, but
1175 * skb_pull() (for ether_pad and eth_type_trans()) requires
1176 * the beginning of the packet in skb_headlen(), move it
1178 skb_copy_to_linear_data(skb
, va
, hlen
);
1179 skb_shinfo(skb
)->frags
[0].page_offset
+= hlen
;
1180 skb_shinfo(skb
)->frags
[0].size
-= hlen
;
1181 skb
->data_len
-= hlen
;
1183 skb_pull(skb
, MXGEFW_PAD
);
1187 myri10ge_alloc_rx_pages(struct myri10ge_priv
*mgp
, struct myri10ge_rx_buf
*rx
,
1188 int bytes
, int watchdog
)
1193 if (unlikely(rx
->watchdog_needed
&& !watchdog
))
1196 /* try to refill entire ring */
1197 while (rx
->fill_cnt
!= (rx
->cnt
+ rx
->mask
+ 1)) {
1198 idx
= rx
->fill_cnt
& rx
->mask
;
1199 if (rx
->page_offset
+ bytes
<= MYRI10GE_ALLOC_SIZE
) {
1200 /* we can use part of previous page */
1203 /* we need a new page */
1205 alloc_pages(GFP_ATOMIC
| __GFP_COMP
,
1206 MYRI10GE_ALLOC_ORDER
);
1207 if (unlikely(page
== NULL
)) {
1208 if (rx
->fill_cnt
- rx
->cnt
< 16)
1209 rx
->watchdog_needed
= 1;
1213 rx
->page_offset
= 0;
1214 rx
->bus
= pci_map_page(mgp
->pdev
, page
, 0,
1215 MYRI10GE_ALLOC_SIZE
,
1216 PCI_DMA_FROMDEVICE
);
1218 rx
->info
[idx
].page
= rx
->page
;
1219 rx
->info
[idx
].page_offset
= rx
->page_offset
;
1220 /* note that this is the address of the start of the
1222 pci_unmap_addr_set(&rx
->info
[idx
], bus
, rx
->bus
);
1223 rx
->shadow
[idx
].addr_low
=
1224 htonl(MYRI10GE_LOWPART_TO_U32(rx
->bus
) + rx
->page_offset
);
1225 rx
->shadow
[idx
].addr_high
=
1226 htonl(MYRI10GE_HIGHPART_TO_U32(rx
->bus
));
1228 /* start next packet on a cacheline boundary */
1229 rx
->page_offset
+= SKB_DATA_ALIGN(bytes
);
1231 #if MYRI10GE_ALLOC_SIZE > 4096
1232 /* don't cross a 4KB boundary */
1233 if ((rx
->page_offset
>> 12) !=
1234 ((rx
->page_offset
+ bytes
- 1) >> 12))
1235 rx
->page_offset
= (rx
->page_offset
+ 4096) & ~4095;
1239 /* copy 8 descriptors to the firmware at a time */
1240 if ((idx
& 7) == 7) {
1241 myri10ge_submit_8rx(&rx
->lanai
[idx
- 7],
1242 &rx
->shadow
[idx
- 7]);
1248 myri10ge_unmap_rx_page(struct pci_dev
*pdev
,
1249 struct myri10ge_rx_buffer_state
*info
, int bytes
)
1251 /* unmap the recvd page if we're the only or last user of it */
1252 if (bytes
>= MYRI10GE_ALLOC_SIZE
/ 2 ||
1253 (info
->page_offset
+ 2 * bytes
) > MYRI10GE_ALLOC_SIZE
) {
1254 pci_unmap_page(pdev
, (pci_unmap_addr(info
, bus
)
1255 & ~(MYRI10GE_ALLOC_SIZE
- 1)),
1256 MYRI10GE_ALLOC_SIZE
, PCI_DMA_FROMDEVICE
);
1260 #define MYRI10GE_HLEN 64 /* The number of bytes to copy from a
1261 * page into an skb */
1264 myri10ge_rx_done(struct myri10ge_slice_state
*ss
, struct myri10ge_rx_buf
*rx
,
1265 int bytes
, int len
, __wsum csum
)
1267 struct myri10ge_priv
*mgp
= ss
->mgp
;
1268 struct sk_buff
*skb
;
1269 struct skb_frag_struct rx_frags
[MYRI10GE_MAX_FRAGS_PER_FRAME
];
1270 int i
, idx
, hlen
, remainder
;
1271 struct pci_dev
*pdev
= mgp
->pdev
;
1272 struct net_device
*dev
= mgp
->dev
;
1276 idx
= rx
->cnt
& rx
->mask
;
1277 va
= page_address(rx
->info
[idx
].page
) + rx
->info
[idx
].page_offset
;
1279 /* Fill skb_frag_struct(s) with data from our receive */
1280 for (i
= 0, remainder
= len
; remainder
> 0; i
++) {
1281 myri10ge_unmap_rx_page(pdev
, &rx
->info
[idx
], bytes
);
1282 rx_frags
[i
].page
= rx
->info
[idx
].page
;
1283 rx_frags
[i
].page_offset
= rx
->info
[idx
].page_offset
;
1284 if (remainder
< MYRI10GE_ALLOC_SIZE
)
1285 rx_frags
[i
].size
= remainder
;
1287 rx_frags
[i
].size
= MYRI10GE_ALLOC_SIZE
;
1289 idx
= rx
->cnt
& rx
->mask
;
1290 remainder
-= MYRI10GE_ALLOC_SIZE
;
1293 if (mgp
->csum_flag
&& myri10ge_lro
) {
1294 rx_frags
[0].page_offset
+= MXGEFW_PAD
;
1295 rx_frags
[0].size
-= MXGEFW_PAD
;
1297 lro_receive_frags(&ss
->rx_done
.lro_mgr
, rx_frags
,
1298 /* opaque, will come back in get_frag_header */
1300 (void *)(__force
unsigned long)csum
, csum
);
1305 hlen
= MYRI10GE_HLEN
> len
? len
: MYRI10GE_HLEN
;
1307 /* allocate an skb to attach the page(s) to. This is done
1308 * after trying LRO, so as to avoid skb allocation overheads */
1310 skb
= netdev_alloc_skb(dev
, MYRI10GE_HLEN
+ 16);
1311 if (unlikely(skb
== NULL
)) {
1312 ss
->stats
.rx_dropped
++;
1315 put_page(rx_frags
[i
].page
);
1320 /* Attach the pages to the skb, and trim off any padding */
1321 myri10ge_rx_skb_build(skb
, va
, rx_frags
, len
, hlen
);
1322 if (skb_shinfo(skb
)->frags
[0].size
<= 0) {
1323 put_page(skb_shinfo(skb
)->frags
[0].page
);
1324 skb_shinfo(skb
)->nr_frags
= 0;
1326 skb
->protocol
= eth_type_trans(skb
, dev
);
1327 skb_record_rx_queue(skb
, ss
- &mgp
->ss
[0]);
1329 if (mgp
->csum_flag
) {
1330 if ((skb
->protocol
== htons(ETH_P_IP
)) ||
1331 (skb
->protocol
== htons(ETH_P_IPV6
))) {
1333 skb
->ip_summed
= CHECKSUM_COMPLETE
;
1335 myri10ge_vlan_ip_csum(skb
, csum
);
1337 netif_receive_skb(skb
);
1342 myri10ge_tx_done(struct myri10ge_slice_state
*ss
, int mcp_index
)
1344 struct pci_dev
*pdev
= ss
->mgp
->pdev
;
1345 struct myri10ge_tx_buf
*tx
= &ss
->tx
;
1346 struct netdev_queue
*dev_queue
;
1347 struct sk_buff
*skb
;
1350 while (tx
->pkt_done
!= mcp_index
) {
1351 idx
= tx
->done
& tx
->mask
;
1352 skb
= tx
->info
[idx
].skb
;
1355 tx
->info
[idx
].skb
= NULL
;
1356 if (tx
->info
[idx
].last
) {
1358 tx
->info
[idx
].last
= 0;
1361 len
= pci_unmap_len(&tx
->info
[idx
], len
);
1362 pci_unmap_len_set(&tx
->info
[idx
], len
, 0);
1364 ss
->stats
.tx_bytes
+= skb
->len
;
1365 ss
->stats
.tx_packets
++;
1366 dev_kfree_skb_irq(skb
);
1368 pci_unmap_single(pdev
,
1369 pci_unmap_addr(&tx
->info
[idx
],
1374 pci_unmap_page(pdev
,
1375 pci_unmap_addr(&tx
->info
[idx
],
1381 dev_queue
= netdev_get_tx_queue(ss
->dev
, ss
- ss
->mgp
->ss
);
1383 * Make a minimal effort to prevent the NIC from polling an
1384 * idle tx queue. If we can't get the lock we leave the queue
1385 * active. In this case, either a thread was about to start
1386 * using the queue anyway, or we lost a race and the NIC will
1387 * waste some of its resources polling an inactive queue for a
1391 if ((ss
->mgp
->dev
->real_num_tx_queues
> 1) &&
1392 __netif_tx_trylock(dev_queue
)) {
1393 if (tx
->req
== tx
->done
) {
1394 tx
->queue_active
= 0;
1395 put_be32(htonl(1), tx
->send_stop
);
1399 __netif_tx_unlock(dev_queue
);
1402 /* start the queue if we've stopped it */
1403 if (netif_tx_queue_stopped(dev_queue
)
1404 && tx
->req
- tx
->done
< (tx
->mask
>> 1)) {
1406 netif_tx_wake_queue(dev_queue
);
1411 myri10ge_clean_rx_done(struct myri10ge_slice_state
*ss
, int budget
)
1413 struct myri10ge_rx_done
*rx_done
= &ss
->rx_done
;
1414 struct myri10ge_priv
*mgp
= ss
->mgp
;
1415 unsigned long rx_bytes
= 0;
1416 unsigned long rx_packets
= 0;
1417 unsigned long rx_ok
;
1419 int idx
= rx_done
->idx
;
1420 int cnt
= rx_done
->cnt
;
1425 while (rx_done
->entry
[idx
].length
!= 0 && work_done
< budget
) {
1426 length
= ntohs(rx_done
->entry
[idx
].length
);
1427 rx_done
->entry
[idx
].length
= 0;
1428 checksum
= csum_unfold(rx_done
->entry
[idx
].checksum
);
1429 if (length
<= mgp
->small_bytes
)
1430 rx_ok
= myri10ge_rx_done(ss
, &ss
->rx_small
,
1434 rx_ok
= myri10ge_rx_done(ss
, &ss
->rx_big
,
1437 rx_packets
+= rx_ok
;
1438 rx_bytes
+= rx_ok
* (unsigned long)length
;
1440 idx
= cnt
& (mgp
->max_intr_slots
- 1);
1445 ss
->stats
.rx_packets
+= rx_packets
;
1446 ss
->stats
.rx_bytes
+= rx_bytes
;
1449 lro_flush_all(&rx_done
->lro_mgr
);
1451 /* restock receive rings if needed */
1452 if (ss
->rx_small
.fill_cnt
- ss
->rx_small
.cnt
< myri10ge_fill_thresh
)
1453 myri10ge_alloc_rx_pages(mgp
, &ss
->rx_small
,
1454 mgp
->small_bytes
+ MXGEFW_PAD
, 0);
1455 if (ss
->rx_big
.fill_cnt
- ss
->rx_big
.cnt
< myri10ge_fill_thresh
)
1456 myri10ge_alloc_rx_pages(mgp
, &ss
->rx_big
, mgp
->big_bytes
, 0);
1461 static inline void myri10ge_check_statblock(struct myri10ge_priv
*mgp
)
1463 struct mcp_irq_data
*stats
= mgp
->ss
[0].fw_stats
;
1465 if (unlikely(stats
->stats_updated
)) {
1466 unsigned link_up
= ntohl(stats
->link_up
);
1467 if (mgp
->link_state
!= link_up
) {
1468 mgp
->link_state
= link_up
;
1470 if (mgp
->link_state
== MXGEFW_LINK_UP
) {
1471 if (netif_msg_link(mgp
))
1473 "myri10ge: %s: link up\n",
1475 netif_carrier_on(mgp
->dev
);
1476 mgp
->link_changes
++;
1478 if (netif_msg_link(mgp
))
1480 "myri10ge: %s: link %s\n",
1482 (link_up
== MXGEFW_LINK_MYRINET
?
1483 "mismatch (Myrinet detected)" :
1485 netif_carrier_off(mgp
->dev
);
1486 mgp
->link_changes
++;
1489 if (mgp
->rdma_tags_available
!=
1490 ntohl(stats
->rdma_tags_available
)) {
1491 mgp
->rdma_tags_available
=
1492 ntohl(stats
->rdma_tags_available
);
1493 printk(KERN_WARNING
"myri10ge: %s: RDMA timed out! "
1494 "%d tags left\n", mgp
->dev
->name
,
1495 mgp
->rdma_tags_available
);
1497 mgp
->down_cnt
+= stats
->link_down
;
1498 if (stats
->link_down
)
1499 wake_up(&mgp
->down_wq
);
1503 static int myri10ge_poll(struct napi_struct
*napi
, int budget
)
1505 struct myri10ge_slice_state
*ss
=
1506 container_of(napi
, struct myri10ge_slice_state
, napi
);
1509 #ifdef CONFIG_MYRI10GE_DCA
1510 if (ss
->mgp
->dca_enabled
)
1511 myri10ge_update_dca(ss
);
1514 /* process as many rx events as NAPI will allow */
1515 work_done
= myri10ge_clean_rx_done(ss
, budget
);
1517 if (work_done
< budget
) {
1518 napi_complete(napi
);
1519 put_be32(htonl(3), ss
->irq_claim
);
1524 static irqreturn_t
myri10ge_intr(int irq
, void *arg
)
1526 struct myri10ge_slice_state
*ss
= arg
;
1527 struct myri10ge_priv
*mgp
= ss
->mgp
;
1528 struct mcp_irq_data
*stats
= ss
->fw_stats
;
1529 struct myri10ge_tx_buf
*tx
= &ss
->tx
;
1530 u32 send_done_count
;
1533 /* an interrupt on a non-zero receive-only slice is implicitly
1534 * valid since MSI-X irqs are not shared */
1535 if ((mgp
->dev
->real_num_tx_queues
== 1) && (ss
!= mgp
->ss
)) {
1536 napi_schedule(&ss
->napi
);
1537 return (IRQ_HANDLED
);
1540 /* make sure it is our IRQ, and that the DMA has finished */
1541 if (unlikely(!stats
->valid
))
1544 /* low bit indicates receives are present, so schedule
1545 * napi poll handler */
1546 if (stats
->valid
& 1)
1547 napi_schedule(&ss
->napi
);
1549 if (!mgp
->msi_enabled
&& !mgp
->msix_enabled
) {
1550 put_be32(0, mgp
->irq_deassert
);
1551 if (!myri10ge_deassert_wait
)
1557 /* Wait for IRQ line to go low, if using INTx */
1561 /* check for transmit completes and receives */
1562 send_done_count
= ntohl(stats
->send_done_count
);
1563 if (send_done_count
!= tx
->pkt_done
)
1564 myri10ge_tx_done(ss
, (int)send_done_count
);
1565 if (unlikely(i
> myri10ge_max_irq_loops
)) {
1566 printk(KERN_WARNING
"myri10ge: %s: irq stuck?\n",
1569 schedule_work(&mgp
->watchdog_work
);
1571 if (likely(stats
->valid
== 0))
1577 /* Only slice 0 updates stats */
1579 myri10ge_check_statblock(mgp
);
1581 put_be32(htonl(3), ss
->irq_claim
+ 1);
1582 return (IRQ_HANDLED
);
1586 myri10ge_get_settings(struct net_device
*netdev
, struct ethtool_cmd
*cmd
)
1588 struct myri10ge_priv
*mgp
= netdev_priv(netdev
);
1592 cmd
->autoneg
= AUTONEG_DISABLE
;
1593 cmd
->speed
= SPEED_10000
;
1594 cmd
->duplex
= DUPLEX_FULL
;
1597 * parse the product code to deterimine the interface type
1598 * (CX4, XFP, Quad Ribbon Fiber) by looking at the character
1599 * after the 3rd dash in the driver's cached copy of the
1600 * EEPROM's product code string.
1602 ptr
= mgp
->product_code_string
;
1604 printk(KERN_ERR
"myri10ge: %s: Missing product code\n",
1608 for (i
= 0; i
< 3; i
++, ptr
++) {
1609 ptr
= strchr(ptr
, '-');
1611 printk(KERN_ERR
"myri10ge: %s: Invalid product "
1612 "code %s\n", netdev
->name
,
1613 mgp
->product_code_string
);
1617 if (*ptr
== 'R' || *ptr
== 'Q') {
1618 /* We've found either an XFP or quad ribbon fiber */
1619 cmd
->port
= PORT_FIBRE
;
1625 myri10ge_get_drvinfo(struct net_device
*netdev
, struct ethtool_drvinfo
*info
)
1627 struct myri10ge_priv
*mgp
= netdev_priv(netdev
);
1629 strlcpy(info
->driver
, "myri10ge", sizeof(info
->driver
));
1630 strlcpy(info
->version
, MYRI10GE_VERSION_STR
, sizeof(info
->version
));
1631 strlcpy(info
->fw_version
, mgp
->fw_version
, sizeof(info
->fw_version
));
1632 strlcpy(info
->bus_info
, pci_name(mgp
->pdev
), sizeof(info
->bus_info
));
1636 myri10ge_get_coalesce(struct net_device
*netdev
, struct ethtool_coalesce
*coal
)
1638 struct myri10ge_priv
*mgp
= netdev_priv(netdev
);
1640 coal
->rx_coalesce_usecs
= mgp
->intr_coal_delay
;
1645 myri10ge_set_coalesce(struct net_device
*netdev
, struct ethtool_coalesce
*coal
)
1647 struct myri10ge_priv
*mgp
= netdev_priv(netdev
);
1649 mgp
->intr_coal_delay
= coal
->rx_coalesce_usecs
;
1650 put_be32(htonl(mgp
->intr_coal_delay
), mgp
->intr_coal_delay_ptr
);
1655 myri10ge_get_pauseparam(struct net_device
*netdev
,
1656 struct ethtool_pauseparam
*pause
)
1658 struct myri10ge_priv
*mgp
= netdev_priv(netdev
);
1661 pause
->rx_pause
= mgp
->pause
;
1662 pause
->tx_pause
= mgp
->pause
;
1666 myri10ge_set_pauseparam(struct net_device
*netdev
,
1667 struct ethtool_pauseparam
*pause
)
1669 struct myri10ge_priv
*mgp
= netdev_priv(netdev
);
1671 if (pause
->tx_pause
!= mgp
->pause
)
1672 return myri10ge_change_pause(mgp
, pause
->tx_pause
);
1673 if (pause
->rx_pause
!= mgp
->pause
)
1674 return myri10ge_change_pause(mgp
, pause
->tx_pause
);
1675 if (pause
->autoneg
!= 0)
1681 myri10ge_get_ringparam(struct net_device
*netdev
,
1682 struct ethtool_ringparam
*ring
)
1684 struct myri10ge_priv
*mgp
= netdev_priv(netdev
);
1686 ring
->rx_mini_max_pending
= mgp
->ss
[0].rx_small
.mask
+ 1;
1687 ring
->rx_max_pending
= mgp
->ss
[0].rx_big
.mask
+ 1;
1688 ring
->rx_jumbo_max_pending
= 0;
1689 ring
->tx_max_pending
= mgp
->ss
[0].rx_small
.mask
+ 1;
1690 ring
->rx_mini_pending
= ring
->rx_mini_max_pending
;
1691 ring
->rx_pending
= ring
->rx_max_pending
;
1692 ring
->rx_jumbo_pending
= ring
->rx_jumbo_max_pending
;
1693 ring
->tx_pending
= ring
->tx_max_pending
;
1696 static u32
myri10ge_get_rx_csum(struct net_device
*netdev
)
1698 struct myri10ge_priv
*mgp
= netdev_priv(netdev
);
1706 static int myri10ge_set_rx_csum(struct net_device
*netdev
, u32 csum_enabled
)
1708 struct myri10ge_priv
*mgp
= netdev_priv(netdev
);
1711 mgp
->csum_flag
= MXGEFW_FLAGS_CKSUM
;
1717 static int myri10ge_set_tso(struct net_device
*netdev
, u32 tso_enabled
)
1719 struct myri10ge_priv
*mgp
= netdev_priv(netdev
);
1720 unsigned long flags
= mgp
->features
& (NETIF_F_TSO6
| NETIF_F_TSO
);
1723 netdev
->features
|= flags
;
1725 netdev
->features
&= ~flags
;
1729 static const char myri10ge_gstrings_main_stats
[][ETH_GSTRING_LEN
] = {
1730 "rx_packets", "tx_packets", "rx_bytes", "tx_bytes", "rx_errors",
1731 "tx_errors", "rx_dropped", "tx_dropped", "multicast", "collisions",
1732 "rx_length_errors", "rx_over_errors", "rx_crc_errors",
1733 "rx_frame_errors", "rx_fifo_errors", "rx_missed_errors",
1734 "tx_aborted_errors", "tx_carrier_errors", "tx_fifo_errors",
1735 "tx_heartbeat_errors", "tx_window_errors",
1736 /* device-specific stats */
1737 "tx_boundary", "WC", "irq", "MSI", "MSIX",
1738 "read_dma_bw_MBs", "write_dma_bw_MBs", "read_write_dma_bw_MBs",
1739 "serial_number", "watchdog_resets",
1740 #ifdef CONFIG_MYRI10GE_DCA
1741 "dca_capable_firmware", "dca_device_present",
1743 "link_changes", "link_up", "dropped_link_overflow",
1744 "dropped_link_error_or_filtered",
1745 "dropped_pause", "dropped_bad_phy", "dropped_bad_crc32",
1746 "dropped_unicast_filtered", "dropped_multicast_filtered",
1747 "dropped_runt", "dropped_overrun", "dropped_no_small_buffer",
1748 "dropped_no_big_buffer"
1751 static const char myri10ge_gstrings_slice_stats
[][ETH_GSTRING_LEN
] = {
1752 "----------- slice ---------",
1753 "tx_pkt_start", "tx_pkt_done", "tx_req", "tx_done",
1754 "rx_small_cnt", "rx_big_cnt",
1755 "wake_queue", "stop_queue", "tx_linearized", "LRO aggregated",
1757 "LRO avg aggr", "LRO no_desc"
1760 #define MYRI10GE_NET_STATS_LEN 21
1761 #define MYRI10GE_MAIN_STATS_LEN ARRAY_SIZE(myri10ge_gstrings_main_stats)
1762 #define MYRI10GE_SLICE_STATS_LEN ARRAY_SIZE(myri10ge_gstrings_slice_stats)
1765 myri10ge_get_strings(struct net_device
*netdev
, u32 stringset
, u8
* data
)
1767 struct myri10ge_priv
*mgp
= netdev_priv(netdev
);
1770 switch (stringset
) {
1772 memcpy(data
, *myri10ge_gstrings_main_stats
,
1773 sizeof(myri10ge_gstrings_main_stats
));
1774 data
+= sizeof(myri10ge_gstrings_main_stats
);
1775 for (i
= 0; i
< mgp
->num_slices
; i
++) {
1776 memcpy(data
, *myri10ge_gstrings_slice_stats
,
1777 sizeof(myri10ge_gstrings_slice_stats
));
1778 data
+= sizeof(myri10ge_gstrings_slice_stats
);
1784 static int myri10ge_get_sset_count(struct net_device
*netdev
, int sset
)
1786 struct myri10ge_priv
*mgp
= netdev_priv(netdev
);
1790 return MYRI10GE_MAIN_STATS_LEN
+
1791 mgp
->num_slices
* MYRI10GE_SLICE_STATS_LEN
;
1798 myri10ge_get_ethtool_stats(struct net_device
*netdev
,
1799 struct ethtool_stats
*stats
, u64
* data
)
1801 struct myri10ge_priv
*mgp
= netdev_priv(netdev
);
1802 struct myri10ge_slice_state
*ss
;
1806 for (i
= 0; i
< MYRI10GE_NET_STATS_LEN
; i
++)
1807 data
[i
] = ((unsigned long *)&mgp
->stats
)[i
];
1809 data
[i
++] = (unsigned int)mgp
->tx_boundary
;
1810 data
[i
++] = (unsigned int)mgp
->wc_enabled
;
1811 data
[i
++] = (unsigned int)mgp
->pdev
->irq
;
1812 data
[i
++] = (unsigned int)mgp
->msi_enabled
;
1813 data
[i
++] = (unsigned int)mgp
->msix_enabled
;
1814 data
[i
++] = (unsigned int)mgp
->read_dma
;
1815 data
[i
++] = (unsigned int)mgp
->write_dma
;
1816 data
[i
++] = (unsigned int)mgp
->read_write_dma
;
1817 data
[i
++] = (unsigned int)mgp
->serial_number
;
1818 data
[i
++] = (unsigned int)mgp
->watchdog_resets
;
1819 #ifdef CONFIG_MYRI10GE_DCA
1820 data
[i
++] = (unsigned int)(mgp
->ss
[0].dca_tag
!= NULL
);
1821 data
[i
++] = (unsigned int)(mgp
->dca_enabled
);
1823 data
[i
++] = (unsigned int)mgp
->link_changes
;
1825 /* firmware stats are useful only in the first slice */
1827 data
[i
++] = (unsigned int)ntohl(ss
->fw_stats
->link_up
);
1828 data
[i
++] = (unsigned int)ntohl(ss
->fw_stats
->dropped_link_overflow
);
1830 (unsigned int)ntohl(ss
->fw_stats
->dropped_link_error_or_filtered
);
1831 data
[i
++] = (unsigned int)ntohl(ss
->fw_stats
->dropped_pause
);
1832 data
[i
++] = (unsigned int)ntohl(ss
->fw_stats
->dropped_bad_phy
);
1833 data
[i
++] = (unsigned int)ntohl(ss
->fw_stats
->dropped_bad_crc32
);
1834 data
[i
++] = (unsigned int)ntohl(ss
->fw_stats
->dropped_unicast_filtered
);
1836 (unsigned int)ntohl(ss
->fw_stats
->dropped_multicast_filtered
);
1837 data
[i
++] = (unsigned int)ntohl(ss
->fw_stats
->dropped_runt
);
1838 data
[i
++] = (unsigned int)ntohl(ss
->fw_stats
->dropped_overrun
);
1839 data
[i
++] = (unsigned int)ntohl(ss
->fw_stats
->dropped_no_small_buffer
);
1840 data
[i
++] = (unsigned int)ntohl(ss
->fw_stats
->dropped_no_big_buffer
);
1842 for (slice
= 0; slice
< mgp
->num_slices
; slice
++) {
1843 ss
= &mgp
->ss
[slice
];
1845 data
[i
++] = (unsigned int)ss
->tx
.pkt_start
;
1846 data
[i
++] = (unsigned int)ss
->tx
.pkt_done
;
1847 data
[i
++] = (unsigned int)ss
->tx
.req
;
1848 data
[i
++] = (unsigned int)ss
->tx
.done
;
1849 data
[i
++] = (unsigned int)ss
->rx_small
.cnt
;
1850 data
[i
++] = (unsigned int)ss
->rx_big
.cnt
;
1851 data
[i
++] = (unsigned int)ss
->tx
.wake_queue
;
1852 data
[i
++] = (unsigned int)ss
->tx
.stop_queue
;
1853 data
[i
++] = (unsigned int)ss
->tx
.linearized
;
1854 data
[i
++] = ss
->rx_done
.lro_mgr
.stats
.aggregated
;
1855 data
[i
++] = ss
->rx_done
.lro_mgr
.stats
.flushed
;
1856 if (ss
->rx_done
.lro_mgr
.stats
.flushed
)
1857 data
[i
++] = ss
->rx_done
.lro_mgr
.stats
.aggregated
/
1858 ss
->rx_done
.lro_mgr
.stats
.flushed
;
1861 data
[i
++] = ss
->rx_done
.lro_mgr
.stats
.no_desc
;
1865 static void myri10ge_set_msglevel(struct net_device
*netdev
, u32 value
)
1867 struct myri10ge_priv
*mgp
= netdev_priv(netdev
);
1868 mgp
->msg_enable
= value
;
1871 static u32
myri10ge_get_msglevel(struct net_device
*netdev
)
1873 struct myri10ge_priv
*mgp
= netdev_priv(netdev
);
1874 return mgp
->msg_enable
;
1877 static const struct ethtool_ops myri10ge_ethtool_ops
= {
1878 .get_settings
= myri10ge_get_settings
,
1879 .get_drvinfo
= myri10ge_get_drvinfo
,
1880 .get_coalesce
= myri10ge_get_coalesce
,
1881 .set_coalesce
= myri10ge_set_coalesce
,
1882 .get_pauseparam
= myri10ge_get_pauseparam
,
1883 .set_pauseparam
= myri10ge_set_pauseparam
,
1884 .get_ringparam
= myri10ge_get_ringparam
,
1885 .get_rx_csum
= myri10ge_get_rx_csum
,
1886 .set_rx_csum
= myri10ge_set_rx_csum
,
1887 .set_tx_csum
= ethtool_op_set_tx_hw_csum
,
1888 .set_sg
= ethtool_op_set_sg
,
1889 .set_tso
= myri10ge_set_tso
,
1890 .get_link
= ethtool_op_get_link
,
1891 .get_strings
= myri10ge_get_strings
,
1892 .get_sset_count
= myri10ge_get_sset_count
,
1893 .get_ethtool_stats
= myri10ge_get_ethtool_stats
,
1894 .set_msglevel
= myri10ge_set_msglevel
,
1895 .get_msglevel
= myri10ge_get_msglevel
1898 static int myri10ge_allocate_rings(struct myri10ge_slice_state
*ss
)
1900 struct myri10ge_priv
*mgp
= ss
->mgp
;
1901 struct myri10ge_cmd cmd
;
1902 struct net_device
*dev
= mgp
->dev
;
1903 int tx_ring_size
, rx_ring_size
;
1904 int tx_ring_entries
, rx_ring_entries
;
1905 int i
, slice
, status
;
1908 /* get ring sizes */
1909 slice
= ss
- mgp
->ss
;
1911 status
= myri10ge_send_cmd(mgp
, MXGEFW_CMD_GET_SEND_RING_SIZE
, &cmd
, 0);
1912 tx_ring_size
= cmd
.data0
;
1914 status
|= myri10ge_send_cmd(mgp
, MXGEFW_CMD_GET_RX_RING_SIZE
, &cmd
, 0);
1917 rx_ring_size
= cmd
.data0
;
1919 tx_ring_entries
= tx_ring_size
/ sizeof(struct mcp_kreq_ether_send
);
1920 rx_ring_entries
= rx_ring_size
/ sizeof(struct mcp_dma_addr
);
1921 ss
->tx
.mask
= tx_ring_entries
- 1;
1922 ss
->rx_small
.mask
= ss
->rx_big
.mask
= rx_ring_entries
- 1;
1926 /* allocate the host shadow rings */
1928 bytes
= 8 + (MYRI10GE_MAX_SEND_DESC_TSO
+ 4)
1929 * sizeof(*ss
->tx
.req_list
);
1930 ss
->tx
.req_bytes
= kzalloc(bytes
, GFP_KERNEL
);
1931 if (ss
->tx
.req_bytes
== NULL
)
1932 goto abort_with_nothing
;
1934 /* ensure req_list entries are aligned to 8 bytes */
1935 ss
->tx
.req_list
= (struct mcp_kreq_ether_send
*)
1936 ALIGN((unsigned long)ss
->tx
.req_bytes
, 8);
1937 ss
->tx
.queue_active
= 0;
1939 bytes
= rx_ring_entries
* sizeof(*ss
->rx_small
.shadow
);
1940 ss
->rx_small
.shadow
= kzalloc(bytes
, GFP_KERNEL
);
1941 if (ss
->rx_small
.shadow
== NULL
)
1942 goto abort_with_tx_req_bytes
;
1944 bytes
= rx_ring_entries
* sizeof(*ss
->rx_big
.shadow
);
1945 ss
->rx_big
.shadow
= kzalloc(bytes
, GFP_KERNEL
);
1946 if (ss
->rx_big
.shadow
== NULL
)
1947 goto abort_with_rx_small_shadow
;
1949 /* allocate the host info rings */
1951 bytes
= tx_ring_entries
* sizeof(*ss
->tx
.info
);
1952 ss
->tx
.info
= kzalloc(bytes
, GFP_KERNEL
);
1953 if (ss
->tx
.info
== NULL
)
1954 goto abort_with_rx_big_shadow
;
1956 bytes
= rx_ring_entries
* sizeof(*ss
->rx_small
.info
);
1957 ss
->rx_small
.info
= kzalloc(bytes
, GFP_KERNEL
);
1958 if (ss
->rx_small
.info
== NULL
)
1959 goto abort_with_tx_info
;
1961 bytes
= rx_ring_entries
* sizeof(*ss
->rx_big
.info
);
1962 ss
->rx_big
.info
= kzalloc(bytes
, GFP_KERNEL
);
1963 if (ss
->rx_big
.info
== NULL
)
1964 goto abort_with_rx_small_info
;
1966 /* Fill the receive rings */
1968 ss
->rx_small
.cnt
= 0;
1969 ss
->rx_big
.fill_cnt
= 0;
1970 ss
->rx_small
.fill_cnt
= 0;
1971 ss
->rx_small
.page_offset
= MYRI10GE_ALLOC_SIZE
;
1972 ss
->rx_big
.page_offset
= MYRI10GE_ALLOC_SIZE
;
1973 ss
->rx_small
.watchdog_needed
= 0;
1974 ss
->rx_big
.watchdog_needed
= 0;
1975 myri10ge_alloc_rx_pages(mgp
, &ss
->rx_small
,
1976 mgp
->small_bytes
+ MXGEFW_PAD
, 0);
1978 if (ss
->rx_small
.fill_cnt
< ss
->rx_small
.mask
+ 1) {
1980 "myri10ge: %s:slice-%d: alloced only %d small bufs\n",
1981 dev
->name
, slice
, ss
->rx_small
.fill_cnt
);
1982 goto abort_with_rx_small_ring
;
1985 myri10ge_alloc_rx_pages(mgp
, &ss
->rx_big
, mgp
->big_bytes
, 0);
1986 if (ss
->rx_big
.fill_cnt
< ss
->rx_big
.mask
+ 1) {
1988 "myri10ge: %s:slice-%d: alloced only %d big bufs\n",
1989 dev
->name
, slice
, ss
->rx_big
.fill_cnt
);
1990 goto abort_with_rx_big_ring
;
1995 abort_with_rx_big_ring
:
1996 for (i
= ss
->rx_big
.cnt
; i
< ss
->rx_big
.fill_cnt
; i
++) {
1997 int idx
= i
& ss
->rx_big
.mask
;
1998 myri10ge_unmap_rx_page(mgp
->pdev
, &ss
->rx_big
.info
[idx
],
2000 put_page(ss
->rx_big
.info
[idx
].page
);
2003 abort_with_rx_small_ring
:
2004 for (i
= ss
->rx_small
.cnt
; i
< ss
->rx_small
.fill_cnt
; i
++) {
2005 int idx
= i
& ss
->rx_small
.mask
;
2006 myri10ge_unmap_rx_page(mgp
->pdev
, &ss
->rx_small
.info
[idx
],
2007 mgp
->small_bytes
+ MXGEFW_PAD
);
2008 put_page(ss
->rx_small
.info
[idx
].page
);
2011 kfree(ss
->rx_big
.info
);
2013 abort_with_rx_small_info
:
2014 kfree(ss
->rx_small
.info
);
2019 abort_with_rx_big_shadow
:
2020 kfree(ss
->rx_big
.shadow
);
2022 abort_with_rx_small_shadow
:
2023 kfree(ss
->rx_small
.shadow
);
2025 abort_with_tx_req_bytes
:
2026 kfree(ss
->tx
.req_bytes
);
2027 ss
->tx
.req_bytes
= NULL
;
2028 ss
->tx
.req_list
= NULL
;
2034 static void myri10ge_free_rings(struct myri10ge_slice_state
*ss
)
2036 struct myri10ge_priv
*mgp
= ss
->mgp
;
2037 struct sk_buff
*skb
;
2038 struct myri10ge_tx_buf
*tx
;
2041 /* If not allocated, skip it */
2042 if (ss
->tx
.req_list
== NULL
)
2045 for (i
= ss
->rx_big
.cnt
; i
< ss
->rx_big
.fill_cnt
; i
++) {
2046 idx
= i
& ss
->rx_big
.mask
;
2047 if (i
== ss
->rx_big
.fill_cnt
- 1)
2048 ss
->rx_big
.info
[idx
].page_offset
= MYRI10GE_ALLOC_SIZE
;
2049 myri10ge_unmap_rx_page(mgp
->pdev
, &ss
->rx_big
.info
[idx
],
2051 put_page(ss
->rx_big
.info
[idx
].page
);
2054 for (i
= ss
->rx_small
.cnt
; i
< ss
->rx_small
.fill_cnt
; i
++) {
2055 idx
= i
& ss
->rx_small
.mask
;
2056 if (i
== ss
->rx_small
.fill_cnt
- 1)
2057 ss
->rx_small
.info
[idx
].page_offset
=
2058 MYRI10GE_ALLOC_SIZE
;
2059 myri10ge_unmap_rx_page(mgp
->pdev
, &ss
->rx_small
.info
[idx
],
2060 mgp
->small_bytes
+ MXGEFW_PAD
);
2061 put_page(ss
->rx_small
.info
[idx
].page
);
2064 while (tx
->done
!= tx
->req
) {
2065 idx
= tx
->done
& tx
->mask
;
2066 skb
= tx
->info
[idx
].skb
;
2069 tx
->info
[idx
].skb
= NULL
;
2071 len
= pci_unmap_len(&tx
->info
[idx
], len
);
2072 pci_unmap_len_set(&tx
->info
[idx
], len
, 0);
2074 ss
->stats
.tx_dropped
++;
2075 dev_kfree_skb_any(skb
);
2077 pci_unmap_single(mgp
->pdev
,
2078 pci_unmap_addr(&tx
->info
[idx
],
2083 pci_unmap_page(mgp
->pdev
,
2084 pci_unmap_addr(&tx
->info
[idx
],
2089 kfree(ss
->rx_big
.info
);
2091 kfree(ss
->rx_small
.info
);
2095 kfree(ss
->rx_big
.shadow
);
2097 kfree(ss
->rx_small
.shadow
);
2099 kfree(ss
->tx
.req_bytes
);
2100 ss
->tx
.req_bytes
= NULL
;
2101 ss
->tx
.req_list
= NULL
;
2104 static int myri10ge_request_irq(struct myri10ge_priv
*mgp
)
2106 struct pci_dev
*pdev
= mgp
->pdev
;
2107 struct myri10ge_slice_state
*ss
;
2108 struct net_device
*netdev
= mgp
->dev
;
2112 mgp
->msi_enabled
= 0;
2113 mgp
->msix_enabled
= 0;
2116 if (mgp
->num_slices
> 1) {
2118 pci_enable_msix(pdev
, mgp
->msix_vectors
,
2121 mgp
->msix_enabled
= 1;
2124 "Error %d setting up MSI-X\n", status
);
2128 if (mgp
->msix_enabled
== 0) {
2129 status
= pci_enable_msi(pdev
);
2132 "Error %d setting up MSI; falling back to xPIC\n",
2135 mgp
->msi_enabled
= 1;
2139 if (mgp
->msix_enabled
) {
2140 for (i
= 0; i
< mgp
->num_slices
; i
++) {
2142 snprintf(ss
->irq_desc
, sizeof(ss
->irq_desc
),
2143 "%s:slice-%d", netdev
->name
, i
);
2144 status
= request_irq(mgp
->msix_vectors
[i
].vector
,
2145 myri10ge_intr
, 0, ss
->irq_desc
,
2149 "slice %d failed to allocate IRQ\n", i
);
2152 free_irq(mgp
->msix_vectors
[i
].vector
,
2156 pci_disable_msix(pdev
);
2161 status
= request_irq(pdev
->irq
, myri10ge_intr
, IRQF_SHARED
,
2162 mgp
->dev
->name
, &mgp
->ss
[0]);
2164 dev_err(&pdev
->dev
, "failed to allocate IRQ\n");
2165 if (mgp
->msi_enabled
)
2166 pci_disable_msi(pdev
);
2172 static void myri10ge_free_irq(struct myri10ge_priv
*mgp
)
2174 struct pci_dev
*pdev
= mgp
->pdev
;
2177 if (mgp
->msix_enabled
) {
2178 for (i
= 0; i
< mgp
->num_slices
; i
++)
2179 free_irq(mgp
->msix_vectors
[i
].vector
, &mgp
->ss
[i
]);
2181 free_irq(pdev
->irq
, &mgp
->ss
[0]);
2183 if (mgp
->msi_enabled
)
2184 pci_disable_msi(pdev
);
2185 if (mgp
->msix_enabled
)
2186 pci_disable_msix(pdev
);
2190 myri10ge_get_frag_header(struct skb_frag_struct
*frag
, void **mac_hdr
,
2191 void **ip_hdr
, void **tcpudp_hdr
,
2192 u64
* hdr_flags
, void *priv
)
2195 struct vlan_ethhdr
*veh
;
2197 u8
*va
= page_address(frag
->page
) + frag
->page_offset
;
2198 unsigned long ll_hlen
;
2199 /* passed opaque through lro_receive_frags() */
2200 __wsum csum
= (__force __wsum
) (unsigned long)priv
;
2202 /* find the mac header, aborting if not IPv4 */
2204 eh
= (struct ethhdr
*)va
;
2207 if (eh
->h_proto
!= htons(ETH_P_IP
)) {
2208 if (eh
->h_proto
== htons(ETH_P_8021Q
)) {
2209 veh
= (struct vlan_ethhdr
*)va
;
2210 if (veh
->h_vlan_encapsulated_proto
!= htons(ETH_P_IP
))
2213 ll_hlen
+= VLAN_HLEN
;
2216 * HW checksum starts ETH_HLEN bytes into
2217 * frame, so we must subtract off the VLAN
2218 * header's checksum before csum can be used
2220 csum
= csum_sub(csum
, csum_partial(va
+ ETH_HLEN
,
2226 *hdr_flags
= LRO_IPV4
;
2228 iph
= (struct iphdr
*)(va
+ ll_hlen
);
2230 if (iph
->protocol
!= IPPROTO_TCP
)
2232 if (iph
->frag_off
& htons(IP_MF
| IP_OFFSET
))
2234 *hdr_flags
|= LRO_TCP
;
2235 *tcpudp_hdr
= (u8
*) (*ip_hdr
) + (iph
->ihl
<< 2);
2237 /* verify the IP checksum */
2238 if (unlikely(ip_fast_csum((u8
*) iph
, iph
->ihl
)))
2241 /* verify the checksum */
2242 if (unlikely(csum_tcpudp_magic(iph
->saddr
, iph
->daddr
,
2243 ntohs(iph
->tot_len
) - (iph
->ihl
<< 2),
2244 IPPROTO_TCP
, csum
)))
2250 static int myri10ge_get_txrx(struct myri10ge_priv
*mgp
, int slice
)
2252 struct myri10ge_cmd cmd
;
2253 struct myri10ge_slice_state
*ss
;
2256 ss
= &mgp
->ss
[slice
];
2258 if (slice
== 0 || (mgp
->dev
->real_num_tx_queues
> 1)) {
2260 status
= myri10ge_send_cmd(mgp
, MXGEFW_CMD_GET_SEND_OFFSET
,
2262 ss
->tx
.lanai
= (struct mcp_kreq_ether_send __iomem
*)
2263 (mgp
->sram
+ cmd
.data0
);
2266 status
|= myri10ge_send_cmd(mgp
, MXGEFW_CMD_GET_SMALL_RX_OFFSET
,
2268 ss
->rx_small
.lanai
= (struct mcp_kreq_ether_recv __iomem
*)
2269 (mgp
->sram
+ cmd
.data0
);
2272 status
|= myri10ge_send_cmd(mgp
, MXGEFW_CMD_GET_BIG_RX_OFFSET
, &cmd
, 0);
2273 ss
->rx_big
.lanai
= (struct mcp_kreq_ether_recv __iomem
*)
2274 (mgp
->sram
+ cmd
.data0
);
2276 ss
->tx
.send_go
= (__iomem __be32
*)
2277 (mgp
->sram
+ MXGEFW_ETH_SEND_GO
+ 64 * slice
);
2278 ss
->tx
.send_stop
= (__iomem __be32
*)
2279 (mgp
->sram
+ MXGEFW_ETH_SEND_STOP
+ 64 * slice
);
2284 static int myri10ge_set_stats(struct myri10ge_priv
*mgp
, int slice
)
2286 struct myri10ge_cmd cmd
;
2287 struct myri10ge_slice_state
*ss
;
2290 ss
= &mgp
->ss
[slice
];
2291 cmd
.data0
= MYRI10GE_LOWPART_TO_U32(ss
->fw_stats_bus
);
2292 cmd
.data1
= MYRI10GE_HIGHPART_TO_U32(ss
->fw_stats_bus
);
2293 cmd
.data2
= sizeof(struct mcp_irq_data
) | (slice
<< 16);
2294 status
= myri10ge_send_cmd(mgp
, MXGEFW_CMD_SET_STATS_DMA_V2
, &cmd
, 0);
2295 if (status
== -ENOSYS
) {
2296 dma_addr_t bus
= ss
->fw_stats_bus
;
2299 bus
+= offsetof(struct mcp_irq_data
, send_done_count
);
2300 cmd
.data0
= MYRI10GE_LOWPART_TO_U32(bus
);
2301 cmd
.data1
= MYRI10GE_HIGHPART_TO_U32(bus
);
2302 status
= myri10ge_send_cmd(mgp
,
2303 MXGEFW_CMD_SET_STATS_DMA_OBSOLETE
,
2305 /* Firmware cannot support multicast without STATS_DMA_V2 */
2306 mgp
->fw_multicast_support
= 0;
2308 mgp
->fw_multicast_support
= 1;
2313 static int myri10ge_open(struct net_device
*dev
)
2315 struct myri10ge_slice_state
*ss
;
2316 struct myri10ge_priv
*mgp
= netdev_priv(dev
);
2317 struct myri10ge_cmd cmd
;
2318 int i
, status
, big_pow2
, slice
;
2320 struct net_lro_mgr
*lro_mgr
;
2322 if (mgp
->running
!= MYRI10GE_ETH_STOPPED
)
2325 mgp
->running
= MYRI10GE_ETH_STARTING
;
2326 status
= myri10ge_reset(mgp
);
2328 printk(KERN_ERR
"myri10ge: %s: failed reset\n", dev
->name
);
2329 goto abort_with_nothing
;
2332 if (mgp
->num_slices
> 1) {
2333 cmd
.data0
= mgp
->num_slices
;
2334 cmd
.data1
= MXGEFW_SLICE_INTR_MODE_ONE_PER_SLICE
;
2335 if (mgp
->dev
->real_num_tx_queues
> 1)
2336 cmd
.data1
|= MXGEFW_SLICE_ENABLE_MULTIPLE_TX_QUEUES
;
2337 status
= myri10ge_send_cmd(mgp
, MXGEFW_CMD_ENABLE_RSS_QUEUES
,
2341 "myri10ge: %s: failed to set number of slices\n",
2343 goto abort_with_nothing
;
2345 /* setup the indirection table */
2346 cmd
.data0
= mgp
->num_slices
;
2347 status
= myri10ge_send_cmd(mgp
, MXGEFW_CMD_SET_RSS_TABLE_SIZE
,
2350 status
|= myri10ge_send_cmd(mgp
,
2351 MXGEFW_CMD_GET_RSS_TABLE_OFFSET
,
2355 "myri10ge: %s: failed to setup rss tables\n",
2357 goto abort_with_nothing
;
2360 /* just enable an identity mapping */
2361 itable
= mgp
->sram
+ cmd
.data0
;
2362 for (i
= 0; i
< mgp
->num_slices
; i
++)
2363 __raw_writeb(i
, &itable
[i
]);
2366 cmd
.data1
= myri10ge_rss_hash
;
2367 status
= myri10ge_send_cmd(mgp
, MXGEFW_CMD_SET_RSS_ENABLE
,
2371 "myri10ge: %s: failed to enable slices\n",
2373 goto abort_with_nothing
;
2377 status
= myri10ge_request_irq(mgp
);
2379 goto abort_with_nothing
;
2381 /* decide what small buffer size to use. For good TCP rx
2382 * performance, it is important to not receive 1514 byte
2383 * frames into jumbo buffers, as it confuses the socket buffer
2384 * accounting code, leading to drops and erratic performance.
2387 if (dev
->mtu
<= ETH_DATA_LEN
)
2388 /* enough for a TCP header */
2389 mgp
->small_bytes
= (128 > SMP_CACHE_BYTES
)
2390 ? (128 - MXGEFW_PAD
)
2391 : (SMP_CACHE_BYTES
- MXGEFW_PAD
);
2393 /* enough for a vlan encapsulated ETH_DATA_LEN frame */
2394 mgp
->small_bytes
= VLAN_ETH_FRAME_LEN
;
2396 /* Override the small buffer size? */
2397 if (myri10ge_small_bytes
> 0)
2398 mgp
->small_bytes
= myri10ge_small_bytes
;
2400 /* Firmware needs the big buff size as a power of 2. Lie and
2401 * tell him the buffer is larger, because we only use 1
2402 * buffer/pkt, and the mtu will prevent overruns.
2404 big_pow2
= dev
->mtu
+ ETH_HLEN
+ VLAN_HLEN
+ MXGEFW_PAD
;
2405 if (big_pow2
< MYRI10GE_ALLOC_SIZE
/ 2) {
2406 while (!is_power_of_2(big_pow2
))
2408 mgp
->big_bytes
= dev
->mtu
+ ETH_HLEN
+ VLAN_HLEN
+ MXGEFW_PAD
;
2410 big_pow2
= MYRI10GE_ALLOC_SIZE
;
2411 mgp
->big_bytes
= big_pow2
;
2414 /* setup the per-slice data structures */
2415 for (slice
= 0; slice
< mgp
->num_slices
; slice
++) {
2416 ss
= &mgp
->ss
[slice
];
2418 status
= myri10ge_get_txrx(mgp
, slice
);
2421 "myri10ge: %s: failed to get ring sizes or locations\n",
2423 goto abort_with_rings
;
2425 status
= myri10ge_allocate_rings(ss
);
2427 goto abort_with_rings
;
2429 /* only firmware which supports multiple TX queues
2430 * supports setting up the tx stats on non-zero
2432 if (slice
== 0 || mgp
->dev
->real_num_tx_queues
> 1)
2433 status
= myri10ge_set_stats(mgp
, slice
);
2436 "myri10ge: %s: Couldn't set stats DMA\n",
2438 goto abort_with_rings
;
2441 lro_mgr
= &ss
->rx_done
.lro_mgr
;
2443 lro_mgr
->features
= LRO_F_NAPI
;
2444 lro_mgr
->ip_summed
= CHECKSUM_COMPLETE
;
2445 lro_mgr
->ip_summed_aggr
= CHECKSUM_UNNECESSARY
;
2446 lro_mgr
->max_desc
= MYRI10GE_MAX_LRO_DESCRIPTORS
;
2447 lro_mgr
->lro_arr
= ss
->rx_done
.lro_desc
;
2448 lro_mgr
->get_frag_header
= myri10ge_get_frag_header
;
2449 lro_mgr
->max_aggr
= myri10ge_lro_max_pkts
;
2450 if (lro_mgr
->max_aggr
> MAX_SKB_FRAGS
)
2451 lro_mgr
->max_aggr
= MAX_SKB_FRAGS
;
2453 /* must happen prior to any irq */
2454 napi_enable(&(ss
)->napi
);
2457 /* now give firmware buffers sizes, and MTU */
2458 cmd
.data0
= dev
->mtu
+ ETH_HLEN
+ VLAN_HLEN
;
2459 status
= myri10ge_send_cmd(mgp
, MXGEFW_CMD_SET_MTU
, &cmd
, 0);
2460 cmd
.data0
= mgp
->small_bytes
;
2462 myri10ge_send_cmd(mgp
, MXGEFW_CMD_SET_SMALL_BUFFER_SIZE
, &cmd
, 0);
2463 cmd
.data0
= big_pow2
;
2465 myri10ge_send_cmd(mgp
, MXGEFW_CMD_SET_BIG_BUFFER_SIZE
, &cmd
, 0);
2467 printk(KERN_ERR
"myri10ge: %s: Couldn't set buffer sizes\n",
2469 goto abort_with_rings
;
2473 * Set Linux style TSO mode; this is needed only on newer
2474 * firmware versions. Older versions default to Linux
2478 status
= myri10ge_send_cmd(mgp
, MXGEFW_CMD_SET_TSO_MODE
, &cmd
, 0);
2479 if (status
&& status
!= -ENOSYS
) {
2480 printk(KERN_ERR
"myri10ge: %s: Couldn't set TSO mode\n",
2482 goto abort_with_rings
;
2485 mgp
->link_state
= ~0U;
2486 mgp
->rdma_tags_available
= 15;
2488 status
= myri10ge_send_cmd(mgp
, MXGEFW_CMD_ETHERNET_UP
, &cmd
, 0);
2490 printk(KERN_ERR
"myri10ge: %s: Couldn't bring up link\n",
2492 goto abort_with_rings
;
2495 mgp
->running
= MYRI10GE_ETH_RUNNING
;
2496 mgp
->watchdog_timer
.expires
= jiffies
+ myri10ge_watchdog_timeout
* HZ
;
2497 add_timer(&mgp
->watchdog_timer
);
2498 netif_tx_wake_all_queues(dev
);
2505 napi_disable(&mgp
->ss
[slice
].napi
);
2507 for (i
= 0; i
< mgp
->num_slices
; i
++)
2508 myri10ge_free_rings(&mgp
->ss
[i
]);
2510 myri10ge_free_irq(mgp
);
2513 mgp
->running
= MYRI10GE_ETH_STOPPED
;
2517 static int myri10ge_close(struct net_device
*dev
)
2519 struct myri10ge_priv
*mgp
= netdev_priv(dev
);
2520 struct myri10ge_cmd cmd
;
2521 int status
, old_down_cnt
;
2524 if (mgp
->running
!= MYRI10GE_ETH_RUNNING
)
2527 if (mgp
->ss
[0].tx
.req_bytes
== NULL
)
2530 del_timer_sync(&mgp
->watchdog_timer
);
2531 mgp
->running
= MYRI10GE_ETH_STOPPING
;
2532 for (i
= 0; i
< mgp
->num_slices
; i
++) {
2533 napi_disable(&mgp
->ss
[i
].napi
);
2535 netif_carrier_off(dev
);
2537 netif_tx_stop_all_queues(dev
);
2538 old_down_cnt
= mgp
->down_cnt
;
2540 status
= myri10ge_send_cmd(mgp
, MXGEFW_CMD_ETHERNET_DOWN
, &cmd
, 0);
2542 printk(KERN_ERR
"myri10ge: %s: Couldn't bring down link\n",
2545 wait_event_timeout(mgp
->down_wq
, old_down_cnt
!= mgp
->down_cnt
, HZ
);
2546 if (old_down_cnt
== mgp
->down_cnt
)
2547 printk(KERN_ERR
"myri10ge: %s never got down irq\n", dev
->name
);
2549 netif_tx_disable(dev
);
2550 myri10ge_free_irq(mgp
);
2551 for (i
= 0; i
< mgp
->num_slices
; i
++)
2552 myri10ge_free_rings(&mgp
->ss
[i
]);
2554 mgp
->running
= MYRI10GE_ETH_STOPPED
;
2558 /* copy an array of struct mcp_kreq_ether_send's to the mcp. Copy
2559 * backwards one at a time and handle ring wraps */
2562 myri10ge_submit_req_backwards(struct myri10ge_tx_buf
*tx
,
2563 struct mcp_kreq_ether_send
*src
, int cnt
)
2565 int idx
, starting_slot
;
2566 starting_slot
= tx
->req
;
2569 idx
= (starting_slot
+ cnt
) & tx
->mask
;
2570 myri10ge_pio_copy(&tx
->lanai
[idx
], &src
[cnt
], sizeof(*src
));
2576 * copy an array of struct mcp_kreq_ether_send's to the mcp. Copy
2577 * at most 32 bytes at a time, so as to avoid involving the software
2578 * pio handler in the nic. We re-write the first segment's flags
2579 * to mark them valid only after writing the entire chain.
2583 myri10ge_submit_req(struct myri10ge_tx_buf
*tx
, struct mcp_kreq_ether_send
*src
,
2587 struct mcp_kreq_ether_send __iomem
*dstp
, *dst
;
2588 struct mcp_kreq_ether_send
*srcp
;
2591 idx
= tx
->req
& tx
->mask
;
2593 last_flags
= src
->flags
;
2596 dst
= dstp
= &tx
->lanai
[idx
];
2599 if ((idx
+ cnt
) < tx
->mask
) {
2600 for (i
= 0; i
< (cnt
- 1); i
+= 2) {
2601 myri10ge_pio_copy(dstp
, srcp
, 2 * sizeof(*src
));
2602 mb(); /* force write every 32 bytes */
2607 /* submit all but the first request, and ensure
2608 * that it is submitted below */
2609 myri10ge_submit_req_backwards(tx
, src
, cnt
);
2613 /* submit the first request */
2614 myri10ge_pio_copy(dstp
, srcp
, sizeof(*src
));
2615 mb(); /* barrier before setting valid flag */
2618 /* re-write the last 32-bits with the valid flags */
2619 src
->flags
= last_flags
;
2620 put_be32(*((__be32
*) src
+ 3), (__be32 __iomem
*) dst
+ 3);
2626 * Transmit a packet. We need to split the packet so that a single
2627 * segment does not cross myri10ge->tx_boundary, so this makes segment
2628 * counting tricky. So rather than try to count segments up front, we
2629 * just give up if there are too few segments to hold a reasonably
2630 * fragmented packet currently available. If we run
2631 * out of segments while preparing a packet for DMA, we just linearize
2635 static int myri10ge_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
2637 struct myri10ge_priv
*mgp
= netdev_priv(dev
);
2638 struct myri10ge_slice_state
*ss
;
2639 struct mcp_kreq_ether_send
*req
;
2640 struct myri10ge_tx_buf
*tx
;
2641 struct skb_frag_struct
*frag
;
2642 struct netdev_queue
*netdev_queue
;
2645 __be32 high_swapped
;
2647 int idx
, last_idx
, avail
, frag_cnt
, frag_idx
, count
, mss
, max_segments
;
2648 u16 pseudo_hdr_offset
, cksum_offset
, queue
;
2649 int cum_len
, seglen
, boundary
, rdma_count
;
2652 queue
= skb_get_queue_mapping(skb
);
2653 ss
= &mgp
->ss
[queue
];
2654 netdev_queue
= netdev_get_tx_queue(mgp
->dev
, queue
);
2659 avail
= tx
->mask
- 1 - (tx
->req
- tx
->done
);
2662 max_segments
= MXGEFW_MAX_SEND_DESC
;
2664 if (skb_is_gso(skb
)) {
2665 mss
= skb_shinfo(skb
)->gso_size
;
2666 max_segments
= MYRI10GE_MAX_SEND_DESC_TSO
;
2669 if ((unlikely(avail
< max_segments
))) {
2670 /* we are out of transmit resources */
2672 netif_tx_stop_queue(netdev_queue
);
2676 /* Setup checksum offloading, if needed */
2678 pseudo_hdr_offset
= 0;
2680 flags
= (MXGEFW_FLAGS_NO_TSO
| MXGEFW_FLAGS_FIRST
);
2681 if (likely(skb
->ip_summed
== CHECKSUM_PARTIAL
)) {
2682 cksum_offset
= skb_transport_offset(skb
);
2683 pseudo_hdr_offset
= cksum_offset
+ skb
->csum_offset
;
2684 /* If the headers are excessively large, then we must
2685 * fall back to a software checksum */
2686 if (unlikely(!mss
&& (cksum_offset
> 255 ||
2687 pseudo_hdr_offset
> 127))) {
2688 if (skb_checksum_help(skb
))
2691 pseudo_hdr_offset
= 0;
2693 odd_flag
= MXGEFW_FLAGS_ALIGN_ODD
;
2694 flags
|= MXGEFW_FLAGS_CKSUM
;
2700 if (mss
) { /* TSO */
2701 /* this removes any CKSUM flag from before */
2702 flags
= (MXGEFW_FLAGS_TSO_HDR
| MXGEFW_FLAGS_FIRST
);
2704 /* negative cum_len signifies to the
2705 * send loop that we are still in the
2706 * header portion of the TSO packet.
2707 * TSO header can be at most 1KB long */
2708 cum_len
= -(skb_transport_offset(skb
) + tcp_hdrlen(skb
));
2710 /* for IPv6 TSO, the checksum offset stores the
2711 * TCP header length, to save the firmware from
2712 * the need to parse the headers */
2713 if (skb_is_gso_v6(skb
)) {
2714 cksum_offset
= tcp_hdrlen(skb
);
2715 /* Can only handle headers <= max_tso6 long */
2716 if (unlikely(-cum_len
> mgp
->max_tso6
))
2717 return myri10ge_sw_tso(skb
, dev
);
2719 /* for TSO, pseudo_hdr_offset holds mss.
2720 * The firmware figures out where to put
2721 * the checksum by parsing the header. */
2722 pseudo_hdr_offset
= mss
;
2724 /* Mark small packets, and pad out tiny packets */
2725 if (skb
->len
<= MXGEFW_SEND_SMALL_SIZE
) {
2726 flags
|= MXGEFW_FLAGS_SMALL
;
2728 /* pad frames to at least ETH_ZLEN bytes */
2729 if (unlikely(skb
->len
< ETH_ZLEN
)) {
2730 if (skb_padto(skb
, ETH_ZLEN
)) {
2731 /* The packet is gone, so we must
2733 ss
->stats
.tx_dropped
+= 1;
2736 /* adjust the len to account for the zero pad
2737 * so that the nic can know how long it is */
2738 skb
->len
= ETH_ZLEN
;
2742 /* map the skb for DMA */
2743 len
= skb
->len
- skb
->data_len
;
2744 idx
= tx
->req
& tx
->mask
;
2745 tx
->info
[idx
].skb
= skb
;
2746 bus
= pci_map_single(mgp
->pdev
, skb
->data
, len
, PCI_DMA_TODEVICE
);
2747 pci_unmap_addr_set(&tx
->info
[idx
], bus
, bus
);
2748 pci_unmap_len_set(&tx
->info
[idx
], len
, len
);
2750 frag_cnt
= skb_shinfo(skb
)->nr_frags
;
2755 /* "rdma_count" is the number of RDMAs belonging to the
2756 * current packet BEFORE the current send request. For
2757 * non-TSO packets, this is equal to "count".
2758 * For TSO packets, rdma_count needs to be reset
2759 * to 0 after a segment cut.
2761 * The rdma_count field of the send request is
2762 * the number of RDMAs of the packet starting at
2763 * that request. For TSO send requests with one ore more cuts
2764 * in the middle, this is the number of RDMAs starting
2765 * after the last cut in the request. All previous
2766 * segments before the last cut implicitly have 1 RDMA.
2768 * Since the number of RDMAs is not known beforehand,
2769 * it must be filled-in retroactively - after each
2770 * segmentation cut or at the end of the entire packet.
2774 /* Break the SKB or Fragment up into pieces which
2775 * do not cross mgp->tx_boundary */
2776 low
= MYRI10GE_LOWPART_TO_U32(bus
);
2777 high_swapped
= htonl(MYRI10GE_HIGHPART_TO_U32(bus
));
2782 if (unlikely(count
== max_segments
))
2783 goto abort_linearize
;
2786 (low
+ mgp
->tx_boundary
) & ~(mgp
->tx_boundary
- 1);
2787 seglen
= boundary
- low
;
2790 flags_next
= flags
& ~MXGEFW_FLAGS_FIRST
;
2791 cum_len_next
= cum_len
+ seglen
;
2792 if (mss
) { /* TSO */
2793 (req
- rdma_count
)->rdma_count
= rdma_count
+ 1;
2795 if (likely(cum_len
>= 0)) { /* payload */
2796 int next_is_first
, chop
;
2798 chop
= (cum_len_next
> mss
);
2799 cum_len_next
= cum_len_next
% mss
;
2800 next_is_first
= (cum_len_next
== 0);
2801 flags
|= chop
* MXGEFW_FLAGS_TSO_CHOP
;
2802 flags_next
|= next_is_first
*
2804 rdma_count
|= -(chop
| next_is_first
);
2805 rdma_count
+= chop
& !next_is_first
;
2806 } else if (likely(cum_len_next
>= 0)) { /* header ends */
2812 small
= (mss
<= MXGEFW_SEND_SMALL_SIZE
);
2813 flags_next
= MXGEFW_FLAGS_TSO_PLD
|
2814 MXGEFW_FLAGS_FIRST
|
2815 (small
* MXGEFW_FLAGS_SMALL
);
2818 req
->addr_high
= high_swapped
;
2819 req
->addr_low
= htonl(low
);
2820 req
->pseudo_hdr_offset
= htons(pseudo_hdr_offset
);
2821 req
->pad
= 0; /* complete solid 16-byte block; does this matter? */
2822 req
->rdma_count
= 1;
2823 req
->length
= htons(seglen
);
2824 req
->cksum_offset
= cksum_offset
;
2825 req
->flags
= flags
| ((cum_len
& 1) * odd_flag
);
2829 cum_len
= cum_len_next
;
2834 if (cksum_offset
!= 0 && !(mss
&& skb_is_gso_v6(skb
))) {
2835 if (unlikely(cksum_offset
> seglen
))
2836 cksum_offset
-= seglen
;
2841 if (frag_idx
== frag_cnt
)
2844 /* map next fragment for DMA */
2845 idx
= (count
+ tx
->req
) & tx
->mask
;
2846 frag
= &skb_shinfo(skb
)->frags
[frag_idx
];
2849 bus
= pci_map_page(mgp
->pdev
, frag
->page
, frag
->page_offset
,
2850 len
, PCI_DMA_TODEVICE
);
2851 pci_unmap_addr_set(&tx
->info
[idx
], bus
, bus
);
2852 pci_unmap_len_set(&tx
->info
[idx
], len
, len
);
2855 (req
- rdma_count
)->rdma_count
= rdma_count
;
2859 req
->flags
|= MXGEFW_FLAGS_TSO_LAST
;
2860 } while (!(req
->flags
& (MXGEFW_FLAGS_TSO_CHOP
|
2861 MXGEFW_FLAGS_FIRST
)));
2862 idx
= ((count
- 1) + tx
->req
) & tx
->mask
;
2863 tx
->info
[idx
].last
= 1;
2864 myri10ge_submit_req(tx
, tx
->req_list
, count
);
2865 /* if using multiple tx queues, make sure NIC polls the
2867 if ((mgp
->dev
->real_num_tx_queues
> 1) && tx
->queue_active
== 0) {
2868 tx
->queue_active
= 1;
2869 put_be32(htonl(1), tx
->send_go
);
2874 if ((avail
- count
) < MXGEFW_MAX_SEND_DESC
) {
2876 netif_tx_stop_queue(netdev_queue
);
2878 dev
->trans_start
= jiffies
;
2882 /* Free any DMA resources we've alloced and clear out the skb
2883 * slot so as to not trip up assertions, and to avoid a
2884 * double-free if linearizing fails */
2886 last_idx
= (idx
+ 1) & tx
->mask
;
2887 idx
= tx
->req
& tx
->mask
;
2888 tx
->info
[idx
].skb
= NULL
;
2890 len
= pci_unmap_len(&tx
->info
[idx
], len
);
2892 if (tx
->info
[idx
].skb
!= NULL
)
2893 pci_unmap_single(mgp
->pdev
,
2894 pci_unmap_addr(&tx
->info
[idx
],
2898 pci_unmap_page(mgp
->pdev
,
2899 pci_unmap_addr(&tx
->info
[idx
],
2902 pci_unmap_len_set(&tx
->info
[idx
], len
, 0);
2903 tx
->info
[idx
].skb
= NULL
;
2905 idx
= (idx
+ 1) & tx
->mask
;
2906 } while (idx
!= last_idx
);
2907 if (skb_is_gso(skb
)) {
2909 "myri10ge: %s: TSO but wanted to linearize?!?!?\n",
2914 if (skb_linearize(skb
))
2921 dev_kfree_skb_any(skb
);
2922 ss
->stats
.tx_dropped
+= 1;
2927 static int myri10ge_sw_tso(struct sk_buff
*skb
, struct net_device
*dev
)
2929 struct sk_buff
*segs
, *curr
;
2930 struct myri10ge_priv
*mgp
= netdev_priv(dev
);
2931 struct myri10ge_slice_state
*ss
;
2934 segs
= skb_gso_segment(skb
, dev
->features
& ~NETIF_F_TSO6
);
2942 status
= myri10ge_xmit(curr
, dev
);
2944 dev_kfree_skb_any(curr
);
2949 dev_kfree_skb_any(segs
);
2954 dev_kfree_skb_any(skb
);
2958 ss
= &mgp
->ss
[skb_get_queue_mapping(skb
)];
2959 dev_kfree_skb_any(skb
);
2960 ss
->stats
.tx_dropped
+= 1;
2964 static struct net_device_stats
*myri10ge_get_stats(struct net_device
*dev
)
2966 struct myri10ge_priv
*mgp
= netdev_priv(dev
);
2967 struct myri10ge_slice_netstats
*slice_stats
;
2968 struct net_device_stats
*stats
= &mgp
->stats
;
2971 memset(stats
, 0, sizeof(*stats
));
2972 for (i
= 0; i
< mgp
->num_slices
; i
++) {
2973 slice_stats
= &mgp
->ss
[i
].stats
;
2974 stats
->rx_packets
+= slice_stats
->rx_packets
;
2975 stats
->tx_packets
+= slice_stats
->tx_packets
;
2976 stats
->rx_bytes
+= slice_stats
->rx_bytes
;
2977 stats
->tx_bytes
+= slice_stats
->tx_bytes
;
2978 stats
->rx_dropped
+= slice_stats
->rx_dropped
;
2979 stats
->tx_dropped
+= slice_stats
->tx_dropped
;
2984 static void myri10ge_set_multicast_list(struct net_device
*dev
)
2986 struct myri10ge_priv
*mgp
= netdev_priv(dev
);
2987 struct myri10ge_cmd cmd
;
2988 struct dev_mc_list
*mc_list
;
2989 __be32 data
[2] = { 0, 0 };
2992 /* can be called from atomic contexts,
2993 * pass 1 to force atomicity in myri10ge_send_cmd() */
2994 myri10ge_change_promisc(mgp
, dev
->flags
& IFF_PROMISC
, 1);
2996 /* This firmware is known to not support multicast */
2997 if (!mgp
->fw_multicast_support
)
3000 /* Disable multicast filtering */
3002 err
= myri10ge_send_cmd(mgp
, MXGEFW_ENABLE_ALLMULTI
, &cmd
, 1);
3004 printk(KERN_ERR
"myri10ge: %s: Failed MXGEFW_ENABLE_ALLMULTI,"
3005 " error status: %d\n", dev
->name
, err
);
3009 if ((dev
->flags
& IFF_ALLMULTI
) || mgp
->adopted_rx_filter_bug
) {
3010 /* request to disable multicast filtering, so quit here */
3014 /* Flush the filters */
3016 err
= myri10ge_send_cmd(mgp
, MXGEFW_LEAVE_ALL_MULTICAST_GROUPS
,
3020 "myri10ge: %s: Failed MXGEFW_LEAVE_ALL_MULTICAST_GROUPS"
3021 ", error status: %d\n", dev
->name
, err
);
3025 /* Walk the multicast list, and add each address */
3026 for (mc_list
= dev
->mc_list
; mc_list
!= NULL
; mc_list
= mc_list
->next
) {
3027 memcpy(data
, &mc_list
->dmi_addr
, 6);
3028 cmd
.data0
= ntohl(data
[0]);
3029 cmd
.data1
= ntohl(data
[1]);
3030 err
= myri10ge_send_cmd(mgp
, MXGEFW_JOIN_MULTICAST_GROUP
,
3034 printk(KERN_ERR
"myri10ge: %s: Failed "
3035 "MXGEFW_JOIN_MULTICAST_GROUP, error status:"
3036 "%d\t", dev
->name
, err
);
3037 printk(KERN_ERR
"MAC %pM\n", mc_list
->dmi_addr
);
3041 /* Enable multicast filtering */
3042 err
= myri10ge_send_cmd(mgp
, MXGEFW_DISABLE_ALLMULTI
, &cmd
, 1);
3044 printk(KERN_ERR
"myri10ge: %s: Failed MXGEFW_DISABLE_ALLMULTI,"
3045 "error status: %d\n", dev
->name
, err
);
3055 static int myri10ge_set_mac_address(struct net_device
*dev
, void *addr
)
3057 struct sockaddr
*sa
= addr
;
3058 struct myri10ge_priv
*mgp
= netdev_priv(dev
);
3061 if (!is_valid_ether_addr(sa
->sa_data
))
3062 return -EADDRNOTAVAIL
;
3064 status
= myri10ge_update_mac_address(mgp
, sa
->sa_data
);
3067 "myri10ge: %s: changing mac address failed with %d\n",
3072 /* change the dev structure */
3073 memcpy(dev
->dev_addr
, sa
->sa_data
, 6);
3077 static int myri10ge_change_mtu(struct net_device
*dev
, int new_mtu
)
3079 struct myri10ge_priv
*mgp
= netdev_priv(dev
);
3082 if ((new_mtu
< 68) || (ETH_HLEN
+ new_mtu
> MYRI10GE_MAX_ETHER_MTU
)) {
3083 printk(KERN_ERR
"myri10ge: %s: new mtu (%d) is not valid\n",
3084 dev
->name
, new_mtu
);
3087 printk(KERN_INFO
"%s: changing mtu from %d to %d\n",
3088 dev
->name
, dev
->mtu
, new_mtu
);
3090 /* if we change the mtu on an active device, we must
3091 * reset the device so the firmware sees the change */
3092 myri10ge_close(dev
);
3102 * Enable ECRC to align PCI-E Completion packets on an 8-byte boundary.
3103 * Only do it if the bridge is a root port since we don't want to disturb
3104 * any other device, except if forced with myri10ge_ecrc_enable > 1.
3107 static void myri10ge_enable_ecrc(struct myri10ge_priv
*mgp
)
3109 struct pci_dev
*bridge
= mgp
->pdev
->bus
->self
;
3110 struct device
*dev
= &mgp
->pdev
->dev
;
3117 if (!myri10ge_ecrc_enable
|| !bridge
)
3120 /* check that the bridge is a root port */
3121 cap
= pci_find_capability(bridge
, PCI_CAP_ID_EXP
);
3122 pci_read_config_word(bridge
, cap
+ PCI_CAP_FLAGS
, &val
);
3123 ext_type
= (val
& PCI_EXP_FLAGS_TYPE
) >> 4;
3124 if (ext_type
!= PCI_EXP_TYPE_ROOT_PORT
) {
3125 if (myri10ge_ecrc_enable
> 1) {
3126 struct pci_dev
*prev_bridge
, *old_bridge
= bridge
;
3128 /* Walk the hierarchy up to the root port
3129 * where ECRC has to be enabled */
3131 prev_bridge
= bridge
;
3132 bridge
= bridge
->bus
->self
;
3133 if (!bridge
|| prev_bridge
== bridge
) {
3135 "Failed to find root port"
3136 " to force ECRC\n");
3140 pci_find_capability(bridge
, PCI_CAP_ID_EXP
);
3141 pci_read_config_word(bridge
,
3142 cap
+ PCI_CAP_FLAGS
, &val
);
3143 ext_type
= (val
& PCI_EXP_FLAGS_TYPE
) >> 4;
3144 } while (ext_type
!= PCI_EXP_TYPE_ROOT_PORT
);
3147 "Forcing ECRC on non-root port %s"
3148 " (enabling on root port %s)\n",
3149 pci_name(old_bridge
), pci_name(bridge
));
3152 "Not enabling ECRC on non-root port %s\n",
3158 cap
= pci_find_ext_capability(bridge
, PCI_EXT_CAP_ID_ERR
);
3162 ret
= pci_read_config_dword(bridge
, cap
+ PCI_ERR_CAP
, &err_cap
);
3164 dev_err(dev
, "failed reading ext-conf-space of %s\n",
3166 dev_err(dev
, "\t pci=nommconf in use? "
3167 "or buggy/incomplete/absent ACPI MCFG attr?\n");
3170 if (!(err_cap
& PCI_ERR_CAP_ECRC_GENC
))
3173 err_cap
|= PCI_ERR_CAP_ECRC_GENE
;
3174 pci_write_config_dword(bridge
, cap
+ PCI_ERR_CAP
, err_cap
);
3175 dev_info(dev
, "Enabled ECRC on upstream bridge %s\n", pci_name(bridge
));
3179 * The Lanai Z8E PCI-E interface achieves higher Read-DMA throughput
3180 * when the PCI-E Completion packets are aligned on an 8-byte
3181 * boundary. Some PCI-E chip sets always align Completion packets; on
3182 * the ones that do not, the alignment can be enforced by enabling
3183 * ECRC generation (if supported).
3185 * When PCI-E Completion packets are not aligned, it is actually more
3186 * efficient to limit Read-DMA transactions to 2KB, rather than 4KB.
3188 * If the driver can neither enable ECRC nor verify that it has
3189 * already been enabled, then it must use a firmware image which works
3190 * around unaligned completion packets (myri10ge_rss_ethp_z8e.dat), and it
3191 * should also ensure that it never gives the device a Read-DMA which is
3192 * larger than 2KB by setting the tx_boundary to 2KB. If ECRC is
3193 * enabled, then the driver should use the aligned (myri10ge_rss_eth_z8e.dat)
3194 * firmware image, and set tx_boundary to 4KB.
3197 static void myri10ge_firmware_probe(struct myri10ge_priv
*mgp
)
3199 struct pci_dev
*pdev
= mgp
->pdev
;
3200 struct device
*dev
= &pdev
->dev
;
3203 mgp
->tx_boundary
= 4096;
3205 * Verify the max read request size was set to 4KB
3206 * before trying the test with 4KB.
3208 status
= pcie_get_readrq(pdev
);
3210 dev_err(dev
, "Couldn't read max read req size: %d\n", status
);
3213 if (status
!= 4096) {
3214 dev_warn(dev
, "Max Read Request size != 4096 (%d)\n", status
);
3215 mgp
->tx_boundary
= 2048;
3218 * load the optimized firmware (which assumes aligned PCIe
3219 * completions) in order to see if it works on this host.
3221 mgp
->fw_name
= myri10ge_fw_aligned
;
3222 status
= myri10ge_load_firmware(mgp
, 1);
3228 * Enable ECRC if possible
3230 myri10ge_enable_ecrc(mgp
);
3233 * Run a DMA test which watches for unaligned completions and
3234 * aborts on the first one seen.
3237 status
= myri10ge_dma_test(mgp
, MXGEFW_CMD_UNALIGNED_TEST
);
3239 return; /* keep the aligned firmware */
3241 if (status
!= -E2BIG
)
3242 dev_warn(dev
, "DMA test failed: %d\n", status
);
3243 if (status
== -ENOSYS
)
3244 dev_warn(dev
, "Falling back to ethp! "
3245 "Please install up to date fw\n");
3247 /* fall back to using the unaligned firmware */
3248 mgp
->tx_boundary
= 2048;
3249 mgp
->fw_name
= myri10ge_fw_unaligned
;
3253 static void myri10ge_select_firmware(struct myri10ge_priv
*mgp
)
3255 if (myri10ge_force_firmware
== 0) {
3256 int link_width
, exp_cap
;
3259 exp_cap
= pci_find_capability(mgp
->pdev
, PCI_CAP_ID_EXP
);
3260 pci_read_config_word(mgp
->pdev
, exp_cap
+ PCI_EXP_LNKSTA
, &lnk
);
3261 link_width
= (lnk
>> 4) & 0x3f;
3263 /* Check to see if Link is less than 8 or if the
3264 * upstream bridge is known to provide aligned
3266 if (link_width
< 8) {
3267 dev_info(&mgp
->pdev
->dev
, "PCIE x%d Link\n",
3269 mgp
->tx_boundary
= 4096;
3270 mgp
->fw_name
= myri10ge_fw_aligned
;
3272 myri10ge_firmware_probe(mgp
);
3275 if (myri10ge_force_firmware
== 1) {
3276 dev_info(&mgp
->pdev
->dev
,
3277 "Assuming aligned completions (forced)\n");
3278 mgp
->tx_boundary
= 4096;
3279 mgp
->fw_name
= myri10ge_fw_aligned
;
3281 dev_info(&mgp
->pdev
->dev
,
3282 "Assuming unaligned completions (forced)\n");
3283 mgp
->tx_boundary
= 2048;
3284 mgp
->fw_name
= myri10ge_fw_unaligned
;
3287 if (myri10ge_fw_name
!= NULL
) {
3288 dev_info(&mgp
->pdev
->dev
, "overriding firmware to %s\n",
3290 mgp
->fw_name
= myri10ge_fw_name
;
3295 static int myri10ge_suspend(struct pci_dev
*pdev
, pm_message_t state
)
3297 struct myri10ge_priv
*mgp
;
3298 struct net_device
*netdev
;
3300 mgp
= pci_get_drvdata(pdev
);
3305 netif_device_detach(netdev
);
3306 if (netif_running(netdev
)) {
3307 printk(KERN_INFO
"myri10ge: closing %s\n", netdev
->name
);
3309 myri10ge_close(netdev
);
3312 myri10ge_dummy_rdma(mgp
, 0);
3313 pci_save_state(pdev
);
3314 pci_disable_device(pdev
);
3316 return pci_set_power_state(pdev
, pci_choose_state(pdev
, state
));
3319 static int myri10ge_resume(struct pci_dev
*pdev
)
3321 struct myri10ge_priv
*mgp
;
3322 struct net_device
*netdev
;
3326 mgp
= pci_get_drvdata(pdev
);
3330 pci_set_power_state(pdev
, 0); /* zeros conf space as a side effect */
3331 msleep(5); /* give card time to respond */
3332 pci_read_config_word(mgp
->pdev
, PCI_VENDOR_ID
, &vendor
);
3333 if (vendor
== 0xffff) {
3334 printk(KERN_ERR
"myri10ge: %s: device disappeared!\n",
3339 status
= pci_restore_state(pdev
);
3343 status
= pci_enable_device(pdev
);
3345 dev_err(&pdev
->dev
, "failed to enable device\n");
3349 pci_set_master(pdev
);
3351 myri10ge_reset(mgp
);
3352 myri10ge_dummy_rdma(mgp
, 1);
3354 /* Save configuration space to be restored if the
3355 * nic resets due to a parity error */
3356 pci_save_state(pdev
);
3358 if (netif_running(netdev
)) {
3360 status
= myri10ge_open(netdev
);
3363 goto abort_with_enabled
;
3366 netif_device_attach(netdev
);
3371 pci_disable_device(pdev
);
3375 #endif /* CONFIG_PM */
3377 static u32
myri10ge_read_reboot(struct myri10ge_priv
*mgp
)
3379 struct pci_dev
*pdev
= mgp
->pdev
;
3380 int vs
= mgp
->vendor_specific_offset
;
3383 /*enter read32 mode */
3384 pci_write_config_byte(pdev
, vs
+ 0x10, 0x3);
3386 /*read REBOOT_STATUS (0xfffffff0) */
3387 pci_write_config_dword(pdev
, vs
+ 0x18, 0xfffffff0);
3388 pci_read_config_dword(pdev
, vs
+ 0x14, &reboot
);
3393 * This watchdog is used to check whether the board has suffered
3394 * from a parity error and needs to be recovered.
3396 static void myri10ge_watchdog(struct work_struct
*work
)
3398 struct myri10ge_priv
*mgp
=
3399 container_of(work
, struct myri10ge_priv
, watchdog_work
);
3400 struct myri10ge_tx_buf
*tx
;
3406 mgp
->watchdog_resets
++;
3407 pci_read_config_word(mgp
->pdev
, PCI_COMMAND
, &cmd
);
3408 if ((cmd
& PCI_COMMAND_MASTER
) == 0) {
3409 /* Bus master DMA disabled? Check to see
3410 * if the card rebooted due to a parity error
3411 * For now, just report it */
3412 reboot
= myri10ge_read_reboot(mgp
);
3414 "myri10ge: %s: NIC rebooted (0x%x),%s resetting\n",
3415 mgp
->dev
->name
, reboot
,
3416 myri10ge_reset_recover
? " " : " not");
3417 if (myri10ge_reset_recover
== 0)
3420 myri10ge_reset_recover
--;
3423 * A rebooted nic will come back with config space as
3424 * it was after power was applied to PCIe bus.
3425 * Attempt to restore config space which was saved
3426 * when the driver was loaded, or the last time the
3427 * nic was resumed from power saving mode.
3429 pci_restore_state(mgp
->pdev
);
3431 /* save state again for accounting reasons */
3432 pci_save_state(mgp
->pdev
);
3435 /* if we get back -1's from our slot, perhaps somebody
3436 * powered off our card. Don't try to reset it in
3438 if (cmd
== 0xffff) {
3439 pci_read_config_word(mgp
->pdev
, PCI_VENDOR_ID
, &vendor
);
3440 if (vendor
== 0xffff) {
3442 "myri10ge: %s: device disappeared!\n",
3447 /* Perhaps it is a software error. Try to reset */
3449 printk(KERN_ERR
"myri10ge: %s: device timeout, resetting\n",
3451 for (i
= 0; i
< mgp
->num_slices
; i
++) {
3452 tx
= &mgp
->ss
[i
].tx
;
3454 "myri10ge: %s: (%d): %d %d %d %d %d %d\n",
3455 mgp
->dev
->name
, i
, tx
->queue_active
, tx
->req
,
3456 tx
->done
, tx
->pkt_start
, tx
->pkt_done
,
3457 (int)ntohl(mgp
->ss
[i
].fw_stats
->
3461 "myri10ge: %s: (%d): %d %d %d %d %d %d\n",
3462 mgp
->dev
->name
, i
, tx
->queue_active
, tx
->req
,
3463 tx
->done
, tx
->pkt_start
, tx
->pkt_done
,
3464 (int)ntohl(mgp
->ss
[i
].fw_stats
->
3470 myri10ge_close(mgp
->dev
);
3471 status
= myri10ge_load_firmware(mgp
, 1);
3473 printk(KERN_ERR
"myri10ge: %s: failed to load firmware\n",
3476 myri10ge_open(mgp
->dev
);
3481 * We use our own timer routine rather than relying upon
3482 * netdev->tx_timeout because we have a very large hardware transmit
3483 * queue. Due to the large queue, the netdev->tx_timeout function
3484 * cannot detect a NIC with a parity error in a timely fashion if the
3485 * NIC is lightly loaded.
3487 static void myri10ge_watchdog_timer(unsigned long arg
)
3489 struct myri10ge_priv
*mgp
;
3490 struct myri10ge_slice_state
*ss
;
3491 int i
, reset_needed
;
3494 mgp
= (struct myri10ge_priv
*)arg
;
3496 rx_pause_cnt
= ntohl(mgp
->ss
[0].fw_stats
->dropped_pause
);
3497 for (i
= 0, reset_needed
= 0;
3498 i
< mgp
->num_slices
&& reset_needed
== 0; ++i
) {
3501 if (ss
->rx_small
.watchdog_needed
) {
3502 myri10ge_alloc_rx_pages(mgp
, &ss
->rx_small
,
3503 mgp
->small_bytes
+ MXGEFW_PAD
,
3505 if (ss
->rx_small
.fill_cnt
- ss
->rx_small
.cnt
>=
3506 myri10ge_fill_thresh
)
3507 ss
->rx_small
.watchdog_needed
= 0;
3509 if (ss
->rx_big
.watchdog_needed
) {
3510 myri10ge_alloc_rx_pages(mgp
, &ss
->rx_big
,
3512 if (ss
->rx_big
.fill_cnt
- ss
->rx_big
.cnt
>=
3513 myri10ge_fill_thresh
)
3514 ss
->rx_big
.watchdog_needed
= 0;
3517 if (ss
->tx
.req
!= ss
->tx
.done
&&
3518 ss
->tx
.done
== ss
->watchdog_tx_done
&&
3519 ss
->watchdog_tx_req
!= ss
->watchdog_tx_done
) {
3520 /* nic seems like it might be stuck.. */
3521 if (rx_pause_cnt
!= mgp
->watchdog_pause
) {
3522 if (net_ratelimit())
3524 "myri10ge %s slice %d:"
3525 "TX paused, check link partner\n",
3529 "myri10ge %s slice %d stuck:",
3534 ss
->watchdog_tx_done
= ss
->tx
.done
;
3535 ss
->watchdog_tx_req
= ss
->tx
.req
;
3537 mgp
->watchdog_pause
= rx_pause_cnt
;
3540 schedule_work(&mgp
->watchdog_work
);
3543 mod_timer(&mgp
->watchdog_timer
,
3544 jiffies
+ myri10ge_watchdog_timeout
* HZ
);
3548 static void myri10ge_free_slices(struct myri10ge_priv
*mgp
)
3550 struct myri10ge_slice_state
*ss
;
3551 struct pci_dev
*pdev
= mgp
->pdev
;
3555 if (mgp
->ss
== NULL
)
3558 for (i
= 0; i
< mgp
->num_slices
; i
++) {
3560 if (ss
->rx_done
.entry
!= NULL
) {
3561 bytes
= mgp
->max_intr_slots
*
3562 sizeof(*ss
->rx_done
.entry
);
3563 dma_free_coherent(&pdev
->dev
, bytes
,
3564 ss
->rx_done
.entry
, ss
->rx_done
.bus
);
3565 ss
->rx_done
.entry
= NULL
;
3567 if (ss
->fw_stats
!= NULL
) {
3568 bytes
= sizeof(*ss
->fw_stats
);
3569 dma_free_coherent(&pdev
->dev
, bytes
,
3570 ss
->fw_stats
, ss
->fw_stats_bus
);
3571 ss
->fw_stats
= NULL
;
3578 static int myri10ge_alloc_slices(struct myri10ge_priv
*mgp
)
3580 struct myri10ge_slice_state
*ss
;
3581 struct pci_dev
*pdev
= mgp
->pdev
;
3585 bytes
= sizeof(*mgp
->ss
) * mgp
->num_slices
;
3586 mgp
->ss
= kzalloc(bytes
, GFP_KERNEL
);
3587 if (mgp
->ss
== NULL
) {
3591 for (i
= 0; i
< mgp
->num_slices
; i
++) {
3593 bytes
= mgp
->max_intr_slots
* sizeof(*ss
->rx_done
.entry
);
3594 ss
->rx_done
.entry
= dma_alloc_coherent(&pdev
->dev
, bytes
,
3597 if (ss
->rx_done
.entry
== NULL
)
3599 memset(ss
->rx_done
.entry
, 0, bytes
);
3600 bytes
= sizeof(*ss
->fw_stats
);
3601 ss
->fw_stats
= dma_alloc_coherent(&pdev
->dev
, bytes
,
3604 if (ss
->fw_stats
== NULL
)
3608 netif_napi_add(ss
->dev
, &ss
->napi
, myri10ge_poll
,
3609 myri10ge_napi_weight
);
3613 myri10ge_free_slices(mgp
);
3618 * This function determines the number of slices supported.
3619 * The number slices is the minumum of the number of CPUS,
3620 * the number of MSI-X irqs supported, the number of slices
3621 * supported by the firmware
3623 static void myri10ge_probe_slices(struct myri10ge_priv
*mgp
)
3625 struct myri10ge_cmd cmd
;
3626 struct pci_dev
*pdev
= mgp
->pdev
;
3628 int i
, status
, ncpus
, msix_cap
;
3630 mgp
->num_slices
= 1;
3631 msix_cap
= pci_find_capability(pdev
, PCI_CAP_ID_MSIX
);
3632 ncpus
= num_online_cpus();
3634 if (myri10ge_max_slices
== 1 || msix_cap
== 0 ||
3635 (myri10ge_max_slices
== -1 && ncpus
< 2))
3638 /* try to load the slice aware rss firmware */
3639 old_fw
= mgp
->fw_name
;
3640 if (myri10ge_fw_name
!= NULL
) {
3641 dev_info(&mgp
->pdev
->dev
, "overriding rss firmware to %s\n",
3643 mgp
->fw_name
= myri10ge_fw_name
;
3644 } else if (old_fw
== myri10ge_fw_aligned
)
3645 mgp
->fw_name
= myri10ge_fw_rss_aligned
;
3647 mgp
->fw_name
= myri10ge_fw_rss_unaligned
;
3648 status
= myri10ge_load_firmware(mgp
, 0);
3650 dev_info(&pdev
->dev
, "Rss firmware not found\n");
3654 /* hit the board with a reset to ensure it is alive */
3655 memset(&cmd
, 0, sizeof(cmd
));
3656 status
= myri10ge_send_cmd(mgp
, MXGEFW_CMD_RESET
, &cmd
, 0);
3658 dev_err(&mgp
->pdev
->dev
, "failed reset\n");
3663 mgp
->max_intr_slots
= cmd
.data0
/ sizeof(struct mcp_slot
);
3665 /* tell it the size of the interrupt queues */
3666 cmd
.data0
= mgp
->max_intr_slots
* sizeof(struct mcp_slot
);
3667 status
= myri10ge_send_cmd(mgp
, MXGEFW_CMD_SET_INTRQ_SIZE
, &cmd
, 0);
3669 dev_err(&mgp
->pdev
->dev
, "failed MXGEFW_CMD_SET_INTRQ_SIZE\n");
3673 /* ask the maximum number of slices it supports */
3674 status
= myri10ge_send_cmd(mgp
, MXGEFW_CMD_GET_MAX_RSS_QUEUES
, &cmd
, 0);
3678 mgp
->num_slices
= cmd
.data0
;
3680 /* Only allow multiple slices if MSI-X is usable */
3681 if (!myri10ge_msi
) {
3685 /* if the admin did not specify a limit to how many
3686 * slices we should use, cap it automatically to the
3687 * number of CPUs currently online */
3688 if (myri10ge_max_slices
== -1)
3689 myri10ge_max_slices
= ncpus
;
3691 if (mgp
->num_slices
> myri10ge_max_slices
)
3692 mgp
->num_slices
= myri10ge_max_slices
;
3694 /* Now try to allocate as many MSI-X vectors as we have
3695 * slices. We give up on MSI-X if we can only get a single
3698 mgp
->msix_vectors
= kzalloc(mgp
->num_slices
*
3699 sizeof(*mgp
->msix_vectors
), GFP_KERNEL
);
3700 if (mgp
->msix_vectors
== NULL
)
3702 for (i
= 0; i
< mgp
->num_slices
; i
++) {
3703 mgp
->msix_vectors
[i
].entry
= i
;
3706 while (mgp
->num_slices
> 1) {
3707 /* make sure it is a power of two */
3708 while (!is_power_of_2(mgp
->num_slices
))
3710 if (mgp
->num_slices
== 1)
3712 status
= pci_enable_msix(pdev
, mgp
->msix_vectors
,
3715 pci_disable_msix(pdev
);
3719 mgp
->num_slices
= status
;
3725 if (mgp
->msix_vectors
!= NULL
) {
3726 kfree(mgp
->msix_vectors
);
3727 mgp
->msix_vectors
= NULL
;
3731 mgp
->num_slices
= 1;
3732 mgp
->fw_name
= old_fw
;
3733 myri10ge_load_firmware(mgp
, 0);
3736 static const struct net_device_ops myri10ge_netdev_ops
= {
3737 .ndo_open
= myri10ge_open
,
3738 .ndo_stop
= myri10ge_close
,
3739 .ndo_start_xmit
= myri10ge_xmit
,
3740 .ndo_get_stats
= myri10ge_get_stats
,
3741 .ndo_validate_addr
= eth_validate_addr
,
3742 .ndo_change_mtu
= myri10ge_change_mtu
,
3743 .ndo_set_multicast_list
= myri10ge_set_multicast_list
,
3744 .ndo_set_mac_address
= myri10ge_set_mac_address
,
3747 static int myri10ge_probe(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
3749 struct net_device
*netdev
;
3750 struct myri10ge_priv
*mgp
;
3751 struct device
*dev
= &pdev
->dev
;
3753 int status
= -ENXIO
;
3755 unsigned hdr_offset
, ss_offset
;
3757 netdev
= alloc_etherdev_mq(sizeof(*mgp
), MYRI10GE_MAX_SLICES
);
3758 if (netdev
== NULL
) {
3759 dev_err(dev
, "Could not allocate ethernet device\n");
3763 SET_NETDEV_DEV(netdev
, &pdev
->dev
);
3765 mgp
= netdev_priv(netdev
);
3768 mgp
->csum_flag
= MXGEFW_FLAGS_CKSUM
;
3769 mgp
->pause
= myri10ge_flow_control
;
3770 mgp
->intr_coal_delay
= myri10ge_intr_coal_delay
;
3771 mgp
->msg_enable
= netif_msg_init(myri10ge_debug
, MYRI10GE_MSG_DEFAULT
);
3772 init_waitqueue_head(&mgp
->down_wq
);
3774 if (pci_enable_device(pdev
)) {
3775 dev_err(&pdev
->dev
, "pci_enable_device call failed\n");
3777 goto abort_with_netdev
;
3780 /* Find the vendor-specific cap so we can check
3781 * the reboot register later on */
3782 mgp
->vendor_specific_offset
3783 = pci_find_capability(pdev
, PCI_CAP_ID_VNDR
);
3785 /* Set our max read request to 4KB */
3786 status
= pcie_set_readrq(pdev
, 4096);
3788 dev_err(&pdev
->dev
, "Error %d writing PCI_EXP_DEVCTL\n",
3790 goto abort_with_enabled
;
3793 pci_set_master(pdev
);
3795 status
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(64));
3799 "64-bit pci address mask was refused, "
3801 status
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(32));
3804 dev_err(&pdev
->dev
, "Error %d setting DMA mask\n", status
);
3805 goto abort_with_enabled
;
3807 (void)pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(64));
3808 mgp
->cmd
= dma_alloc_coherent(&pdev
->dev
, sizeof(*mgp
->cmd
),
3809 &mgp
->cmd_bus
, GFP_KERNEL
);
3810 if (mgp
->cmd
== NULL
)
3811 goto abort_with_enabled
;
3813 mgp
->board_span
= pci_resource_len(pdev
, 0);
3814 mgp
->iomem_base
= pci_resource_start(pdev
, 0);
3816 mgp
->wc_enabled
= 0;
3818 mgp
->mtrr
= mtrr_add(mgp
->iomem_base
, mgp
->board_span
,
3819 MTRR_TYPE_WRCOMB
, 1);
3821 mgp
->wc_enabled
= 1;
3823 mgp
->sram
= ioremap_wc(mgp
->iomem_base
, mgp
->board_span
);
3824 if (mgp
->sram
== NULL
) {
3825 dev_err(&pdev
->dev
, "ioremap failed for %ld bytes at 0x%lx\n",
3826 mgp
->board_span
, mgp
->iomem_base
);
3828 goto abort_with_mtrr
;
3831 ntohl(__raw_readl(mgp
->sram
+ MCP_HEADER_PTR_OFFSET
)) & 0xffffc;
3832 ss_offset
= hdr_offset
+ offsetof(struct mcp_gen_header
, string_specs
);
3833 mgp
->sram_size
= ntohl(__raw_readl(mgp
->sram
+ ss_offset
));
3834 if (mgp
->sram_size
> mgp
->board_span
||
3835 mgp
->sram_size
<= MYRI10GE_FW_OFFSET
) {
3837 "invalid sram_size %dB or board span %ldB\n",
3838 mgp
->sram_size
, mgp
->board_span
);
3839 goto abort_with_ioremap
;
3841 memcpy_fromio(mgp
->eeprom_strings
,
3842 mgp
->sram
+ mgp
->sram_size
, MYRI10GE_EEPROM_STRINGS_SIZE
);
3843 memset(mgp
->eeprom_strings
+ MYRI10GE_EEPROM_STRINGS_SIZE
- 2, 0, 2);
3844 status
= myri10ge_read_mac_addr(mgp
);
3846 goto abort_with_ioremap
;
3848 for (i
= 0; i
< ETH_ALEN
; i
++)
3849 netdev
->dev_addr
[i
] = mgp
->mac_addr
[i
];
3851 myri10ge_select_firmware(mgp
);
3853 status
= myri10ge_load_firmware(mgp
, 1);
3855 dev_err(&pdev
->dev
, "failed to load firmware\n");
3856 goto abort_with_ioremap
;
3858 myri10ge_probe_slices(mgp
);
3859 status
= myri10ge_alloc_slices(mgp
);
3861 dev_err(&pdev
->dev
, "failed to alloc slice state\n");
3862 goto abort_with_firmware
;
3864 netdev
->real_num_tx_queues
= mgp
->num_slices
;
3865 status
= myri10ge_reset(mgp
);
3867 dev_err(&pdev
->dev
, "failed reset\n");
3868 goto abort_with_slices
;
3870 #ifdef CONFIG_MYRI10GE_DCA
3871 myri10ge_setup_dca(mgp
);
3873 pci_set_drvdata(pdev
, mgp
);
3874 if ((myri10ge_initial_mtu
+ ETH_HLEN
) > MYRI10GE_MAX_ETHER_MTU
)
3875 myri10ge_initial_mtu
= MYRI10GE_MAX_ETHER_MTU
- ETH_HLEN
;
3876 if ((myri10ge_initial_mtu
+ ETH_HLEN
) < 68)
3877 myri10ge_initial_mtu
= 68;
3879 netdev
->netdev_ops
= &myri10ge_netdev_ops
;
3880 netdev
->mtu
= myri10ge_initial_mtu
;
3881 netdev
->base_addr
= mgp
->iomem_base
;
3882 netdev
->features
= mgp
->features
;
3885 netdev
->features
|= NETIF_F_HIGHDMA
;
3887 /* make sure we can get an irq, and that MSI can be
3888 * setup (if available). Also ensure netdev->irq
3889 * is set to correct value if MSI is enabled */
3890 status
= myri10ge_request_irq(mgp
);
3892 goto abort_with_firmware
;
3893 netdev
->irq
= pdev
->irq
;
3894 myri10ge_free_irq(mgp
);
3896 /* Save configuration space to be restored if the
3897 * nic resets due to a parity error */
3898 pci_save_state(pdev
);
3900 /* Setup the watchdog timer */
3901 setup_timer(&mgp
->watchdog_timer
, myri10ge_watchdog_timer
,
3902 (unsigned long)mgp
);
3904 SET_ETHTOOL_OPS(netdev
, &myri10ge_ethtool_ops
);
3905 INIT_WORK(&mgp
->watchdog_work
, myri10ge_watchdog
);
3906 status
= register_netdev(netdev
);
3908 dev_err(&pdev
->dev
, "register_netdev failed: %d\n", status
);
3909 goto abort_with_state
;
3911 if (mgp
->msix_enabled
)
3912 dev_info(dev
, "%d MSI-X IRQs, tx bndry %d, fw %s, WC %s\n",
3913 mgp
->num_slices
, mgp
->tx_boundary
, mgp
->fw_name
,
3914 (mgp
->wc_enabled
? "Enabled" : "Disabled"));
3916 dev_info(dev
, "%s IRQ %d, tx bndry %d, fw %s, WC %s\n",
3917 mgp
->msi_enabled
? "MSI" : "xPIC",
3918 netdev
->irq
, mgp
->tx_boundary
, mgp
->fw_name
,
3919 (mgp
->wc_enabled
? "Enabled" : "Disabled"));
3924 pci_restore_state(pdev
);
3927 myri10ge_free_slices(mgp
);
3929 abort_with_firmware
:
3930 myri10ge_dummy_rdma(mgp
, 0);
3933 if (mgp
->mac_addr_string
!= NULL
)
3935 "myri10ge_probe() failed: MAC=%s, SN=%ld\n",
3936 mgp
->mac_addr_string
, mgp
->serial_number
);
3942 mtrr_del(mgp
->mtrr
, mgp
->iomem_base
, mgp
->board_span
);
3944 dma_free_coherent(&pdev
->dev
, sizeof(*mgp
->cmd
),
3945 mgp
->cmd
, mgp
->cmd_bus
);
3948 pci_disable_device(pdev
);
3951 free_netdev(netdev
);
3958 * Does what is necessary to shutdown one Myrinet device. Called
3959 * once for each Myrinet card by the kernel when a module is
3962 static void myri10ge_remove(struct pci_dev
*pdev
)
3964 struct myri10ge_priv
*mgp
;
3965 struct net_device
*netdev
;
3967 mgp
= pci_get_drvdata(pdev
);
3971 flush_scheduled_work();
3973 unregister_netdev(netdev
);
3975 #ifdef CONFIG_MYRI10GE_DCA
3976 myri10ge_teardown_dca(mgp
);
3978 myri10ge_dummy_rdma(mgp
, 0);
3980 /* avoid a memory leak */
3981 pci_restore_state(pdev
);
3987 mtrr_del(mgp
->mtrr
, mgp
->iomem_base
, mgp
->board_span
);
3989 myri10ge_free_slices(mgp
);
3990 if (mgp
->msix_vectors
!= NULL
)
3991 kfree(mgp
->msix_vectors
);
3992 dma_free_coherent(&pdev
->dev
, sizeof(*mgp
->cmd
),
3993 mgp
->cmd
, mgp
->cmd_bus
);
3995 free_netdev(netdev
);
3996 pci_disable_device(pdev
);
3997 pci_set_drvdata(pdev
, NULL
);
4000 #define PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E 0x0008
4001 #define PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E_9 0x0009
4003 static struct pci_device_id myri10ge_pci_tbl
[] = {
4004 {PCI_DEVICE(PCI_VENDOR_ID_MYRICOM
, PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E
)},
4006 (PCI_VENDOR_ID_MYRICOM
, PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E_9
)},
4010 static struct pci_driver myri10ge_driver
= {
4012 .probe
= myri10ge_probe
,
4013 .remove
= myri10ge_remove
,
4014 .id_table
= myri10ge_pci_tbl
,
4016 .suspend
= myri10ge_suspend
,
4017 .resume
= myri10ge_resume
,
4021 #ifdef CONFIG_MYRI10GE_DCA
4023 myri10ge_notify_dca(struct notifier_block
*nb
, unsigned long event
, void *p
)
4025 int err
= driver_for_each_device(&myri10ge_driver
.driver
,
4027 myri10ge_notify_dca_device
);
4034 static struct notifier_block myri10ge_dca_notifier
= {
4035 .notifier_call
= myri10ge_notify_dca
,
4039 #endif /* CONFIG_MYRI10GE_DCA */
4041 static __init
int myri10ge_init_module(void)
4043 printk(KERN_INFO
"%s: Version %s\n", myri10ge_driver
.name
,
4044 MYRI10GE_VERSION_STR
);
4046 if (myri10ge_rss_hash
> MXGEFW_RSS_HASH_TYPE_MAX
) {
4048 "%s: Illegal rssh hash type %d, defaulting to source port\n",
4049 myri10ge_driver
.name
, myri10ge_rss_hash
);
4050 myri10ge_rss_hash
= MXGEFW_RSS_HASH_TYPE_SRC_PORT
;
4052 #ifdef CONFIG_MYRI10GE_DCA
4053 dca_register_notify(&myri10ge_dca_notifier
);
4055 if (myri10ge_max_slices
> MYRI10GE_MAX_SLICES
)
4056 myri10ge_max_slices
= MYRI10GE_MAX_SLICES
;
4058 return pci_register_driver(&myri10ge_driver
);
4061 module_init(myri10ge_init_module
);
4063 static __exit
void myri10ge_cleanup_module(void)
4065 #ifdef CONFIG_MYRI10GE_DCA
4066 dca_unregister_notify(&myri10ge_dca_notifier
);
4068 pci_unregister_driver(&myri10ge_driver
);
4071 module_exit(myri10ge_cleanup_module
);