include/asm-arm/arch-aaec2000/aaec2000.h

   1 /*
   2  *  linux/include/asm-arm/arch-aaec2000/aaec2000.h
   3  *
   4  *  AAEC-2000 registers definition
   5  *
   6  *  Copyright (c) 2005 Nicolas Bellido Y Ortega
   7  *
   8  *  This program is free software; you can redistribute it and/or modify
   9  *  it under the terms of the GNU General Public License version 2 as
  10  *  published by the Free Software Foundation.
  11  */
  12
  13 #ifndef __ASM_ARCH_AAEC2000_H
  14 #define __ASM_ARCH_AAEC2000_H
  15
  16 #ifndef __ASM_ARCH_HARDWARE_H
  17 #error You must include hardware.h not this file
  18 #endif /* __ASM_ARCH_HARDWARE_H */
  19
  20 /* Interrupt controller */
  21 #define IRQ_BASE        __REG(0x80000500)
  22 #define IRQ_INTSR       __REG(0x80000500)       /* Int Status Register */
  23 #define IRQ_INTRSR      __REG(0x80000504)       /* Int Raw (unmasked) Status */
  24 #define IRQ_INTENS      __REG(0x80000508)       /* Int Enable Set */
  25 #define IRQ_INTENC      __REG(0x8000050c)       /* Int Enable Clear */
  26
  27 /* UART 1 */
  28 #define UART1_BASE      __REG(0x80000600)
  29 #define UART1_DR        __REG(0x80000600) /* Data/FIFO Register */
  30 #define UART1_LCR       __REG(0x80000604) /* Link Control Register */
  31 #define UART1_BRCR      __REG(0x80000608) /* Baud Rate Control Register */
  32 #define UART1_CR        __REG(0x8000060c) /* Control Register */
  33 #define UART1_SR        __REG(0x80000610) /* Status Register */
  34 #define UART1_INT       __REG(0x80000614) /* Interrupt Status Register */
  35 #define UART1_INTM      __REG(0x80000618) /* Interrupt Mask Register */
  36 #define UART1_INTRES    __REG(0x8000061c) /* Int Result (masked status) Register */
  37
  38 /* UART 2 */
  39 #define UART2_BASE      __REG(0x80000700)
  40 #define UART2_DR        __REG(0x80000700) /* Data/FIFO Register */
  41 #define UART2_LCR       __REG(0x80000704) /* Link Control Register */
  42 #define UART2_BRCR      __REG(0x80000708) /* Baud Rate Control Register */
  43 #define UART2_CR        __REG(0x8000070c) /* Control Register */
  44 #define UART2_SR        __REG(0x80000710) /* Status Register */
  45 #define UART2_INT       __REG(0x80000714) /* Interrupt Status Register */
  46 #define UART2_INTM      __REG(0x80000718) /* Interrupt Mask Register */
  47 #define UART2_INTRES    __REG(0x8000071c) /* Int Result (masked status) Register */
  48
  49 /* UART 3 */
  50 #define UART3_BASE      __REG(0x80000800)
  51 #define UART3_DR        __REG(0x80000800) /* Data/FIFO Register */
  52 #define UART3_LCR       __REG(0x80000804) /* Link Control Register */
  53 #define UART3_BRCR      __REG(0x80000808) /* Baud Rate Control Register */
  54 #define UART3_CR        __REG(0x8000080c) /* Control Register */
  55 #define UART3_SR        __REG(0x80000810) /* Status Register */
  56 #define UART3_INT       __REG(0x80000814) /* Interrupt Status Register */
  57 #define UART3_INTM      __REG(0x80000818) /* Interrupt Mask Register */
  58 #define UART3_INTRES    __REG(0x8000081c) /* Int Result (masked status) Register */
  59
  60 /* These are used in some places */
  61 #define _UART1_BASE __PREG(UART1_BASE)
  62 #define _UART2_BASE __PREG(UART2_BASE)
  63 #define _UART3_BASE __PREG(UART3_BASE)
  64
  65 /* UART Registers Offsets */
  66 #define UART_DR         0x00
  67 #define UART_LCR        0x04
  68 #define UART_BRCR       0x08
  69 #define UART_CR         0x0c
  70 #define UART_SR         0x10
  71 #define UART_INT        0x14
  72 #define UART_INTM       0x18
  73 #define UART_INTRES     0x1c
  74
  75 /* UART_LCR Bitmask */
  76 #define UART_LCR_BRK    (1 << 0) /* Send Break */
  77 #define UART_LCR_PEN    (1 << 1) /* Parity Enable */
  78 #define UART_LCR_EP     (1 << 2) /* Even/Odd Parity */
  79 #define UART_LCR_S2     (1 << 3) /* One/Two Stop bits */
  80 #define UART_LCR_FIFO   (1 << 4) /* FIFO Enable */
  81 #define UART_LCR_WL5    (0 << 5) /* Word Length - 5 bits */
  82 #define UART_LCR_WL6    (1 << 5) /* Word Length - 6 bits */
  83 #define UART_LCR_WL7    (1 << 6) /* Word Length - 7 bits */
  84 #define UART_LCR_WL8    (1 << 7) /* Word Length - 8 bits */
  85
  86 /* UART_CR Bitmask */
  87 #define UART_CR_EN      (1 << 0) /* UART Enable */
  88 #define UART_CR_SIR     (1 << 1) /* IrDA SIR Enable */
  89 #define UART_CR_SIRLP   (1 << 2) /* Low Power IrDA Enable */
  90 #define UART_CR_RXP     (1 << 3) /* Receive Pin Polarity */
  91 #define UART_CR_TXP     (1 << 4) /* Transmit Pin Polarity */
  92 #define UART_CR_MXP     (1 << 5) /* Modem Pin Polarity */
  93 #define UART_CR_LOOP    (1 << 6) /* Loopback Mode */
  94
  95 /* UART_SR Bitmask */
  96 #define UART_SR_CTS     (1 << 0) /* Clear To Send Status */
  97 #define UART_SR_DSR     (1 << 1) /* Data Set Ready Status */
  98 #define UART_SR_DCD     (1 << 2) /* Data Carrier Detect Status */
  99 #define UART_SR_TxBSY   (1 << 3) /* Transmitter Busy Status */
 100 #define UART_SR_RxFE    (1 << 4) /* Receive FIFO Empty Status */
 101 #define UART_SR_TxFF    (1 << 5) /* Transmit FIFO Full Status */
 102 #define UART_SR_RxFF    (1 << 6) /* Receive FIFO Full Status */
 103 #define UART_SR_TxFE    (1 << 7) /* Transmit FIFO Empty Status */
 104
 105 /* UART_INT Bitmask */
 106 #define UART_INT_RIS    (1 << 0) /* Rx Interrupt */
 107 #define UART_INT_TIS    (1 << 1) /* Tx Interrupt */
 108 #define UART_INT_MIS    (1 << 2) /* Modem Interrupt */
 109 #define UART_INT_RTIS   (1 << 3) /* Receive Timeout Interrupt */
 110
 111 /* Timer 1 */
 112 #define TIMER1_BASE     __REG(0x80000c00)
 113 #define TIMER1_LOAD     __REG(0x80000c00)       /* Timer 1 Load Register */
 114 #define TIMER1_VAL      __REG(0x80000c04)       /* Timer 1 Value Register */
 115 #define TIMER1_CTRL     __REG(0x80000c08)       /* Timer 1 Control Register */
 116 #define TIMER1_CLEAR    __REG(0x80000c0c)       /* Timer 1 Clear Register */
 117
 118 /* Timer 2 */
 119 #define TIMER2_BASE     __REG(0x80000d00)
 120 #define TIMER2_LOAD     __REG(0x80000d00)       /* Timer 2 Load Register */
 121 #define TIMER2_VAL      __REG(0x80000d04)       /* Timer 2 Value Register */
 122 #define TIMER2_CTRL     __REG(0x80000d08)       /* Timer 2 Control Register */
 123 #define TIMER2_CLEAR    __REG(0x80000d0c)       /* Timer 2 Clear Register */
 124
 125 /* Timer 3 */
 126 #define TIMER3_BASE     __REG(0x80000e00)
 127 #define TIMER3_LOAD     __REG(0x80000e00)       /* Timer 3 Load Register */
 128 #define TIMER3_VAL      __REG(0x80000e04)       /* Timer 3 Value Register */
 129 #define TIMER3_CTRL     __REG(0x80000e08)       /* Timer 3 Control Register */
 130 #define TIMER3_CLEAR    __REG(0x80000e0c)       /* Timer 3 Clear Register */
 131
 132 /* Timer Control register bits */
 133 #define TIMER_CTRL_ENABLE       (1 << 7) /* Enable (Start° Timer */
 134 #define TIMER_CTRL_PERIODIC     (1 << 6) /* Periodic Running Mode */
 135 #define TIMER_CTRL_FREE_RUNNING (0 << 6) /* Normal Running Mode */
 136 #define TIMER_CTRL_CLKSEL_508K  (1 << 3) /* 508KHz Clock select (Timer 1, 2) */
 137 #define TIMER_CTRL_CLKSEL_2K    (0 << 3) /* 2KHz Clock Select (Timer 1, 2)*/
 138
 139 /* Power and State Control */
 140 #define POWER_BASE      __REG(0x80000400)
 141 #define POWER_PWRSR     __REG(0x80000400) /* Power Status Register */
 142 #define POWER_PWRCNT    __REG(0x80000404) /* Power/Clock control */
 143 #define POWER_HALT      __REG(0x80000408) /* Power Idle Mode */
 144 #define POWER_STDBY     __REG(0x8000040c) /* Power Standby Mode */
 145 #define POWER_BLEOI     __REG(0x80000410) /* Battery Low End of Interrupt */
 146 #define POWER_MCEOI     __REG(0x80000414) /* Media Changed EoI */
 147 #define POWER_TEOI      __REG(0x80000418) /* Tick EoI */
 148 #define POWER_STFCLR    __REG(0x8000041c) /* NbFlg, RSTFlg, PFFlg, CLDFlg Clear */
 149 #define POWER_CLKSET    __REG(0x80000420) /* Clock Speed Control */
 150
 151 #endif /* __ARM_ARCH_AAEC2000_H */