[PATCH] w1: Adds a sysfs entry (w1_master_search) that allows you to disable/enable...
[linux-2.6/verdex.git] / include / asm-arm / system.h
blob39dd7008013c839a102bc49f53ba4ba5691ab864
1 #ifndef __ASM_ARM_SYSTEM_H
2 #define __ASM_ARM_SYSTEM_H
4 #ifdef __KERNEL__
6 #include <linux/config.h>
8 #define CPU_ARCH_UNKNOWN 0
9 #define CPU_ARCH_ARMv3 1
10 #define CPU_ARCH_ARMv4 2
11 #define CPU_ARCH_ARMv4T 3
12 #define CPU_ARCH_ARMv5 4
13 #define CPU_ARCH_ARMv5T 5
14 #define CPU_ARCH_ARMv5TE 6
15 #define CPU_ARCH_ARMv5TEJ 7
16 #define CPU_ARCH_ARMv6 8
19 * CR1 bits (CP#15 CR1)
21 #define CR_M (1 << 0) /* MMU enable */
22 #define CR_A (1 << 1) /* Alignment abort enable */
23 #define CR_C (1 << 2) /* Dcache enable */
24 #define CR_W (1 << 3) /* Write buffer enable */
25 #define CR_P (1 << 4) /* 32-bit exception handler */
26 #define CR_D (1 << 5) /* 32-bit data address range */
27 #define CR_L (1 << 6) /* Implementation defined */
28 #define CR_B (1 << 7) /* Big endian */
29 #define CR_S (1 << 8) /* System MMU protection */
30 #define CR_R (1 << 9) /* ROM MMU protection */
31 #define CR_F (1 << 10) /* Implementation defined */
32 #define CR_Z (1 << 11) /* Implementation defined */
33 #define CR_I (1 << 12) /* Icache enable */
34 #define CR_V (1 << 13) /* Vectors relocated to 0xffff0000 */
35 #define CR_RR (1 << 14) /* Round Robin cache replacement */
36 #define CR_L4 (1 << 15) /* LDR pc can set T bit */
37 #define CR_DT (1 << 16)
38 #define CR_IT (1 << 18)
39 #define CR_ST (1 << 19)
40 #define CR_FI (1 << 21) /* Fast interrupt (lower latency mode) */
41 #define CR_U (1 << 22) /* Unaligned access operation */
42 #define CR_XP (1 << 23) /* Extended page tables */
43 #define CR_VE (1 << 24) /* Vectored interrupts */
45 #define CPUID_ID 0
46 #define CPUID_CACHETYPE 1
47 #define CPUID_TCM 2
48 #define CPUID_TLBTYPE 3
50 #define read_cpuid(reg) \
51 ({ \
52 unsigned int __val; \
53 asm("mrc p15, 0, %0, c0, c0, " __stringify(reg) \
54 : "=r" (__val) \
55 : \
56 : "cc"); \
57 __val; \
61 * This is used to ensure the compiler did actually allocate the register we
62 * asked it for some inline assembly sequences. Apparently we can't trust
63 * the compiler from one version to another so a bit of paranoia won't hurt.
64 * This string is meant to be concatenated with the inline asm string and
65 * will cause compilation to stop on mismatch.
66 * (for details, see gcc PR 15089)
68 #define __asmeq(x, y) ".ifnc " x "," y " ; .err ; .endif\n\t"
70 #ifndef __ASSEMBLY__
72 #include <linux/linkage.h>
74 struct thread_info;
75 struct task_struct;
77 /* information about the system we're running on */
78 extern unsigned int system_rev;
79 extern unsigned int system_serial_low;
80 extern unsigned int system_serial_high;
81 extern unsigned int mem_fclk_21285;
83 struct pt_regs;
85 void die(const char *msg, struct pt_regs *regs, int err)
86 __attribute__((noreturn));
88 void die_if_kernel(const char *str, struct pt_regs *regs, int err);
90 void hook_fault_code(int nr, int (*fn)(unsigned long, unsigned int,
91 struct pt_regs *),
92 int sig, const char *name);
94 #include <asm/proc-fns.h>
96 #define xchg(ptr,x) \
97 ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
99 #define tas(ptr) (xchg((ptr),1))
101 extern asmlinkage void __backtrace(void);
102 extern asmlinkage void c_backtrace(unsigned long fp, int pmode);
103 extern void show_pte(struct mm_struct *mm, unsigned long addr);
104 extern void __show_regs(struct pt_regs *);
106 extern int cpu_architecture(void);
107 extern void cpu_init(void);
109 #define set_cr(x) \
110 __asm__ __volatile__( \
111 "mcr p15, 0, %0, c1, c0, 0 @ set CR" \
112 : : "r" (x) : "cc")
114 #define get_cr() \
115 ({ \
116 unsigned int __val; \
117 __asm__ __volatile__( \
118 "mrc p15, 0, %0, c1, c0, 0 @ get CR" \
119 : "=r" (__val) : : "cc"); \
120 __val; \
123 extern unsigned long cr_no_alignment; /* defined in entry-armv.S */
124 extern unsigned long cr_alignment; /* defined in entry-armv.S */
126 #define UDBG_UNDEFINED (1 << 0)
127 #define UDBG_SYSCALL (1 << 1)
128 #define UDBG_BADABORT (1 << 2)
129 #define UDBG_SEGV (1 << 3)
130 #define UDBG_BUS (1 << 4)
132 extern unsigned int user_debug;
134 #if __LINUX_ARM_ARCH__ >= 4
135 #define vectors_high() (cr_alignment & CR_V)
136 #else
137 #define vectors_high() (0)
138 #endif
140 #define mb() __asm__ __volatile__ ("" : : : "memory")
141 #define rmb() mb()
142 #define wmb() mb()
143 #define read_barrier_depends() do { } while(0)
144 #define set_mb(var, value) do { var = value; mb(); } while (0)
145 #define set_wmb(var, value) do { var = value; wmb(); } while (0)
146 #define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t");
148 #ifdef CONFIG_SMP
150 * Define our own context switch locking. This allows us to enable
151 * interrupts over the context switch, otherwise we end up with high
152 * interrupt latency. The real problem area is switch_mm() which may
153 * do a full cache flush.
155 #define prepare_arch_switch(rq,next) \
156 do { \
157 spin_lock(&(next)->switch_lock); \
158 spin_unlock_irq(&(rq)->lock); \
159 } while (0)
161 #define finish_arch_switch(rq,prev) \
162 spin_unlock(&(prev)->switch_lock)
164 #define task_running(rq,p) \
165 ((rq)->curr == (p) || spin_is_locked(&(p)->switch_lock))
166 #else
168 * Our UP-case is more simple, but we assume knowledge of how
169 * spin_unlock_irq() and friends are implemented. This avoids
170 * us needlessly decrementing and incrementing the preempt count.
172 #define prepare_arch_switch(rq,next) local_irq_enable()
173 #define finish_arch_switch(rq,prev) spin_unlock(&(rq)->lock)
174 #define task_running(rq,p) ((rq)->curr == (p))
175 #endif
178 * switch_to(prev, next) should switch from task `prev' to `next'
179 * `prev' will never be the same as `next'. schedule() itself
180 * contains the memory barrier to tell GCC not to cache `current'.
182 extern struct task_struct *__switch_to(struct task_struct *, struct thread_info *, struct thread_info *);
184 #define switch_to(prev,next,last) \
185 do { \
186 last = __switch_to(prev,prev->thread_info,next->thread_info); \
187 } while (0)
190 * CPU interrupt mask handling.
192 #if __LINUX_ARM_ARCH__ >= 6
194 #define local_irq_save(x) \
195 ({ \
196 __asm__ __volatile__( \
197 "mrs %0, cpsr @ local_irq_save\n" \
198 "cpsid i" \
199 : "=r" (x) : : "memory", "cc"); \
202 #define local_irq_enable() __asm__("cpsie i @ __sti" : : : "memory", "cc")
203 #define local_irq_disable() __asm__("cpsid i @ __cli" : : : "memory", "cc")
204 #define local_fiq_enable() __asm__("cpsie f @ __stf" : : : "memory", "cc")
205 #define local_fiq_disable() __asm__("cpsid f @ __clf" : : : "memory", "cc")
207 #else
210 * Save the current interrupt enable state & disable IRQs
212 #define local_irq_save(x) \
213 ({ \
214 unsigned long temp; \
215 (void) (&temp == &x); \
216 __asm__ __volatile__( \
217 "mrs %0, cpsr @ local_irq_save\n" \
218 " orr %1, %0, #128\n" \
219 " msr cpsr_c, %1" \
220 : "=r" (x), "=r" (temp) \
222 : "memory", "cc"); \
226 * Enable IRQs
228 #define local_irq_enable() \
229 ({ \
230 unsigned long temp; \
231 __asm__ __volatile__( \
232 "mrs %0, cpsr @ local_irq_enable\n" \
233 " bic %0, %0, #128\n" \
234 " msr cpsr_c, %0" \
235 : "=r" (temp) \
237 : "memory", "cc"); \
241 * Disable IRQs
243 #define local_irq_disable() \
244 ({ \
245 unsigned long temp; \
246 __asm__ __volatile__( \
247 "mrs %0, cpsr @ local_irq_disable\n" \
248 " orr %0, %0, #128\n" \
249 " msr cpsr_c, %0" \
250 : "=r" (temp) \
252 : "memory", "cc"); \
256 * Enable FIQs
258 #define local_fiq_enable() \
259 ({ \
260 unsigned long temp; \
261 __asm__ __volatile__( \
262 "mrs %0, cpsr @ stf\n" \
263 " bic %0, %0, #64\n" \
264 " msr cpsr_c, %0" \
265 : "=r" (temp) \
267 : "memory", "cc"); \
271 * Disable FIQs
273 #define local_fiq_disable() \
274 ({ \
275 unsigned long temp; \
276 __asm__ __volatile__( \
277 "mrs %0, cpsr @ clf\n" \
278 " orr %0, %0, #64\n" \
279 " msr cpsr_c, %0" \
280 : "=r" (temp) \
282 : "memory", "cc"); \
285 #endif
288 * Save the current interrupt enable state.
290 #define local_save_flags(x) \
291 ({ \
292 __asm__ __volatile__( \
293 "mrs %0, cpsr @ local_save_flags" \
294 : "=r" (x) : : "memory", "cc"); \
298 * restore saved IRQ & FIQ state
300 #define local_irq_restore(x) \
301 __asm__ __volatile__( \
302 "msr cpsr_c, %0 @ local_irq_restore\n" \
304 : "r" (x) \
305 : "memory", "cc")
307 #define irqs_disabled() \
308 ({ \
309 unsigned long flags; \
310 local_save_flags(flags); \
311 (int)(flags & PSR_I_BIT); \
314 #ifdef CONFIG_SMP
315 #error SMP not supported
317 #define smp_mb() mb()
318 #define smp_rmb() rmb()
319 #define smp_wmb() wmb()
320 #define smp_read_barrier_depends() read_barrier_depends()
322 #else
324 #define smp_mb() barrier()
325 #define smp_rmb() barrier()
326 #define smp_wmb() barrier()
327 #define smp_read_barrier_depends() do { } while(0)
329 #if defined(CONFIG_CPU_SA1100) || defined(CONFIG_CPU_SA110)
331 * On the StrongARM, "swp" is terminally broken since it bypasses the
332 * cache totally. This means that the cache becomes inconsistent, and,
333 * since we use normal loads/stores as well, this is really bad.
334 * Typically, this causes oopsen in filp_close, but could have other,
335 * more disasterous effects. There are two work-arounds:
336 * 1. Disable interrupts and emulate the atomic swap
337 * 2. Clean the cache, perform atomic swap, flush the cache
339 * We choose (1) since its the "easiest" to achieve here and is not
340 * dependent on the processor type.
342 #define swp_is_buggy
343 #endif
345 static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size)
347 extern void __bad_xchg(volatile void *, int);
348 unsigned long ret;
349 #ifdef swp_is_buggy
350 unsigned long flags;
351 #endif
353 switch (size) {
354 #ifdef swp_is_buggy
355 case 1:
356 local_irq_save(flags);
357 ret = *(volatile unsigned char *)ptr;
358 *(volatile unsigned char *)ptr = x;
359 local_irq_restore(flags);
360 break;
362 case 4:
363 local_irq_save(flags);
364 ret = *(volatile unsigned long *)ptr;
365 *(volatile unsigned long *)ptr = x;
366 local_irq_restore(flags);
367 break;
368 #else
369 case 1: __asm__ __volatile__ ("swpb %0, %1, [%2]"
370 : "=&r" (ret)
371 : "r" (x), "r" (ptr)
372 : "memory", "cc");
373 break;
374 case 4: __asm__ __volatile__ ("swp %0, %1, [%2]"
375 : "=&r" (ret)
376 : "r" (x), "r" (ptr)
377 : "memory", "cc");
378 break;
379 #endif
380 default: __bad_xchg(ptr, size), ret = 0;
383 return ret;
386 #endif /* CONFIG_SMP */
388 #endif /* __ASSEMBLY__ */
390 #define arch_align_stack(x) (x)
392 #endif /* __KERNEL__ */
394 #endif