include/asm-mips/mach-au1x00/au1000_dma.h

   1 /*
   2  * BRIEF MODULE DESCRIPTION
   3  *      Defines for using and allocating dma channels on the Alchemy
   4  *      Au1000 mips processor.
   5  *
   6  * Copyright 2000 MontaVista Software Inc.
   7  * Author: MontaVista Software, Inc.
   8  *              stevel@mvista.com or source@mvista.com
   9  *
  10  *  This program is free software; you can redistribute  it and/or modify it
  11  *  under  the terms of  the GNU General  Public License as published by the
  12  *  Free Software Foundation;  either version 2 of the  License, or (at your
  13  *  option) any later version.
  14  *
  15  *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
  16  *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
  17  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
  18  *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
  19  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  20  *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
  21  *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  22  *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
  23  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  24  *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  25  *
  26  *  You should have received a copy of the  GNU General Public License along
  27  *  with this program; if not, write  to the Free Software Foundation, Inc.,
  28  *  675 Mass Ave, Cambridge, MA 02139, USA.
  29  *
  30  */
  31 #ifndef __ASM_AU1000_DMA_H
  32 #define __ASM_AU1000_DMA_H
  33
  34 #include <asm/io.h>             /* need byte IO */
  35 #include <linux/spinlock.h>     /* And spinlocks */
  36 #include <linux/delay.h>
  37 #include <asm/system.h>
  38
  39 #define NUM_AU1000_DMA_CHANNELS 8
  40
  41 /* DMA Channel Base Addresses */
  42 #define DMA_CHANNEL_BASE        0xB4002000
  43 #define DMA_CHANNEL_LEN         0x00000100
  44
  45 /* DMA Channel Register Offsets */
  46 #define DMA_MODE_SET            0x00000000
  47 #define DMA_MODE_READ           DMA_MODE_SET
  48 #define DMA_MODE_CLEAR          0x00000004
  49 /* DMA Mode register bits follow */
  50 #define DMA_DAH_MASK            (0x0f << 20)
  51 #define DMA_DID_BIT             16
  52 #define DMA_DID_MASK            (0x0f << DMA_DID_BIT)
  53 #define DMA_DS                  (1<<15)
  54 #define DMA_BE                  (1<<13)
  55 #define DMA_DR                  (1<<12)
  56 #define DMA_TS8                 (1<<11)
  57 #define DMA_DW_BIT              9
  58 #define DMA_DW_MASK             (0x03 << DMA_DW_BIT)
  59 #define DMA_DW8                 (0 << DMA_DW_BIT)
  60 #define DMA_DW16                (1 << DMA_DW_BIT)
  61 #define DMA_DW32                (2 << DMA_DW_BIT)
  62 #define DMA_NC                  (1<<8)
  63 #define DMA_IE                  (1<<7)
  64 #define DMA_HALT                (1<<6)
  65 #define DMA_GO                  (1<<5)
  66 #define DMA_AB                  (1<<4)
  67 #define DMA_D1                  (1<<3)
  68 #define DMA_BE1                 (1<<2)
  69 #define DMA_D0                  (1<<1)
  70 #define DMA_BE0                 (1<<0)
  71
  72 #define DMA_PERIPHERAL_ADDR       0x00000008
  73 #define DMA_BUFFER0_START         0x0000000C
  74 #define DMA_BUFFER1_START         0x00000014
  75 #define DMA_BUFFER0_COUNT         0x00000010
  76 #define DMA_BUFFER1_COUNT         0x00000018
  77 #define DMA_BAH_BIT 16
  78 #define DMA_BAH_MASK (0x0f << DMA_BAH_BIT)
  79 #define DMA_COUNT_BIT 0
  80 #define DMA_COUNT_MASK (0xffff << DMA_COUNT_BIT)
  81
  82 /* DMA Device ID's follow */
  83 enum {
  84         DMA_ID_UART0_TX = 0,
  85         DMA_ID_UART0_RX,
  86         DMA_ID_GP04,
  87         DMA_ID_GP05,
  88         DMA_ID_AC97C_TX,
  89         DMA_ID_AC97C_RX,
  90         DMA_ID_UART3_TX,
  91         DMA_ID_UART3_RX,
  92         DMA_ID_USBDEV_EP0_RX,
  93         DMA_ID_USBDEV_EP0_TX,
  94         DMA_ID_USBDEV_EP2_TX,
  95         DMA_ID_USBDEV_EP3_TX,
  96         DMA_ID_USBDEV_EP4_RX,
  97         DMA_ID_USBDEV_EP5_RX,
  98         DMA_ID_I2S_TX,
  99         DMA_ID_I2S_RX,
 100         DMA_NUM_DEV
 101 };
 102
 103 /* DMA Device ID's for 2nd bank (AU1100) follow */
 104 enum {
 105         DMA_ID_SD0_TX = 0,
 106         DMA_ID_SD0_RX,
 107         DMA_ID_SD1_TX,
 108         DMA_ID_SD1_RX,
 109         DMA_NUM_DEV_BANK2
 110 };
 111
 112 struct dma_chan {
 113         int dev_id;             // this channel is allocated if >=0, free otherwise
 114         unsigned int io;
 115         const char *dev_str;
 116         int irq;
 117         void *irq_dev;
 118         unsigned int fifo_addr;
 119         unsigned int mode;
 120 };
 121
 122 /* These are in arch/mips/au1000/common/dma.c */
 123 extern struct dma_chan au1000_dma_table[];
 124 extern int request_au1000_dma(int dev_id,
 125                               const char *dev_str,
 126                               irqreturn_t (*irqhandler)(int, void *,
 127                                                  struct pt_regs *),
 128                               unsigned long irqflags,
 129                               void *irq_dev_id);
 130 extern void free_au1000_dma(unsigned int dmanr);
 131 extern int au1000_dma_read_proc(char *buf, char **start, off_t fpos,
 132                                 int length, int *eof, void *data);
 133 extern void dump_au1000_dma_channel(unsigned int dmanr);
 134 extern spinlock_t au1000_dma_spin_lock;
 135
 136
 137 static __inline__ struct dma_chan *get_dma_chan(unsigned int dmanr)
 138 {
 139         if (dmanr >= NUM_AU1000_DMA_CHANNELS
 140             || au1000_dma_table[dmanr].dev_id < 0)
 141                 return NULL;
 142         return &au1000_dma_table[dmanr];
 143 }
 144
 145 static __inline__ unsigned long claim_dma_lock(void)
 146 {
 147         unsigned long flags;
 148         spin_lock_irqsave(&au1000_dma_spin_lock, flags);
 149         return flags;
 150 }
 151
 152 static __inline__ void release_dma_lock(unsigned long flags)
 153 {
 154         spin_unlock_irqrestore(&au1000_dma_spin_lock, flags);
 155 }
 156
 157 /*
 158  * Set the DMA buffer enable bits in the mode register.
 159  */
 160 static __inline__ void enable_dma_buffer0(unsigned int dmanr)
 161 {
 162         struct dma_chan *chan = get_dma_chan(dmanr);
 163         if (!chan)
 164                 return;
 165         au_writel(DMA_BE0, chan->io + DMA_MODE_SET);
 166 }
 167 static __inline__ void enable_dma_buffer1(unsigned int dmanr)
 168 {
 169         struct dma_chan *chan = get_dma_chan(dmanr);
 170         if (!chan)
 171                 return;
 172         au_writel(DMA_BE1, chan->io + DMA_MODE_SET);
 173 }
 174 static __inline__ void enable_dma_buffers(unsigned int dmanr)
 175 {
 176         struct dma_chan *chan = get_dma_chan(dmanr);
 177         if (!chan)
 178                 return;
 179         au_writel(DMA_BE0 | DMA_BE1, chan->io + DMA_MODE_SET);
 180 }
 181
 182 static __inline__ void start_dma(unsigned int dmanr)
 183 {
 184         struct dma_chan *chan = get_dma_chan(dmanr);
 185         if (!chan)
 186                 return;
 187
 188         au_writel(DMA_GO, chan->io + DMA_MODE_SET);
 189 }
 190
 191 #define DMA_HALT_POLL 0x5000
 192
 193 static __inline__ void halt_dma(unsigned int dmanr)
 194 {
 195         struct dma_chan *chan = get_dma_chan(dmanr);
 196         int i;
 197         if (!chan)
 198                 return;
 199
 200         au_writel(DMA_GO, chan->io + DMA_MODE_CLEAR);
 201         // poll the halt bit
 202         for (i = 0; i < DMA_HALT_POLL; i++)
 203                 if (au_readl(chan->io + DMA_MODE_READ) & DMA_HALT)
 204                         break;
 205         if (i == DMA_HALT_POLL)
 206                 printk(KERN_INFO "halt_dma: HALT poll expired!\n");
 207 }
 208
 209
 210 static __inline__ void disable_dma(unsigned int dmanr)
 211 {
 212         struct dma_chan *chan = get_dma_chan(dmanr);
 213         if (!chan)
 214                 return;
 215
 216         halt_dma(dmanr);
 217
 218         // now we can disable the buffers
 219         au_writel(~DMA_GO, chan->io + DMA_MODE_CLEAR);
 220 }
 221
 222 static __inline__ int dma_halted(unsigned int dmanr)
 223 {
 224         struct dma_chan *chan = get_dma_chan(dmanr);
 225         if (!chan)
 226                 return 1;
 227         return (au_readl(chan->io + DMA_MODE_READ) & DMA_HALT) ? 1 : 0;
 228 }
 229
 230 /* initialize a DMA channel */
 231 static __inline__ void init_dma(unsigned int dmanr)
 232 {
 233         struct dma_chan *chan = get_dma_chan(dmanr);
 234         u32 mode;
 235         if (!chan)
 236                 return;
 237
 238         disable_dma(dmanr);
 239
 240         // set device FIFO address
 241         au_writel(CPHYSADDR(chan->fifo_addr),
 242                   chan->io + DMA_PERIPHERAL_ADDR);
 243
 244         mode = chan->mode | (chan->dev_id << DMA_DID_BIT);
 245         if (chan->irq)
 246                 mode |= DMA_IE;
 247
 248         au_writel(~mode, chan->io + DMA_MODE_CLEAR);
 249         au_writel(mode, chan->io + DMA_MODE_SET);
 250 }
 251
 252 /*
 253  * set mode for a specific DMA channel
 254  */
 255 static __inline__ void set_dma_mode(unsigned int dmanr, unsigned int mode)
 256 {
 257         struct dma_chan *chan = get_dma_chan(dmanr);
 258         if (!chan)
 259                 return;
 260         /*
 261          * set_dma_mode is only allowed to change endianess, direction,
 262          * transfer size, device FIFO width, and coherency settings.
 263          * Make sure anything else is masked off.
 264          */
 265         mode &= (DMA_BE | DMA_DR | DMA_TS8 | DMA_DW_MASK | DMA_NC);
 266         chan->mode &= ~(DMA_BE | DMA_DR | DMA_TS8 | DMA_DW_MASK | DMA_NC);
 267         chan->mode |= mode;
 268 }
 269
 270 static __inline__ unsigned int get_dma_mode(unsigned int dmanr)
 271 {
 272         struct dma_chan *chan = get_dma_chan(dmanr);
 273         if (!chan)
 274                 return 0;
 275         return chan->mode;
 276 }
 277
 278 static __inline__ int get_dma_active_buffer(unsigned int dmanr)
 279 {
 280         struct dma_chan *chan = get_dma_chan(dmanr);
 281         if (!chan)
 282                 return -1;
 283         return (au_readl(chan->io + DMA_MODE_READ) & DMA_AB) ? 1 : 0;
 284 }
 285
 286
 287 /*
 288  * set the device FIFO address for a specific DMA channel - only
 289  * applicable to GPO4 and GPO5. All the other devices have fixed
 290  * FIFO addresses.
 291  */
 292 static __inline__ void set_dma_fifo_addr(unsigned int dmanr,
 293                                          unsigned int a)
 294 {
 295         struct dma_chan *chan = get_dma_chan(dmanr);
 296         if (!chan)
 297                 return;
 298
 299         if (chan->mode & DMA_DS)        /* second bank of device ids */
 300                 return;
 301
 302         if (chan->dev_id != DMA_ID_GP04 && chan->dev_id != DMA_ID_GP05)
 303                 return;
 304
 305         au_writel(CPHYSADDR(a), chan->io + DMA_PERIPHERAL_ADDR);
 306 }
 307
 308 /*
 309  * Clear the DMA buffer done bits in the mode register.
 310  */
 311 static __inline__ void clear_dma_done0(unsigned int dmanr)
 312 {
 313         struct dma_chan *chan = get_dma_chan(dmanr);
 314         if (!chan)
 315                 return;
 316         au_writel(DMA_D0, chan->io + DMA_MODE_CLEAR);
 317 }
 318 static __inline__ void clear_dma_done1(unsigned int dmanr)
 319 {
 320         struct dma_chan *chan = get_dma_chan(dmanr);
 321         if (!chan)
 322                 return;
 323         au_writel(DMA_D1, chan->io + DMA_MODE_CLEAR);
 324 }
 325
 326 /*
 327  * This does nothing - not applicable to Au1000 DMA.
 328  */
 329 static __inline__ void set_dma_page(unsigned int dmanr, char pagenr)
 330 {
 331 }
 332
 333 /*
 334  * Set Buffer 0 transfer address for specific DMA channel.
 335  */
 336 static __inline__ void set_dma_addr0(unsigned int dmanr, unsigned int a)
 337 {
 338         struct dma_chan *chan = get_dma_chan(dmanr);
 339         if (!chan)
 340                 return;
 341         au_writel(a, chan->io + DMA_BUFFER0_START);
 342 }
 343
 344 /*
 345  * Set Buffer 1 transfer address for specific DMA channel.
 346  */
 347 static __inline__ void set_dma_addr1(unsigned int dmanr, unsigned int a)
 348 {
 349         struct dma_chan *chan = get_dma_chan(dmanr);
 350         if (!chan)
 351                 return;
 352         au_writel(a, chan->io + DMA_BUFFER1_START);
 353 }
 354
 355
 356 /*
 357  * Set Buffer 0 transfer size (max 64k) for a specific DMA channel.
 358  */
 359 static __inline__ void set_dma_count0(unsigned int dmanr,
 360                                       unsigned int count)
 361 {
 362         struct dma_chan *chan = get_dma_chan(dmanr);
 363         if (!chan)
 364                 return;
 365         count &= DMA_COUNT_MASK;
 366         au_writel(count, chan->io + DMA_BUFFER0_COUNT);
 367 }
 368
 369 /*
 370  * Set Buffer 1 transfer size (max 64k) for a specific DMA channel.
 371  */
 372 static __inline__ void set_dma_count1(unsigned int dmanr,
 373                                       unsigned int count)
 374 {
 375         struct dma_chan *chan = get_dma_chan(dmanr);
 376         if (!chan)
 377                 return;
 378         count &= DMA_COUNT_MASK;
 379         au_writel(count, chan->io + DMA_BUFFER1_COUNT);
 380 }
 381
 382 /*
 383  * Set both buffer transfer sizes (max 64k) for a specific DMA channel.
 384  */
 385 static __inline__ void set_dma_count(unsigned int dmanr,
 386                                      unsigned int count)
 387 {
 388         struct dma_chan *chan = get_dma_chan(dmanr);
 389         if (!chan)
 390                 return;
 391         count &= DMA_COUNT_MASK;
 392         au_writel(count, chan->io + DMA_BUFFER0_COUNT);
 393         au_writel(count, chan->io + DMA_BUFFER1_COUNT);
 394 }
 395
 396 /*
 397  * Returns which buffer has its done bit set in the mode register.
 398  * Returns -1 if neither or both done bits set.
 399  */
 400 static __inline__ unsigned int get_dma_buffer_done(unsigned int dmanr)
 401 {
 402         struct dma_chan *chan = get_dma_chan(dmanr);
 403         if (!chan)
 404                 return 0;
 405
 406     return au_readl(chan->io + DMA_MODE_READ) & (DMA_D0 | DMA_D1);
 407 }
 408
 409
 410 /*
 411  * Returns the DMA channel's Buffer Done IRQ number.
 412  */
 413 static __inline__ int get_dma_done_irq(unsigned int dmanr)
 414 {
 415         struct dma_chan *chan = get_dma_chan(dmanr);
 416         if (!chan)
 417                 return -1;
 418
 419         return chan->irq;
 420 }
 421
 422 /*
 423  * Get DMA residue count. Returns the number of _bytes_ left to transfer.
 424  */
 425 static __inline__ int get_dma_residue(unsigned int dmanr)
 426 {
 427         int curBufCntReg, count;
 428         struct dma_chan *chan = get_dma_chan(dmanr);
 429         if (!chan)
 430                 return 0;
 431
 432         curBufCntReg = (au_readl(chan->io + DMA_MODE_READ) & DMA_AB) ?
 433             DMA_BUFFER1_COUNT : DMA_BUFFER0_COUNT;
 434
 435         count = au_readl(chan->io + curBufCntReg) & DMA_COUNT_MASK;
 436
 437         if ((chan->mode & DMA_DW_MASK) == DMA_DW16)
 438                 count <<= 1;
 439         else if ((chan->mode & DMA_DW_MASK) == DMA_DW32)
 440                 count <<= 2;
 441
 442         return count;
 443 }
 444
 445 #endif /* __ASM_AU1000_DMA_H */
 446